diff --git a/yosys/techlibs/quicklogic/ql_dsp_macc_pm.h b/yosys/techlibs/quicklogic/ql_dsp_macc_pm.h new file mode 100644 index 00000000000..534c88c71c0 --- /dev/null +++ b/yosys/techlibs/quicklogic/ql_dsp_macc_pm.h @@ -0,0 +1,476 @@ +// Generated by pmgen.py from techlibs/quicklogic/ql_dsp_macc.pmg + +struct ql_dsp_macc_pm { + Module *module; + SigMap sigmap; + std::function on_accept; + bool setup_done; + bool generate_mode; + int accept_cnt; + + uint32_t rngseed; + int rng(unsigned int n) { + rngseed ^= rngseed << 13; + rngseed ^= rngseed >> 17; + rngseed ^= rngseed << 5; + return rngseed % n; + } + + typedef std::tuple<> index_1_key_type; + typedef std::tuple index_1_value_type; + dict> index_1; + typedef std::tuple index_3_key_type; + typedef std::tuple index_3_value_type; + dict> index_3; + typedef std::tuple index_4_key_type; + typedef std::tuple index_4_value_type; + dict> index_4; + typedef std::tuple index_5_key_type; + typedef std::tuple index_5_value_type; + dict> index_5; + dict> sigusers; + pool blacklist_cells; + pool autoremove_cells; + dict rollback_cache; + int rollback; + + struct state_ql_dsp_macc_t { + Cell* add; + IdString add_ba; + Cell* ff; + Cell* mul; + Cell* mux; + IdString mux_ab; + bool mux_in_pattern; + bool output_registered; + } st_ql_dsp_macc; + + struct udata_ql_dsp_macc_t { + } ud_ql_dsp_macc; + + IdString id_b_A{"\\A"}; + IdString id_b_B{"\\B"}; + IdString id_b_CLK_POLARITY{"\\CLK_POLARITY"}; + IdString id_b_D{"\\D"}; + IdString id_b_Q{"\\Q"}; + IdString id_b_Y{"\\Y"}; + IdString id_d_add{"$add"}; + IdString id_d_adff{"$adff"}; + IdString id_d_adffe{"$adffe"}; + IdString id_d_dff{"$dff"}; + IdString id_d_dffe{"$dffe"}; + IdString id_d_mul{"$mul"}; + IdString id_d_mux{"$mux"}; + IdString id_d_sub{"$sub"}; + + void add_siguser(const SigSpec &sig, Cell *cell) { + for (auto bit : sigmap(sig)) { + if (bit.wire == nullptr) continue; + sigusers[bit].insert(cell); + } + } + + void blacklist(Cell *cell) { + if (cell != nullptr && blacklist_cells.insert(cell).second) { + auto ptr = rollback_cache.find(cell); + if (ptr == rollback_cache.end()) return; + int rb = ptr->second; + if (rollback == 0 || rollback > rb) + rollback = rb; + } + } + + void autoremove(Cell *cell) { + if (cell != nullptr) { + autoremove_cells.insert(cell); + blacklist(cell); + } + } + + SigSpec port(Cell *cell, IdString portname) { + try { + return sigmap(cell->getPort(portname)); + } catch(std::out_of_range&) { log_error("Accessing non existing port %s\n",portname.c_str()); } + } + + SigSpec port(Cell *cell, IdString portname, const SigSpec& defval) { + return sigmap(cell->connections_.at(portname, defval)); + } + + Const param(Cell *cell, IdString paramname) { + try { + return cell->getParam(paramname); + } catch(std::out_of_range&) { log_error("Accessing non existing parameter %s\n",paramname.c_str()); } + } + + Const param(Cell *cell, IdString paramname, const Const& defval) { + return cell->parameters.at(paramname, defval); + } + + int nusers(const SigSpec &sig) { + pool users; + for (auto bit : sigmap(sig)) + for (auto user : sigusers[bit]) + users.insert(user); + return GetSize(users); + } + + ql_dsp_macc_pm(Module *module, const vector &cells) : + module(module), sigmap(module), setup_done(false), generate_mode(false), rngseed(12345678) { + setup(cells); + } + + ql_dsp_macc_pm(Module *module) : + module(module), sigmap(module), setup_done(false), generate_mode(false), rngseed(12345678) { + } + + void setup(const vector &cells) { + log_assert(!setup_done); + setup_done = true; + for (auto port : module->ports) + add_siguser(module->wire(port), nullptr); + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) + add_siguser(conn.second, cell); + for (auto cell : cells) { + do { + Cell *mul = cell; + index_1_value_type value; + std::get<0>(value) = cell; + if (!(mul->type.in(id_d_mul))) continue; + if (!(nusers(port(mul, id_b_Y)) <= 3)) continue; + index_1_key_type key; + index_1[key].push_back(value); + } while (0); + do { + Cell *add = cell; + index_3_value_type value; + std::get<0>(value) = cell; + if (!(add->type.in(id_d_add, id_d_sub))) continue; + vector _pmg_choices_AB = {id_b_A, id_b_B}; + for (const IdString &AB : _pmg_choices_AB) { + std::get<1>(value) = AB; + IdString &BA = std::get<2>(value); + BA = (AB == id_b_A ? id_b_B : id_b_A); + index_3_key_type key; + std::get<0>(key) = port(add, AB); + index_3[key].push_back(value); + } + } while (0); + do { + Cell *mux = cell; + index_4_value_type value; + std::get<0>(value) = cell; + if (!(mux->type.in(id_d_mux))) continue; + vector _pmg_choices_AB = {id_b_A, id_b_B}; + for (const IdString &AB : _pmg_choices_AB) { + std::get<1>(value) = AB; + IdString &BA = std::get<2>(value); + BA = (AB == id_b_A ? id_b_B : id_b_A); + index_4_key_type key; + std::get<0>(key) = port(mux, AB); + std::get<1>(key) = port(mux, BA); + index_4[key].push_back(value); + } + } while (0); + do { + Cell *ff = cell; + index_5_value_type value; + std::get<0>(value) = cell; + if (!(ff->type.in(id_d_dff, id_d_adff, id_d_dffe, id_d_adffe))) continue; + if (!(param(ff, id_b_CLK_POLARITY).as_bool())) continue; + index_5_key_type key; + std::get<0>(key) = port(ff, id_b_D); + std::get<1>(key) = port(ff, id_b_Q); + index_5[key].push_back(value); + } while (0); + } + } + + ~ql_dsp_macc_pm() { + for (auto cell : autoremove_cells) + module->remove(cell); + } + + int run_ql_dsp_macc(std::function on_accept_f) { + log_assert(setup_done); + accept_cnt = 0; + on_accept = on_accept_f; + rollback = 0; + st_ql_dsp_macc.add = nullptr; + st_ql_dsp_macc.add_ba = IdString(); + st_ql_dsp_macc.ff = nullptr; + st_ql_dsp_macc.mul = nullptr; + st_ql_dsp_macc.mux = nullptr; + st_ql_dsp_macc.mux_ab = IdString(); + st_ql_dsp_macc.mux_in_pattern = bool(); + st_ql_dsp_macc.output_registered = bool(); + block_0(1); + log_assert(rollback_cache.empty()); + return accept_cnt; + } + + int run_ql_dsp_macc(std::function on_accept_f) { + return run_ql_dsp_macc([&](){on_accept_f(*this);}); + } + + int run_ql_dsp_macc() { + return run_ql_dsp_macc([](){}); + } + + void block_subpattern_ql_dsp_macc_(int recursion) { block_0(recursion); } + + // techlibs/quicklogic/ql_dsp_macc.pmg:21 + void block_0(int recursion YS_MAYBE_UNUSED) { + bool &mux_in_pattern YS_MAYBE_UNUSED = st_ql_dsp_macc.mux_in_pattern; + +#define reject do { goto rollback_label; } while(0) +#define accept do { accept_cnt++; on_accept(); if (rollback) goto rollback_label; } while(0) +#define finish do { rollback = -1; goto rollback_label; } while(0) +#define branch do { block_1(recursion+1); if (rollback) goto rollback_label; } while(0) +#define subpattern(pattern_name) do { block_subpattern_ql_dsp_macc_ ## pattern_name (recursion+1); if (rollback) goto rollback_label; } while(0) + mux_in_pattern = false; + branch; + mux_in_pattern = true; + + block_1(recursion+1); +#undef reject +#undef accept +#undef finish +#undef branch +#undef subpattern + +rollback_label: + YS_MAYBE_UNUSED; + + mux_in_pattern = bool(); + } + + // techlibs/quicklogic/ql_dsp_macc.pmg:28 + void block_1(int recursion YS_MAYBE_UNUSED) { + const bool &mux_in_pattern YS_MAYBE_UNUSED = st_ql_dsp_macc.mux_in_pattern; + Cell* &mul YS_MAYBE_UNUSED = st_ql_dsp_macc.mul; + Cell* _pmg_backup_mul = mul; + + index_1_key_type key; + auto cells_ptr = index_1.find(key); + + if (cells_ptr != index_1.end()) { + const vector &cells = cells_ptr->second; + for (int _pmg_idx = 0; _pmg_idx < GetSize(cells); _pmg_idx++) { + mul = std::get<0>(cells[_pmg_idx]); + if (blacklist_cells.count(mul)) continue; + if (!(nusers(port(mul, id_b_Y)) == (mux_in_pattern ? 3 : 2))) continue; + auto rollback_ptr = rollback_cache.insert(make_pair(std::get<0>(cells[_pmg_idx]), recursion)); + block_2(recursion+1); + if (rollback_ptr.second) + rollback_cache.erase(rollback_ptr.first); + if (rollback) { + if (rollback != recursion) { + mul = _pmg_backup_mul; + return; + } + rollback = 0; + } + } + } + + mul = nullptr; + mul = _pmg_backup_mul; + } + + // techlibs/quicklogic/ql_dsp_macc.pmg:36 + void block_2(int recursion YS_MAYBE_UNUSED) { + Cell* const &mul YS_MAYBE_UNUSED = st_ql_dsp_macc.mul; + const bool &mux_in_pattern YS_MAYBE_UNUSED = st_ql_dsp_macc.mux_in_pattern; + bool &output_registered YS_MAYBE_UNUSED = st_ql_dsp_macc.output_registered; + +#define reject do { goto rollback_label; } while(0) +#define accept do { accept_cnt++; on_accept(); if (rollback) goto rollback_label; } while(0) +#define finish do { rollback = -1; goto rollback_label; } while(0) +#define branch do { block_3(recursion+1); if (rollback) goto rollback_label; } while(0) +#define subpattern(pattern_name) do { block_subpattern_ql_dsp_macc_ ## pattern_name (recursion+1); if (rollback) goto rollback_label; } while(0) + output_registered = false; + branch; + output_registered = true; + + block_3(recursion+1); +#undef reject +#undef accept +#undef finish +#undef branch +#undef subpattern + +rollback_label: + YS_MAYBE_UNUSED; + + output_registered = bool(); + } + + // techlibs/quicklogic/ql_dsp_macc.pmg:42 + void block_3(int recursion YS_MAYBE_UNUSED) { + Cell* const &mul YS_MAYBE_UNUSED = st_ql_dsp_macc.mul; + const bool &mux_in_pattern YS_MAYBE_UNUSED = st_ql_dsp_macc.mux_in_pattern; + const bool &output_registered YS_MAYBE_UNUSED = st_ql_dsp_macc.output_registered; + Cell* &add YS_MAYBE_UNUSED = st_ql_dsp_macc.add; + IdString &add_ba YS_MAYBE_UNUSED = st_ql_dsp_macc.add_ba; + Cell* _pmg_backup_add = add; + + index_3_key_type key; + std::get<0>(key) = port(mul, id_b_Y); + auto cells_ptr = index_3.find(key); + + if (cells_ptr != index_3.end()) { + const vector &cells = cells_ptr->second; + for (int _pmg_idx = 0; _pmg_idx < GetSize(cells); _pmg_idx++) { + add = std::get<0>(cells[_pmg_idx]); + const IdString &AB YS_MAYBE_UNUSED = std::get<1>(cells[_pmg_idx]); + const IdString &BA YS_MAYBE_UNUSED = std::get<2>(cells[_pmg_idx]); + if (blacklist_cells.count(add)) continue; + if (!(nusers(port(add, id_b_Y)) == (!mux_in_pattern && !output_registered ? 3 : 2))) continue; + auto _pmg_backup_add_ba = add_ba; + add_ba = BA; + auto rollback_ptr = rollback_cache.insert(make_pair(std::get<0>(cells[_pmg_idx]), recursion)); + block_4(recursion+1); + add_ba = _pmg_backup_add_ba; + if (rollback_ptr.second) + rollback_cache.erase(rollback_ptr.first); + if (rollback) { + if (rollback != recursion) { + add = _pmg_backup_add; + return; + } + rollback = 0; + } + } + } + + add = nullptr; + add = _pmg_backup_add; + } + + // techlibs/quicklogic/ql_dsp_macc.pmg:56 + void block_4(int recursion YS_MAYBE_UNUSED) { + Cell* const &add YS_MAYBE_UNUSED = st_ql_dsp_macc.add; + const IdString &add_ba YS_MAYBE_UNUSED = st_ql_dsp_macc.add_ba; + Cell* const &mul YS_MAYBE_UNUSED = st_ql_dsp_macc.mul; + const bool &mux_in_pattern YS_MAYBE_UNUSED = st_ql_dsp_macc.mux_in_pattern; + const bool &output_registered YS_MAYBE_UNUSED = st_ql_dsp_macc.output_registered; + Cell* &mux YS_MAYBE_UNUSED = st_ql_dsp_macc.mux; + IdString &mux_ab YS_MAYBE_UNUSED = st_ql_dsp_macc.mux_ab; + Cell* _pmg_backup_mux = mux; + + if (!(mux_in_pattern)) { + mux = nullptr; + block_5(recursion+1); + mux = _pmg_backup_mux; + return; + } + + index_4_key_type key; + std::get<0>(key) = port(mul, id_b_Y); + std::get<1>(key) = port(add, id_b_Y); + auto cells_ptr = index_4.find(key); + + if (cells_ptr != index_4.end()) { + const vector &cells = cells_ptr->second; + for (int _pmg_idx = 0; _pmg_idx < GetSize(cells); _pmg_idx++) { + mux = std::get<0>(cells[_pmg_idx]); + const IdString &AB YS_MAYBE_UNUSED = std::get<1>(cells[_pmg_idx]); + const IdString &BA YS_MAYBE_UNUSED = std::get<2>(cells[_pmg_idx]); + if (blacklist_cells.count(mux)) continue; + if (!(nusers(port(mux, id_b_Y)) == (output_registered ? 2 : 3))) continue; + auto _pmg_backup_mux_ab = mux_ab; + mux_ab = AB; + auto rollback_ptr = rollback_cache.insert(make_pair(std::get<0>(cells[_pmg_idx]), recursion)); + block_5(recursion+1); + mux_ab = _pmg_backup_mux_ab; + if (rollback_ptr.second) + rollback_cache.erase(rollback_ptr.first); + if (rollback) { + if (rollback != recursion) { + mux = _pmg_backup_mux; + return; + } + rollback = 0; + } + } + } + + mux = nullptr; + mux = _pmg_backup_mux; + } + + // techlibs/quicklogic/ql_dsp_macc.pmg:67 + void block_5(int recursion YS_MAYBE_UNUSED) { + Cell* const &add YS_MAYBE_UNUSED = st_ql_dsp_macc.add; + const IdString &add_ba YS_MAYBE_UNUSED = st_ql_dsp_macc.add_ba; + Cell* const &mul YS_MAYBE_UNUSED = st_ql_dsp_macc.mul; + Cell* const &mux YS_MAYBE_UNUSED = st_ql_dsp_macc.mux; + const IdString &mux_ab YS_MAYBE_UNUSED = st_ql_dsp_macc.mux_ab; + const bool &mux_in_pattern YS_MAYBE_UNUSED = st_ql_dsp_macc.mux_in_pattern; + const bool &output_registered YS_MAYBE_UNUSED = st_ql_dsp_macc.output_registered; + Cell* &ff YS_MAYBE_UNUSED = st_ql_dsp_macc.ff; + Cell* _pmg_backup_ff = ff; + + index_5_key_type key; + std::get<0>(key) = mux_in_pattern ? port(mux, id_b_Y) : port(add, id_b_Y);; + std::get<1>(key) = port(add, add_ba); + auto cells_ptr = index_5.find(key); + + if (cells_ptr != index_5.end()) { + const vector &cells = cells_ptr->second; + for (int _pmg_idx = 0; _pmg_idx < GetSize(cells); _pmg_idx++) { + ff = std::get<0>(cells[_pmg_idx]); + if (blacklist_cells.count(ff)) continue; + if (!(nusers(port(ff, id_b_Q)) == (output_registered ? 3 : 2))) continue; + auto rollback_ptr = rollback_cache.insert(make_pair(std::get<0>(cells[_pmg_idx]), recursion)); + block_6(recursion+1); + if (rollback_ptr.second) + rollback_cache.erase(rollback_ptr.first); + if (rollback) { + if (rollback != recursion) { + ff = _pmg_backup_ff; + return; + } + rollback = 0; + } + } + } + + ff = nullptr; + ff = _pmg_backup_ff; + } + + // techlibs/quicklogic/ql_dsp_macc.pmg:75 + void block_6(int recursion YS_MAYBE_UNUSED) { + Cell* const &add YS_MAYBE_UNUSED = st_ql_dsp_macc.add; + const IdString &add_ba YS_MAYBE_UNUSED = st_ql_dsp_macc.add_ba; + Cell* const &ff YS_MAYBE_UNUSED = st_ql_dsp_macc.ff; + Cell* const &mul YS_MAYBE_UNUSED = st_ql_dsp_macc.mul; + Cell* const &mux YS_MAYBE_UNUSED = st_ql_dsp_macc.mux; + const IdString &mux_ab YS_MAYBE_UNUSED = st_ql_dsp_macc.mux_ab; + const bool &mux_in_pattern YS_MAYBE_UNUSED = st_ql_dsp_macc.mux_in_pattern; + const bool &output_registered YS_MAYBE_UNUSED = st_ql_dsp_macc.output_registered; + +#define reject do { goto rollback_label; } while(0) +#define accept do { accept_cnt++; on_accept(); if (rollback) goto rollback_label; } while(0) +#define finish do { rollback = -1; goto rollback_label; } while(0) +#define branch do { block_7(recursion+1); if (rollback) goto rollback_label; } while(0) +#define subpattern(pattern_name) do { block_subpattern_ql_dsp_macc_ ## pattern_name (recursion+1); if (rollback) goto rollback_label; } while(0) + accept; + + block_7(recursion+1); +#undef reject +#undef accept +#undef finish +#undef branch +#undef subpattern + +rollback_label: + YS_MAYBE_UNUSED; + } + + void block_7(int recursion YS_MAYBE_UNUSED) { + } +}; diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v b/yosys/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v new file mode 100644 index 00000000000..c3c3a2d6c52 --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v @@ -0,0 +1,74035 @@ +// **AUTOGENERATED FILE** **DO NOT EDIT** +// Generated by techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py at 2024-06-07 04:34:03.245851+00:00 +`timescale 1ns /10ps + +module TDP36K_BRAM_A_X1_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule