diff --git a/odin_ii/src/verilog/verilog_bison.y b/odin_ii/src/verilog/verilog_bison.y
index a4f373ffa25..1c782499138 100644
--- a/odin_ii/src/verilog/verilog_bison.y
+++ b/odin_ii/src/verilog/verilog_bison.y
@@ -52,6 +52,7 @@ int yylex(void);
 %define parse.error verbose
 
 %locations
+%expect 2
 
 %union{
 	char *id_name;
@@ -208,6 +209,8 @@ int yylex(void);
 %type <node> list_of_generate_block_items generate_item generate_block_item generate loop_generate_construct if_generate_construct 
 %type <node> case_generate_construct case_generate_item_list case_generate_items generate_block generate_localparam_declaration generate_defparam_declaration
 
+
+
 /* capture wether an operation is signed or not */
 %type <op> var_signedness