diff --git a/vtr_flow/arch/multi_die/README.md b/vtr_flow/arch/multi_die/README.md
new file mode 100644
index 00000000000..f47d733979f
--- /dev/null
+++ b/vtr_flow/arch/multi_die/README.md
@@ -0,0 +1,39 @@
+# 3D FPGA Architectures
+
+This directory contains architecture files for 3D FPGAs. The architectures are divided into three sub-directories:
+
+1. **koios_3d:**
+- Contains architecture files based on the [k6FracN10LB_mem20K_complexDSP_customSB_22nm](../COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml) architecture, utilized in Koios benchmarks.
+- Inside the architecture file, the fabric with multiple sizes based on the sector size is defined.
+- Routing resource and switch delays in this architecture are configured for 7 nm technology. The inter-die connection delay is 73 ps.
+- Detailed information on how these delays are obtained can be found in the paper "Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices," presented at FPT '23.
+- **Architectures:**
+   - `3d_full_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml`
+     - The inter-die connection is only from output pins, with all output pins connected to the channel on the same die and the other.
+     - Inside the architecture file, the fabric with multiple sizes based on the sector size is defined.
+   - `3d_limited_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml`
+   - The inter-die connection is only from output pins, with all OPINs of BRAMs and DSPs connected to the channels on the same die and the other die. 
+   - Only 60% of the OPINs of CLBs are connected to the channels on the other die and all of them can get connected to the channels on the same die.
+
+2. **stratixiv_3d:**
+   - Contains architecture files based on a [StratixIV-like](../titan/stratixiv_arch.timing.xml) architecture.
+   - Delays of switches and routing resources are similar to those reported in the capture of the StratixIV architecture.
+   - For the inter-die connection, we multiply the L4 wire delay of SIV by the ratio of the inter-die connection delay to the L4 wire delay of the Koios_3d benchmark.
+   - **Architectures:**
+     - `3d_10x10_noc_base_stratixiv_up.xml`
+       - A 10x10 NoC mech is put on the base die.
+       - The upper die is SIV-like FPGA fabric.
+     - `3d_full_inter_die_stratixiv_arch.timing.xml`
+       - The architecture has two dice.
+       - Both dice are SIV-like FPGA fabric.
+       - All pins can cross die.
+     - `3d_full_OPIN_inter_die_stratixiv_arch.timing.xml`
+       - The architecture has two dice.
+       - Both dice are SIV-like FPGA fabric.
+       - Only OPINs can cross die.
+
+3. **simple_arch:**
+   - Simple architectures primarily used for quick testing in the flow.
+   - The inter-die delay of architectures in this file is considered to be zero.
+   - Contains two dice and both have the simple fabric.
+   - All pins can cross die.
diff --git a/vtr_flow/arch/multi_die/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml b/vtr_flow/arch/multi_die/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
deleted file mode 100644
index a02b9e52313..00000000000
--- a/vtr_flow/arch/multi_die/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
+++ /dev/null
@@ -1,3272 +0,0 @@
-<!--
-    This is the architecture file for a modern Intel FPGA. The blocks (logic, RAM, DSP)
-    are Agilex-like, but the routing architecture is similar to Stratix IV. It is based
-    off the Stratix-10-like Architecture discussed in [1], the Agilex-like Architecture
-    mentioned in [6] and Stratix-IV-like Architecture mentioned in [5].
-
-    The delays and areas of various components in this arch come from COFFE [2]
-    runs using a 22nm technology node [3].
-
-    ##############################
-    Parameters
-    ##############################
-    Parameter | Value | Definition
-    __________|_______|______________________________
-    N         |    10 | Number of BLEs per cluster
-    W         |   300 | Channel width
-    L         |  4,16 | Wire segment length
-    I         |    60 | Number of cluster inputs
-    O         |    40 | Number of cluster outputs
-    K         |     6 | LUT size
-    Fs        |     3 | Switch block flexibility
-    Fcin      |  0.15 | Cluster input flexibility
-    Fcout     |   0.1 | Cluster output flexibility
-    Fclocal   |   0.5 | Local input crossbar population
-
-    ##############################
-    Logic Cluster
-    ##############################
-    This architecture has 10 ALMs (or FLEs: Fracturable Logic Elements) per Logic Cluster
-    (or LAB or CLB), where each ALM is a 6-LUT fracturable into
-    two 5-LUTs. The ALM has 8 inputs and 4 optionally registered outputs.The two 5-LUTs should
-    share at least two inputs. Each two ALM outputs are logically equivalent, which means any
-    output signal that can reach ALM.out[0] can reach ALM.out[1] and the same thing for
-    ALM.out[2] and ALM.out[3]. The ALMs in this architecture have an arithmetic mode
-    where each 5-LUT is fractured into two 4-LUTs, resulting in a total of four 4-LUTs and two
-    bits of addition per ALM. This architecture has a single carry chain that spans the 10 ALMs
-    in the LAB.
-
-    The LAB (or Logic Cluster or CLB) has 60 inputs and 40 outputs. Two outputs of each ALM are fed 
-    to the right and left LAB using direct links and are also fed back to the LAB as feedback connections 
-    sharing the 60 input ports with the signals coming from the routing channels.
-
-    The LAB has a 50% sparsely populated input crossbar.
-    
-    ##############################
-    DSP Slice
-    ##############################
-    This architecture has a DSP block that supports the following modes:
-
-    Fixed point modes:
-    _________________
-    1. 27x27 fixed point multiplier (multiply)
-    2. 27x27 fixed point mac (mac_int_27x27)
-    3. Two 18x19 fixed point multipliers (multiply)
-    4. Two 18x19 fixed point macs (mac_int_18x19)
-    5. Four 9x9 fixed point multipliers (multiply)
-    6. Four 9x9 fixed point macs (mac_int_9x9)
-    7. 27x27 plus 64 mode (mult_add_mode_27_27_64/mult_add_int_27x27). 27 * 27 + 64 -> 64. result = ax * ay + bx + chainin. chainout = result 
-    8. 18x19 sum-of-2 mode (sop_2_mode/int_sop_2) result = (bx * by) + (ax * ay) + chainin. chainout = result    
-    9. 18x19 plus 36 mode (mult_add_mode_18_19_36/mult_add_int_18x19). 18 * 19 + 36 -> 64. result = ax * ay + bx + chainin. chainout = result 
-    10. 9x9 sum-of-4 mode (sop_4_mode/int_sop_4) result = (dx * dy) + (cx * cy) + (bx * by) + (ax * ay) + chainin. chainout = result 
-    11. 9x9 sum-of-4 accum mode (sop_4_accum_mode/int_sop_accum_4) result = (dx * dy) + (cx * cy) + (bx * by) + (ax * ay) + chainin + accumulator. chainout = result 
-
-    Floating point modes:
-    ____________________
-
-    IMPORTANT:
-    The precisions supported are IEEE floating point 32-bit, IEEE floating point 16-bit and
-    Brain floating point (BF16). In the 16-bit mode descriptions, wherever "fp16" is used, it
-    refers to either IEEE floating point 16-bit or BF16. There are mode bits on the DSP slice
-    that can be used to differentiate between them. Doing this saves the effort of explicitly
-    specifying all the 16-bit modes twice in this file. 
-    Since the goal is architectural exploration and not functional simulation, the mode bits 
-    can be specified to any random value while instantiating the DSP slice in a Verilog benchmark.
-
-    1A. One fp32 multiplier (mult_fp_32)
-    1B. One fp32 multiplier, clocked (mult_fp_clk_32)
-    2A. One fp32 adder/subtractor (addition_fp_32)
-    2B. One fp32 adder/subtractor, clocked (addition_fp_clk_32)
-    3. One fp32 mac (mac_fp_32)
-    4A. Two fp16 multipliers (mult_fp_16)
-    4B. Two fp16 multipliers, clocked (mult_fp_clk_16)
-    5A. Two fp16 adders/subtractors (addition_fp_16)
-    5B. Two fp16 adders/subtractors, clocked (addition_fp_clk_16)
-    6. Two fp16 macs (mac_fp_16)
-    7. floating point fp16 sum-of-products mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b. chainout = third_inp or result) (fp16_sum_of_products_mode/fp16_mult_add)
-    8. floating point fp16 sum-of-2 mult mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b + fp32 chainin or third inp. chainout = third_inp or result) (fp16_sum_of_products_2_mult_mode/fp16_sop2_mult)
-    9. floating point fp16 sum-of-2 accum mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b + accumulator. chainout = result) (fp16_sum_of_products_2_accum_mode/fp16_sop2_accum)
-    10. floating point fp16 mult, fp32 add mode (chainout = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b. result = chainin + third_inp) (fp16_mult_fp32_add/fp16_mult_fp32_add)
-    11. floating point fp16 mult, fp32 accum mode (chainout = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b. result = third_inp + accumulator) (fp16_mult_fp32_accum/fp16_mult_fp32_accum)
-    12. floating point fp32 mult_then_add mode (result = fp32_mult_a * fp32_mult_b + chainin. chainout = third_inp or result) (fp32_mult_then_add/fp32_mult_then_add)
-    13. floating point fp32 mult_add mode (chainout = fp32_mult_a * fp32_mult_b. chainout = third_inp + chainin) (fp32_mult_add/fp32_mult_add)
-
-    The DSP block was designed in Verilog and COFFE's [2] hybrid flow was used to generate
-    area and delay results. The standard cell library used was Cadence GPDK 45nm (gsclib045_svt_v4.4)
-    and area/delay scaling euqations from [4] were used.
-
-    A 50% sparsely populated input crossbar was added to the DSP block but is commented out.
-    It was leading to a failure in in VPR. See the discussion on this commit: 
-    https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ea7acf1582ece35e892c26b756aa302d2e12ddb2
-
-    Once this is fixed, the input crossbar code can be enabled.
-
-    ##############################
-    Memory Blocks
-    ##############################
-    The architecture also has a 20Kb memory blocks (or M20k or BRAM) that has true and simple dual port modes. 
-    In simple dual port mode the memory can be configured in the following modes: 512x40, 1024x20 and 2048x10,
-    while in true dual port mode it can be configured as: 1024x20 and 2048x10.
-
-    The BRAM has registered inputs and outputs. See details on how the delays for this block were 
-    obtained, in the comments before the specification of the BRAM primitive, towards the end of this file.
-
-    The BRAM doesn't have an input crossbar. Adding an input crossbar was leading to a 
-    seg fault in VPR, likely because of https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1475
-
-    Once this is fixed, an input crossbar can be added. The input crossbar delay from COFFE was: 29.47ps
-
-    ##############################
-    Routing/Interconnect
-    ##############################
-    The routing channel width is 300. Note that the channel width isn't specified directly in this arch file. 
-    Switch pattern calculations assume that value. During experiments, channel width can be specified using 
-    the command line switch `route_chan_width`.
-    The architecture uses unidirectional routing with wire segments of length 4 (260 out of 300 wires) and 
-    length 16 (40 out of 300 wires). The length 16 wires do not directly connect to block pins and are only 
-    accessible from the length 4 wires. Switches appear after every 4 blocks on the length 16 wires. 
-    The switch blocks use a custom switching pattern based on the Stratix-IV-like architecture used in the 
-    Titan flow [5]. 
-
-    ##############################
-    I/Os
-    ##############################
-    I/O pads are arranged along the perimeter of the FPGA. No area values provided for the I/Os.
-
-    ##############################
-    Comments on similarities and differences with Intel FPGA architecture.
-    ##############################
-    The main parameters of the logic blocks, DSPs and RAMs are similar to Intel FPGAs. But here are
-    some important points:
-    1. The DSP slice supports lower precision modes - int8 (actually 9x9) and 16-bit floating point
-       (IEEE half-precision and bfloat16). These modes are present in Intel Agilex FPGA DSPs.
-    2. DSPs are chained in vertical direction (chainin-chainout connections for output cascading
-       and scanin-scanout connections for input cascading). This is a common feature
-       in modern FPGAs.
-    3. There are no registers on the interconnect/routing wires in this architecture. That is a main
-       feature in the Stratix10 and Agilex families of Intel FPGA (it's called HyperFlex by Intel).
-    4. The architecture doesn't have sectors. All blocks are laid out in columns on the entire chip.
-       Most modern Intel FPGAs have sector based layout.
-    5. The IOs are on the perimeter, instead of being arranged in columns. Modern FPGAs arrange I/Os in
-       columns.
-    6. The routing architecture is similar to Stratix IV. There are wire segments of L=4 
-       and L=16. And a custom switch pattern (not a standard wilton switch) is used. 
-
-    [1] M. Eldafrawy, A. Boutros, S. Yazdanshenas, and V. Betz, "FPGA Logic Block Architectures for
-        Efficient Deep Learning Inference" in ACM TRETS, 2020
-    [2] S. Yazdanshenas, and V. Betz, "COFFE 2: Automatic Modelling and Optimization of
-        Complex and Heterogeneous FPGA Architectures" in ACM TRETS, 2019. 
-    [3] PTM High Performance 22nm Metal Gate / High-K / Strained-Si 22NM_BULK_HP, from http://ptm.asu.edu/
-        See: https://github.com/vaughnbetz/COFFE/blob/master/spice_models/ptm_22nm_bulk_hp.l
-    [4] A. Stillmaker and B. Baas, "Scaling equations for the accurate prediction of CMOS device 
-        performance from 180 nm to 7 nm" in Integration, the VLSI Journal (2017)
-    [5] K. E. Murray et al., “Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap between 
-        Academic and Commercial CAD,” TRETS 2015.
-    [6] A. Arora et al., "Tensor Slices to the Rescue: Supercharging ML Acceleration on FPGAs", ISFPGA 2020.
--->
-
-<architecture>
-  <!-- 
-         ODIN II specific config begins 
-         Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-         ".model [type_of_block]") that this architecture supports.
-
-         Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-         already special structures in blif (.names, .input, .output, and .latch) 
-         that describe them.
-    -->
-  <models>
-    <model name="single_port_ram">
-      <input_ports>
-        <port name="we" clock="clk" combinational_sink_ports="out"/>
-        <!-- control -->
-        <port name="addr" clock="clk" combinational_sink_ports="out"/>
-        <!-- address lines -->
-        <port name="data" clock="clk" combinational_sink_ports="out"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="clk" is_clock="1"/>
-        <!-- memories are often clocked -->
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-      </output_ports>
-    </model>
-    <model name="dual_port_ram">
-      <input_ports>
-        <port name="we1" clock="clk" combinational_sink_ports="out1"/>
-        <!-- write enable -->
-        <port name="we2" clock="clk" combinational_sink_ports="out2"/>
-        <!-- write enable -->
-        <port name="addr1" clock="clk" combinational_sink_ports="out1"/>
-        <!-- address lines -->
-        <port name="addr2" clock="clk" combinational_sink_ports="out2"/>
-        <!-- address lines -->
-        <port name="data1" clock="clk" combinational_sink_ports="out1"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="data2" clock="clk" combinational_sink_ports="out2"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="clk" is_clock="1"/>
-        <!-- memories are often clocked -->
-      </input_ports>
-      <output_ports>
-        <port name="out1" clock="clk"/>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-        <port name="out2" clock="clk"/>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-      </output_ports>
-    </model>
-    <!-- Used inside DSPs. 
-         Fixed point multiplication.
-         ODIN infers these when * sign appears in RTL. -->
-    <model name="multiply">
-      <input_ports>
-        <port name="a" combinational_sink_ports="out"/>
-        <port name="b" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out"/>
-      </output_ports>
-    </model>
-    <!-- Used inside DSPs. 
-         Floating point multiplication. -->
-    <model name="mult_fp_16">
-      <input_ports>
-        <port name="a" combinational_sink_ports="out"/>
-        <port name="b" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out"/>
-      </output_ports>
-    </model>   
-    <model name="mult_fp_32">
-      <input_ports>
-        <port name="a" combinational_sink_ports="out"/>
-        <port name="b" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out"/>
-      </output_ports>
-    </model>   
-    <model name="mult_fp_clk_16">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <model name="mult_fp_clk_32">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <!-- Only used inside CLBs for 1-bit adder.
-         ODIN infers these when + sign appears in RTL.
-         Can't use this inside DSP slice
-         because ODIN gets confused and starts to connect multi
-         bit adders and single bit adders in different PBs -->
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="cout sumout"/>
-        <port name="b" combinational_sink_ports="cout sumout"/>
-        <port name="cin" combinational_sink_ports="cout sumout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- Multi bit floating point adder inside DSP slices -->
-    <model name="addition_fp_16">
-      <input_ports>
-        <port name="a" combinational_sink_ports="out"/>
-        <port name="b" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out"/>
-      </output_ports>
-    </model>
-    <model name="addition_fp_32">
-      <input_ports>
-        <port name="a" combinational_sink_ports="out"/>
-        <port name="b" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out"/>
-      </output_ports>
-    </model>
-    <model name="addition_fp_clk_16">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <model name="addition_fp_clk_32">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="int_sop_2">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ax" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ay" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="by" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="mult_add_int_27x27">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="ax" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="ay" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="bx" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="scanin" clock="clk" combinational_sink_ports="result scanout chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-        <port name="scanout"/>
-      </output_ports>
-    </model>
-    <model name="mult_add_int_18x19">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="ax" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="ay" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="bx" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="scanin" clock="clk" combinational_sink_ports="result scanout chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-        <port name="scanout"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="int_sop_4">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ax" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ay" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="by" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="cx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="cy" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="dx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="dy" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="int_sop_accum_4">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ax" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ay" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="by" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="cx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="cy" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="dx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="dy" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>
-    <!-- Floating point MAC inside DSP slices -->
-    <model name="mac_fp_16">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="out"/>
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <model name="mac_fp_32">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="out"/>
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <!-- Fixed point MAC inside DSP slices -->
-    <model name="mac_int_27x27">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="out"/>
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <model name="mac_int_18x19">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="out"/>
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <model name="mac_int_9x9">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="out"/>
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="fp16_mult_add">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model> 
-    <!--A mode in DSP slice-->
-    <model name="fp16_sop2_mult">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model> 
-    <!--A mode in DSP slice-->
-    <model name="fp16_sop2_accum">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_b" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="fp16_mult_fp32_add">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>    
-    <!--A mode in DSP slice-->
-    <model name="fp16_mult_fp32_accum">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="fp32_mult_add">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model> 
-    <!--A mode in DSP slice-->
-    <model name="fp32_mult_then_add">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model> 
-  </models>
-  <tiles>
-    <tile name="io" area="0">
-      <sub_tile name="io" capacity="8">
-        <equivalent_sites>
-          <site pb_type="io" pin_mapping="direct"/>
-        </equivalent_sites>
-        <input name="outpad" num_pins="1"/>
-        <output name="inpad" num_pins="1"/>
-        <clock name="clock" num_pins="1"/>
-        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-        <pinlocations pattern="custom">
-          <loc side="left" layer_offset="1">io.outpad io.inpad io.clock</loc>
-          <loc side="top" layer_offset ="1">io.outpad io.inpad io.clock</loc>
-          <loc side="right" layer_offset="1">io.outpad io.inpad io.clock</loc>
-          <loc side="bottom" layer_offset="1">io.outpad io.inpad io.clock</loc>
-        </pinlocations>
-      </sub_tile>
-    </tile>
-    <tile name="clb" height="1" width="1" area="27905">
-      <sub_tile name="clb">
-        <equivalent_sites>
-          <site pb_type="clb" pin_mapping="direct"/>
-        </equivalent_sites>
-        <input name="I1" num_pins="15" equivalent="full"/>
-        <input name="I2" num_pins="15" equivalent="full"/>
-        <input name="I3" num_pins="15" equivalent="full"/>
-        <input name="I4" num_pins="15" equivalent="full"/>
-        <input name="cin" num_pins="1"/>
-        <output name="O" num_pins="40" equivalent="none"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-          <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-          <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-          <!-- clock pins do not connect to local routing -->
-          <fc_override fc_type="frac" fc_val="0" port_name="clk"/>
-        </fc>
-        <pinlocations pattern="custom">
-          <loc side="top" layer_offset = "1"> clb.I1[0] clb.I1[4] clb.I1[8] clb.I1[12] clb.I2[1] clb.I2[5] clb.I2[9] clb.I2[13] clb.I3[2] clb.I3[6] clb.I3[10] clb.I3[14] clb.I4[3] clb.I4[7] clb.I4[11] clb.cin clb.O[3] clb.O[7] clb.O[11] clb.O[15] clb.O[19] clb.O[23] clb.O[27] clb.O[31] clb.O[35] clb.O[39]  </loc>
-          <loc side="right" layer_offset="1"> clb.I1[1] clb.I1[5] clb.I1[9] clb.I1[13] clb.I2[2] clb.I2[6] clb.I2[10] clb.I2[14] clb.I3[3] clb.I3[7] clb.I3[11] clb.I4[0] clb.I4[4] clb.I4[8] clb.I4[12] clb.O[0] clb.O[4] clb.O[8] clb.O[12] clb.O[16] clb.O[20] clb.O[24] clb.O[28] clb.O[32] clb.O[36] clb.cout  </loc>
-          <loc side="bottom" layer_offset="1"> clb.I1[2] clb.I1[6] clb.I1[10] clb.I1[14] clb.I2[3] clb.I2[7] clb.I2[11] clb.I3[0] clb.I3[4] clb.I3[8] clb.I3[12] clb.I4[1] clb.I4[5] clb.I4[9] clb.I4[13] clb.O[1] clb.O[5] clb.O[9] clb.O[13] clb.O[17] clb.O[21] clb.O[25] clb.O[29] clb.O[33] clb.O[37] clb.clk</loc>
-          <loc side="left" layer_offset="1"> clb.I1[3] clb.I1[7] clb.I1[11] clb.I2[0] clb.I2[4] clb.I2[8] clb.I2[12] clb.I3[1] clb.I3[5] clb.I3[9] clb.I3[13] clb.I4[2] clb.I4[6] clb.I4[10] clb.I4[14] clb.O[2] clb.O[6] clb.O[10] clb.O[14] clb.O[18] clb.O[22] clb.O[26] clb.O[30] clb.O[34] clb.O[38] </loc>
-        </pinlocations>
-      </sub_tile>
-    </tile>
-    <tile name="dsp_top" height="4" width="1" area="253779">
-      <sub_tile name="dsp_top">
-        <equivalent_sites>
-          <site pb_type="dsp_top" pin_mapping="direct"/>
-        </equivalent_sites>
-        <input name="reset" num_pins="1" is_non_clock_global="true"/>
-        <input name="dsp_I1" num_pins="64" />
-        <input name="dsp_I2" num_pins="64" />
-        <input name="chainin" num_pins="64"/>
-        <input name="scanin" num_pins="27"/>
-        <output name="result" num_pins="74"/>
-        <output name="chainout" num_pins="64"/>
-        <output name="scanout" num_pins="27"/>
-        <clock name="clk" num_pins="1"/>
-        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-          <!-- clock pins and chain ports do not connect to local routing -->
-          <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
-          <fc_override port_name="chainin" fc_type="frac" fc_val="0"/>
-          <fc_override port_name="chainout" fc_type="frac" fc_val="0"/>
-          <fc_override port_name="scanin" fc_type="frac" fc_val="0"/>
-          <fc_override port_name="scanout" fc_type="frac" fc_val="0"/>
-        </fc>
-        <pinlocations pattern="custom">
-        	  <loc side="left" yoffset="0" layer_offset="1">dsp_top.dsp_I1[31:0]</loc>
-	          <loc side="right" yoffset="1" layer_offset="1">dsp_top.dsp_I1[63:32]</loc>
-	          <loc side="left" yoffset="2" layer_offset="1">dsp_top.dsp_I2[31:0]</loc>
-	          <loc side="right" yoffset="3" layer_offset="1">dsp_top.dsp_I2[63:32]</loc>
-	          <loc side="top" layer_offset="1">dsp_top.chainin dsp_top.scanin</loc>
-	          <loc side="bottom" layer_offset="1">dsp_top.chainout dsp_top.scanout</loc>
-	          <loc side="right" yoffset="0" layer_offset="1">dsp_top.result[17:0] dsp_top.clk</loc>
-	          <loc side="left" yoffset="1" layer_offset="1">dsp_top.result[36:18]</loc>
-	          <loc side="right" yoffset="2" layer_offset="1">dsp_top.result[55:37] </loc>
-	          <loc side="left" yoffset="3" layer_offset="1">dsp_top.result[73:56] dsp_top.reset</loc>
-        </pinlocations>
-      </sub_tile>
-    </tile>
-    <tile name="memory" height="2" width="1" area="137668">
-      <sub_tile name="memory">
-        <equivalent_sites>
-          <site pb_type="memory" pin_mapping="direct"/>
-        </equivalent_sites>
-      <input name="addr1" num_pins="11"/>
-      <input name="addr2" num_pins="11"/>
-      <input name="data" num_pins="40"/>
-      <input name="we1" num_pins="1"/>
-      <input name="we2" num_pins="1"/>
-      <output name="out" num_pins="40"/>
-      <clock name="clk" num_pins="1"/>
-        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-          <fc_override fc_type="frac" fc_val="0" port_name="clk"/>
-        </fc>  
-        <pinlocations pattern="custom">
-          <loc side="top" layer_offset="1"> memory.addr1[0] memory.addr1[8] memory.addr2[5] memory.data[2] memory.data[10] memory.data[18] memory.data[26] memory.data[34] memory.out[0] memory.out[8] memory.out[16] memory.out[24] memory.out[32] memory.clk </loc>
-          <loc side="top" layer_offset="1" yoffset="1"> memory.addr1[1] memory.addr1[9] memory.addr2[6] memory.data[3] memory.data[11] memory.data[19] memory.data[27] memory.data[35] memory.out[1] memory.out[9] memory.out[17] memory.out[25] memory.out[33] </loc>
-          <loc side="right" layer_offset="1"> memory.addr1[2] memory.addr1[10] memory.addr2[7] memory.data[4] memory.data[12] memory.data[20] memory.data[28] memory.data[36] memory.out[2] memory.out[10] memory.out[18] memory.out[26] memory.out[34] </loc>
-          <loc side="right" layer_offset="1" yoffset="1"> memory.addr1[3] memory.addr2[0] memory.addr2[8] memory.data[5] memory.data[13] memory.data[21] memory.data[29] memory.data[37] memory.out[3] memory.out[11] memory.out[19] memory.out[27] memory.out[35] </loc>
-          <loc side="bottom" layer_offset="1"> memory.addr1[4] memory.addr2[1] memory.addr2[9] memory.data[6] memory.data[14] memory.data[22] memory.data[30] memory.data[38] memory.out[4] memory.out[12] memory.out[20] memory.out[28] memory.out[36] </loc>
-          <loc side="bottom" layer_offset="1" yoffset="1"> memory.addr1[5] memory.addr2[2] memory.addr2[10] memory.data[7] memory.data[15] memory.data[23] memory.data[31] memory.data[39] memory.out[5] memory.out[13] memory.out[21] memory.out[29] memory.out[37] </loc>
-          <loc side="left" layer_offset="1"> memory.addr1[6] memory.addr2[3] memory.data[0] memory.data[8] memory.data[16] memory.data[24] memory.data[32] memory.we1 memory.out[6] memory.out[14] memory.out[22] memory.out[30] memory.out[38] </loc>
-          <loc side="left" layer_offset="1" yoffset="1"> memory.addr1[7] memory.addr2[4] memory.data[1] memory.data[9] memory.data[17] memory.data[25] memory.data[33] memory.we2 memory.out[7] memory.out[15] memory.out[23] memory.out[31] memory.out[39] </loc>
-        </pinlocations>
-      </sub_tile>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <layout>
-    <!-- Physical descriptions begin -->
-    <auto_layout aspect_ratio="1.0">
-      <layer die="0">
-        <perimeter type="io" priority="101"/>
-        <corners type="EMPTY" priority="102"/>
-        <fill type="clb" priority="10"/>
-        <col type="dsp_top" startx="6" starty="1" repeatx="16" priority="20"/>
-        <col type="memory" startx="2" starty="1" repeatx="16" priority="20"/>
-      </layer>
-      <layer die="1">
-        <perimeter type="io" priority="101"/>
-        <corners type="EMPTY" priority="102"/>
-        <fill type="clb" priority="10"/>
-        <col type="dsp_top" startx="6" starty="1" repeatx="16" priority="20"/>
-        <col type="memory" startx="2" starty="1" repeatx="16" priority="20"/>
-      </layer>
-    </auto_layout>
-    <!--
-    <fixed_layout name="mylayout" width="178" height="82">
-      <perimeter type="io" priority="101"/>
-      <corners type="EMPTY" priority="102"/>
-      
-      <col type="dsp_top"  startx="1"  starty="1"  priority="100"/>
-      <col type="clb"  startx="2"  starty="1"  priority="100"/>
-      <col type="clb"  startx="3"  starty="1"  priority="100"/>
-      <col type="dsp_top"  startx="4"  starty="1"  priority="100"/>
-      <col type="clb"  startx="5"  starty="1"  priority="100"/>
-      <col type="clb"  startx="6"  starty="1"  priority="100"/>
-      <col type="dsp_top"  startx="7"  starty="1"  priority="100"/>
-      <col type="clb"  startx="8"  starty="1"  priority="100"/>
-      <col type="clb"  startx="9"  starty="1"  priority="100"/>
-      <col type="dsp_top"  startx="10"  starty="1"  priority="100"/>
-      <col type="clb"  startx="11"  starty="1"  priority="100"/>
-      <col type="clb"  startx="12"  starty="1"  priority="100"/>
-      <col type="dsp_top"  startx="13"  starty="1"  priority="100"/>
-
-      <region type="clb" startx="14"   endx="88"   starty="1" incrx="5"  priority="20"/>
-      <region type="clb" startx="15"   endx="88"   starty="1" incrx="5"  priority="20"/>
-      <region type="clb" startx="16"   endx="88"   starty="1" incrx="5"  priority="20"/>
-      <region type="dsp_top" startx="17"   endx="88"   starty="1" incrx="5"  priority="20"/>
-      <region type="memory" startx="18"   endx="88"   starty="1" incrx="5"  priority="20"/>
-
-      <region type="memory" startx="89"   endx="163"   starty="1" incrx="5"  priority="20"/>
-      <region type="dsp_top" startx="90"   endx="163"   starty="1" incrx="5"  priority="20"/>
-      <region type="clb" startx="91"   endx="163"   starty="1" incrx="5"  priority="20"/>
-      <region type="clb" startx="92"   endx="163"   starty="1" incrx="5"  priority="20"/>
-      <region type="clb" startx="93"   endx="163"   starty="1" incrx="5"  priority="20"/>
-
-      <col type="dsp_top"  startx="164"  starty="1"  priority="20"/>
-      <col type="clb"  startx="165"  starty="1"  priority="1"/>
-      <col type="clb"  startx="166"  starty="1"  priority="1"/>
-      <col type="dsp_top"  startx="167"  starty="1"  priority="20"/>
-      <col type="clb"  startx="168"  starty="1"  priority="1"/>
-      <col type="clb"  startx="169"  starty="1"  priority="1"/>
-      <col type="dsp_top"  startx="170"  starty="1"  priority="20"/>
-      <col type="clb"  startx="171"  starty="1"  priority="1"/>
-      <col type="clb"  startx="172"  starty="1"  priority="1"/>
-      <col type="dsp_top"  startx="173"  starty="1"  priority="20"/>
-      <col type="clb"  startx="174"  starty="1"  priority="1"/>
-      <col type="clb"  startx="175"  starty="1"  priority="1"/>
-      <col type="dsp_top"  startx="176"  starty="1"  priority="20"/>
-    </fixed_layout> 
-    -->
-  </layout>
-  <device>
-    <sizing R_minW_nmos="13090" R_minW_pmos="19086.83"/>
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="custom"/>
-    <connection_block input_switch_name="ipin_cblock" input_inter_die_switch_name="die_connection"/>
-  </device>
-  <switchlist>
-    <switch type="mux" name="L4_driver" R="0.0" Cin="0.0" Cout="0.0" Tdel="207.9e-12" mux_trans_size="2.377" buf_size="35.69"/>
-    <!-- Delay of L16 driver is scaled from L4 by a factor of 1.5x (based on numbers from the Titan Stratix IV architecture file)
-	 Area numbers will not be totally accurate because of the same buf_size -->
-    <switch type="mux" name="L16_driver" R="0.0" Cin="0.0" Cout="0.0" Tdel="312.9e-12" mux_trans_size="2.377" buf_size="35.69"/> 
-    <switch type="mux" name="ipin_cblock" R="0.0" Cout="0.0" Cin="0.0" Tdel="130e-12" mux_trans_size="1.508" buf_size="11.71"/>
-    <switch type="mux" name="die_connection" R="0.0" Cout="0.0" Cin="0.0" Tdel="130e-12" mux_trans_size="1.508" buf_size="11.71"/>
-  </switchlist>
-  <segmentlist>
-    <segment name="L4" freq="260" length="4" type="unidir" Rmetal="0.0" Cmetal="0.0">
-      <mux name="L4_driver"/>
-      <mux_inter_die name="L4_driver"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-    <segment name="L16" freq="40" length="16" type="unidir" Rmetal="0.0" Cmetal="0.0">
-      <mux name="L16_driver"/>
-      <mux_inter_die name="L16_driver"/>
-      <!-- Vias from the top of the metal stack (global layers, where the long wires are 
-           implemented) down to the middle/bottom of the metal stack (semi-global layers, 
-           where the short wires are implemented) are expensive and restrictive.
-           As a result Startix IV only places long wire switch blocks every 4 LABs -->
-      <sb type="pattern">1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1</sb>
-      <!-- For the same reasons, long wires do not connect to block pins in Stratix IV -->
-      <cb type="pattern">0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <!-- Direct connect from one LAB to the LAB directly below it (carry chain) -->
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-    <!-- Direct connect from one DSP to the DSP directly below it -->
-    <direct name="dsp_out_chain" from_pin="dsp_top.chainout" from_side="bottom" to_pin="dsp_top.chainin" to_side="top" x_offset="0" y_offset="-4" z_offset="0"/>
-    <direct name="dsp_in_chain" from_pin="dsp_top.scanout" from_side="bottom" to_pin="dsp_top.scanin" to_side="top" x_offset="0" y_offset="-4" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <pb_type name="clb">
-      <input name="I1" num_pins="15" equivalent="full"/>
-      <input name="I2" num_pins="15" equivalent="full"/>
-      <input name="I3" num_pins="15" equivalent="full"/>
-      <input name="I4" num_pins="15" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="40" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <pb_type name="lab" num_pb="1">
-        <input name="I1" num_pins="15"/>
-        <input name="I2" num_pins="15"/>
-        <input name="I3" num_pins="15"/>
-        <input name="I4" num_pins="15"/>
-        <input name="cin" num_pins="1"/>
-        <output name="O" num_pins="40"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Describe fracturable logic element.  
-                 Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-                 The outputs of the fracturable logic element can be optionally registered
-            -->
-        <pb_type name="fle" num_pb="10">
-          <input name="in" num_pins="8"/>
-          <input name="cin" num_pins="1"/>
-          <output name="out" num_pins="4"/>
-          <output name="cout" num_pins="1"/>
-          <clock name="clk" num_pins="1"/>
-          <!-- 
-                    The ALM inputs are as follows:
-                            A -> fle[0]
-                            B -> fle[1]
-                            C -> fle[2]
-                            D -> fle[3]
-                            E -> fle[4]
-                            F -> fle[5]
-                            G -> fle[6]
-                            H -> fle[7]
-              -->
-          <mode name="n2_lut5">
-            <pb_type name="ble5" num_pb="2">
-              <input name="in" num_pins="5"/>
-              <input name="cin" num_pins="1"/>
-              <output name="out" num_pins="2"/>
-              <output name="cout" num_pins="1"/>
-              <clock name="clk" num_pins="1"/>
-              <mode name="blut5">
-                <pb_type name="flut5" num_pb="1">
-                  <input name="in" num_pins="5"/>
-                  <output name="out" num_pins="2"/>
-                  <clock name="clk" num_pins="1"/>
-                  <!-- Regular LUT mode -->
-                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-                    <input name="in" num_pins="5" port_class="lut_in"/>
-                    <output name="out" num_pins="1" port_class="lut_out"/>
-                    <!-- LUT timing using delay matrix -->
-                    <!-- These are the physical delay inputs on a Stratix 10 LUT but because VPR cannot do LUT rebalancing,
-                             we instead take the average of these numbers to get more stable results
-                             note that those are the same delays for inputs A - E as the ones used for the 6-LUT, however, we have 
-                             subtracted the delay of the last mux stage to get the delay of inputs A - E till the 5-LUT output
-                             210.96e-12
-                             206.85e-12
-                             143.46e-12
-                             136.94e-12
-                             68.12e-12
-                          -->
-                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                            153.27e-12
-                            153.27e-12
-                            153.27e-12
-                            153.27e-12
-                            153.27e-12
-                        </delay_matrix>
-                  </pb_type>
-                  <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-                    <input name="D" num_pins="1" port_class="D"/>
-                    <output name="Q" num_pins="1" port_class="Q"/>
-                    <clock name="clk" num_pins="1" port_class="clock"/>
-                    <T_setup value="18.91e-12" port="ff.D" clock="clk"/>
-                    <T_clock_to_Q max="60.32e-12" port="ff.Q" clock="clk"/>
-                  </pb_type>
-                  <interconnect>
-                    <direct name="lut5_in" input="flut5.in" output="lut5.in"/>
-                    <direct name="reg_in" input="flut5.in[0]" output="ff[0].D"/>
-                    <direct name="lut5_ff" input="lut5.out" output="ff[1].D">
-                      <delay_constant max="18.96e-12" in_port="lut5.out" out_port="ff[1].D"/>
-                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff[1].D"/>
-                    </direct>
-                    <complete name="clock" input="flut5.clk" output="ff.clk"/>
-                    <complete name="out_mux" input="ff.Q lut5.out" output="flut5.out">
-                      <delay_constant max="39.85e-12" in_port="lut5.out" out_port="flut5.out"/>
-                      <delay_constant max="39.85e-12" in_port="ff.Q" out_port="flut5.out"/>
-                    </complete>
-                  </interconnect>
-                </pb_type>
-                <interconnect>
-                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
-                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
-                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
-                </interconnect>
-              </mode>
-              <mode name="arithmetic">
-                <pb_type name="arithmetic" num_pb="1">
-                  <input name="in" num_pins="4"/>
-                  <input name="cin" num_pins="1"/>
-                  <output name="out" num_pins="2"/>
-                  <output name="cout" num_pins="1"/>
-                  <clock name="clk" num_pins="1"/>
-                  <!-- Special dual-LUT mode that drives adder only -->
-                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-                    <input name="in" num_pins="4" port_class="lut_in"/>
-                    <output name="out" num_pins="1" port_class="lut_out"/>
-                    <!-- LUT timing using delay matrix -->
-                    <!-- These are the physical delay inputs on a Stratix 10 LUT but because VPR cannot do LUT rebalancing,
-                           we instead take the average of these numbers to get more stable results
-                           note that those are the same delays for inputs A - E as the ones used for the 6-LUT, however, we have 
-                           subtracted the delay of the last mux stage to get the delay of inputs A - E till the 5-LUT output
-                             168.12e-12
-                             164.02e-12
-                             100.63e-12
-                             94.11e-12
-                          -->
-                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                            131.72e-12
-                            131.72e-12
-                            131.72e-12
-                            131.72e-12
-                        </delay_matrix>
-                  </pb_type>
-                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-                    <input name="a" num_pins="1"/>
-                    <input name="b" num_pins="1"/>
-                    <input name="cin" num_pins="1"/>
-                    <output name="cout" num_pins="1"/>
-                    <output name="sumout" num_pins="1"/>
-                    <delay_constant max="68.74e-12" in_port="adder.a" out_port="adder.sumout"/>
-                    <delay_constant max="68.74e-12" in_port="adder.b" out_port="adder.sumout"/>
-                    <delay_constant max="35.46e-12" in_port="adder.cin" out_port="adder.sumout"/>
-                    <delay_constant max="49.32e-12" in_port="adder.a" out_port="adder.cout"/>
-                    <delay_constant max="49.32e-12" in_port="adder.b" out_port="adder.cout"/>
-                    <delay_constant max="25.56e-12" in_port="adder.cin" out_port="adder.cout"/>
-                  </pb_type>
-                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-                    <input name="D" num_pins="1" port_class="D"/>
-                    <output name="Q" num_pins="1" port_class="Q"/>
-                    <clock name="clk" num_pins="1" port_class="clock"/>
-                    <T_setup value="18.91e-12" port="ff.D" clock="clk"/>
-                    <T_clock_to_Q max="60.32e-12" port="ff.Q" clock="clk"/>
-                  </pb_type>
-                  <interconnect>
-                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-                    <direct name="lut4_in1" input="arithmetic.in" output="lut4[0].in"/>
-                    <direct name="lut4_in2" input="arithmetic.in" output="lut4[1].in"/>
-                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a"/>
-                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b"/>
-                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                      <delay_constant max="18.96e-12" in_port="adder.sumout" out_port="ff.D"/>
-                      <!--pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/-->
-                    </direct>
-                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-                    </direct>
-                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-                    </direct>
-                    <complete name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                      <delay_constant max="39.85e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                      <delay_constant max="39.85e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-                    </complete>
-                  </interconnect>
-                </pb_type>
-                <interconnect>
-                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
-                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
-                    <pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/>
-                  </direct>
-                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
-                    <pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/>
-                  </direct>
-                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
-                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
-                </interconnect>
-              </mode>
-            </pb_type>
-            <interconnect>
-              <!-- Shared inputs between the two 5-LUTs -->
-              <complete name="lut5_reg1" input="fle.in[0]" output="ble5[0].in[0] ble5[1].in[1]"/>
-              <complete name="lut5_reg2" input="fle.in[1]" output="ble5[0].in[1] ble5[1].in[0]"/>
-              <!-- Rest of the 5-LUT inputs -->
-              <direct name="lut5_inputs_1" input="fle.in[4:2]" output="ble5[0].in[4:2]"/>
-              <direct name="lut5_inputs_22" input="fle.in[7:5]" output="ble5[1].in[4:2]"/>
-              <direct name="lut5_outputs_1" input="ble5[0].out" output="fle.out[1:0]"/>
-              <direct name="lut5_outputs_2" input="ble5[1].out" output="fle.out[3:2]"/>
-              <direct name="carry_in" input="fle.cin" output="ble5[0].cin">
-                <pack_pattern name="chain" in_port="fle.cin" out_port="ble5[0].cin"/>
-              </direct>
-              <direct name="carry_out" input="ble5[1].cout" output="fle.cout">
-                <pack_pattern name="chain" in_port="ble5[1].cout" out_port="fle.cout"/>
-              </direct>
-              <direct name="carry_link" input="ble5[0].cout" output="ble5[1].cin">
-                <pack_pattern name="chain" in_port="ble5[0].cout" out_port="ble5[1].cout"/>
-              </direct>
-              <complete name="clock" input="fle.clk" output="ble5[1:0].clk"/>
-            </interconnect>
-          </mode>
-          <!-- n2_lut5 -->
-          <mode name="n1_lut6">
-            <pb_type name="ble6" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="out" num_pins="4"/>
-              <clock name="clk" num_pins="1"/>
-              <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-                <input name="in" num_pins="6" port_class="lut_in"/>
-                <output name="out" num_pins="1" port_class="lut_out"/>
-                <!-- LUT timing using delay matrix -->
-                <!-- These are the physical delay inputs on a Stratix 10 LUT but because VPR cannot do LUT rebalancing,
-                           we instead take the average of these numbers to get more stable results
-                           257.8e-12
-                           253.69e-12
-                           190.3e-12
-                           183.78e-12
-                           114.96e-12
-                           77.18e-12
-                      -->
-                <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                        179.6e-12
-                        179.6e-12
-                        179.6e-12
-                        179.6e-12
-                        179.6e-12
-                        179.6e-12
-                    </delay_matrix>
-              </pb_type>
-              <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-                <input name="D" num_pins="1" port_class="D"/>
-                <output name="Q" num_pins="1" port_class="Q"/>
-                <clock name="clk" num_pins="1" port_class="clock"/>
-                <T_setup value="18.91e-12" port="ff.D" clock="clk"/>
-                <T_clock_to_Q max="60.32e-12" port="ff.Q" clock="clk"/>
-              </pb_type>
-              <interconnect>
-                <direct name="lut6_inputs" input="ble6.in" output="lut6.in"/>
-                <direct name="lut6_ff" input="lut6.out" output="ff[1].D">
-                  <delay_constant max="18.96e-12" in_port="lut6.out" out_port="ff[1].D"/>
-                  <pack_pattern name="ble6" in_port="lut6.out" out_port="ff[1].D"/>
-                </direct>
-                <complete name="clock" input="ble6.clk" output="ff.clk"/>
-                <direct name="input_to_ff" input="ble6.in[0]" output="ff[0].D"/>
-                <mux name="mux1" input="ff[0].Q lut6.out" output="ble6.out[0]">
-                  <delay_constant max="39.85e-12" in_port="lut6.out" out_port="ble6.out[0]"/>
-                  <delay_constant max="39.85e-12" in_port="ff[0].Q" out_port="ble6.out[0]"/>
-                </mux>
-                <!-- This mux is the same as mux1 but connected to output 2 -->
-                <mux name="mux2" input="ff[0].Q lut6.out" output="ble6.out[1]">
-                  <delay_constant max="39.85e-12" in_port="lut6.out" out_port="ble6.out[1]"/>
-                  <delay_constant max="39.85e-12" in_port="ff[0].Q" out_port="ble6.out[1]"/>
-                </mux>
-                <mux name="mux3" input="ff[1].Q lut6.out" output="ble6.out[2]">
-                  <delay_constant max="39.85e-12" in_port="lut6.out" out_port="ble6.out[2]"/>
-                  <delay_constant max="39.85e-12" in_port="ff[1].Q" out_port="ble6.out[2]"/>
-                </mux>
-                <!-- This mux is the same as mux2 but connected to output 3 -->
-                <mux name="mux4" input="ff[1].Q lut6.out" output="ble6.out[3]">
-                  <delay_constant max="39.85e-12" in_port="lut6.out" out_port="ble6.out[3]"/>
-                  <delay_constant max="39.85e-12" in_port="ff[1].Q" out_port="ble6.out[3]"/>
-                </mux>
-              </interconnect>
-            </pb_type>
-            <interconnect>
-              <!-- ble6 takes inputs A, B, C, D, E, & F; where F is fle[7] -->
-              <direct name="lut6_inputs1" input="fle.in[4:0]" output="ble6.in[4:0]"/>
-              <direct name="lut6_inputs2" input="fle.in[7]" output="ble6.in[5]"/>
-              <direct name="direct2" input="ble6.out" output="fle.out"/>
-              <direct name="direct4" input="fle.clk" output="ble6.clk"/>
-            </interconnect>
-          </mode>
-          <!-- n1_lut6 -->
-        </pb_type>
-        <interconnect>
-          <!-- 50% sparsely populated local routing -->
-          <!-- This 50% sparsity pattern divides the cluster inputs and local feedbacks into four groups, 
-               and then selects two of the four groups to feed each LUT input. This means half of the cluster 
-               inputs and local feedbacks can feed each LUT input. There is partial overlap in the inputs that 
-               feed the various LUT inputs, which helps routability vs. simply having half the cluster inputs 
-               feed one set of half the LUT inputs and the other half of cluster inputs feed the other set of 
-               LUT inputs. This pattern is used by Stratix (I - 10) architectures. -->
-          <complete name="lutA" input="lab.I4 lab.I3" output="fle[9:0].in[0:0]">
-            <delay_constant max="74.71e-12" in_port="lab.I4" out_port="fle.in[0:0]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I3" out_port="fle.in[0:0]"/>
-          </complete>
-          <complete name="lutB" input="lab.I3 lab.I2" output="fle[9:0].in[1:1]">
-            <delay_constant max="74.71e-12" in_port="lab.I3" out_port="fle.in[1:1]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I2" out_port="fle.in[1:1]"/>
-          </complete>
-          <complete name="lutC" input="lab.I2 lab.I1" output="fle[9:0].in[2:2]">
-            <delay_constant max="74.71e-12" in_port="lab.I2" out_port="fle.in[2:2]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I1" out_port="fle.in[2:2]"/>
-          </complete>
-          <complete name="lutD" input="lab.I4 lab.I2" output="fle[9:0].in[3:3]">
-            <delay_constant max="74.71e-12" in_port="lab.I4" out_port="fle.in[3:3]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I2" out_port="fle.in[3:3]"/>
-          </complete>
-          <complete name="lutE" input="lab.I3 lab.I1" output="fle[9:0].in[4:4]">
-            <delay_constant max="74.71e-12" in_port="lab.I3" out_port="fle.in[4:4]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I1" out_port="fle.in[4:4]"/>
-          </complete>
-          <complete name="lutF" input="lab.I4 lab.I1" output="fle[9:0].in[5:5]">
-            <delay_constant max="74.71e-12" in_port="lab.I4" out_port="fle.in[5:5]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I1" out_port="fle.in[5:5]"/>
-          </complete>
-          <complete name="lutG" input="lab.I4 lab.I3" output="fle[9:0].in[6:6]">
-            <delay_constant max="74.71e-12" in_port="lab.I4" out_port="fle.in[6:6]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I3" out_port="fle.in[6:6]"/>
-          </complete>
-          <complete name="lutH" input="lab.I3 lab.I2" output="fle[9:0].in[7:7]">
-            <delay_constant max="74.71e-12" in_port="lab.I3" out_port="fle.in[7:7]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I2" out_port="fle.in[7:7]"/>
-          </complete>
-          <complete name="clks" input="lab.clk" output="fle[9:0].clk"/>
-          <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                     By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                     then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                     naive specification).
-              -->
-          <direct name="labouts1" input="fle[9:0].out[0]" output="lab.O[9:0]"/>
-          <direct name="labouts2" input="fle[9:0].out[1]" output="lab.O[19:10]"/>
-          <direct name="labouts3" input="fle[9:0].out[2]" output="lab.O[29:20]"/>
-          <direct name="labouts4" input="fle[9:0].out[3]" output="lab.O[39:30]"/>
-          <!-- Carry chain links -->
-          <direct name="carry_in" input="lab.cin" output="fle[0:0].cin">
-            <!-- Put all inter-block carry chain delay on this one edge -->
-            <delay_constant max="18.47e-12" in_port="lab.cin" out_port="fle[0:0].cin"/>
-            <pack_pattern name="chain" in_port="lab.cin" out_port="fle[0:0].cin"/>
-          </direct>
-          <direct name="carry_out" input="fle[9:9].cout" output="lab.cout">
-            <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="lab.cout"/>
-          </direct>
-          <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-            <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-          </direct>
-        </interconnect>
-      </pb_type>
-      <interconnect>
-        <direct name="carry_in" input="clb.cin" output="lab.cin"/>
-        <direct name="carry_out" input="lab.cout" output="clb.cout"/>
-        <direct name="clock" input="clb.clk" output="lab.clk"/>
-        <complete name="Input_feedback_I1" input="clb.I1 lab.O[4:0]" output="lab.I1"/>
-        <complete name="Input_feedback_I2" input="clb.I2 lab.O[24:20]" output="lab.I2"/>
-        <complete name="Input_feedback_I3" input="clb.I3 lab.O[9:5]" output="lab.I3"/>
-        <complete name="Input_feedback_I4" input="clb.I4 lab.O[29:25]" output="lab.I4"/>
-        <!--
-        <direct name="Input_I1" input="clb.I1" output="lab.I1"/>
-        <direct name="Input_I2" input="clb.I2" output="lab.I2"/>
-        <direct name="Input_I3" input="clb.I3" output="lab.I3"/>
-        <direct name="Input_I4" input="clb.I4" output="lab.I4"/>
-        -->
-        <direct name="output" input="lab.O" output="clb.O"/>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-
-    <!-- Define DSP slice begin -->
-    <pb_type name="dsp_top">
-      <input name="reset" num_pins="1" is_non_clock_global="true"/>
-      <input name="dsp_I1" num_pins="64" />
-      <input name="dsp_I2" num_pins="64" />
-      <input name="chainin" num_pins="64"/>
-      <input name="scanin" num_pins="27"/>
-      <output name="result" num_pins="74"/>
-      <output name="chainout" num_pins="64"/>
-      <output name="scanout" num_pins="27"/>
-      <clock name="clk" num_pins="1"/>
-
-    <pb_type name="dsp" num_pb="1">
-      <input name="reset" num_pins="1"/>
-      <input name="dsp_I1" num_pins="64"/>
-      <input name="dsp_I2" num_pins="64"/>
-      <input name="chainin" num_pins="64"/>
-      <input name="scanin" num_pins="27"/>
-      <output name="result" num_pins="74"/>
-      <output name="chainout" num_pins="64"/>
-      <output name="scanout" num_pins="27"/>
-      <clock name="clk" num_pins="1"/>
-
-      <pb_type name="dsp_pb" num_pb="1">
-        <input name="reset" num_pins="1"/>
-        <input name="mode_sigs" num_pins="12"/>
-        <input name="datain" num_pins="116"/>
-        <input name="chainin" num_pins="64"/>
-        <input name="scanin" num_pins="27"/>
-        <output name="result" num_pins="74"/>
-        <output name="chainout" num_pins="64"/>
-        <output name="scanout" num_pins="27"/>
-        <clock name="clk" num_pins="1"/>
-
-        <!-- fixed-point multiplier mode (1 27x27 multiplier) result = ax*ay -->
-        <mode name="one_mult_27x27">
-          <pb_type name="one_mult_27x27" num_pb="1">
-            <input name="a" num_pins="27"/>
-            <input name="b" num_pins="27"/>
-            <output name="out" num_pins="54"/>
-            <pb_type name="mult_27x27" blif_model=".subckt multiply" num_pb="1">
-              <input name="a" num_pins="27"/>
-              <input name="b" num_pins="27"/>
-              <output name="out" num_pins="54"/>
-              <delay_constant max="2.14e-9" in_port="mult_27x27.a" out_port="mult_27x27.out"/>
-              <delay_constant max="2.14e-9" in_port="mult_27x27.b" out_port="mult_27x27.out"/>
-            </pb_type>
-            <interconnect>
-              <direct name="a2a" input="one_mult_27x27.a" output="mult_27x27.a">
-              </direct>
-              <direct name="b2b" input="one_mult_27x27.b" output="mult_27x27.b">
-              </direct>
-              <direct name="out2out" input="mult_27x27.out" output="one_mult_27x27.out">
-              </direct>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="datain2a" input="dsp_pb.datain[26:0]" output="one_mult_27x27.a">
-            </direct>
-            <direct name="datain2b" input="dsp_pb.datain[53:27]" output="one_mult_27x27.b">
-            </direct>
-            <direct name="out2dataout" input="one_mult_27x27.out" output="dsp_pb.result[53:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point multiplier mode (2 18x19 multipliers) result[some:bits] = ax*ay, result[other:bits] = bx*by -->
-        <mode name="two_mult_18x19">
-          <pb_type name="two_mult_18x19" num_pb="2">
-            <input name="a" num_pins="18"/>
-            <input name="b" num_pins="19"/>
-            <output name="out" num_pins="37"/>
-            <pb_type name="mult_18x19" blif_model=".subckt multiply" num_pb="1">
-              <input name="a" num_pins="18"/>
-              <input name="b" num_pins="19"/>
-              <output name="out" num_pins="37"/>
-              <delay_constant max="2.14e-9" in_port="mult_18x19.a" out_port="mult_18x19.out"/>
-              <delay_constant max="2.14e-9" in_port="mult_18x19.b" out_port="mult_18x19.out"/>
-            </pb_type>
-            <interconnect>
-              <direct name="a2a" input="two_mult_18x19.a" output="mult_18x19.a">
-                 </direct>
-              <direct name="b2b" input="two_mult_18x19.b" output="mult_18x19.b">
-                 </direct>
-              <direct name="out2out" input="mult_18x19.out" output="two_mult_18x19.out">
-                 </direct>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="datain2a1" input="dsp_pb.datain[17:0]" output="two_mult_18x19[0].a">
-            </direct>
-            <direct name="datain2b1" input="dsp_pb.datain[36:18]" output="two_mult_18x19[0].b">
-            </direct>
-            <direct name="datain2a2" input="dsp_pb.datain[54:37]" output="two_mult_18x19[1].a">
-            </direct>
-            <direct name="datain2b2" input="dsp_pb.datain[73:55]" output="two_mult_18x19[1].b">
-            </direct>
-            <direct name="out2result" input="two_mult_18x19.out" output="dsp_pb.result[73:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- Fixed point multiplier mode (4 9x9 multipliers) result = ax*ay -->
-        <mode name="mult_9x9_fixed_pt_mode">
-          <pb_type name="mult_9x9_fixed_pt" blif_model=".subckt multiply" num_pb="4">
-            <input name="a" num_pins="9"/>
-            <input name="b" num_pins="9"/>
-            <output name="out" num_pins="18"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_9x9_fixed_pt.a" out_port="mult_9x9_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mult_9x9_fixed_pt.b" out_port="mult_9x9_fixed_pt.out"/>
-          </pb_type>
-          <interconnect>
-            <direct name="atoa0" input="dsp_pb.datain[8:0]" output="mult_9x9_fixed_pt[0].a"/>
-            <direct name="btob0" input="dsp_pb.datain[17:9]" output="mult_9x9_fixed_pt[0].b"/>
-            <direct name="atoa1" input="dsp_pb.datain[26:18]" output="mult_9x9_fixed_pt[1].a"/>
-            <direct name="btob1" input="dsp_pb.datain[35:27]" output="mult_9x9_fixed_pt[1].b"/>
-            <direct name="atoa2" input="dsp_pb.datain[44:36]" output="mult_9x9_fixed_pt[2].a"/>
-            <direct name="btob2" input="dsp_pb.datain[53:45]" output="mult_9x9_fixed_pt[2].b"/>
-            <direct name="atoa3" input="dsp_pb.datain[62:54]" output="mult_9x9_fixed_pt[3].a"/>
-            <direct name="btob3" input="dsp_pb.datain[71:63]" output="mult_9x9_fixed_pt[3].b"/>
-            <direct name="sumouttosumout0" input="mult_9x9_fixed_pt[0].out" output="dsp_pb.result[17:0]"/>
-            <direct name="sumouttosumout1" input="mult_9x9_fixed_pt[1].out" output="dsp_pb.result[35:18]"/>
-            <direct name="sumouttosumout2" input="mult_9x9_fixed_pt[2].out" output="dsp_pb.result[53:36]"/>
-            <direct name="sumouttosumout3" input="mult_9x9_fixed_pt[3].out" output="dsp_pb.result[71:54]"/>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point multiplier-add-sum mode result = (bx * by) + (ax * ay) + chainin. chainout = result -->
-        <mode name="sop_2_mode">
-          <pb_type name="sop_2" num_pb="1" blif_model=".subckt int_sop_2">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="ax" num_pins="18"/>
-            <input name="ay" num_pins="19"/>
-            <input name="bx" num_pins="18"/>
-            <input name="by" num_pins="19"/>
-            <input name="chainin" num_pins="37"/>
-            <output name="result" num_pins="37"/>
-            <output name="chainout" num_pins="37"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_2.reset" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.mode_sigs" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.ax" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.ay" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.bx" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.by" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.chainin" out_port="sop_2.result"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_2.reset" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.mode_sigs" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.ax" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.ay" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.bx" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.by" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.chainin" out_port="sop_2.chainout"/>
-
-            <T_setup value="18.91e-12" port="sop_2.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.ax" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.ay" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.bx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.by" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.ax" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.ay" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.bx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.by" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="sop_2.clk">
-            </direct>
-            <direct name="reset" input="dsp_pb.reset" output="sop_2.reset">
-            </direct>
-            <direct name="modesigs" input="dsp_pb.mode_sigs" output="sop_2.mode_sigs">
-            </direct>
-            <direct name="datain2ax" input="dsp_pb.datain[17:0]" output="sop_2.ax">
-            </direct>
-            <direct name="datain2ay" input="dsp_pb.datain[36:18]" output="sop_2.ay">
-            </direct>
-            <direct name="datain2bx" input="dsp_pb.datain[54:37]" output="sop_2.bx">
-            </direct>
-            <direct name="datain2by" input="dsp_pb.datain[73:55]" output="sop_2.by">
-            </direct>
-            <direct name="chainin"   input="dsp_pb.chainin[36:0]" output="sop_2.chainin">
-            </direct>
-            <direct name="dataout2result" input="sop_2.result" output="dsp_pb.result[36:0]">
-            </direct>
-            <direct name="chainout" input="sop_2.chainout" output="dsp_pb.chainout[36:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point multiplier-add-sum mode result = (ax * ay) + bx + chainin. chainout = result. with scanin-scanout support -->
-        <mode name="mult_add_mode_18_19_36">
-          <pb_type name="mult_add" num_pb="1" blif_model=".subckt mult_add_int_18x19">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="ax" num_pins="18"/>
-            <input name="ay" num_pins="19"/>
-            <input name="bx" num_pins="36"/>
-            <input name="chainin" num_pins="64"/>
-            <input name="scanin" num_pins="19"/>
-            <output name="result" num_pins="64"/>
-            <output name="chainout" num_pins="64"/>
-            <output name="scanout" num_pins="19"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.result"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.chainout"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.scanout"/>
-
-            <T_setup value="18.91e-12" port="mult_add.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.ax" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.ay" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.bx" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.scanin" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.ax" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.ay" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.bx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.scanin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="mult_add.clk">
-            </direct>
-            <direct name="reset" input="dsp_pb.reset" output="mult_add.reset">
-            </direct>
-            <direct name="modesigs" input="dsp_pb.mode_sigs" output="mult_add.mode_sigs">
-            </direct>
-            <direct name="datain2ax" input="dsp_pb.datain[17:0]" output="mult_add.ax">
-            </direct>
-            <direct name="datain2ay" input="dsp_pb.datain[36:18]" output="mult_add.ay">
-            </direct>
-            <direct name="datain2bx" input="dsp_pb.datain[72:37]" output="mult_add.bx">
-            </direct>
-            <direct name="chainin"   input="dsp_pb.chainin[63:0]" output="mult_add.chainin">
-            </direct>
-            <direct name="scanin"   input="dsp_pb.scanin[18:0]" output="mult_add.scanin">
-            </direct>
-            <direct name="dataout2result" input="mult_add.result" output="dsp_pb.result[63:0]">
-            </direct>
-            <direct name="chainout" input="mult_add.chainout" output="dsp_pb.chainout[63:0]">
-            </direct>
-            <direct name="scanout" input="mult_add.scanout" output="dsp_pb.scanout[18:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point multiplier-add-sum mode result = (ax * ay) + bx + chainin. chainout = result. with scanin-scanout support -->
-        <mode name="mult_add_mode_27_27_64">
-          <pb_type name="mult_add" num_pb="1" blif_model=".subckt mult_add_int_27x27">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="ax" num_pins="27"/>
-            <input name="ay" num_pins="27"/>
-            <input name="bx" num_pins="36"/>
-            <input name="chainin" num_pins="64"/>
-            <input name="scanin" num_pins="27"/>
-            <output name="result" num_pins="64"/>
-            <output name="chainout" num_pins="64"/>
-            <output name="scanout" num_pins="27"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.result"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.chainout"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.scanout"/>
-
-            <T_setup value="18.91e-12" port="mult_add.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.ax" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.ay" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.bx" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.scanin" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.ax" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.ay" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.bx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.scanin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="mult_add.clk">
-            </direct>
-            <direct name="reset" input="dsp_pb.reset" output="mult_add.reset">
-            </direct>
-            <direct name="modesigs" input="dsp_pb.mode_sigs" output="mult_add.mode_sigs">
-            </direct>
-            <direct name="datain2ax" input="dsp_pb.datain[26:0]" output="mult_add.ax">
-            </direct>
-            <direct name="datain2ay" input="dsp_pb.datain[53:27]" output="mult_add.ay">
-            </direct>
-            <direct name="datain2bx" input="dsp_pb.datain[89:54]" output="mult_add.bx">
-            </direct>
-            <direct name="chainin"   input="dsp_pb.chainin[63:0]" output="mult_add.chainin">
-            </direct>
-            <direct name="scanin"   input="dsp_pb.scanin[26:0]" output="mult_add.scanin">
-            </direct>
-            <direct name="dataout2result" input="mult_add.result" output="dsp_pb.result[63:0]">
-            </direct>
-            <direct name="chainout" input="mult_add.chainout" output="dsp_pb.chainout[63:0]">
-            </direct>
-            <direct name="scanout" input="mult_add.scanout" output="dsp_pb.scanout[26:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point sum-of-4 mode result = (dx * dy) + (cx * cy) + (bx * by) + (ax * ay) + chainin. chainout = result -->
-        <mode name="sop_4_mode">
-          <pb_type name="sop_4" num_pb="1" blif_model=".subckt int_sop_4">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="ax" num_pins="9"/>
-            <input name="ay" num_pins="9"/>
-            <input name="bx" num_pins="9"/>
-            <input name="by" num_pins="9"/>
-            <input name="cx" num_pins="9"/>
-            <input name="cy" num_pins="9"/>
-            <input name="dx" num_pins="9"/>
-            <input name="dy" num_pins="9"/>
-            <input name="chainin" num_pins="64"/>
-            <output name="result" num_pins="64"/>
-            <output name="chainout" num_pins="64"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_4.reset" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.mode_sigs" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ax" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ay" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.bx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.by" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cy" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dy" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.chainin" out_port="sop_4.result"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_4.reset" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.mode_sigs" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ax" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ay" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.bx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.by" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cy" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dy" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.chainin" out_port="sop_4.chainout"/>
-
-            <T_setup value="18.91e-12" port="sop_4.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.ax" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.ay" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.bx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.by" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.cx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.cy" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.dx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.dy" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.ax" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.ay" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.bx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.by" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.cx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.cy" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.dx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.dy" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="sop_4.clk">
-            </direct>
-            <direct name="reset" input="dsp_pb.reset" output="sop_4.reset">
-            </direct>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="sop_4.mode_sigs">
-            </direct>
-            <direct name="datain2ax" input="dsp_pb.datain[8:0]" output="sop_4.ax">
-            </direct>
-            <direct name="datain2ay" input="dsp_pb.datain[17:9]" output="sop_4.ay">
-            </direct>
-            <direct name="datain2bx" input="dsp_pb.datain[26:18]" output="sop_4.bx">
-            </direct>
-            <direct name="datain2by" input="dsp_pb.datain[35:27]" output="sop_4.by">
-            </direct>
-            <direct name="datain2cx" input="dsp_pb.datain[44:36]" output="sop_4.cx">
-            </direct>
-            <direct name="datain2cy" input="dsp_pb.datain[53:45]" output="sop_4.cy">
-            </direct>
-            <direct name="datain2dx" input="dsp_pb.datain[62:54]" output="sop_4.dx">
-            </direct>
-            <direct name="datain2dy" input="dsp_pb.datain[71:63]" output="sop_4.dy">
-            </direct>
-            <direct name="chainin"   input="dsp_pb.chainin[63:0]" output="sop_4.chainin">
-            </direct>
-            <direct name="dataout2result" input="sop_4.result" output="dsp_pb.result[63:0]">
-            </direct>
-            <direct name="chainout" input="sop_4.chainout" output="dsp_pb.chainout[63:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point sum-of-4 accum mode result = (dx * dy) + (cx * cy) + (bx * by) + (ax * ay) + chainin + accumulator. chainout = result -->
-        <mode name="sop_4_accum_mode">
-          <pb_type name="sop_4" num_pb="1" blif_model=".subckt int_sop_accum_4">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="ax" num_pins="9"/>
-            <input name="ay" num_pins="9"/>
-            <input name="bx" num_pins="9"/>
-            <input name="by" num_pins="9"/>
-            <input name="cx" num_pins="9"/>
-            <input name="cy" num_pins="9"/>
-            <input name="dx" num_pins="9"/>
-            <input name="dy" num_pins="9"/>
-            <input name="chainin" num_pins="64"/>
-            <output name="result" num_pins="64"/>
-            <output name="chainout" num_pins="64"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_4.mode_sigs" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ax" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ay" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.bx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.by" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cy" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dy" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.chainin" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.reset" out_port="sop_4.result"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_4.mode_sigs" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ax" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ay" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.bx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.by" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cy" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dy" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.chainin" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.reset" out_port="sop_4.chainout"/>
-
-            <T_setup value="18.91e-12" port="sop_4.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.ax" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.ay" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.bx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.by" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.cx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.cy" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.dx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.dy" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.ax" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.ay" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.bx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.by" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.cx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.cy" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.dx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.dy" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="sop_4.clk">
-            </direct>
-            <direct name="reset" input="dsp_pb.reset" output="sop_4.reset">
-            </direct>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="sop_4.mode_sigs">
-            </direct>
-            <direct name="datain2ax" input="dsp_pb.datain[8:0]" output="sop_4.ax">
-            </direct>
-            <direct name="datain2ay" input="dsp_pb.datain[17:9]" output="sop_4.ay">
-            </direct>
-            <direct name="datain2bx" input="dsp_pb.datain[26:18]" output="sop_4.bx">
-            </direct>
-            <direct name="datain2by" input="dsp_pb.datain[35:27]" output="sop_4.by">
-            </direct>
-            <direct name="datain2cx" input="dsp_pb.datain[44:36]" output="sop_4.cx">
-            </direct>
-            <direct name="datain2cy" input="dsp_pb.datain[53:45]" output="sop_4.cy">
-            </direct>
-            <direct name="datain2dx" input="dsp_pb.datain[62:54]" output="sop_4.dx">
-            </direct>
-            <direct name="datain2dy" input="dsp_pb.datain[71:63]" output="sop_4.dy">
-            </direct>
-            <direct name="chainin"   input="dsp_pb.chainin[63:0]" output="sop_4.chainin">
-            </direct>
-            <direct name="dataout2result" input="sop_4.result" output="dsp_pb.result[63:0]">
-            </direct>
-            <direct name="chainout" input="sop_4.chainout" output="dsp_pb.chainout[63:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- Fixed point mac mode (result = a*b + accumulated value-->
-        <mode name="mac_27x27_fixed_pt_mode">
-          <pb_type name="mac_27x27_fixed_pt" blif_model=".subckt mac_int_27x27" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="a" num_pins="27"/>
-            <input name="b" num_pins="27"/>
-            <output name="out" num_pins="54"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="mac_27x27_fixed_pt.a" out_port="mac_27x27_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_27x27_fixed_pt.b" out_port="mac_27x27_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_27x27_fixed_pt.reset" out_port="mac_27x27_fixed_pt.out"/>
-
-            <T_setup value="18.91e-12" port="mac_27x27_fixed_pt.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_27x27_fixed_pt.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_27x27_fixed_pt.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_27x27_fixed_pt.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_27x27_fixed_pt.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_27x27_fixed_pt.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_27x27_fixed_pt.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_27x27_fixed_pt.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="mac_27x27_fixed_pt.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="mac_27x27_fixed_pt.clk"/>
-            <direct name="atoa" input="dsp_pb.datain[26:0]" output="mac_27x27_fixed_pt.a"/>
-            <direct name="btob" input="dsp_pb.datain[53:27]" output="mac_27x27_fixed_pt.b"/>
-            <direct name="sumouttosumout" input="mac_27x27_fixed_pt.out" output="dsp_pb.result[53:0]"/>
-          </interconnect>
-        </mode>
-
-        <!-- Fixed point mac mode (result = a*b + accumulated value-->
-        <mode name="mac_18x19_fixed_pt_mode">
-          <pb_type name="mac_fixed_pt" blif_model=".subckt mac_int_18x19" num_pb="2">
-            <input name="reset" num_pins="1"/>
-            <input name="a" num_pins="18"/>
-            <input name="b" num_pins="19"/>
-            <output name="out" num_pins="37"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="mac_fixed_pt.a" out_port="mac_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_fixed_pt.b" out_port="mac_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_fixed_pt.reset" out_port="mac_fixed_pt.out"/>
-
-            <T_setup value="18.91e-12" port="mac_fixed_pt.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fixed_pt.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fixed_pt.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fixed_pt.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fixed_pt.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fixed_pt.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fixed_pt.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fixed_pt.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset0" input="dsp_pb.reset" output="mac_fixed_pt[0].reset"/>
-            <direct name="reset1" input="dsp_pb.reset" output="mac_fixed_pt[1].reset"/>
-            <direct name="clk0" input="dsp_pb.clk" output="mac_fixed_pt[0].clk"/>
-            <direct name="clk1" input="dsp_pb.clk" output="mac_fixed_pt[1].clk"/>
-            <direct name="atoa0" input="dsp_pb.datain[17:0]" output="mac_fixed_pt[0].a"/>
-            <direct name="btob0" input="dsp_pb.datain[36:18]" output="mac_fixed_pt[0].b"/>
-            <direct name="atoa1" input="dsp_pb.datain[54:37]" output="mac_fixed_pt[1].a"/>
-            <direct name="btob1" input="dsp_pb.datain[73:55]" output="mac_fixed_pt[1].b"/>
-            <direct name="sumouttosumout0" input="mac_fixed_pt[0].out" output="dsp_pb.result[36:0]"/>
-            <direct name="sumouttosumout1" input="mac_fixed_pt[1].out" output="dsp_pb.result[73:37]"/>
-          </interconnect>
-        </mode>
-
-        <!-- Fixed point mac mode (result = a*b + accumulated value-->
-        <mode name="mac_9x9_fixed_pt_mode">
-          <pb_type name="mac_9x9_fixed_pt" blif_model=".subckt mac_int_9x9" num_pb="4">
-            <input name="reset" num_pins="1"/>
-            <input name="a" num_pins="9"/>
-            <input name="b" num_pins="9"/>
-            <output name="out" num_pins="18"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="mac_9x9_fixed_pt.a" out_port="mac_9x9_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_9x9_fixed_pt.b" out_port="mac_9x9_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_9x9_fixed_pt.reset" out_port="mac_9x9_fixed_pt.out"/>
-
-            <T_setup value="18.91e-12" port="mac_9x9_fixed_pt.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_9x9_fixed_pt.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_9x9_fixed_pt.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_9x9_fixed_pt.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_9x9_fixed_pt.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_9x9_fixed_pt.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_9x9_fixed_pt.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_9x9_fixed_pt.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset0" input="dsp_pb.reset" output="mac_9x9_fixed_pt[0].reset"/>
-            <direct name="reset1" input="dsp_pb.reset" output="mac_9x9_fixed_pt[1].reset"/>
-            <direct name="reset2" input="dsp_pb.reset" output="mac_9x9_fixed_pt[2].reset"/>
-            <direct name="reset3" input="dsp_pb.reset" output="mac_9x9_fixed_pt[3].reset"/>
-            <direct name="clk0" input="dsp_pb.clk" output="mac_9x9_fixed_pt[0].clk"/>
-            <direct name="clk1" input="dsp_pb.clk" output="mac_9x9_fixed_pt[1].clk"/>
-            <direct name="clk2" input="dsp_pb.clk" output="mac_9x9_fixed_pt[2].clk"/>
-            <direct name="clk3" input="dsp_pb.clk" output="mac_9x9_fixed_pt[3].clk"/>
-            <direct name="atoa0" input="dsp_pb.datain[8:0]" output="mac_9x9_fixed_pt[0].a"/>
-            <direct name="btob0" input="dsp_pb.datain[17:9]" output="mac_9x9_fixed_pt[0].b"/>
-            <direct name="atoa1" input="dsp_pb.datain[26:18]" output="mac_9x9_fixed_pt[1].a"/>
-            <direct name="btob1" input="dsp_pb.datain[35:27]" output="mac_9x9_fixed_pt[1].b"/>
-            <direct name="atoa2" input="dsp_pb.datain[44:36]" output="mac_9x9_fixed_pt[2].a"/>
-            <direct name="btob2" input="dsp_pb.datain[53:45]" output="mac_9x9_fixed_pt[2].b"/>
-            <direct name="atoa3" input="dsp_pb.datain[62:54]" output="mac_9x9_fixed_pt[3].a"/>
-            <direct name="btob3" input="dsp_pb.datain[71:63]" output="mac_9x9_fixed_pt[3].b"/>
-            <direct name="sumouttosumout0" input="mac_9x9_fixed_pt[0].out" output="dsp_pb.result[17:0]"/>
-            <direct name="sumouttosumout1" input="mac_9x9_fixed_pt[1].out" output="dsp_pb.result[35:18]"/>
-            <direct name="sumouttosumout2" input="mac_9x9_fixed_pt[2].out" output="dsp_pb.result[53:36]"/>
-            <direct name="sumouttosumout3" input="mac_9x9_fixed_pt[3].out" output="dsp_pb.result[71:54]"/>
-          </interconnect>
-        </mode>
-
-        <!-- floating point multiplier mode (result = a * b)-->
-        <mode name="mult_fp32_mode">
-          <pb_type name="mult_fp32" blif_model=".subckt mult_fp_32" num_pb="1">
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <output name="out" num_pins="32"/>
-
-            <delay_constant max="2.56e-9" in_port="mult_fp32.a" out_port="mult_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="mult_fp32.b" out_port="mult_fp32.out"/>
-          </pb_type>
-          <interconnect>
-            <direct name="a2a" input="dsp_pb.datain[31:0]" output="mult_fp32.a">
-            </direct>
-            <direct name="b2b" input="dsp_pb.datain[63:32]" output="mult_fp32.b">
-            </direct>
-            <direct name="out2out" input="mult_fp32.out" output="dsp_pb.result[31:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point multiplier mode (result = a * b)-->
-        <mode name="mult_fp16_mode">
-          <pb_type name="mult_fp16" blif_model=".subckt mult_fp_16" num_pb="2">
-            <input name="a" num_pins="16"/>
-            <input name="b" num_pins="16"/>
-            <output name="out" num_pins="16"/>
-
-            <delay_constant max="2.56e-9" in_port="mult_fp16.a" out_port="mult_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="mult_fp16.b" out_port="mult_fp16.out"/>
-          </pb_type>
-          <interconnect>
-            <direct name="a2a0" input="dsp_pb.datain[15:0]" output="mult_fp16[0].a"></direct>
-            <direct name="a2a1" input="dsp_pb.datain[31:16]" output="mult_fp16[1].a"></direct>
-            <direct name="b2b0" input="dsp_pb.datain[47:32]" output="mult_fp16[0].b"></direct>
-            <direct name="b2b1" input="dsp_pb.datain[63:48]" output="mult_fp16[1].b"></direct>
-            <direct name="out2out0" input="mult_fp16[0].out" output="dsp_pb.result[15:0]"></direct>
-            <direct name="out2out1" input="mult_fp16[1].out" output="dsp_pb.result[31:16]"></direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point adder mode (result = a + b)-->
-        <mode name="adder_fp32_mode"> 
-          <pb_type name="adder_fp32" blif_model=".subckt addition_fp_32" num_pb="1">
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <output name="out" num_pins="32"/>
-
-            <delay_constant max="2.56e-9" in_port="adder_fp32.a" out_port="adder_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="adder_fp32.b" out_port="adder_fp32.out"/>
-          </pb_type>
-          <interconnect>
-            <direct name="atoa" input="dsp_pb.datain[31:0]" output="adder_fp32.a">
-            </direct>
-            <direct name="btob" input="dsp_pb.datain[63:32]" output="adder_fp32.b">
-            </direct>
-            <direct name="sumouttosumout" input="adder_fp32.out" output="dsp_pb.result[31:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point adder mode (result = a + b)-->
-        <mode name="adder_fp16_mode">
-          <pb_type name="adder_fp16" blif_model=".subckt addition_fp_16" num_pb="2">
-            <input name="a" num_pins="16"/>
-            <input name="b" num_pins="16"/>
-            <output name="out" num_pins="16"/>
-
-            <delay_constant max="2.56e-9" in_port="adder_fp16.a" out_port="adder_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="adder_fp16.b" out_port="adder_fp16.out"/>
-          </pb_type>
-          <interconnect>
-            <direct name="a2a0" input="dsp_pb.datain[15:0]" output="adder_fp16[0].a"></direct>
-            <direct name="a2a1" input="dsp_pb.datain[31:16]" output="adder_fp16[1].a"></direct>
-            <direct name="b2b0" input="dsp_pb.datain[47:32]" output="adder_fp16[0].b"></direct>
-            <direct name="b2b1" input="dsp_pb.datain[63:48]" output="adder_fp16[1].b"></direct>
-            <direct name="out2out0" input="adder_fp16[0].out" output="dsp_pb.result[15:0]"></direct>
-            <direct name="out2out1" input="adder_fp16[1].out" output="dsp_pb.result[31:16]"></direct>
-          </interconnect>
-        </mode>
-
-        <!-- clocked floating point multiplier mode (result = a * b)-->
-        <mode name="mult_fp32_clocked_mode">
-          <pb_type name="mult_fp32" blif_model=".subckt mult_fp_clk_32" num_pb="1">
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <output name="out" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="mult_fp32.a" out_port="mult_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="mult_fp32.b" out_port="mult_fp32.out"/>
-
-            <T_setup value="18.91e-12" port="mult_fp32.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_fp32.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_fp32.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp32.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp32.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp32.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="mult_fp32.clk"/>
-            <direct name="a2a" input="dsp_pb.datain[31:0]" output="mult_fp32.a">
-            </direct>
-            <direct name="b2b" input="dsp_pb.datain[63:32]" output="mult_fp32.b">
-            </direct>
-            <direct name="out2out" input="mult_fp32.out" output="dsp_pb.result[31:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- clocked floating point multiplier mode (result = a * b)-->
-        <mode name="mult_fp16_clocked_mode">
-          <pb_type name="mult_fp16" blif_model=".subckt mult_fp_clk_16" num_pb="2">
-            <input name="a" num_pins="16"/>
-            <input name="b" num_pins="16"/>
-            <output name="out" num_pins="16"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="mult_fp16.a" out_port="mult_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="mult_fp16.b" out_port="mult_fp16.out"/>
-
-            <T_setup value="18.91e-12" port="mult_fp16.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_fp16.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_fp16.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp16.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp16.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp16.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk0" input="dsp_pb.clk" output="mult_fp16[0].clk"/>
-            <direct name="clk1" input="dsp_pb.clk" output="mult_fp16[1].clk"/>
-            <direct name="a2a0" input="dsp_pb.datain[15:0]" output="mult_fp16[0].a"></direct>
-            <direct name="a2a1" input="dsp_pb.datain[31:16]" output="mult_fp16[1].a"></direct>
-            <direct name="b2b0" input="dsp_pb.datain[47:32]" output="mult_fp16[0].b"></direct>
-            <direct name="b2b1" input="dsp_pb.datain[63:48]" output="mult_fp16[1].b"></direct>
-            <direct name="out2out0" input="mult_fp16[0].out" output="dsp_pb.result[15:0]"></direct>
-            <direct name="out2out1" input="mult_fp16[1].out" output="dsp_pb.result[31:16]"></direct>
-          </interconnect>
-        </mode>
-
-        <!-- clocked floating point adder mode (result = a + b)-->
-        <mode name="adder_fp32_clocked_mode"> 
-          <pb_type name="adder_fp32" blif_model=".subckt addition_fp_clk_32" num_pb="1">
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <output name="out" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="adder_fp32.a" out_port="adder_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="adder_fp32.b" out_port="adder_fp32.out"/>
-
-            <T_setup value="18.91e-12" port="adder_fp32.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="adder_fp32.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="adder_fp32.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp32.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp32.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp32.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="adder_fp32.clk"/>
-            <direct name="atoa" input="dsp_pb.datain[31:0]" output="adder_fp32.a">
-            </direct>
-            <direct name="btob" input="dsp_pb.datain[63:32]" output="adder_fp32.b">
-            </direct>
-            <direct name="sumouttosumout" input="adder_fp32.out" output="dsp_pb.result[31:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- clocked floating point adder mode (result = a + b)-->
-        <mode name="adder_fp16_clocked_mode">
-          <pb_type name="adder_fp16" blif_model=".subckt addition_fp_clk_16" num_pb="2">
-            <input name="a" num_pins="16"/>
-            <input name="b" num_pins="16"/>
-            <output name="out" num_pins="16"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="adder_fp16.a" out_port="adder_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="adder_fp16.b" out_port="adder_fp16.out"/>
-
-            <T_setup value="18.91e-12" port="adder_fp16.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="adder_fp16.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="adder_fp16.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp16.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp16.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp16.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk0" input="dsp_pb.clk" output="adder_fp16[0].clk"/>
-            <direct name="clk1" input="dsp_pb.clk" output="adder_fp16[1].clk"/>
-            <direct name="a2a0" input="dsp_pb.datain[15:0]" output="adder_fp16[0].a"></direct>
-            <direct name="a2a1" input="dsp_pb.datain[31:16]" output="adder_fp16[1].a"></direct>
-            <direct name="b2b0" input="dsp_pb.datain[47:32]" output="adder_fp16[0].b"></direct>
-            <direct name="b2b1" input="dsp_pb.datain[63:48]" output="adder_fp16[1].b"></direct>
-            <direct name="out2out0" input="adder_fp16[0].out" output="dsp_pb.result[15:0]"></direct>
-            <direct name="out2out1" input="adder_fp16[1].out" output="dsp_pb.result[31:16]"></direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point mac mode (result = a*b + accumulated value-->
-        <mode name="mac_fp32_mode">
-          <pb_type name="mac_fp32" blif_model=".subckt mac_fp_32" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <output name="out" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="mac_fp32.a" out_port="mac_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="mac_fp32.b" out_port="mac_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="mac_fp32.reset" out_port="mac_fp32.out"/>
-
-            <T_setup value="18.91e-12" port="mac_fp32.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp32.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp32.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp32.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp32.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp32.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp32.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp32.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="mac_fp32.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="mac_fp32.clk"/>
-            <direct name="atoa" input="dsp_pb.datain[31:0]" output="mac_fp32.a">
-            </direct>
-            <direct name="btob" input="dsp_pb.datain[63:32]" output="mac_fp32.b">
-            </direct>
-            <direct name="sumouttosumout" input="mac_fp32.out" output="dsp_pb.result[31:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point 16-bit mac mode (result = a*b + accumulated value-->
-        <mode name="mac_fp16_mode">
-          <pb_type name="mac_fp16" blif_model=".subckt mac_fp_16" num_pb="2">
-            <input name="reset" num_pins="1"/>
-            <input name="a" num_pins="16"/>
-            <input name="b" num_pins="16"/>
-            <output name="out" num_pins="16"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="mac_fp16.a" out_port="mac_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="mac_fp16.b" out_port="mac_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="mac_fp16.reset" out_port="mac_fp16.out"/>
-
-            <T_setup value="18.91e-12" port="mac_fp16.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp16.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp16.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp16.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp16.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp16.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp16.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp16.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset0" input="dsp_pb.reset" output="mac_fp16[0].reset"></direct>
-            <direct name="reset1" input="dsp_pb.reset" output="mac_fp16[1].reset"></direct>
-            <direct name="clk0" input="dsp_pb.clk" output="mac_fp16[0].clk"></direct>
-            <direct name="clk1" input="dsp_pb.clk" output="mac_fp16[1].clk"></direct>
-            <direct name="atoa0" input="dsp_pb.datain[15:0]"  output="mac_fp16[0].a"></direct>
-            <direct name="atoa1" input="dsp_pb.datain[31:16]" output="mac_fp16[1].a"></direct>
-            <direct name="btob0" input="dsp_pb.datain[47:32]" output="mac_fp16[0].b"></direct>
-            <direct name="btob1" input="dsp_pb.datain[63:48]" output="mac_fp16[1].b"></direct>
-            <direct name="sumouttosumout0" input="mac_fp16[0].out" output="dsp_pb.result[15:0]"></direct>
-            <direct name="sumouttosumout1" input="mac_fp16[1].out" output="dsp_pb.result[31:16]"></direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point fp16 sum-of-2 mult mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b). chainout = third_inp or result-->
-        <mode name="fp16_sum_of_products_mode"> 
-          <pb_type name="fp16_sum_of_2_mult" blif_model=".subckt fp16_mult_add" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="top_a" num_pins="16"/>
-            <input name="top_b" num_pins="16"/>
-            <input name="bot_a" num_pins="16"/>
-            <input name="bot_b" num_pins="16"/>
-            <input name="fp32_in" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.reset" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.mode_sigs" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_a" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_b" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_a" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_b" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.fp32_in" out_port="fp16_sum_of_2_mult.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.reset" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.mode_sigs" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_a" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_b" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_a" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_b" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.fp32_in" out_port="fp16_sum_of_2_mult.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.top_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.top_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.bot_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.bot_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.top_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.top_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.bot_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.bot_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="fp16_sum_of_2_mult.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp16_sum_of_2_mult.clk"/>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp16_sum_of_2_mult.mode_sigs">
-            </direct>
-            <direct name="atoa_top" input="dsp_pb.datain[15:0]" output="fp16_sum_of_2_mult.top_a">
-            </direct>
-            <direct name="btob_top" input="dsp_pb.datain[31:16]" output="fp16_sum_of_2_mult.top_b">
-            </direct>
-            <direct name="result_top" input="fp16_sum_of_2_mult.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="atoa_bot" input="dsp_pb.datain[47:32]" output="fp16_sum_of_2_mult.bot_a">
-            </direct>
-            <direct name="btob_bot" input="dsp_pb.datain[63:48]" output="fp16_sum_of_2_mult.bot_b">
-            </direct>
-            <direct name="result_bot" input="fp16_sum_of_2_mult.result" output="dsp_pb.result[63:32]">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]" output="fp16_sum_of_2_mult.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp16_sum_of_2_mult.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>  
-
-        <!-- floating point fp16 sum-of-2 mult mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b + fp32 chainin or third inp. chainout = third_inp or result)-->
-        <mode name="fp16_sum_of_products_2_mult_mode"> 
-          <pb_type name="fp16_sum_of_2_mult" blif_model=".subckt fp16_sop2_mult" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="top_a" num_pins="16"/>
-            <input name="top_b" num_pins="16"/>
-            <input name="bot_a" num_pins="16"/>
-            <input name="bot_b" num_pins="16"/>
-            <input name="fp32_in" num_pins="32"/>
-            <input name="chainin" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.reset" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.mode_sigs" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_a" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_b" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_a" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_b" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.chainin" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.fp32_in" out_port="fp16_sum_of_2_mult.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.reset" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.mode_sigs" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_a" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_b" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_a" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_b" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.chainin" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.fp32_in" out_port="fp16_sum_of_2_mult.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.top_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.top_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.bot_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.bot_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.top_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.top_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.bot_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.bot_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="fp16_sum_of_2_mult.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp16_sum_of_2_mult.clk"/>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp16_sum_of_2_mult.mode_sigs">
-            </direct>
-            <direct name="atoa_top" input="dsp_pb.datain[15:0]" output="fp16_sum_of_2_mult.top_a">
-            </direct>
-            <direct name="btob_top" input="dsp_pb.datain[31:16]" output="fp16_sum_of_2_mult.top_b">
-            </direct>
-            <direct name="result_top" input="fp16_sum_of_2_mult.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="atoa_bot" input="dsp_pb.datain[47:32]" output="fp16_sum_of_2_mult.bot_a">
-            </direct>
-            <direct name="btob_bot" input="dsp_pb.datain[63:48]" output="fp16_sum_of_2_mult.bot_b">
-            </direct>
-            <direct name="result_bot" input="fp16_sum_of_2_mult.result" output="dsp_pb.result[63:32]">
-            </direct>
-            <direct name="chainin" input="dsp_pb.chainin[31:0]" output="fp16_sum_of_2_mult.chainin">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]" output="fp16_sum_of_2_mult.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp16_sum_of_2_mult.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>        
-
-        <!-- floating point fp16 sum-of-2 accum mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b + accumulator. chainout = result)-->
-        <mode name="fp16_sum_of_products_2_accum_mode"> 
-          <pb_type name="fp16_sum_of_2_accum" blif_model=".subckt fp16_sop2_accum" num_pb="1">
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="reset" num_pins="1"/>
-            <input name="top_a" num_pins="16"/>
-            <input name="top_b" num_pins="16"/>
-            <input name="bot_a" num_pins="16"/>
-            <input name="bot_b" num_pins="16"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.mode_sigs" out_port="fp16_sum_of_2_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.top_a" out_port="fp16_sum_of_2_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.top_b" out_port="fp16_sum_of_2_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.bot_a" out_port="fp16_sum_of_2_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.bot_b" out_port="fp16_sum_of_2_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.reset" out_port="fp16_sum_of_2_accum.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.mode_sigs" out_port="fp16_sum_of_2_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.top_a" out_port="fp16_sum_of_2_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.top_b" out_port="fp16_sum_of_2_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.bot_a" out_port="fp16_sum_of_2_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.bot_b" out_port="fp16_sum_of_2_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.reset" out_port="fp16_sum_of_2_accum.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.top_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.top_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.bot_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.bot_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.top_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.top_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.bot_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.bot_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp16_sum_of_2_accum.mode_sigs"/>
-            <direct name="reset" input="dsp_pb.reset" output="fp16_sum_of_2_accum.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp16_sum_of_2_accum.clk"/>
-            <direct name="atoa_top" input="dsp_pb.datain[15:0]" output="fp16_sum_of_2_accum.top_a">
-            </direct>
-            <direct name="btob_top" input="dsp_pb.datain[31:16]" output="fp16_sum_of_2_accum.top_b">
-            </direct>
-            <direct name="result_top" input="fp16_sum_of_2_accum.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="atoa_bot" input="dsp_pb.datain[47:32]" output="fp16_sum_of_2_accum.bot_a">
-            </direct>
-            <direct name="btob_bot" input="dsp_pb.datain[63:48]" output="fp16_sum_of_2_accum.bot_b">
-            </direct>
-            <direct name="result_bot" input="fp16_sum_of_2_accum.result" output="dsp_pb.result[63:32]">
-            </direct>
-            <direct name="chainout" input="fp16_sum_of_2_accum.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>        
-
-        <!-- floating point fp16 mult, fp32 add mode (chainout = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b. result = chainin + third_inp)-->
-        <mode name="fp16_mult_fp32_add"> 
-          <pb_type name="fp16_mult_fp32_add" blif_model=".subckt fp16_mult_fp32_add" num_pb="1">
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="reset" num_pins="1"/>
-            <input name="top_a" num_pins="16"/>
-            <input name="top_b" num_pins="16"/>
-            <input name="bot_a" num_pins="16"/>
-            <input name="bot_b" num_pins="16"/>
-            <input name="fp32_in" num_pins="32"/>
-            <input name="chainin" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.reset" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.mode_sigs" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.top_a" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.top_b" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.bot_a" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.bot_b" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.chainin" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.fp32_in" out_port="fp16_mult_fp32_add.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.reset" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.mode_sigs" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.top_a" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.top_b" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.bot_a" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.bot_b" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.chainin" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.fp32_in" out_port="fp16_mult_fp32_add.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.top_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.top_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.bot_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.bot_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.top_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.top_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.bot_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.bot_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="fp16_mult_fp32_add.clk"/>
-            <direct name="reset" input="dsp_pb.reset" output="fp16_mult_fp32_add.reset"/>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp16_mult_fp32_add.mode_sigs">
-            </direct>
-            <direct name="atoa_top" input="dsp_pb.datain[15:0]" output="fp16_mult_fp32_add.top_a">
-            </direct>
-            <direct name="btob_top" input="dsp_pb.datain[31:16]" output="fp16_mult_fp32_add.top_b">
-            </direct>
-            <direct name="result_top" input="fp16_mult_fp32_add.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="atoa_bot" input="dsp_pb.datain[47:32]" output="fp16_mult_fp32_add.bot_a">
-            </direct>
-            <direct name="btob_bot" input="dsp_pb.datain[63:48]" output="fp16_mult_fp32_add.bot_b">
-            </direct>
-            <direct name="result_bot" input="fp16_mult_fp32_add.result" output="dsp_pb.result[63:32]">
-            </direct>
-            <direct name="chainin" input="dsp_pb.chainin[31:0]" output="fp16_mult_fp32_add.chainin">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]]" output="fp16_mult_fp32_add.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp16_mult_fp32_add.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>      
-
-        <!-- floating point fp16 mult, fp32 accum mode (chainout = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b. result = third_inp + accumulator)-->
-        <mode name="fp16_mult_fp32_accum"> 
-          <pb_type name="fp16_mult_fp32_accum" blif_model=".subckt fp16_mult_fp32_accum" num_pb="1">
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="reset" num_pins="1"/>
-            <input name="top_a" num_pins="16"/>
-            <input name="top_b" num_pins="16"/>
-            <input name="bot_a" num_pins="16"/>
-            <input name="bot_b" num_pins="16"/>
-            <input name="fp32_in" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.mode_sigs" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.top_a" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.top_b" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.bot_a" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.bot_b" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.fp32_in" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.reset" out_port="fp16_mult_fp32_accum.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.mode_sigs" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.top_a" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.top_b" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.bot_a" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.bot_b" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.fp32_in" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.reset" out_port="fp16_mult_fp32_accum.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.top_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.top_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.bot_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.bot_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.top_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.top_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.bot_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.bot_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp16_mult_fp32_accum.mode_sigs"/>
-            <direct name="reset" input="dsp_pb.reset" output="fp16_mult_fp32_accum.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp16_mult_fp32_accum.clk"/>
-            <direct name="atoa_top" input="dsp_pb.datain[15:0]" output="fp16_mult_fp32_accum.top_a">
-            </direct>
-            <direct name="btob_top" input="dsp_pb.datain[31:16]" output="fp16_mult_fp32_accum.top_b">
-            </direct>
-            <direct name="result_top" input="fp16_mult_fp32_accum.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="atoa_bot" input="dsp_pb.datain[47:32]" output="fp16_mult_fp32_accum.bot_a">
-            </direct>
-            <direct name="btob_bot" input="dsp_pb.datain[63:48]" output="fp16_mult_fp32_accum.bot_b">
-            </direct>
-            <direct name="result_bot" input="fp16_mult_fp32_accum.result" output="dsp_pb.result[63:32]">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]" output="fp16_mult_fp32_accum.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp16_mult_fp32_accum.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>      
-
-        <!-- floating point fp32 mult_then_add mode (result = fp32_mult_a * fp32_mult_b + chainin. chainout = third_inp or result) -->
-        <mode name="fp32_mult_then_add"> 
-          <pb_type name="fp32_mult_then_add" blif_model=".subckt fp32_mult_then_add" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <input name="fp32_in" num_pins="32"/>
-            <input name="chainin" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.reset" out_port="fp32_mult_then_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.mode_sigs" out_port="fp32_mult_then_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.a" out_port="fp32_mult_then_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.b" out_port="fp32_mult_then_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.chainin" out_port="fp32_mult_then_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.fp32_in" out_port="fp32_mult_then_add.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.reset" out_port="fp32_mult_then_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.mode_sigs" out_port="fp32_mult_then_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.a" out_port="fp32_mult_then_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.b" out_port="fp32_mult_then_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.chainin" out_port="fp32_mult_then_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.fp32_in" out_port="fp32_mult_then_add.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="fp32_mult_then_add.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp32_mult_then_add.clk"/>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp32_mult_then_add.mode_sigs">
-            </direct>
-            <direct name="atoa" input="dsp_pb.datain[31:0]" output="fp32_mult_then_add.a">
-            </direct>
-            <direct name="btob" input="dsp_pb.datain[63:32]" output="fp32_mult_then_add.b">
-            </direct>
-            <direct name="result" input="fp32_mult_then_add.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="chainin" input="dsp_pb.chainin[31:0]" output="fp32_mult_then_add.chainin">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]]" output="fp32_mult_then_add.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp32_mult_then_add.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>      
-
-        <!-- floating point fp32 mult_add mode (chainout = fp32_mult_a * fp32_mult_b. chainout = third_inp + chainin)-->
-        <mode name="fp32_mult_add"> 
-          <pb_type name="fp32_mult_add" blif_model=".subckt fp32_mult_add" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <input name="fp32_in" num_pins="32"/>
-            <input name="chainin" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.reset" out_port="fp32_mult_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.mode_sigs" out_port="fp32_mult_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.a" out_port="fp32_mult_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.b" out_port="fp32_mult_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.chainin" out_port="fp32_mult_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.fp32_in" out_port="fp32_mult_add.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.reset" out_port="fp32_mult_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.mode_sigs" out_port="fp32_mult_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.a" out_port="fp32_mult_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.b" out_port="fp32_mult_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.chainin" out_port="fp32_mult_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.fp32_in" out_port="fp32_mult_add.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp32_mult_add.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="fp32_mult_add.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp32_mult_add.clk"/>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp32_mult_add.mode_sigs">
-            </direct>
-            <direct name="atoa" input="dsp_pb.datain[31:0]" output="fp32_mult_add.a">
-            </direct>
-            <direct name="btob" input="dsp_pb.datain[63:32]" output="fp32_mult_add.b">
-            </direct>
-            <direct name="result" input="fp32_mult_add.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="chainin" input="dsp_pb.chainin[31:0]" output="fp32_mult_add.chainin">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]]" output="fp32_mult_add.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp32_mult_add.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>      
-      </pb_type>
-
-      <interconnect>
-        <direct name="mode_sigs" input="dsp.dsp_I1[11:0]" output ="dsp_pb.mode_sigs"/>
-        <direct name="datain1" input="dsp.dsp_I1[63:12]" output ="dsp_pb.datain[51:0]"/>
-        <direct name="datain2" input="dsp.dsp_I2" output ="dsp_pb.datain[115:52]"/>
-        <direct name="reset" input="dsp.reset" output="dsp_pb.reset"></direct>
-        <direct name="chainin" input="dsp.chainin"    output="dsp_pb.chainin"></direct>
-        <direct name="chainout" input="dsp_pb.chainout" output="dsp.chainout"></direct>
-        <direct name="scanin" input="dsp.scanin"    output="dsp_pb.scanin"></direct>
-        <direct name="scanout" input="dsp_pb.scanout" output="dsp.scanout"></direct>
-        <direct name="result" input="dsp_pb.result" output="dsp.result"></direct>
-        <direct name="clk" input="dsp.clk" output="dsp_pb.clk"></direct>
-      </interconnect>  
-
-    </pb_type>
-    <interconnect>
-        <!--50% sparse crossbar means 50% of the lines can reach an actual input of the dsp 
-        We do this by splitting inputs into two buckets and having two full crossbars-->
-        <!--
-       <complete name="first_half" input="dsp_top.dsp_I1" output="dsp.dsp_I1">
-            <delay_constant max="333e-12" in_port="dsp_top.dsp_I1" out_port="dsp.dsp_I1"/>
-       </complete>
-
-        <complete name="second_half" input="dsp_top.dsp_I2" output="dsp.dsp_I2">
-            <delay_constant max="333e-12" in_port="dsp_top.dsp_I2" out_port="dsp.dsp_I2"/>
-        </complete>
-        -->
-        <direct name="enable" input="dsp_top.dsp_I1[0]" output ="dsp.dsp_I1[0]"/>
-        <direct name="loadconst" input="dsp_top.dsp_I1[1]" output ="dsp.dsp_I1[1]"/>
-        <direct name="accumulate" input="dsp_top.dsp_I1[2]" output ="dsp.dsp_I1[2]"/>
-        <direct name="negate" input="dsp_top.dsp_I1[3]" output ="dsp.dsp_I1[3]"/>
-        <direct name="sub" input="dsp_top.dsp_I1[4]" output ="dsp.dsp_I1[4]"/>
-        <direct name="mode" input="dsp_top.dsp_I1[7:5]" output ="dsp.dsp_I1[7:5]"/>
-        <direct name="mux9_select" input="dsp_top.dsp_I1[8]" output ="dsp.dsp_I1[8]"/>
-        <direct name="internal_coeffa" input="dsp_top.dsp_I1[9]" output ="dsp.dsp_I1[9]"/>
-        <direct name="internal_coeffb" input="dsp_top.dsp_I1[10]" output ="dsp.dsp_I1[10]"/>
-        <direct name="datain1" input="dsp_top.dsp_I1[63:11]" output ="dsp.dsp_I1[63:11]"/>
-        <direct name="datain2" input="dsp_top.dsp_I2" output ="dsp.dsp_I2"/>
- 
-        <direct name="reset" input="dsp_top.reset" output="dsp.reset"></direct>
-        <direct name="chainin" input="dsp_top.chainin" output="dsp.chainin">
-            <delay_constant max="1179e-12" in_port="dsp_top.chainin" out_port="dsp.chainin"/>
-        </direct>
-        <direct name="chainout" input="dsp.chainout" output="dsp_top.chainout">
-            <delay_constant max="1179e-12" in_port="dsp.chainout" out_port="dsp_top.chainout"/>
-        </direct>
-        <direct name="scanin" input="dsp_top.scanin" output="dsp.scanin">
-            <delay_constant max="1179e-12" in_port="dsp_top.scanin" out_port="dsp.scanin"/>
-        </direct>
-        <direct name="scanout" input="dsp.scanout" output="dsp_top.scanout">
-            <delay_constant max="1179e-12" in_port="dsp.scanout" out_port="dsp_top.scanout"/>
-        </direct>
-        <direct name="result" input="dsp.result" output="dsp_top.result"></direct>
-        <direct name="clk" input="dsp_top.clk" output="dsp.clk"></direct>
-    </interconnect>
-    </pb_type>
-    <!-- Define DSP slice end -->
-
-
-    <!-- Define fracturable memory begin -->
-    <!-- 
-    RAM blocks always have registered inputs. The input FFs appear before the address decoder & wordline driver,
-    and after the local input crossbar & level shifter.
-    RAM blocks optionally have registered outputs. The output FFs (if present) appear after the output crossbar.
-    If BRAM doesn't have registered outputs, then T_clk_to_q is the whole delay of the read/write operation.
-    If BRAM does have registered output, then T_clk_to_q is just the FF clk_to_q and then delay_constant
-    can be used to specify the whole delay of the read/write operation.
-
-    This RAM block has registered outputs.
-
-    The area and delay values of this RAM block were obtained (indirectly) from COFFE simulations.
-    COFFE only support widths and depths that are powers of 2. For M20K (20 Kilobit BRAM), we need
-    the width to be 40 bits and depth to be 512 (for the logically widest mode: 512x40). We can't
-    simulate these dimensions directly in COFFE. So, we simulated and obtained the results for M32K
-    (32 Kilobits BRAM) and (16 Kilobits BRAM). Then we interpolated the results.
-    For delay, a linear interpolation was used, based on the size of the Memory (16K->20K->32K).
-    For area, the value was calculated using two interpolations: (1) port based (change in number of 
-    ports in going from 16K->20K->32K) and (2) number of bits based (change in number of bits in
-    going from 16K->20K->32K). The interpolation that resulted in the larger area was picked.
-    
-
-    Here are the equations used to calculate the delays based on COFFE results:
-    T_setup (inputs) = T_level_shifter + T_register_micro_setup = 32.3ps + 18.91ps = 51.21ps
-    T_clk_to_q (inputs) = T_register_micro_clk_to_q = 60.32ps
-    T_setup (outputs) = T_register_micro_setup = 18.91ps 
-    T_clk_to_q (outputs) = T_register_micro_clk_to_q = 60.32ps
-
-    (Register setup and clk_to_q timings are actually from the FF used in the logic cluster.)
-
-    T_read = T1 + T2 + T3
-    = max (Row decoder, Pre-charge time) + (Wordline driver + Bit line delay) + (Sense amp + Output crossbar)
-
-    * Bit line delay is included in self.RAM.samp.delay time in COFFE. The Sense amp delay is actually
-    self.RAM.samp_part2.delay
-
-    T_write = T1 + T2 + T3
-    = max (Row decoder, Pre-charge time) + (Wordline driver) + (Write driver)
-
-    delay_constant values model the internal limits of a block (the combinatorial delay).
-    delay_constant = max (T_read, T_write) 
-
-	  Overall internal delay of the RAM is T_clk_to_q (inputs) + delay_constant + T_setup (outputs)
-    -->
-    <pb_type name="memory">
-      <input name="addr1" num_pins="11"/>
-      <input name="addr2" num_pins="11"/>
-      <input name="data" num_pins="40"/>
-      <input name="we1" num_pins="1"/>
-      <input name="we2" num_pins="1"/>
-      <output name="out" num_pins="40"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Specify single port mode first -->
-      <mode name="mem_512x40_sp">
-        <pb_type name="mem_512x40_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="9" port_class="address"/>
-          <input name="data" num_pins="40" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="40" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-
-          <T_setup value="51.12e-12" port="mem_512x40_sp.addr" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_512x40_sp.data" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_512x40_sp.we" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_512x40_sp.out" clock="clk"/>
-
-          <T_clock_to_Q max="60.32e-12" port="mem_512x40_sp.addr" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_512x40_sp.data" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_512x40_sp.we" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_512x40_sp.out" clock="clk"/>
-
-          <delay_constant max="0.852e-9" in_port="mem_512x40_sp.addr" out_port="mem_512x40_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_512x40_sp.data" out_port="mem_512x40_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_512x40_sp.we"   out_port="mem_512x40_sp.out"/>
-
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[8:0]" output="mem_512x40_sp.addr">
-          </direct>
-          <direct name="data1" input="memory.data" output="mem_512x40_sp.data">
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_512x40_sp.we">
-          </direct>
-          <direct name="dataout1" input="mem_512x40_sp.out" output="memory.out">
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_512x40_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-
-      <mode name="mem_1024x20_sp">
-        <pb_type name="mem_1024x20_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="10" port_class="address"/>
-          <input name="data" num_pins="20" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="20" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-
-          <T_setup value="51.12e-12" port="mem_1024x20_sp.addr" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_sp.data" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_sp.we" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_1024x20_sp.out" clock="clk"/>
-
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_sp.addr" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_sp.data" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_sp.we" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_sp.out" clock="clk"/>
-
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_sp.addr" out_port="mem_1024x20_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_sp.data" out_port="mem_1024x20_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_sp.we"   out_port="mem_1024x20_sp.out"/>
-
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x20_sp.addr">
-          </direct>
-          <direct name="data1" input="memory.data[19:0]" output="mem_1024x20_sp.data">
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_1024x20_sp.we">
-          </direct>
-          <direct name="dataout1" input="mem_1024x20_sp.out" output="memory.out[19:0]">
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_1024x20_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-
-      <mode name="mem_2048x10_sp">
-        <pb_type name="mem_2048x10_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="11" port_class="address"/>
-          <input name="data" num_pins="10" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="10" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-
-          <T_setup value="51.12e-12" port="mem_2048x10_sp.addr" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_sp.data" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_sp.we" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_2048x10_sp.out" clock="clk"/>
-
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_sp.addr" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_sp.data" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_sp.we" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_sp.out" clock="clk"/>
-
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_sp.addr" out_port="mem_2048x10_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_sp.data" out_port="mem_2048x10_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_sp.we"   out_port="mem_2048x10_sp.out"/>
-
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x10_sp.addr">
-          </direct>
-          <direct name="data1" input="memory.data[9:0]" output="mem_2048x10_sp.data">
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_2048x10_sp.we">
-          </direct>
-          <direct name="dataout1" input="mem_2048x10_sp.out" output="memory.out[9:0]">
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_2048x10_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- Specify true dual port mode next -->
-      <mode name="mem_1024x20_dp">
-        <pb_type name="mem_1024x20_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="addr1" num_pins="10" port_class="address1"/>
-          <input name="addr2" num_pins="10" port_class="address2"/>
-          <input name="data1" num_pins="20" port_class="data_in1"/>
-          <input name="data2" num_pins="20" port_class="data_in2"/>
-          <input name="we1" num_pins="1" port_class="write_en1"/>
-          <input name="we2" num_pins="1" port_class="write_en2"/>
-          <output name="out1" num_pins="20" port_class="data_out1"/>
-          <output name="out2" num_pins="20" port_class="data_out2"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.addr1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.data1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.we1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.addr2" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.data2" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.we2" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_1024x20_dp.out1" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_1024x20_dp.out2" clock="clk"/>
-
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.addr1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.data1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.we1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.addr2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.data2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.we2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.out1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.out2" clock="clk"/>
-
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.addr1" out_port="mem_1024x20_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.data1" out_port="mem_1024x20_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.we1" out_port="mem_1024x20_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.addr2" out_port="mem_1024x20_dp.out2"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.data2" out_port="mem_1024x20_dp.out2"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.we2" out_port="mem_1024x20_dp.out2"/>
-
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x20_dp.addr1">
-          </direct>
-          <direct name="address2" input="memory.addr2[9:0]" output="mem_1024x20_dp.addr2">
-          </direct>
-          <direct name="data1" input="memory.data[19:0]" output="mem_1024x20_dp.data1">
-          </direct>
-          <direct name="data2" input="memory.data[39:20]" output="mem_1024x20_dp.data2">
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_1024x20_dp.we1">
-          </direct>
-          <direct name="writeen2" input="memory.we2" output="mem_1024x20_dp.we2">
-          </direct>
-          <direct name="dataout1" input="mem_1024x20_dp.out1" output="memory.out[19:0]">
-          </direct>
-          <direct name="dataout2" input="mem_1024x20_dp.out2" output="memory.out[39:20]">
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_1024x20_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-
-      <mode name="mem_2048x10_dp">
-        <pb_type name="mem_2048x10_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="addr1" num_pins="11" port_class="address1"/>
-          <input name="addr2" num_pins="11" port_class="address2"/>
-          <input name="data1" num_pins="10" port_class="data_in1"/>
-          <input name="data2" num_pins="10" port_class="data_in2"/>
-          <input name="we1" num_pins="1" port_class="write_en1"/>
-          <input name="we2" num_pins="1" port_class="write_en2"/>
-          <output name="out1" num_pins="10" port_class="data_out1"/>
-          <output name="out2" num_pins="10" port_class="data_out2"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.addr1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.data1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.we1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.addr2" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.data2" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.we2" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_2048x10_dp.out1" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_2048x10_dp.out2" clock="clk"/>
-
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.addr1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.data1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.we1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.addr2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.data2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.we2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.out1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.out2" clock="clk"/>
-
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.addr1" out_port="mem_2048x10_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.data1" out_port="mem_2048x10_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.we1" out_port="mem_2048x10_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.addr2" out_port="mem_2048x10_dp.out2"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.data2" out_port="mem_2048x10_dp.out2"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.we2" out_port="mem_2048x10_dp.out2"/>
-
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x10_dp.addr1">
-          </direct>
-          <direct name="address2" input="memory.addr2[10:0]" output="mem_2048x10_dp.addr2">
-          </direct>
-          <direct name="data1" input="memory.data[9:0]" output="mem_2048x10_dp.data1">
-          </direct>
-          <direct name="data2" input="memory.data[19:10]" output="mem_2048x10_dp.data2">
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_2048x10_dp.we1">
-          </direct>
-          <direct name="writeen2" input="memory.we2" output="mem_2048x10_dp.we2">
-          </direct>
-          <direct name="dataout1" input="mem_2048x10_dp.out1" output="memory.out[9:0]">
-          </direct>
-          <direct name="dataout2" input="mem_2048x10_dp.out2" output="memory.out[19:10]">
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_2048x10_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-    </pb_type>
-    <!-- Define fracturable memory end -->
-  </complexblocklist>
-
-  <switchblocklist>
-    <!-- Stratix IV uses a uni-directional routing architecture with a Driver Input Mux (DIM) size of 12 (i.e.
-           each wire can be driven by one of 12 block/outputs or wires) for the L4s.
-           
-           In the Stratix IV architecture the long wires (L16 here) are accessible only from the short wires, 
-           and are not connected to the block pins (i.e. connection blocks). Furthermore, they only connect 
-           to switch blocks every 4 LABs (to avoid expensive deep via stacks).
-           We approximate the L16 DIM size as 40:1 (in reality it is a pair of 20:1 (?) muxes with a 2:1 swap mux
-           in front, which has nearly the same connectivity as a full 40:1).
-
-           L4 wires
-           ================
-           At a channel width of 300 there are 260 L4/L4prime wires. At an effective Fc_out of 0.075 
-           and 40 LAB outputs this yeilds:
-
-                40 * 2 = 80 outputs per channel  [2 LABs per-channel]
-
-                80 * 0.075 = 6 outputs drive each L4 wire [output connection block]
-
-           This leaves:
-
-                12 - 6 = 6 inputs to the DIMs from other routing wires [switch block]
-
-           Since L4s connect at every switch block, there are:
-
-                260 L16 wires per channel + direction which can drive wires at a particular switchblock
-                (via switchpoints 0, 1, 2, 3)
-
-           And for each direction (260 wires) only:
-
-               260 / 4 = 65 wires starting/ending per channel + direction at each switch block
-               (i.e. from each direction, north/south/east/west, there are 32 L4s starting, and 32 L4s ending; + 1 wire for the 65th)
-
-           Which we allocate as follows:
-
-                L4
-                =====
-                straight-through connection: 2 (from L4 or L16)
-                clock-wise turn            : 2 (from L4 or L16)
-                counter-clock-wise turn    : 2 (from L4 or L16)
-
-           L16 wires
-           =========
-           At a channel width of 300 there are 40 L16 wires (20 in each direction), which do not connect to the input/output connection blocks.
-           This leaves 40 inputs to the DIM to select from routing wires (long wires use larger DIMs to improve reachability,
-           the area cost is relatively small since they are so rare).
-
-           Since L16s only connect at every 4th switch block there are:
-
-                40 / 4 = 10 L16 wires per channel (5 in each direction) which can drive wires at a particular switchblock
-                (via switchpoints 0, 4, 8, 12)
-
-           And for each direction (20 wires) only:
-
-               40 / 16 = 2.25 => 2 wires starting/ending per channel + direction at each switch block
-               (i.e. from each direction, north/south/east/west, there is one L16 starting, and one L16 ending)
-           
-           We assign the 40 DIM inputs as follows:
-
-                L16
-                =====
-                straight-through connection:  3 (from L16)
-                straight-through connection: 11 (from L4)
-                clock-wise turn            :  3 (from L16)
-                clock-wise turn            : 10 (from L4)
-                counter clock-wise turn    :  3 (from L16)
-                counter clock-wise turn    : 10 (from L4)
-
-           Switch pattern
-           ==============
-           This switch block is based on the Wilton switch block (see Page 103 of Steve Wilton's PhD Thesis 
-           "Architecture and Algorithms for Field-Programmable Gate Arrays with Embedded Memory", 1997):
-
-                left-to-top: W - t
-                top-to-right: t + 1
-                right-to-bottom: 2*W - 2 - t
-                bottom-to-left: t + 1
-                left-to-right: t
-                top-to-bottom: t
-
-           Since Wilton assumed bidirection routing (while we use unidirectional routing),
-           we mirror the clock-wise turns to match the conter-clock-wise specification.
-           -->
-    <switchblock name="wilton_turn_clockwise_core" type="unidir">
-      <switchblock_location type="CORE"/>
-      <switchfuncs>
-        <!-- Clock-wise turns -->
-        <func type="tl" formula="W-t"/>
-        <!-- top to left -->
-        <func type="rt" formula="t+1"/>
-        <!-- right to top -->
-        <func type="br" formula="2*W-2-t"/>
-        <!-- bottom to right -->
-        <func type="lb" formula="t+1"/>
-        <!-- left to bottom -->
-      </switchfuncs>
-      <!-- L16 drivers -->
-      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
-      <wireconn num_conns="10*to" from_type="L4" from_switchpoint="0" to_type="L16" to_switchpoint="0"/>
-      <!-- L4 drivers 
-
-               Driving from L16 (few) to L4 (many) preferr driving from end-point of L16, although since there are many they will
-               all be multiply connected.
-               
-               Driving from L4 (many) to L4 (many) shuffle the switchpoints so the L4's are driven from a variety of switchpoints.
-               Since the actual number L4s starting/ending are equal, using 'fixed' from_order would mean only switchpoint 0 -> 0
-               connections. A 'shuffled' order will mix-up the from switchpoints for more diversity.
-               -->
-      <wireconn num_conns="2*to" from_order="shuffled">
-        <from type="L16" switchpoint="0,12,8,4"/>
-        <from type="L4" switchpoint="0,1,2,3"/>
-        <to type="L4" switchpoint="0"/>
-      </wireconn>
-    </switchblock>
-    <switchblock name="wilton_turn_counter_clockwise_core" type="unidir">
-      <switchblock_location type="CORE"/>
-      <switchfuncs>
-        <!-- Counter-clock-wise turns -->
-        <func type="lt" formula="W-t"/>
-        <!-- left to top -->
-        <func type="tr" formula="t+1"/>
-        <!-- top to right -->
-        <func type="rb" formula="2*W-2-t"/>
-        <!-- right to bottom -->
-        <func type="bl" formula="t+1"/>
-        <!-- bottom to left -->
-      </switchfuncs>
-      <!-- L16 drivers -->
-      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
-      <wireconn num_conns="10*to" from_type="L4" from_switchpoint="0" to_type="L16" to_switchpoint="0"/>
-      <!-- L4 drivers 
-
-               Driving from L16 (few) to L4 (many) preferr driving from end-point of L16, although since there are many they will
-               all be multiply connected.
-               
-               Driving from L4 (many) to L4 (many) shuffle the switchpoints so the L4's are driven from a variety of switchpoints.
-               Since the actual number L4s starting/ending are equal, using 'fixed' from_order would mean only switchpoint 0 -> 0
-               connections. A 'shuffled' order will mix-up the from switchpoints for more diversity.
-
-               Note that a different from_switchpoints ordering is used to ensure a different shuffling occurs compared to 
-               wilton_turn_clockwise_core.
-               -->
-      <wireconn num_conns="2*to" from_order="shuffled">
-        <from type="L16" switchpoint="0,12,8,4"/>
-        <from type="L4" switchpoint="0,1,2,3"/>
-        <to type="L4" switchpoint="0"/>
-      </wireconn>
-    </switchblock>
-    <switchblock name="wilton_straight" type="unidir">
-      <switchblock_location type="EVERYWHERE"/>
-      <switchfuncs>
-        <!-- Straight -->
-        <func type="lr" formula="t"/>
-        <!-- left to right -->
-        <func type="tb" formula="t"/>
-        <!-- top to bottom -->
-        <func type="rl" formula="t"/>
-        <!-- right to left -->
-        <func type="bt" formula="t"/>
-        <!-- bottom to top -->
-      </switchfuncs>
-      <!-- L16 Drivers 
-                Note that we order the switchpoints in order of preference, since VPR currently
-                iterates through the source sets in order, such that we connect first to wires
-                ending at the switchblock (switchpoint 0), and then fallback to switchpoints
-                in decreasing distance from the drive point (if we have more to's than from's
-                it then wraps around).
-
-                Note also that we multiply the number of expected connections by 'to', since while usually
-                there is only one 'to' wire, ocasionally there may be more, and we want to ensure they all
-                get the same number of connections.
-
-                For L16->L16:
-                  We allow any valid switchpoint to be used as the 'from' point.
-                  Allow 'low' switchpoints like '4' may seem counter-intuitive (i.e. why not use a cheaper L4)
-                  this makes it easier to bypass once on the L16 network (e.g. to get around congestion).
-           -->
-      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
-      <wireconn num_conns="11*to" from_type="L4" from_switchpoint="0,3,2,1" to_type="L16" to_switchpoint="0"/>
-      <!-- L4 Drivers -->
-      <wireconn num_conns="2*to" from_order="shuffled">
-        <from type="L16" switchpoint="0,12,8,4"/>
-        <from type="L4" switchpoint="0"/>
-        <to type="L4" switchpoint="0"/>
-      </wireconn>
-      <!--<wireconn num_conns="1*to" from_type="L4" from_switchpoint="0" to_type="L4" to_switchpoint="0"/>-->
-      <!--<wireconn num_conns="1*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L4" to_switchpoint="0"/>-->
-    </switchblock>
-    <switchblock name="wilton_straight_corner" type="unidir">
-      <!-- Same as wilton straight, but turning around a corner -->
-      <switchblock_location type="CORNER"/>
-      <switchfuncs>
-        <!-- Counter-clock-wise turns -->
-        <func type="lt" formula="t"/>
-        <!-- left to top -->
-        <func type="tr" formula="t"/>
-        <!-- top to right -->
-        <func type="rb" formula="t"/>
-        <!-- right to bottom -->
-        <func type="bl" formula="t"/>
-        <!-- bottom to left -->
-        <!-- Clock-wise turns -->
-        <func type="tl" formula="t"/>
-        <!-- top to left -->
-        <func type="rt" formula="t"/>
-        <!-- right to top -->
-        <func type="br" formula="t"/>
-        <!-- bottom to right -->
-        <func type="lb" formula="t"/>
-        <!-- left to bottom -->
-      </switchfuncs>
-      <!-- L16 Drivers -->
-      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
-      <wireconn num_conns="11*to" from_type="L4" from_switchpoint="0,3,2,1" to_type="L16" to_switchpoint="0"/>
-      <!-- L4 Drivers -->
-      <wireconn num_conns="2*to" from_order="shuffled">
-        <from type="L16" switchpoint="0,12,8,4"/>
-        <from type="L4" switchpoint="0"/>
-        <to type="L4" switchpoint="0"/>
-      </wireconn>
-      <!--<wireconn num_conns="1*to" from_type="L4" from_switchpoint="0" to_type="L4" to_switchpoint="0"/>-->
-      <!--<wireconn num_conns="1*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L4" to_switchpoint="0"/>-->
-    </switchblock>
-    <switchblock name="wilton_turn_fringe" type="unidir">
-      <!-- Non-corner perimeter SBs -->
-      <switchblock_location type="FRINGE"/>
-      <switchfuncs>
-        <!-- Counter-clock-wise turns -->
-        <func type="lt" formula="W-t"/>
-        <!-- left to top -->
-        <func type="tr" formula="t+1"/>
-        <!-- top to right -->
-        <func type="rb" formula="2*W-2-t"/>
-        <!-- right to bottom -->
-        <func type="bl" formula="t+1"/>
-        <!-- bottom to left -->
-        <!-- Clock-wise turns -->
-        <func type="tl" formula="W-t"/>
-        <!-- top to left -->
-        <func type="rt" formula="t+1"/>
-        <!-- right to top -->
-        <func type="br" formula="2*W-2-t"/>
-        <!-- bottom to right -->
-        <func type="lb" formula="t+1"/>
-        <!-- left to bottom -->
-      </switchfuncs>
-      <!-- We use 'max' style connections here to ensure there are no dangling wires, otherwise like core turns -->
-      <!-- L16 drivers -->
-      <wireconn num_conns="3*max(from,to)" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
-      <wireconn num_conns="21*max(from,to)" from_type="L4" from_switchpoint="0" to_type="L16" to_switchpoint="0"/>
-      <!-- L4 drivers -->
-      <wireconn num_conns="1*max(from,to)" from_type="L16" from_switchpoint="0,12,8,4" from_order="fixed" to_type="L4" to_switchpoint="0"/>
-      <wireconn num_conns="1*max(from,to)" from_type="L4" from_switchpoint="0,1,2,3" from_order="shuffled" to_type="L4" to_switchpoint="0"/>
-    </switchblock>
-  </switchblocklist>
-
-  <clocks>
-    <clock buffer_size="auto" C_wire="2.5e-10"/>
-  </clocks>
-</architecture>
-
-
diff --git a/vtr_flow/arch/multi_die/k6FracN10LB_mem20K_complexDSP_customSB_22nm_OPINs.xml b/vtr_flow/arch/multi_die/k6FracN10LB_mem20K_complexDSP_customSB_22nm_OPINs.xml
deleted file mode 100644
index d9cb89e9d34..00000000000
--- a/vtr_flow/arch/multi_die/k6FracN10LB_mem20K_complexDSP_customSB_22nm_OPINs.xml
+++ /dev/null
@@ -1,3290 +0,0 @@
-<!--
-    This is the architecture file for a modern Intel FPGA. The blocks (logic, RAM, DSP)
-    are Agilex-like, but the routing architecture is similar to Stratix IV. It is based
-    off the Stratix-10-like Architecture discussed in [1], the Agilex-like Architecture
-    mentioned in [6] and Stratix-IV-like Architecture mentioned in [5].
-
-    The delays and areas of various components in this arch come from COFFE [2]
-    runs using a 22nm technology node [3].
-
-    ##############################
-    Parameters
-    ##############################
-    Parameter | Value | Definition
-    __________|_______|______________________________
-    N         |    10 | Number of BLEs per cluster
-    W         |   300 | Channel width
-    L         |  4,16 | Wire segment length
-    I         |    60 | Number of cluster inputs
-    O         |    40 | Number of cluster outputs
-    K         |     6 | LUT size
-    Fs        |     3 | Switch block flexibility
-    Fcin      |  0.15 | Cluster input flexibility
-    Fcout     |   0.1 | Cluster output flexibility
-    Fclocal   |   0.5 | Local input crossbar population
-
-    ##############################
-    Logic Cluster
-    ##############################
-    This architecture has 10 ALMs (or FLEs: Fracturable Logic Elements) per Logic Cluster
-    (or LAB or CLB), where each ALM is a 6-LUT fracturable into
-    two 5-LUTs. The ALM has 8 inputs and 4 optionally registered outputs.The two 5-LUTs should
-    share at least two inputs. Each two ALM outputs are logically equivalent, which means any
-    output signal that can reach ALM.out[0] can reach ALM.out[1] and the same thing for
-    ALM.out[2] and ALM.out[3]. The ALMs in this architecture have an arithmetic mode
-    where each 5-LUT is fractured into two 4-LUTs, resulting in a total of four 4-LUTs and two
-    bits of addition per ALM. This architecture has a single carry chain that spans the 10 ALMs
-    in the LAB.
-
-    The LAB (or Logic Cluster or CLB) has 60 inputs and 40 outputs. Two outputs of each ALM are fed 
-    to the right and left LAB using direct links and are also fed back to the LAB as feedback connections 
-    sharing the 60 input ports with the signals coming from the routing channels.
-
-    The LAB has a 50% sparsely populated input crossbar.
-    
-    ##############################
-    DSP Slice
-    ##############################
-    This architecture has a DSP block that supports the following modes:
-
-    Fixed point modes:
-    _________________
-    1. 27x27 fixed point multiplier (multiply)
-    2. 27x27 fixed point mac (mac_int_27x27)
-    3. Two 18x19 fixed point multipliers (multiply)
-    4. Two 18x19 fixed point macs (mac_int_18x19)
-    5. Four 9x9 fixed point multipliers (multiply)
-    6. Four 9x9 fixed point macs (mac_int_9x9)
-    7. 27x27 plus 64 mode (mult_add_mode_27_27_64/mult_add_int_27x27). 27 * 27 + 64 -> 64. result = ax * ay + bx + chainin. chainout = result 
-    8. 18x19 sum-of-2 mode (sop_2_mode/int_sop_2) result = (bx * by) + (ax * ay) + chainin. chainout = result    
-    9. 18x19 plus 36 mode (mult_add_mode_18_19_36/mult_add_int_18x19). 18 * 19 + 36 -> 64. result = ax * ay + bx + chainin. chainout = result 
-    10. 9x9 sum-of-4 mode (sop_4_mode/int_sop_4) result = (dx * dy) + (cx * cy) + (bx * by) + (ax * ay) + chainin. chainout = result 
-    11. 9x9 sum-of-4 accum mode (sop_4_accum_mode/int_sop_accum_4) result = (dx * dy) + (cx * cy) + (bx * by) + (ax * ay) + chainin + accumulator. chainout = result 
-
-    Floating point modes:
-    ____________________
-
-    IMPORTANT:
-    The precisions supported are IEEE floating point 32-bit, IEEE floating point 16-bit and
-    Brain floating point (BF16). In the 16-bit mode descriptions, wherever "fp16" is used, it
-    refers to either IEEE floating point 16-bit or BF16. There are mode bits on the DSP slice
-    that can be used to differentiate between them. Doing this saves the effort of explicitly
-    specifying all the 16-bit modes twice in this file. 
-    Since the goal is architectural exploration and not functional simulation, the mode bits 
-    can be specified to any random value while instantiating the DSP slice in a Verilog benchmark.
-
-    1A. One fp32 multiplier (mult_fp_32)
-    1B. One fp32 multiplier, clocked (mult_fp_clk_32)
-    2A. One fp32 adder/subtractor (addition_fp_32)
-    2B. One fp32 adder/subtractor, clocked (addition_fp_clk_32)
-    3. One fp32 mac (mac_fp_32)
-    4A. Two fp16 multipliers (mult_fp_16)
-    4B. Two fp16 multipliers, clocked (mult_fp_clk_16)
-    5A. Two fp16 adders/subtractors (addition_fp_16)
-    5B. Two fp16 adders/subtractors, clocked (addition_fp_clk_16)
-    6. Two fp16 macs (mac_fp_16)
-    7. floating point fp16 sum-of-products mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b. chainout = third_inp or result) (fp16_sum_of_products_mode/fp16_mult_add)
-    8. floating point fp16 sum-of-2 mult mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b + fp32 chainin or third inp. chainout = third_inp or result) (fp16_sum_of_products_2_mult_mode/fp16_sop2_mult)
-    9. floating point fp16 sum-of-2 accum mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b + accumulator. chainout = result) (fp16_sum_of_products_2_accum_mode/fp16_sop2_accum)
-    10. floating point fp16 mult, fp32 add mode (chainout = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b. result = chainin + third_inp) (fp16_mult_fp32_add/fp16_mult_fp32_add)
-    11. floating point fp16 mult, fp32 accum mode (chainout = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b. result = third_inp + accumulator) (fp16_mult_fp32_accum/fp16_mult_fp32_accum)
-    12. floating point fp32 mult_then_add mode (result = fp32_mult_a * fp32_mult_b + chainin. chainout = third_inp or result) (fp32_mult_then_add/fp32_mult_then_add)
-    13. floating point fp32 mult_add mode (chainout = fp32_mult_a * fp32_mult_b. chainout = third_inp + chainin) (fp32_mult_add/fp32_mult_add)
-
-    The DSP block was designed in Verilog and COFFE's [2] hybrid flow was used to generate
-    area and delay results. The standard cell library used was Cadence GPDK 45nm (gsclib045_svt_v4.4)
-    and area/delay scaling euqations from [4] were used.
-
-    A 50% sparsely populated input crossbar was added to the DSP block but is commented out.
-    It was leading to a failure in in VPR. See the discussion on this commit: 
-    https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ea7acf1582ece35e892c26b756aa302d2e12ddb2
-
-    Once this is fixed, the input crossbar code can be enabled.
-
-    ##############################
-    Memory Blocks
-    ##############################
-    The architecture also has a 20Kb memory blocks (or M20k or BRAM) that has true and simple dual port modes. 
-    In simple dual port mode the memory can be configured in the following modes: 512x40, 1024x20 and 2048x10,
-    while in true dual port mode it can be configured as: 1024x20 and 2048x10.
-
-    The BRAM has registered inputs and outputs. See details on how the delays for this block were 
-    obtained, in the comments before the specification of the BRAM primitive, towards the end of this file.
-
-    The BRAM doesn't have an input crossbar. Adding an input crossbar was leading to a 
-    seg fault in VPR, likely because of https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1475
-
-    Once this is fixed, an input crossbar can be added. The input crossbar delay from COFFE was: 29.47ps
-
-    ##############################
-    Routing/Interconnect
-    ##############################
-    The routing channel width is 300. Note that the channel width isn't specified directly in this arch file. 
-    Switch pattern calculations assume that value. During experiments, channel width can be specified using 
-    the command line switch `route_chan_width`.
-    The architecture uses unidirectional routing with wire segments of length 4 (260 out of 300 wires) and 
-    length 16 (40 out of 300 wires). The length 16 wires do not directly connect to block pins and are only 
-    accessible from the length 4 wires. Switches appear after every 4 blocks on the length 16 wires. 
-    The switch blocks use a custom switching pattern based on the Stratix-IV-like architecture used in the 
-    Titan flow [5]. 
-
-    ##############################
-    I/Os
-    ##############################
-    I/O pads are arranged along the perimeter of the FPGA. No area values provided for the I/Os.
-
-    ##############################
-    Comments on similarities and differences with Intel FPGA architecture.
-    ##############################
-    The main parameters of the logic blocks, DSPs and RAMs are similar to Intel FPGAs. But here are
-    some important points:
-    1. The DSP slice supports lower precision modes - int8 (actually 9x9) and 16-bit floating point
-       (IEEE half-precision and bfloat16). These modes are present in Intel Agilex FPGA DSPs.
-    2. DSPs are chained in vertical direction (chainin-chainout connections for output cascading
-       and scanin-scanout connections for input cascading). This is a common feature
-       in modern FPGAs.
-    3. There are no registers on the interconnect/routing wires in this architecture. That is a main
-       feature in the Stratix10 and Agilex families of Intel FPGA (it's called HyperFlex by Intel).
-    4. The architecture doesn't have sectors. All blocks are laid out in columns on the entire chip.
-       Most modern Intel FPGAs have sector based layout.
-    5. The IOs are on the perimeter, instead of being arranged in columns. Modern FPGAs arrange I/Os in
-       columns.
-    6. The routing architecture is similar to Stratix IV. There are wire segments of L=4 
-       and L=16. And a custom switch pattern (not a standard wilton switch) is used. 
-
-    [1] M. Eldafrawy, A. Boutros, S. Yazdanshenas, and V. Betz, "FPGA Logic Block Architectures for
-        Efficient Deep Learning Inference" in ACM TRETS, 2020
-    [2] S. Yazdanshenas, and V. Betz, "COFFE 2: Automatic Modelling and Optimization of
-        Complex and Heterogeneous FPGA Architectures" in ACM TRETS, 2019. 
-    [3] PTM High Performance 22nm Metal Gate / High-K / Strained-Si 22NM_BULK_HP, from http://ptm.asu.edu/
-        See: https://github.com/vaughnbetz/COFFE/blob/master/spice_models/ptm_22nm_bulk_hp.l
-    [4] A. Stillmaker and B. Baas, "Scaling equations for the accurate prediction of CMOS device 
-        performance from 180 nm to 7 nm" in Integration, the VLSI Journal (2017)
-    [5] K. E. Murray et al., “Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap between 
-        Academic and Commercial CAD,” TRETS 2015.
-    [6] A. Arora et al., "Tensor Slices to the Rescue: Supercharging ML Acceleration on FPGAs", ISFPGA 2020.
--->
-
-<architecture>
-  <!-- 
-         ODIN II specific config begins 
-         Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-         ".model [type_of_block]") that this architecture supports.
-
-         Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-         already special structures in blif (.names, .input, .output, and .latch) 
-         that describe them.
-    -->
-  <models>
-    <model name="single_port_ram">
-      <input_ports>
-        <port name="we" clock="clk" combinational_sink_ports="out"/>
-        <!-- control -->
-        <port name="addr" clock="clk" combinational_sink_ports="out"/>
-        <!-- address lines -->
-        <port name="data" clock="clk" combinational_sink_ports="out"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="clk" is_clock="1"/>
-        <!-- memories are often clocked -->
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-      </output_ports>
-    </model>
-    <model name="dual_port_ram">
-      <input_ports>
-        <port name="we1" clock="clk" combinational_sink_ports="out1"/>
-        <!-- write enable -->
-        <port name="we2" clock="clk" combinational_sink_ports="out2"/>
-        <!-- write enable -->
-        <port name="addr1" clock="clk" combinational_sink_ports="out1"/>
-        <!-- address lines -->
-        <port name="addr2" clock="clk" combinational_sink_ports="out2"/>
-        <!-- address lines -->
-        <port name="data1" clock="clk" combinational_sink_ports="out1"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="data2" clock="clk" combinational_sink_ports="out2"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="clk" is_clock="1"/>
-        <!-- memories are often clocked -->
-      </input_ports>
-      <output_ports>
-        <port name="out1" clock="clk"/>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-        <port name="out2" clock="clk"/>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-      </output_ports>
-    </model>
-    <!-- Used inside DSPs. 
-         Fixed point multiplication.
-         ODIN infers these when * sign appears in RTL. -->
-    <model name="multiply">
-      <input_ports>
-        <port name="a" combinational_sink_ports="out"/>
-        <port name="b" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out"/>
-      </output_ports>
-    </model>
-    <!-- Used inside DSPs. 
-         Floating point multiplication. -->
-    <model name="mult_fp_16">
-      <input_ports>
-        <port name="a" combinational_sink_ports="out"/>
-        <port name="b" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out"/>
-      </output_ports>
-    </model>   
-    <model name="mult_fp_32">
-      <input_ports>
-        <port name="a" combinational_sink_ports="out"/>
-        <port name="b" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out"/>
-      </output_ports>
-    </model>   
-    <model name="mult_fp_clk_16">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <model name="mult_fp_clk_32">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <!-- Only used inside CLBs for 1-bit adder.
-         ODIN infers these when + sign appears in RTL.
-         Can't use this inside DSP slice
-         because ODIN gets confused and starts to connect multi
-         bit adders and single bit adders in different PBs -->
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="cout sumout"/>
-        <port name="b" combinational_sink_ports="cout sumout"/>
-        <port name="cin" combinational_sink_ports="cout sumout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- Multi bit floating point adder inside DSP slices -->
-    <model name="addition_fp_16">
-      <input_ports>
-        <port name="a" combinational_sink_ports="out"/>
-        <port name="b" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out"/>
-      </output_ports>
-    </model>
-    <model name="addition_fp_32">
-      <input_ports>
-        <port name="a" combinational_sink_ports="out"/>
-        <port name="b" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out"/>
-      </output_ports>
-    </model>
-    <model name="addition_fp_clk_16">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <model name="addition_fp_clk_32">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="int_sop_2">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ax" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ay" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="by" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="mult_add_int_27x27">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="ax" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="ay" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="bx" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="scanin" clock="clk" combinational_sink_ports="result scanout chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-        <port name="scanout"/>
-      </output_ports>
-    </model>
-    <model name="mult_add_int_18x19">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="ax" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="ay" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="bx" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result scanout chainout"/>
-        <port name="scanin" clock="clk" combinational_sink_ports="result scanout chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-        <port name="scanout"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="int_sop_4">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ax" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ay" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="by" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="cx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="cy" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="dx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="dy" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="int_sop_accum_4">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ax" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="ay" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="by" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="cx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="cy" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="dx" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="dy" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>
-    <!-- Floating point MAC inside DSP slices -->
-    <model name="mac_fp_16">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="out"/>
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <model name="mac_fp_32">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="out"/>
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <!-- Fixed point MAC inside DSP slices -->
-    <model name="mac_int_27x27">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="out"/>
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <model name="mac_int_18x19">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="out"/>
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <model name="mac_int_9x9">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="out"/>
-        <port name="a" clock="clk" combinational_sink_ports="out"/>
-        <port name="b" clock="clk" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="fp16_mult_add">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model> 
-    <!--A mode in DSP slice-->
-    <model name="fp16_sop2_mult">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model> 
-    <!--A mode in DSP slice-->
-    <model name="fp16_sop2_accum">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_b" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="fp16_mult_fp32_add">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>    
-    <!--A mode in DSP slice-->
-    <model name="fp16_mult_fp32_accum">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="top_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="bot_b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model>
-    <!--A mode in DSP slice-->
-    <model name="fp32_mult_add">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model> 
-    <!--A mode in DSP slice-->
-    <model name="fp32_mult_then_add">
-      <input_ports>
-        <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="a" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="b" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="fp32_in" clock="clk" combinational_sink_ports="result chainout"/>
-        <port name="chainin" clock="clk" combinational_sink_ports="result chainout"/>
-      </input_ports>
-      <output_ports>
-        <port name="result" clock="clk"/>
-        <port name="chainout"/>
-      </output_ports>
-    </model> 
-  </models>
-  <tiles>
-    <tile name="io" area="0">
-      <sub_tile name="io" capacity="8">
-        <equivalent_sites>
-          <site pb_type="io" pin_mapping="direct"/>
-        </equivalent_sites>
-        <input name="outpad" num_pins="1"/>
-        <output name="inpad" num_pins="1"/>
-        <clock name="clock" num_pins="1"/>
-        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-        <pinlocations pattern="custom">
-          <loc side="left" layer_offset="1">io.inpad</loc>
-          <loc side="left">io.outpad io.clock</loc>
-          <loc side="top" layer_offset="1">io.inpad</loc>
-          <loc side="top">io.outpad io.clock</loc>
-          <loc side="right" layer_offset="1">io.inpad</loc>
-          <loc side="right">io.outpad io.clock</loc>
-          <loc side="bottom" layer_offset="1">io.inpad</loc>
-          <loc side="bottom">io.outpad io.clock</loc>
-        </pinlocations>
-      </sub_tile>
-    </tile>
-    <tile name="clb" height="1" width="1" area="27905">
-      <sub_tile name="clb">
-        <equivalent_sites>
-          <site pb_type="clb" pin_mapping="direct"/>
-        </equivalent_sites>
-        <input name="I1" num_pins="15" equivalent="full"/>
-        <input name="I2" num_pins="15" equivalent="full"/>
-        <input name="I3" num_pins="15" equivalent="full"/>
-        <input name="I4" num_pins="15" equivalent="full"/>
-        <input name="cin" num_pins="1"/>
-        <output name="O" num_pins="40" equivalent="none"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-          <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-          <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-          <!-- clock pins do not connect to local routing -->
-          <fc_override fc_type="frac" fc_val="0" port_name="clk"/>
-        </fc>
-        <pinlocations pattern="custom">
-          <loc side="top"> clb.I1[0] clb.I1[4] clb.I1[8] clb.I1[12] clb.I2[1] clb.I2[5] clb.I2[9] clb.I2[13] clb.I3[2] clb.I3[6] clb.I3[10] clb.I3[14] clb.I4[3] clb.I4[7] clb.I4[11] clb.cin</loc>
-          <loc side="top" layer_offset="1"> clb.O[3] clb.O[7] clb.O[11] clb.O[15] clb.O[19] clb.O[23] clb.O[27] clb.O[31] clb.O[35] clb.O[39] </loc>
-          <loc side="right"> clb.I1[1] clb.I1[5] clb.I1[9] clb.I1[13] clb.I2[2] clb.I2[6] clb.I2[10] clb.I2[14] clb.I3[3] clb.I3[7] clb.I3[11] clb.I4[0] clb.I4[4] clb.I4[8] clb.I4[12] </loc>
-          <loc side="right" layer_offset="1"> clb.O[0] clb.O[4] clb.O[8] clb.O[12] clb.O[16] clb.O[20] clb.O[24] clb.O[28] clb.O[32] clb.O[36] clb.cout </loc>
-          <loc side="bottom"> clb.I1[2] clb.I1[6] clb.I1[10] clb.I1[14] clb.I2[3] clb.I2[7] clb.I2[11] clb.I3[0] clb.I3[4] clb.I3[8] clb.I3[12] clb.I4[1] clb.I4[5] clb.I4[9] clb.I4[13] clb.clk</loc>
-          <loc side="bottom" layer_offset="1"> clb.O[1] clb.O[5] clb.O[9] clb.O[13] clb.O[17] clb.O[21] clb.O[25] clb.O[29] clb.O[33] clb.O[37]</loc>
-          <loc side="left"> clb.I1[3] clb.I1[7] clb.I1[11] clb.I2[0] clb.I2[4] clb.I2[8] clb.I2[12] clb.I3[1] clb.I3[5] clb.I3[9] clb.I3[13] clb.I4[2] clb.I4[6] clb.I4[10] clb.I4[14] clb.O[2] clb.O[6] clb.O[10] clb.O[14] clb.O[18] clb.O[22] clb.O[26] clb.O[30] clb.O[34] clb.O[38] </loc>
-          <loc side="left" layer_offset="1">clb.O[2] clb.O[6] clb.O[10] clb.O[14] clb.O[18] clb.O[22] clb.O[26] clb.O[30] clb.O[34] clb.O[38] </loc>
-        </pinlocations>
-      </sub_tile>
-    </tile>
-    <tile name="dsp_top" height="4" width="1" area="253779">
-      <sub_tile name="dsp_top">
-        <equivalent_sites>
-          <site pb_type="dsp_top" pin_mapping="direct"/>
-        </equivalent_sites>
-        <input name="reset" num_pins="1" is_non_clock_global="true"/>
-        <input name="dsp_I1" num_pins="64" />
-        <input name="dsp_I2" num_pins="64" />
-        <input name="chainin" num_pins="64"/>
-        <input name="scanin" num_pins="27"/>
-        <output name="result" num_pins="74"/>
-        <output name="chainout" num_pins="64"/>
-        <output name="scanout" num_pins="27"/>
-        <clock name="clk" num_pins="1"/>
-        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-          <!-- clock pins and chain ports do not connect to local routing -->
-          <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
-          <fc_override port_name="chainin" fc_type="frac" fc_val="0"/>
-          <fc_override port_name="chainout" fc_type="frac" fc_val="0"/>
-          <fc_override port_name="scanin" fc_type="frac" fc_val="0"/>
-          <fc_override port_name="scanout" fc_type="frac" fc_val="0"/>
-        </fc>
-        <pinlocations pattern="custom">
-        	  <loc side="left" yoffset="0">dsp_top.dsp_I1[31:0]</loc>
-	          <loc side="right" yoffset="1">dsp_top.dsp_I1[63:32]</loc>
-	          <loc side="left" yoffset="2">dsp_top.dsp_I2[31:0]</loc>
-	          <loc side="right" yoffset="3" >dsp_top.dsp_I2[63:32]</loc>
-	          <loc side="top">dsp_top.chainin dsp_top.scanin</loc>
-	          <loc side="bottom" layer_offset="1">dsp_top.chainout dsp_top.scanout</loc>
-	          <loc side="right" yoffset="0" layer_offset="1">dsp_top.result[17:0]</loc>
-            <loc side="right" yoffset="0"> dsp_top.clk </loc>
-	          <loc side="left" yoffset="1" layer_offset="1">dsp_top.result[36:18]</loc>
-	          <loc side="right" yoffset="2" layer_offset="1">dsp_top.result[55:37] </loc>
-	          <loc side="left" yoffset="3" layer_offset="1">dsp_top.result[73:56]</loc>
-            <loc side="left" yoffset="3">dsp_top.reset</loc>
-        </pinlocations>
-      </sub_tile>
-    </tile>
-    <tile name="memory" height="2" width="1" area="137668">
-      <sub_tile name="memory">
-        <equivalent_sites>
-          <site pb_type="memory" pin_mapping="direct"/>
-        </equivalent_sites>
-      <input name="addr1" num_pins="11"/>
-      <input name="addr2" num_pins="11"/>
-      <input name="data" num_pins="40"/>
-      <input name="we1" num_pins="1"/>
-      <input name="we2" num_pins="1"/>
-      <output name="out" num_pins="40"/>
-      <clock name="clk" num_pins="1"/>
-        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-          <fc_override fc_type="frac" fc_val="0" port_name="clk"/>
-        </fc>  
-        <pinlocations pattern="custom">
-          <loc side="top" layer_offset="1"> memory.out[0] memory.out[8] memory.out[16] memory.out[24] memory.out[32]</loc>
-          <loc side="top"> memory.addr1[0] memory.addr1[8] memory.addr2[5] memory.data[2] memory.data[10] memory.data[18] memory.data[26] memory.data[34] memory.clk </loc>
-          <loc side="top" layer_offset="1" yoffset="1"> memory.out[1] memory.out[9] memory.out[17] memory.out[25] memory.out[33] </loc>
-          <loc side="top" yoffset="1"> memory.addr1[1] memory.addr1[9] memory.addr2[6] memory.data[3] memory.data[11] memory.data[19] memory.data[27] memory.data[35]</loc>
-          <loc side="right" layer_offset="1"> memory.out[2] memory.out[10] memory.out[18] memory.out[26] memory.out[34] </loc>
-          <loc side="right"> memory.addr1[2] memory.addr1[10] memory.addr2[7] memory.data[4] memory.data[12] memory.data[20] memory.data[28] memory.data[36] </loc>
-          <loc side="right" layer_offset="1" yoffset="1"> memory.out[3] memory.out[11] memory.out[19] memory.out[27] memory.out[35] </loc>
-          <loc side="right" yoffset="1"> memory.addr1[3] memory.addr2[0] memory.addr2[8] memory.data[5] memory.data[13] memory.data[21] memory.data[29] memory.data[37]</loc>
-          <loc side="bottom" layer_offset="1"> memory.out[4] memory.out[12] memory.out[20] memory.out[28] memory.out[36] </loc>
-          <loc side="bottom"> memory.addr1[4] memory.addr2[1] memory.addr2[9] memory.data[6] memory.data[14] memory.data[22] memory.data[30] memory.data[38]</loc>
-          <loc side="bottom" yoffset="1"> memory.addr1[5] memory.addr2[2] memory.addr2[10] memory.data[7] memory.data[15] memory.data[23] memory.data[31] memory.data[39] </loc>
-          <loc side="bottom" layer_offset="1" yoffset="1"> memory.out[5] memory.out[13] memory.out[21] memory.out[29] memory.out[37] </loc>
-          <loc side="left" > memory.addr1[6] memory.addr2[3] memory.data[0] memory.data[8] memory.data[16] memory.data[24] memory.data[32] memory.we1</loc>
-          <loc side="left" layer_offset="1"> memory.out[6] memory.out[14] memory.out[22] memory.out[30] memory.out[38] </loc>
-          <loc side="left" yoffset="1"> memory.addr1[7] memory.addr2[4] memory.data[1] memory.data[9] memory.data[17] memory.data[25] memory.data[33] memory.we2 </loc>
-          <loc side="left" layer_offset="1" yoffset="1"> memory.out[7] memory.out[15] memory.out[23] memory.out[31] memory.out[39] </loc>
-        </pinlocations>
-      </sub_tile>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <layout>
-    <!-- Physical descriptions begin -->
-    <auto_layout aspect_ratio="1.0">
-      <layer die="0">
-        <perimeter type="io" priority="101"/>
-        <corners type="EMPTY" priority="102"/>
-        <fill type="clb" priority="10"/>
-        <col type="dsp_top" startx="6" starty="1" repeatx="16" priority="20"/>
-        <col type="memory" startx="2" starty="1" repeatx="16" priority="20"/>
-      </layer>
-      <layer die="1">
-        <perimeter type="io" priority="101"/>
-        <corners type="EMPTY" priority="102"/>
-        <fill type="clb" priority="10"/>
-        <col type="dsp_top" startx="6" starty="1" repeatx="16" priority="20"/>
-        <col type="memory" startx="2" starty="1" repeatx="16" priority="20"/>
-      </layer>
-    </auto_layout>
-    <!--
-    <fixed_layout name="mylayout" width="178" height="82">
-      <perimeter type="io" priority="101"/>
-      <corners type="EMPTY" priority="102"/>
-      
-      <col type="dsp_top"  startx="1"  starty="1"  priority="100"/>
-      <col type="clb"  startx="2"  starty="1"  priority="100"/>
-      <col type="clb"  startx="3"  starty="1"  priority="100"/>
-      <col type="dsp_top"  startx="4"  starty="1"  priority="100"/>
-      <col type="clb"  startx="5"  starty="1"  priority="100"/>
-      <col type="clb"  startx="6"  starty="1"  priority="100"/>
-      <col type="dsp_top"  startx="7"  starty="1"  priority="100"/>
-      <col type="clb"  startx="8"  starty="1"  priority="100"/>
-      <col type="clb"  startx="9"  starty="1"  priority="100"/>
-      <col type="dsp_top"  startx="10"  starty="1"  priority="100"/>
-      <col type="clb"  startx="11"  starty="1"  priority="100"/>
-      <col type="clb"  startx="12"  starty="1"  priority="100"/>
-      <col type="dsp_top"  startx="13"  starty="1"  priority="100"/>
-
-      <region type="clb" startx="14"   endx="88"   starty="1" incrx="5"  priority="20"/>
-      <region type="clb" startx="15"   endx="88"   starty="1" incrx="5"  priority="20"/>
-      <region type="clb" startx="16"   endx="88"   starty="1" incrx="5"  priority="20"/>
-      <region type="dsp_top" startx="17"   endx="88"   starty="1" incrx="5"  priority="20"/>
-      <region type="memory" startx="18"   endx="88"   starty="1" incrx="5"  priority="20"/>
-
-      <region type="memory" startx="89"   endx="163"   starty="1" incrx="5"  priority="20"/>
-      <region type="dsp_top" startx="90"   endx="163"   starty="1" incrx="5"  priority="20"/>
-      <region type="clb" startx="91"   endx="163"   starty="1" incrx="5"  priority="20"/>
-      <region type="clb" startx="92"   endx="163"   starty="1" incrx="5"  priority="20"/>
-      <region type="clb" startx="93"   endx="163"   starty="1" incrx="5"  priority="20"/>
-
-      <col type="dsp_top"  startx="164"  starty="1"  priority="20"/>
-      <col type="clb"  startx="165"  starty="1"  priority="1"/>
-      <col type="clb"  startx="166"  starty="1"  priority="1"/>
-      <col type="dsp_top"  startx="167"  starty="1"  priority="20"/>
-      <col type="clb"  startx="168"  starty="1"  priority="1"/>
-      <col type="clb"  startx="169"  starty="1"  priority="1"/>
-      <col type="dsp_top"  startx="170"  starty="1"  priority="20"/>
-      <col type="clb"  startx="171"  starty="1"  priority="1"/>
-      <col type="clb"  startx="172"  starty="1"  priority="1"/>
-      <col type="dsp_top"  startx="173"  starty="1"  priority="20"/>
-      <col type="clb"  startx="174"  starty="1"  priority="1"/>
-      <col type="clb"  startx="175"  starty="1"  priority="1"/>
-      <col type="dsp_top"  startx="176"  starty="1"  priority="20"/>
-    </fixed_layout> 
-    -->
-  </layout>
-  <device>
-    <sizing R_minW_nmos="13090" R_minW_pmos="19086.83"/>
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="custom"/>
-    <connection_block input_switch_name="ipin_cblock" input_inter_die_switch_name="die_connection"/>
-  </device>
-  <switchlist>
-    <switch type="mux" name="L4_driver" R="0.0" Cin="0.0" Cout="0.0" Tdel="207.9e-12" mux_trans_size="2.377" buf_size="35.69"/>
-    <!-- Delay of L16 driver is scaled from L4 by a factor of 1.5x (based on numbers from the Titan Stratix IV architecture file)
-	 Area numbers will not be totally accurate because of the same buf_size -->
-    <switch type="mux" name="L16_driver" R="0.0" Cin="0.0" Cout="0.0" Tdel="312.9e-12" mux_trans_size="2.377" buf_size="35.69"/> 
-    <switch type="mux" name="ipin_cblock" R="0.0" Cout="0.0" Cin="0.0" Tdel="130e-12" mux_trans_size="1.508" buf_size="11.71"/>
-    <switch type="mux" name="die_connection" R="0.0" Cout="0.0" Cin="0.0" Tdel="130e-12" mux_trans_size="1.508" buf_size="11.71"/>
-  </switchlist>
-  <segmentlist>
-    <segment name="L4" freq="260" length="4" type="unidir" Rmetal="0.0" Cmetal="0.0">
-      <mux name="L4_driver"/>
-      <mux_inter_die name="L4_driver"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-    <segment name="L16" freq="40" length="16" type="unidir" Rmetal="0.0" Cmetal="0.0">
-      <mux name="L16_driver"/>
-      <mux_inter_die name="L16_driver"/>
-      <!-- Vias from the top of the metal stack (global layers, where the long wires are 
-           implemented) down to the middle/bottom of the metal stack (semi-global layers, 
-           where the short wires are implemented) are expensive and restrictive.
-           As a result Startix IV only places long wire switch blocks every 4 LABs -->
-      <sb type="pattern">1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1</sb>
-      <!-- For the same reasons, long wires do not connect to block pins in Stratix IV -->
-      <cb type="pattern">0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <!-- Direct connect from one LAB to the LAB directly below it (carry chain) -->
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-    <!-- Direct connect from one DSP to the DSP directly below it -->
-    <direct name="dsp_out_chain" from_pin="dsp_top.chainout" from_side="bottom" to_pin="dsp_top.chainin" to_side="top" x_offset="0" y_offset="-4" z_offset="0"/>
-    <direct name="dsp_in_chain" from_pin="dsp_top.scanout" from_side="bottom" to_pin="dsp_top.scanin" to_side="top" x_offset="0" y_offset="-4" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <pb_type name="clb">
-      <input name="I1" num_pins="15" equivalent="full"/>
-      <input name="I2" num_pins="15" equivalent="full"/>
-      <input name="I3" num_pins="15" equivalent="full"/>
-      <input name="I4" num_pins="15" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="40" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <pb_type name="lab" num_pb="1">
-        <input name="I1" num_pins="15"/>
-        <input name="I2" num_pins="15"/>
-        <input name="I3" num_pins="15"/>
-        <input name="I4" num_pins="15"/>
-        <input name="cin" num_pins="1"/>
-        <output name="O" num_pins="40"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Describe fracturable logic element.  
-                 Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-                 The outputs of the fracturable logic element can be optionally registered
-            -->
-        <pb_type name="fle" num_pb="10">
-          <input name="in" num_pins="8"/>
-          <input name="cin" num_pins="1"/>
-          <output name="out" num_pins="4"/>
-          <output name="cout" num_pins="1"/>
-          <clock name="clk" num_pins="1"/>
-          <!-- 
-                    The ALM inputs are as follows:
-                            A -> fle[0]
-                            B -> fle[1]
-                            C -> fle[2]
-                            D -> fle[3]
-                            E -> fle[4]
-                            F -> fle[5]
-                            G -> fle[6]
-                            H -> fle[7]
-              -->
-          <mode name="n2_lut5">
-            <pb_type name="ble5" num_pb="2">
-              <input name="in" num_pins="5"/>
-              <input name="cin" num_pins="1"/>
-              <output name="out" num_pins="2"/>
-              <output name="cout" num_pins="1"/>
-              <clock name="clk" num_pins="1"/>
-              <mode name="blut5">
-                <pb_type name="flut5" num_pb="1">
-                  <input name="in" num_pins="5"/>
-                  <output name="out" num_pins="2"/>
-                  <clock name="clk" num_pins="1"/>
-                  <!-- Regular LUT mode -->
-                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-                    <input name="in" num_pins="5" port_class="lut_in"/>
-                    <output name="out" num_pins="1" port_class="lut_out"/>
-                    <!-- LUT timing using delay matrix -->
-                    <!-- These are the physical delay inputs on a Stratix 10 LUT but because VPR cannot do LUT rebalancing,
-                             we instead take the average of these numbers to get more stable results
-                             note that those are the same delays for inputs A - E as the ones used for the 6-LUT, however, we have 
-                             subtracted the delay of the last mux stage to get the delay of inputs A - E till the 5-LUT output
-                             210.96e-12
-                             206.85e-12
-                             143.46e-12
-                             136.94e-12
-                             68.12e-12
-                          -->
-                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                            153.27e-12
-                            153.27e-12
-                            153.27e-12
-                            153.27e-12
-                            153.27e-12
-                        </delay_matrix>
-                  </pb_type>
-                  <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-                    <input name="D" num_pins="1" port_class="D"/>
-                    <output name="Q" num_pins="1" port_class="Q"/>
-                    <clock name="clk" num_pins="1" port_class="clock"/>
-                    <T_setup value="18.91e-12" port="ff.D" clock="clk"/>
-                    <T_clock_to_Q max="60.32e-12" port="ff.Q" clock="clk"/>
-                  </pb_type>
-                  <interconnect>
-                    <direct name="lut5_in" input="flut5.in" output="lut5.in"/>
-                    <direct name="reg_in" input="flut5.in[0]" output="ff[0].D"/>
-                    <direct name="lut5_ff" input="lut5.out" output="ff[1].D">
-                      <delay_constant max="18.96e-12" in_port="lut5.out" out_port="ff[1].D"/>
-                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff[1].D"/>
-                    </direct>
-                    <complete name="clock" input="flut5.clk" output="ff.clk"/>
-                    <complete name="out_mux" input="ff.Q lut5.out" output="flut5.out">
-                      <delay_constant max="39.85e-12" in_port="lut5.out" out_port="flut5.out"/>
-                      <delay_constant max="39.85e-12" in_port="ff.Q" out_port="flut5.out"/>
-                    </complete>
-                  </interconnect>
-                </pb_type>
-                <interconnect>
-                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
-                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
-                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
-                </interconnect>
-              </mode>
-              <mode name="arithmetic">
-                <pb_type name="arithmetic" num_pb="1">
-                  <input name="in" num_pins="4"/>
-                  <input name="cin" num_pins="1"/>
-                  <output name="out" num_pins="2"/>
-                  <output name="cout" num_pins="1"/>
-                  <clock name="clk" num_pins="1"/>
-                  <!-- Special dual-LUT mode that drives adder only -->
-                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-                    <input name="in" num_pins="4" port_class="lut_in"/>
-                    <output name="out" num_pins="1" port_class="lut_out"/>
-                    <!-- LUT timing using delay matrix -->
-                    <!-- These are the physical delay inputs on a Stratix 10 LUT but because VPR cannot do LUT rebalancing,
-                           we instead take the average of these numbers to get more stable results
-                           note that those are the same delays for inputs A - E as the ones used for the 6-LUT, however, we have 
-                           subtracted the delay of the last mux stage to get the delay of inputs A - E till the 5-LUT output
-                             168.12e-12
-                             164.02e-12
-                             100.63e-12
-                             94.11e-12
-                          -->
-                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                            131.72e-12
-                            131.72e-12
-                            131.72e-12
-                            131.72e-12
-                        </delay_matrix>
-                  </pb_type>
-                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-                    <input name="a" num_pins="1"/>
-                    <input name="b" num_pins="1"/>
-                    <input name="cin" num_pins="1"/>
-                    <output name="cout" num_pins="1"/>
-                    <output name="sumout" num_pins="1"/>
-                    <delay_constant max="68.74e-12" in_port="adder.a" out_port="adder.sumout"/>
-                    <delay_constant max="68.74e-12" in_port="adder.b" out_port="adder.sumout"/>
-                    <delay_constant max="35.46e-12" in_port="adder.cin" out_port="adder.sumout"/>
-                    <delay_constant max="49.32e-12" in_port="adder.a" out_port="adder.cout"/>
-                    <delay_constant max="49.32e-12" in_port="adder.b" out_port="adder.cout"/>
-                    <delay_constant max="25.56e-12" in_port="adder.cin" out_port="adder.cout"/>
-                  </pb_type>
-                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-                    <input name="D" num_pins="1" port_class="D"/>
-                    <output name="Q" num_pins="1" port_class="Q"/>
-                    <clock name="clk" num_pins="1" port_class="clock"/>
-                    <T_setup value="18.91e-12" port="ff.D" clock="clk"/>
-                    <T_clock_to_Q max="60.32e-12" port="ff.Q" clock="clk"/>
-                  </pb_type>
-                  <interconnect>
-                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-                    <direct name="lut4_in1" input="arithmetic.in" output="lut4[0].in"/>
-                    <direct name="lut4_in2" input="arithmetic.in" output="lut4[1].in"/>
-                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a"/>
-                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b"/>
-                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                      <delay_constant max="18.96e-12" in_port="adder.sumout" out_port="ff.D"/>
-                      <!--pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/-->
-                    </direct>
-                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-                    </direct>
-                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-                    </direct>
-                    <complete name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                      <delay_constant max="39.85e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                      <delay_constant max="39.85e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-                    </complete>
-                  </interconnect>
-                </pb_type>
-                <interconnect>
-                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
-                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
-                    <pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/>
-                  </direct>
-                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
-                    <pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/>
-                  </direct>
-                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
-                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
-                </interconnect>
-              </mode>
-            </pb_type>
-            <interconnect>
-              <!-- Shared inputs between the two 5-LUTs -->
-              <complete name="lut5_reg1" input="fle.in[0]" output="ble5[0].in[0] ble5[1].in[1]"/>
-              <complete name="lut5_reg2" input="fle.in[1]" output="ble5[0].in[1] ble5[1].in[0]"/>
-              <!-- Rest of the 5-LUT inputs -->
-              <direct name="lut5_inputs_1" input="fle.in[4:2]" output="ble5[0].in[4:2]"/>
-              <direct name="lut5_inputs_22" input="fle.in[7:5]" output="ble5[1].in[4:2]"/>
-              <direct name="lut5_outputs_1" input="ble5[0].out" output="fle.out[1:0]"/>
-              <direct name="lut5_outputs_2" input="ble5[1].out" output="fle.out[3:2]"/>
-              <direct name="carry_in" input="fle.cin" output="ble5[0].cin">
-                <pack_pattern name="chain" in_port="fle.cin" out_port="ble5[0].cin"/>
-              </direct>
-              <direct name="carry_out" input="ble5[1].cout" output="fle.cout">
-                <pack_pattern name="chain" in_port="ble5[1].cout" out_port="fle.cout"/>
-              </direct>
-              <direct name="carry_link" input="ble5[0].cout" output="ble5[1].cin">
-                <pack_pattern name="chain" in_port="ble5[0].cout" out_port="ble5[1].cout"/>
-              </direct>
-              <complete name="clock" input="fle.clk" output="ble5[1:0].clk"/>
-            </interconnect>
-          </mode>
-          <!-- n2_lut5 -->
-          <mode name="n1_lut6">
-            <pb_type name="ble6" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="out" num_pins="4"/>
-              <clock name="clk" num_pins="1"/>
-              <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-                <input name="in" num_pins="6" port_class="lut_in"/>
-                <output name="out" num_pins="1" port_class="lut_out"/>
-                <!-- LUT timing using delay matrix -->
-                <!-- These are the physical delay inputs on a Stratix 10 LUT but because VPR cannot do LUT rebalancing,
-                           we instead take the average of these numbers to get more stable results
-                           257.8e-12
-                           253.69e-12
-                           190.3e-12
-                           183.78e-12
-                           114.96e-12
-                           77.18e-12
-                      -->
-                <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                        179.6e-12
-                        179.6e-12
-                        179.6e-12
-                        179.6e-12
-                        179.6e-12
-                        179.6e-12
-                    </delay_matrix>
-              </pb_type>
-              <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-                <input name="D" num_pins="1" port_class="D"/>
-                <output name="Q" num_pins="1" port_class="Q"/>
-                <clock name="clk" num_pins="1" port_class="clock"/>
-                <T_setup value="18.91e-12" port="ff.D" clock="clk"/>
-                <T_clock_to_Q max="60.32e-12" port="ff.Q" clock="clk"/>
-              </pb_type>
-              <interconnect>
-                <direct name="lut6_inputs" input="ble6.in" output="lut6.in"/>
-                <direct name="lut6_ff" input="lut6.out" output="ff[1].D">
-                  <delay_constant max="18.96e-12" in_port="lut6.out" out_port="ff[1].D"/>
-                  <pack_pattern name="ble6" in_port="lut6.out" out_port="ff[1].D"/>
-                </direct>
-                <complete name="clock" input="ble6.clk" output="ff.clk"/>
-                <direct name="input_to_ff" input="ble6.in[0]" output="ff[0].D"/>
-                <mux name="mux1" input="ff[0].Q lut6.out" output="ble6.out[0]">
-                  <delay_constant max="39.85e-12" in_port="lut6.out" out_port="ble6.out[0]"/>
-                  <delay_constant max="39.85e-12" in_port="ff[0].Q" out_port="ble6.out[0]"/>
-                </mux>
-                <!-- This mux is the same as mux1 but connected to output 2 -->
-                <mux name="mux2" input="ff[0].Q lut6.out" output="ble6.out[1]">
-                  <delay_constant max="39.85e-12" in_port="lut6.out" out_port="ble6.out[1]"/>
-                  <delay_constant max="39.85e-12" in_port="ff[0].Q" out_port="ble6.out[1]"/>
-                </mux>
-                <mux name="mux3" input="ff[1].Q lut6.out" output="ble6.out[2]">
-                  <delay_constant max="39.85e-12" in_port="lut6.out" out_port="ble6.out[2]"/>
-                  <delay_constant max="39.85e-12" in_port="ff[1].Q" out_port="ble6.out[2]"/>
-                </mux>
-                <!-- This mux is the same as mux2 but connected to output 3 -->
-                <mux name="mux4" input="ff[1].Q lut6.out" output="ble6.out[3]">
-                  <delay_constant max="39.85e-12" in_port="lut6.out" out_port="ble6.out[3]"/>
-                  <delay_constant max="39.85e-12" in_port="ff[1].Q" out_port="ble6.out[3]"/>
-                </mux>
-              </interconnect>
-            </pb_type>
-            <interconnect>
-              <!-- ble6 takes inputs A, B, C, D, E, & F; where F is fle[7] -->
-              <direct name="lut6_inputs1" input="fle.in[4:0]" output="ble6.in[4:0]"/>
-              <direct name="lut6_inputs2" input="fle.in[7]" output="ble6.in[5]"/>
-              <direct name="direct2" input="ble6.out" output="fle.out"/>
-              <direct name="direct4" input="fle.clk" output="ble6.clk"/>
-            </interconnect>
-          </mode>
-          <!-- n1_lut6 -->
-        </pb_type>
-        <interconnect>
-          <!-- 50% sparsely populated local routing -->
-          <!-- This 50% sparsity pattern divides the cluster inputs and local feedbacks into four groups, 
-               and then selects two of the four groups to feed each LUT input. This means half of the cluster 
-               inputs and local feedbacks can feed each LUT input. There is partial overlap in the inputs that 
-               feed the various LUT inputs, which helps routability vs. simply having half the cluster inputs 
-               feed one set of half the LUT inputs and the other half of cluster inputs feed the other set of 
-               LUT inputs. This pattern is used by Stratix (I - 10) architectures. -->
-          <complete name="lutA" input="lab.I4 lab.I3" output="fle[9:0].in[0:0]">
-            <delay_constant max="74.71e-12" in_port="lab.I4" out_port="fle.in[0:0]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I3" out_port="fle.in[0:0]"/>
-          </complete>
-          <complete name="lutB" input="lab.I3 lab.I2" output="fle[9:0].in[1:1]">
-            <delay_constant max="74.71e-12" in_port="lab.I3" out_port="fle.in[1:1]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I2" out_port="fle.in[1:1]"/>
-          </complete>
-          <complete name="lutC" input="lab.I2 lab.I1" output="fle[9:0].in[2:2]">
-            <delay_constant max="74.71e-12" in_port="lab.I2" out_port="fle.in[2:2]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I1" out_port="fle.in[2:2]"/>
-          </complete>
-          <complete name="lutD" input="lab.I4 lab.I2" output="fle[9:0].in[3:3]">
-            <delay_constant max="74.71e-12" in_port="lab.I4" out_port="fle.in[3:3]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I2" out_port="fle.in[3:3]"/>
-          </complete>
-          <complete name="lutE" input="lab.I3 lab.I1" output="fle[9:0].in[4:4]">
-            <delay_constant max="74.71e-12" in_port="lab.I3" out_port="fle.in[4:4]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I1" out_port="fle.in[4:4]"/>
-          </complete>
-          <complete name="lutF" input="lab.I4 lab.I1" output="fle[9:0].in[5:5]">
-            <delay_constant max="74.71e-12" in_port="lab.I4" out_port="fle.in[5:5]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I1" out_port="fle.in[5:5]"/>
-          </complete>
-          <complete name="lutG" input="lab.I4 lab.I3" output="fle[9:0].in[6:6]">
-            <delay_constant max="74.71e-12" in_port="lab.I4" out_port="fle.in[6:6]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I3" out_port="fle.in[6:6]"/>
-          </complete>
-          <complete name="lutH" input="lab.I3 lab.I2" output="fle[9:0].in[7:7]">
-            <delay_constant max="74.71e-12" in_port="lab.I3" out_port="fle.in[7:7]"/>
-            <delay_constant max="74.71e-12" in_port="lab.I2" out_port="fle.in[7:7]"/>
-          </complete>
-          <complete name="clks" input="lab.clk" output="fle[9:0].clk"/>
-          <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                     By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                     then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                     naive specification).
-              -->
-          <direct name="labouts1" input="fle[9:0].out[0]" output="lab.O[9:0]"/>
-          <direct name="labouts2" input="fle[9:0].out[1]" output="lab.O[19:10]"/>
-          <direct name="labouts3" input="fle[9:0].out[2]" output="lab.O[29:20]"/>
-          <direct name="labouts4" input="fle[9:0].out[3]" output="lab.O[39:30]"/>
-          <!-- Carry chain links -->
-          <direct name="carry_in" input="lab.cin" output="fle[0:0].cin">
-            <!-- Put all inter-block carry chain delay on this one edge -->
-            <delay_constant max="18.47e-12" in_port="lab.cin" out_port="fle[0:0].cin"/>
-            <pack_pattern name="chain" in_port="lab.cin" out_port="fle[0:0].cin"/>
-          </direct>
-          <direct name="carry_out" input="fle[9:9].cout" output="lab.cout">
-            <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="lab.cout"/>
-          </direct>
-          <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-            <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-          </direct>
-        </interconnect>
-      </pb_type>
-      <interconnect>
-        <direct name="carry_in" input="clb.cin" output="lab.cin"/>
-        <direct name="carry_out" input="lab.cout" output="clb.cout"/>
-        <direct name="clock" input="clb.clk" output="lab.clk"/>
-        <complete name="Input_feedback_I1" input="clb.I1 lab.O[4:0]" output="lab.I1"/>
-        <complete name="Input_feedback_I2" input="clb.I2 lab.O[24:20]" output="lab.I2"/>
-        <complete name="Input_feedback_I3" input="clb.I3 lab.O[9:5]" output="lab.I3"/>
-        <complete name="Input_feedback_I4" input="clb.I4 lab.O[29:25]" output="lab.I4"/>
-        <!--
-        <direct name="Input_I1" input="clb.I1" output="lab.I1"/>
-        <direct name="Input_I2" input="clb.I2" output="lab.I2"/>
-        <direct name="Input_I3" input="clb.I3" output="lab.I3"/>
-        <direct name="Input_I4" input="clb.I4" output="lab.I4"/>
-        -->
-        <direct name="output" input="lab.O" output="clb.O"/>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-
-    <!-- Define DSP slice begin -->
-    <pb_type name="dsp_top">
-      <input name="reset" num_pins="1" is_non_clock_global="true"/>
-      <input name="dsp_I1" num_pins="64" />
-      <input name="dsp_I2" num_pins="64" />
-      <input name="chainin" num_pins="64"/>
-      <input name="scanin" num_pins="27"/>
-      <output name="result" num_pins="74"/>
-      <output name="chainout" num_pins="64"/>
-      <output name="scanout" num_pins="27"/>
-      <clock name="clk" num_pins="1"/>
-
-    <pb_type name="dsp" num_pb="1">
-      <input name="reset" num_pins="1"/>
-      <input name="dsp_I1" num_pins="64"/>
-      <input name="dsp_I2" num_pins="64"/>
-      <input name="chainin" num_pins="64"/>
-      <input name="scanin" num_pins="27"/>
-      <output name="result" num_pins="74"/>
-      <output name="chainout" num_pins="64"/>
-      <output name="scanout" num_pins="27"/>
-      <clock name="clk" num_pins="1"/>
-
-      <pb_type name="dsp_pb" num_pb="1">
-        <input name="reset" num_pins="1"/>
-        <input name="mode_sigs" num_pins="12"/>
-        <input name="datain" num_pins="116"/>
-        <input name="chainin" num_pins="64"/>
-        <input name="scanin" num_pins="27"/>
-        <output name="result" num_pins="74"/>
-        <output name="chainout" num_pins="64"/>
-        <output name="scanout" num_pins="27"/>
-        <clock name="clk" num_pins="1"/>
-
-        <!-- fixed-point multiplier mode (1 27x27 multiplier) result = ax*ay -->
-        <mode name="one_mult_27x27">
-          <pb_type name="one_mult_27x27" num_pb="1">
-            <input name="a" num_pins="27"/>
-            <input name="b" num_pins="27"/>
-            <output name="out" num_pins="54"/>
-            <pb_type name="mult_27x27" blif_model=".subckt multiply" num_pb="1">
-              <input name="a" num_pins="27"/>
-              <input name="b" num_pins="27"/>
-              <output name="out" num_pins="54"/>
-              <delay_constant max="2.14e-9" in_port="mult_27x27.a" out_port="mult_27x27.out"/>
-              <delay_constant max="2.14e-9" in_port="mult_27x27.b" out_port="mult_27x27.out"/>
-            </pb_type>
-            <interconnect>
-              <direct name="a2a" input="one_mult_27x27.a" output="mult_27x27.a">
-              </direct>
-              <direct name="b2b" input="one_mult_27x27.b" output="mult_27x27.b">
-              </direct>
-              <direct name="out2out" input="mult_27x27.out" output="one_mult_27x27.out">
-              </direct>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="datain2a" input="dsp_pb.datain[26:0]" output="one_mult_27x27.a">
-            </direct>
-            <direct name="datain2b" input="dsp_pb.datain[53:27]" output="one_mult_27x27.b">
-            </direct>
-            <direct name="out2dataout" input="one_mult_27x27.out" output="dsp_pb.result[53:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point multiplier mode (2 18x19 multipliers) result[some:bits] = ax*ay, result[other:bits] = bx*by -->
-        <mode name="two_mult_18x19">
-          <pb_type name="two_mult_18x19" num_pb="2">
-            <input name="a" num_pins="18"/>
-            <input name="b" num_pins="19"/>
-            <output name="out" num_pins="37"/>
-            <pb_type name="mult_18x19" blif_model=".subckt multiply" num_pb="1">
-              <input name="a" num_pins="18"/>
-              <input name="b" num_pins="19"/>
-              <output name="out" num_pins="37"/>
-              <delay_constant max="2.14e-9" in_port="mult_18x19.a" out_port="mult_18x19.out"/>
-              <delay_constant max="2.14e-9" in_port="mult_18x19.b" out_port="mult_18x19.out"/>
-            </pb_type>
-            <interconnect>
-              <direct name="a2a" input="two_mult_18x19.a" output="mult_18x19.a">
-                 </direct>
-              <direct name="b2b" input="two_mult_18x19.b" output="mult_18x19.b">
-                 </direct>
-              <direct name="out2out" input="mult_18x19.out" output="two_mult_18x19.out">
-                 </direct>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="datain2a1" input="dsp_pb.datain[17:0]" output="two_mult_18x19[0].a">
-            </direct>
-            <direct name="datain2b1" input="dsp_pb.datain[36:18]" output="two_mult_18x19[0].b">
-            </direct>
-            <direct name="datain2a2" input="dsp_pb.datain[54:37]" output="two_mult_18x19[1].a">
-            </direct>
-            <direct name="datain2b2" input="dsp_pb.datain[73:55]" output="two_mult_18x19[1].b">
-            </direct>
-            <direct name="out2result" input="two_mult_18x19.out" output="dsp_pb.result[73:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- Fixed point multiplier mode (4 9x9 multipliers) result = ax*ay -->
-        <mode name="mult_9x9_fixed_pt_mode">
-          <pb_type name="mult_9x9_fixed_pt" blif_model=".subckt multiply" num_pb="4">
-            <input name="a" num_pins="9"/>
-            <input name="b" num_pins="9"/>
-            <output name="out" num_pins="18"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_9x9_fixed_pt.a" out_port="mult_9x9_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mult_9x9_fixed_pt.b" out_port="mult_9x9_fixed_pt.out"/>
-          </pb_type>
-          <interconnect>
-            <direct name="atoa0" input="dsp_pb.datain[8:0]" output="mult_9x9_fixed_pt[0].a"/>
-            <direct name="btob0" input="dsp_pb.datain[17:9]" output="mult_9x9_fixed_pt[0].b"/>
-            <direct name="atoa1" input="dsp_pb.datain[26:18]" output="mult_9x9_fixed_pt[1].a"/>
-            <direct name="btob1" input="dsp_pb.datain[35:27]" output="mult_9x9_fixed_pt[1].b"/>
-            <direct name="atoa2" input="dsp_pb.datain[44:36]" output="mult_9x9_fixed_pt[2].a"/>
-            <direct name="btob2" input="dsp_pb.datain[53:45]" output="mult_9x9_fixed_pt[2].b"/>
-            <direct name="atoa3" input="dsp_pb.datain[62:54]" output="mult_9x9_fixed_pt[3].a"/>
-            <direct name="btob3" input="dsp_pb.datain[71:63]" output="mult_9x9_fixed_pt[3].b"/>
-            <direct name="sumouttosumout0" input="mult_9x9_fixed_pt[0].out" output="dsp_pb.result[17:0]"/>
-            <direct name="sumouttosumout1" input="mult_9x9_fixed_pt[1].out" output="dsp_pb.result[35:18]"/>
-            <direct name="sumouttosumout2" input="mult_9x9_fixed_pt[2].out" output="dsp_pb.result[53:36]"/>
-            <direct name="sumouttosumout3" input="mult_9x9_fixed_pt[3].out" output="dsp_pb.result[71:54]"/>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point multiplier-add-sum mode result = (bx * by) + (ax * ay) + chainin. chainout = result -->
-        <mode name="sop_2_mode">
-          <pb_type name="sop_2" num_pb="1" blif_model=".subckt int_sop_2">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="ax" num_pins="18"/>
-            <input name="ay" num_pins="19"/>
-            <input name="bx" num_pins="18"/>
-            <input name="by" num_pins="19"/>
-            <input name="chainin" num_pins="37"/>
-            <output name="result" num_pins="37"/>
-            <output name="chainout" num_pins="37"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_2.reset" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.mode_sigs" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.ax" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.ay" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.bx" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.by" out_port="sop_2.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.chainin" out_port="sop_2.result"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_2.reset" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.mode_sigs" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.ax" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.ay" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.bx" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.by" out_port="sop_2.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_2.chainin" out_port="sop_2.chainout"/>
-
-            <T_setup value="18.91e-12" port="sop_2.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.ax" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.ay" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.bx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.by" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_2.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.ax" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.ay" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.bx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.by" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_2.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="sop_2.clk">
-            </direct>
-            <direct name="reset" input="dsp_pb.reset" output="sop_2.reset">
-            </direct>
-            <direct name="modesigs" input="dsp_pb.mode_sigs" output="sop_2.mode_sigs">
-            </direct>
-            <direct name="datain2ax" input="dsp_pb.datain[17:0]" output="sop_2.ax">
-            </direct>
-            <direct name="datain2ay" input="dsp_pb.datain[36:18]" output="sop_2.ay">
-            </direct>
-            <direct name="datain2bx" input="dsp_pb.datain[54:37]" output="sop_2.bx">
-            </direct>
-            <direct name="datain2by" input="dsp_pb.datain[73:55]" output="sop_2.by">
-            </direct>
-            <direct name="chainin"   input="dsp_pb.chainin[36:0]" output="sop_2.chainin">
-            </direct>
-            <direct name="dataout2result" input="sop_2.result" output="dsp_pb.result[36:0]">
-            </direct>
-            <direct name="chainout" input="sop_2.chainout" output="dsp_pb.chainout[36:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point multiplier-add-sum mode result = (ax * ay) + bx + chainin. chainout = result. with scanin-scanout support -->
-        <mode name="mult_add_mode_18_19_36">
-          <pb_type name="mult_add" num_pb="1" blif_model=".subckt mult_add_int_18x19">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="ax" num_pins="18"/>
-            <input name="ay" num_pins="19"/>
-            <input name="bx" num_pins="36"/>
-            <input name="chainin" num_pins="64"/>
-            <input name="scanin" num_pins="19"/>
-            <output name="result" num_pins="64"/>
-            <output name="chainout" num_pins="64"/>
-            <output name="scanout" num_pins="19"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.result"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.chainout"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.scanout"/>
-
-            <T_setup value="18.91e-12" port="mult_add.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.ax" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.ay" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.bx" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.scanin" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.ax" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.ay" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.bx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.scanin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="mult_add.clk">
-            </direct>
-            <direct name="reset" input="dsp_pb.reset" output="mult_add.reset">
-            </direct>
-            <direct name="modesigs" input="dsp_pb.mode_sigs" output="mult_add.mode_sigs">
-            </direct>
-            <direct name="datain2ax" input="dsp_pb.datain[17:0]" output="mult_add.ax">
-            </direct>
-            <direct name="datain2ay" input="dsp_pb.datain[36:18]" output="mult_add.ay">
-            </direct>
-            <direct name="datain2bx" input="dsp_pb.datain[72:37]" output="mult_add.bx">
-            </direct>
-            <direct name="chainin"   input="dsp_pb.chainin[63:0]" output="mult_add.chainin">
-            </direct>
-            <direct name="scanin"   input="dsp_pb.scanin[18:0]" output="mult_add.scanin">
-            </direct>
-            <direct name="dataout2result" input="mult_add.result" output="dsp_pb.result[63:0]">
-            </direct>
-            <direct name="chainout" input="mult_add.chainout" output="dsp_pb.chainout[63:0]">
-            </direct>
-            <direct name="scanout" input="mult_add.scanout" output="dsp_pb.scanout[18:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point multiplier-add-sum mode result = (ax * ay) + bx + chainin. chainout = result. with scanin-scanout support -->
-        <mode name="mult_add_mode_27_27_64">
-          <pb_type name="mult_add" num_pb="1" blif_model=".subckt mult_add_int_27x27">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="ax" num_pins="27"/>
-            <input name="ay" num_pins="27"/>
-            <input name="bx" num_pins="36"/>
-            <input name="chainin" num_pins="64"/>
-            <input name="scanin" num_pins="27"/>
-            <output name="result" num_pins="64"/>
-            <output name="chainout" num_pins="64"/>
-            <output name="scanout" num_pins="27"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.result"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.result"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.chainout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.chainout"/>
-
-            <delay_constant max="2.14e-9" in_port="mult_add.reset" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.mode_sigs" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ax" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.ay" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.bx" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.chainin" out_port="mult_add.scanout"/>
-            <delay_constant max="2.14e-9" in_port="mult_add.scanin" out_port="mult_add.scanout"/>
-
-            <T_setup value="18.91e-12" port="mult_add.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.ax" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.ay" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.bx" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.scanin" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_add.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.ax" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.ay" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.bx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.scanin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_add.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="mult_add.clk">
-            </direct>
-            <direct name="reset" input="dsp_pb.reset" output="mult_add.reset">
-            </direct>
-            <direct name="modesigs" input="dsp_pb.mode_sigs" output="mult_add.mode_sigs">
-            </direct>
-            <direct name="datain2ax" input="dsp_pb.datain[26:0]" output="mult_add.ax">
-            </direct>
-            <direct name="datain2ay" input="dsp_pb.datain[53:27]" output="mult_add.ay">
-            </direct>
-            <direct name="datain2bx" input="dsp_pb.datain[89:54]" output="mult_add.bx">
-            </direct>
-            <direct name="chainin"   input="dsp_pb.chainin[63:0]" output="mult_add.chainin">
-            </direct>
-            <direct name="scanin"   input="dsp_pb.scanin[26:0]" output="mult_add.scanin">
-            </direct>
-            <direct name="dataout2result" input="mult_add.result" output="dsp_pb.result[63:0]">
-            </direct>
-            <direct name="chainout" input="mult_add.chainout" output="dsp_pb.chainout[63:0]">
-            </direct>
-            <direct name="scanout" input="mult_add.scanout" output="dsp_pb.scanout[26:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point sum-of-4 mode result = (dx * dy) + (cx * cy) + (bx * by) + (ax * ay) + chainin. chainout = result -->
-        <mode name="sop_4_mode">
-          <pb_type name="sop_4" num_pb="1" blif_model=".subckt int_sop_4">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="ax" num_pins="9"/>
-            <input name="ay" num_pins="9"/>
-            <input name="bx" num_pins="9"/>
-            <input name="by" num_pins="9"/>
-            <input name="cx" num_pins="9"/>
-            <input name="cy" num_pins="9"/>
-            <input name="dx" num_pins="9"/>
-            <input name="dy" num_pins="9"/>
-            <input name="chainin" num_pins="64"/>
-            <output name="result" num_pins="64"/>
-            <output name="chainout" num_pins="64"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_4.reset" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.mode_sigs" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ax" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ay" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.bx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.by" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cy" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dy" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.chainin" out_port="sop_4.result"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_4.reset" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.mode_sigs" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ax" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ay" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.bx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.by" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cy" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dy" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.chainin" out_port="sop_4.chainout"/>
-
-            <T_setup value="18.91e-12" port="sop_4.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.ax" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.ay" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.bx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.by" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.cx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.cy" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.dx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.dy" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.ax" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.ay" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.bx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.by" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.cx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.cy" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.dx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.dy" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="sop_4.clk">
-            </direct>
-            <direct name="reset" input="dsp_pb.reset" output="sop_4.reset">
-            </direct>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="sop_4.mode_sigs">
-            </direct>
-            <direct name="datain2ax" input="dsp_pb.datain[8:0]" output="sop_4.ax">
-            </direct>
-            <direct name="datain2ay" input="dsp_pb.datain[17:9]" output="sop_4.ay">
-            </direct>
-            <direct name="datain2bx" input="dsp_pb.datain[26:18]" output="sop_4.bx">
-            </direct>
-            <direct name="datain2by" input="dsp_pb.datain[35:27]" output="sop_4.by">
-            </direct>
-            <direct name="datain2cx" input="dsp_pb.datain[44:36]" output="sop_4.cx">
-            </direct>
-            <direct name="datain2cy" input="dsp_pb.datain[53:45]" output="sop_4.cy">
-            </direct>
-            <direct name="datain2dx" input="dsp_pb.datain[62:54]" output="sop_4.dx">
-            </direct>
-            <direct name="datain2dy" input="dsp_pb.datain[71:63]" output="sop_4.dy">
-            </direct>
-            <direct name="chainin"   input="dsp_pb.chainin[63:0]" output="sop_4.chainin">
-            </direct>
-            <direct name="dataout2result" input="sop_4.result" output="dsp_pb.result[63:0]">
-            </direct>
-            <direct name="chainout" input="sop_4.chainout" output="dsp_pb.chainout[63:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- fixed-point sum-of-4 accum mode result = (dx * dy) + (cx * cy) + (bx * by) + (ax * ay) + chainin + accumulator. chainout = result -->
-        <mode name="sop_4_accum_mode">
-          <pb_type name="sop_4" num_pb="1" blif_model=".subckt int_sop_accum_4">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="ax" num_pins="9"/>
-            <input name="ay" num_pins="9"/>
-            <input name="bx" num_pins="9"/>
-            <input name="by" num_pins="9"/>
-            <input name="cx" num_pins="9"/>
-            <input name="cy" num_pins="9"/>
-            <input name="dx" num_pins="9"/>
-            <input name="dy" num_pins="9"/>
-            <input name="chainin" num_pins="64"/>
-            <output name="result" num_pins="64"/>
-            <output name="chainout" num_pins="64"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_4.mode_sigs" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ax" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ay" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.bx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.by" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cy" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dx" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dy" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.chainin" out_port="sop_4.result"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.reset" out_port="sop_4.result"/>
-
-            <delay_constant max="2.14e-9" in_port="sop_4.mode_sigs" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ax" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.ay" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.bx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.by" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.cy" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dx" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.dy" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.chainin" out_port="sop_4.chainout"/>
-            <delay_constant max="2.14e-9" in_port="sop_4.reset" out_port="sop_4.chainout"/>
-
-            <T_setup value="18.91e-12" port="sop_4.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.ax" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.ay" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.bx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.by" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.cx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.cy" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.dx" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.dy" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="sop_4.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.ax" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.ay" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.bx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.by" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.cx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.cy" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.dx" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.dy" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="sop_4.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="sop_4.clk">
-            </direct>
-            <direct name="reset" input="dsp_pb.reset" output="sop_4.reset">
-            </direct>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="sop_4.mode_sigs">
-            </direct>
-            <direct name="datain2ax" input="dsp_pb.datain[8:0]" output="sop_4.ax">
-            </direct>
-            <direct name="datain2ay" input="dsp_pb.datain[17:9]" output="sop_4.ay">
-            </direct>
-            <direct name="datain2bx" input="dsp_pb.datain[26:18]" output="sop_4.bx">
-            </direct>
-            <direct name="datain2by" input="dsp_pb.datain[35:27]" output="sop_4.by">
-            </direct>
-            <direct name="datain2cx" input="dsp_pb.datain[44:36]" output="sop_4.cx">
-            </direct>
-            <direct name="datain2cy" input="dsp_pb.datain[53:45]" output="sop_4.cy">
-            </direct>
-            <direct name="datain2dx" input="dsp_pb.datain[62:54]" output="sop_4.dx">
-            </direct>
-            <direct name="datain2dy" input="dsp_pb.datain[71:63]" output="sop_4.dy">
-            </direct>
-            <direct name="chainin"   input="dsp_pb.chainin[63:0]" output="sop_4.chainin">
-            </direct>
-            <direct name="dataout2result" input="sop_4.result" output="dsp_pb.result[63:0]">
-            </direct>
-            <direct name="chainout" input="sop_4.chainout" output="dsp_pb.chainout[63:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- Fixed point mac mode (result = a*b + accumulated value-->
-        <mode name="mac_27x27_fixed_pt_mode">
-          <pb_type name="mac_27x27_fixed_pt" blif_model=".subckt mac_int_27x27" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="a" num_pins="27"/>
-            <input name="b" num_pins="27"/>
-            <output name="out" num_pins="54"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="mac_27x27_fixed_pt.a" out_port="mac_27x27_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_27x27_fixed_pt.b" out_port="mac_27x27_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_27x27_fixed_pt.reset" out_port="mac_27x27_fixed_pt.out"/>
-
-            <T_setup value="18.91e-12" port="mac_27x27_fixed_pt.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_27x27_fixed_pt.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_27x27_fixed_pt.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_27x27_fixed_pt.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_27x27_fixed_pt.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_27x27_fixed_pt.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_27x27_fixed_pt.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_27x27_fixed_pt.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="mac_27x27_fixed_pt.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="mac_27x27_fixed_pt.clk"/>
-            <direct name="atoa" input="dsp_pb.datain[26:0]" output="mac_27x27_fixed_pt.a"/>
-            <direct name="btob" input="dsp_pb.datain[53:27]" output="mac_27x27_fixed_pt.b"/>
-            <direct name="sumouttosumout" input="mac_27x27_fixed_pt.out" output="dsp_pb.result[53:0]"/>
-          </interconnect>
-        </mode>
-
-        <!-- Fixed point mac mode (result = a*b + accumulated value-->
-        <mode name="mac_18x19_fixed_pt_mode">
-          <pb_type name="mac_fixed_pt" blif_model=".subckt mac_int_18x19" num_pb="2">
-            <input name="reset" num_pins="1"/>
-            <input name="a" num_pins="18"/>
-            <input name="b" num_pins="19"/>
-            <output name="out" num_pins="37"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="mac_fixed_pt.a" out_port="mac_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_fixed_pt.b" out_port="mac_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_fixed_pt.reset" out_port="mac_fixed_pt.out"/>
-
-            <T_setup value="18.91e-12" port="mac_fixed_pt.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fixed_pt.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fixed_pt.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fixed_pt.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fixed_pt.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fixed_pt.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fixed_pt.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fixed_pt.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset0" input="dsp_pb.reset" output="mac_fixed_pt[0].reset"/>
-            <direct name="reset1" input="dsp_pb.reset" output="mac_fixed_pt[1].reset"/>
-            <direct name="clk0" input="dsp_pb.clk" output="mac_fixed_pt[0].clk"/>
-            <direct name="clk1" input="dsp_pb.clk" output="mac_fixed_pt[1].clk"/>
-            <direct name="atoa0" input="dsp_pb.datain[17:0]" output="mac_fixed_pt[0].a"/>
-            <direct name="btob0" input="dsp_pb.datain[36:18]" output="mac_fixed_pt[0].b"/>
-            <direct name="atoa1" input="dsp_pb.datain[54:37]" output="mac_fixed_pt[1].a"/>
-            <direct name="btob1" input="dsp_pb.datain[73:55]" output="mac_fixed_pt[1].b"/>
-            <direct name="sumouttosumout0" input="mac_fixed_pt[0].out" output="dsp_pb.result[36:0]"/>
-            <direct name="sumouttosumout1" input="mac_fixed_pt[1].out" output="dsp_pb.result[73:37]"/>
-          </interconnect>
-        </mode>
-
-        <!-- Fixed point mac mode (result = a*b + accumulated value-->
-        <mode name="mac_9x9_fixed_pt_mode">
-          <pb_type name="mac_9x9_fixed_pt" blif_model=".subckt mac_int_9x9" num_pb="4">
-            <input name="reset" num_pins="1"/>
-            <input name="a" num_pins="9"/>
-            <input name="b" num_pins="9"/>
-            <output name="out" num_pins="18"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.14e-9" in_port="mac_9x9_fixed_pt.a" out_port="mac_9x9_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_9x9_fixed_pt.b" out_port="mac_9x9_fixed_pt.out"/>
-            <delay_constant max="2.14e-9" in_port="mac_9x9_fixed_pt.reset" out_port="mac_9x9_fixed_pt.out"/>
-
-            <T_setup value="18.91e-12" port="mac_9x9_fixed_pt.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_9x9_fixed_pt.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_9x9_fixed_pt.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_9x9_fixed_pt.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_9x9_fixed_pt.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_9x9_fixed_pt.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_9x9_fixed_pt.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_9x9_fixed_pt.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset0" input="dsp_pb.reset" output="mac_9x9_fixed_pt[0].reset"/>
-            <direct name="reset1" input="dsp_pb.reset" output="mac_9x9_fixed_pt[1].reset"/>
-            <direct name="reset2" input="dsp_pb.reset" output="mac_9x9_fixed_pt[2].reset"/>
-            <direct name="reset3" input="dsp_pb.reset" output="mac_9x9_fixed_pt[3].reset"/>
-            <direct name="clk0" input="dsp_pb.clk" output="mac_9x9_fixed_pt[0].clk"/>
-            <direct name="clk1" input="dsp_pb.clk" output="mac_9x9_fixed_pt[1].clk"/>
-            <direct name="clk2" input="dsp_pb.clk" output="mac_9x9_fixed_pt[2].clk"/>
-            <direct name="clk3" input="dsp_pb.clk" output="mac_9x9_fixed_pt[3].clk"/>
-            <direct name="atoa0" input="dsp_pb.datain[8:0]" output="mac_9x9_fixed_pt[0].a"/>
-            <direct name="btob0" input="dsp_pb.datain[17:9]" output="mac_9x9_fixed_pt[0].b"/>
-            <direct name="atoa1" input="dsp_pb.datain[26:18]" output="mac_9x9_fixed_pt[1].a"/>
-            <direct name="btob1" input="dsp_pb.datain[35:27]" output="mac_9x9_fixed_pt[1].b"/>
-            <direct name="atoa2" input="dsp_pb.datain[44:36]" output="mac_9x9_fixed_pt[2].a"/>
-            <direct name="btob2" input="dsp_pb.datain[53:45]" output="mac_9x9_fixed_pt[2].b"/>
-            <direct name="atoa3" input="dsp_pb.datain[62:54]" output="mac_9x9_fixed_pt[3].a"/>
-            <direct name="btob3" input="dsp_pb.datain[71:63]" output="mac_9x9_fixed_pt[3].b"/>
-            <direct name="sumouttosumout0" input="mac_9x9_fixed_pt[0].out" output="dsp_pb.result[17:0]"/>
-            <direct name="sumouttosumout1" input="mac_9x9_fixed_pt[1].out" output="dsp_pb.result[35:18]"/>
-            <direct name="sumouttosumout2" input="mac_9x9_fixed_pt[2].out" output="dsp_pb.result[53:36]"/>
-            <direct name="sumouttosumout3" input="mac_9x9_fixed_pt[3].out" output="dsp_pb.result[71:54]"/>
-          </interconnect>
-        </mode>
-
-        <!-- floating point multiplier mode (result = a * b)-->
-        <mode name="mult_fp32_mode">
-          <pb_type name="mult_fp32" blif_model=".subckt mult_fp_32" num_pb="1">
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <output name="out" num_pins="32"/>
-
-            <delay_constant max="2.56e-9" in_port="mult_fp32.a" out_port="mult_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="mult_fp32.b" out_port="mult_fp32.out"/>
-          </pb_type>
-          <interconnect>
-            <direct name="a2a" input="dsp_pb.datain[31:0]" output="mult_fp32.a">
-            </direct>
-            <direct name="b2b" input="dsp_pb.datain[63:32]" output="mult_fp32.b">
-            </direct>
-            <direct name="out2out" input="mult_fp32.out" output="dsp_pb.result[31:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point multiplier mode (result = a * b)-->
-        <mode name="mult_fp16_mode">
-          <pb_type name="mult_fp16" blif_model=".subckt mult_fp_16" num_pb="2">
-            <input name="a" num_pins="16"/>
-            <input name="b" num_pins="16"/>
-            <output name="out" num_pins="16"/>
-
-            <delay_constant max="2.56e-9" in_port="mult_fp16.a" out_port="mult_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="mult_fp16.b" out_port="mult_fp16.out"/>
-          </pb_type>
-          <interconnect>
-            <direct name="a2a0" input="dsp_pb.datain[15:0]" output="mult_fp16[0].a"></direct>
-            <direct name="a2a1" input="dsp_pb.datain[31:16]" output="mult_fp16[1].a"></direct>
-            <direct name="b2b0" input="dsp_pb.datain[47:32]" output="mult_fp16[0].b"></direct>
-            <direct name="b2b1" input="dsp_pb.datain[63:48]" output="mult_fp16[1].b"></direct>
-            <direct name="out2out0" input="mult_fp16[0].out" output="dsp_pb.result[15:0]"></direct>
-            <direct name="out2out1" input="mult_fp16[1].out" output="dsp_pb.result[31:16]"></direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point adder mode (result = a + b)-->
-        <mode name="adder_fp32_mode"> 
-          <pb_type name="adder_fp32" blif_model=".subckt addition_fp_32" num_pb="1">
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <output name="out" num_pins="32"/>
-
-            <delay_constant max="2.56e-9" in_port="adder_fp32.a" out_port="adder_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="adder_fp32.b" out_port="adder_fp32.out"/>
-          </pb_type>
-          <interconnect>
-            <direct name="atoa" input="dsp_pb.datain[31:0]" output="adder_fp32.a">
-            </direct>
-            <direct name="btob" input="dsp_pb.datain[63:32]" output="adder_fp32.b">
-            </direct>
-            <direct name="sumouttosumout" input="adder_fp32.out" output="dsp_pb.result[31:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point adder mode (result = a + b)-->
-        <mode name="adder_fp16_mode">
-          <pb_type name="adder_fp16" blif_model=".subckt addition_fp_16" num_pb="2">
-            <input name="a" num_pins="16"/>
-            <input name="b" num_pins="16"/>
-            <output name="out" num_pins="16"/>
-
-            <delay_constant max="2.56e-9" in_port="adder_fp16.a" out_port="adder_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="adder_fp16.b" out_port="adder_fp16.out"/>
-          </pb_type>
-          <interconnect>
-            <direct name="a2a0" input="dsp_pb.datain[15:0]" output="adder_fp16[0].a"></direct>
-            <direct name="a2a1" input="dsp_pb.datain[31:16]" output="adder_fp16[1].a"></direct>
-            <direct name="b2b0" input="dsp_pb.datain[47:32]" output="adder_fp16[0].b"></direct>
-            <direct name="b2b1" input="dsp_pb.datain[63:48]" output="adder_fp16[1].b"></direct>
-            <direct name="out2out0" input="adder_fp16[0].out" output="dsp_pb.result[15:0]"></direct>
-            <direct name="out2out1" input="adder_fp16[1].out" output="dsp_pb.result[31:16]"></direct>
-          </interconnect>
-        </mode>
-
-        <!-- clocked floating point multiplier mode (result = a * b)-->
-        <mode name="mult_fp32_clocked_mode">
-          <pb_type name="mult_fp32" blif_model=".subckt mult_fp_clk_32" num_pb="1">
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <output name="out" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="mult_fp32.a" out_port="mult_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="mult_fp32.b" out_port="mult_fp32.out"/>
-
-            <T_setup value="18.91e-12" port="mult_fp32.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_fp32.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_fp32.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp32.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp32.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp32.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="mult_fp32.clk"/>
-            <direct name="a2a" input="dsp_pb.datain[31:0]" output="mult_fp32.a">
-            </direct>
-            <direct name="b2b" input="dsp_pb.datain[63:32]" output="mult_fp32.b">
-            </direct>
-            <direct name="out2out" input="mult_fp32.out" output="dsp_pb.result[31:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- clocked floating point multiplier mode (result = a * b)-->
-        <mode name="mult_fp16_clocked_mode">
-          <pb_type name="mult_fp16" blif_model=".subckt mult_fp_clk_16" num_pb="2">
-            <input name="a" num_pins="16"/>
-            <input name="b" num_pins="16"/>
-            <output name="out" num_pins="16"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="mult_fp16.a" out_port="mult_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="mult_fp16.b" out_port="mult_fp16.out"/>
-
-            <T_setup value="18.91e-12" port="mult_fp16.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_fp16.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mult_fp16.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp16.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp16.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mult_fp16.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk0" input="dsp_pb.clk" output="mult_fp16[0].clk"/>
-            <direct name="clk1" input="dsp_pb.clk" output="mult_fp16[1].clk"/>
-            <direct name="a2a0" input="dsp_pb.datain[15:0]" output="mult_fp16[0].a"></direct>
-            <direct name="a2a1" input="dsp_pb.datain[31:16]" output="mult_fp16[1].a"></direct>
-            <direct name="b2b0" input="dsp_pb.datain[47:32]" output="mult_fp16[0].b"></direct>
-            <direct name="b2b1" input="dsp_pb.datain[63:48]" output="mult_fp16[1].b"></direct>
-            <direct name="out2out0" input="mult_fp16[0].out" output="dsp_pb.result[15:0]"></direct>
-            <direct name="out2out1" input="mult_fp16[1].out" output="dsp_pb.result[31:16]"></direct>
-          </interconnect>
-        </mode>
-
-        <!-- clocked floating point adder mode (result = a + b)-->
-        <mode name="adder_fp32_clocked_mode"> 
-          <pb_type name="adder_fp32" blif_model=".subckt addition_fp_clk_32" num_pb="1">
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <output name="out" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="adder_fp32.a" out_port="adder_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="adder_fp32.b" out_port="adder_fp32.out"/>
-
-            <T_setup value="18.91e-12" port="adder_fp32.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="adder_fp32.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="adder_fp32.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp32.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp32.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp32.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="adder_fp32.clk"/>
-            <direct name="atoa" input="dsp_pb.datain[31:0]" output="adder_fp32.a">
-            </direct>
-            <direct name="btob" input="dsp_pb.datain[63:32]" output="adder_fp32.b">
-            </direct>
-            <direct name="sumouttosumout" input="adder_fp32.out" output="dsp_pb.result[31:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- clocked floating point adder mode (result = a + b)-->
-        <mode name="adder_fp16_clocked_mode">
-          <pb_type name="adder_fp16" blif_model=".subckt addition_fp_clk_16" num_pb="2">
-            <input name="a" num_pins="16"/>
-            <input name="b" num_pins="16"/>
-            <output name="out" num_pins="16"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="adder_fp16.a" out_port="adder_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="adder_fp16.b" out_port="adder_fp16.out"/>
-
-            <T_setup value="18.91e-12" port="adder_fp16.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="adder_fp16.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="adder_fp16.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp16.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp16.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="adder_fp16.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk0" input="dsp_pb.clk" output="adder_fp16[0].clk"/>
-            <direct name="clk1" input="dsp_pb.clk" output="adder_fp16[1].clk"/>
-            <direct name="a2a0" input="dsp_pb.datain[15:0]" output="adder_fp16[0].a"></direct>
-            <direct name="a2a1" input="dsp_pb.datain[31:16]" output="adder_fp16[1].a"></direct>
-            <direct name="b2b0" input="dsp_pb.datain[47:32]" output="adder_fp16[0].b"></direct>
-            <direct name="b2b1" input="dsp_pb.datain[63:48]" output="adder_fp16[1].b"></direct>
-            <direct name="out2out0" input="adder_fp16[0].out" output="dsp_pb.result[15:0]"></direct>
-            <direct name="out2out1" input="adder_fp16[1].out" output="dsp_pb.result[31:16]"></direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point mac mode (result = a*b + accumulated value-->
-        <mode name="mac_fp32_mode">
-          <pb_type name="mac_fp32" blif_model=".subckt mac_fp_32" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <output name="out" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="mac_fp32.a" out_port="mac_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="mac_fp32.b" out_port="mac_fp32.out"/>
-            <delay_constant max="2.56e-9" in_port="mac_fp32.reset" out_port="mac_fp32.out"/>
-
-            <T_setup value="18.91e-12" port="mac_fp32.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp32.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp32.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp32.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp32.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp32.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp32.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp32.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="mac_fp32.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="mac_fp32.clk"/>
-            <direct name="atoa" input="dsp_pb.datain[31:0]" output="mac_fp32.a">
-            </direct>
-            <direct name="btob" input="dsp_pb.datain[63:32]" output="mac_fp32.b">
-            </direct>
-            <direct name="sumouttosumout" input="mac_fp32.out" output="dsp_pb.result[31:0]">
-            </direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point 16-bit mac mode (result = a*b + accumulated value-->
-        <mode name="mac_fp16_mode">
-          <pb_type name="mac_fp16" blif_model=".subckt mac_fp_16" num_pb="2">
-            <input name="reset" num_pins="1"/>
-            <input name="a" num_pins="16"/>
-            <input name="b" num_pins="16"/>
-            <output name="out" num_pins="16"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="mac_fp16.a" out_port="mac_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="mac_fp16.b" out_port="mac_fp16.out"/>
-            <delay_constant max="2.56e-9" in_port="mac_fp16.reset" out_port="mac_fp16.out"/>
-
-            <T_setup value="18.91e-12" port="mac_fp16.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp16.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp16.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="mac_fp16.out" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp16.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp16.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp16.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="mac_fp16.out" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset0" input="dsp_pb.reset" output="mac_fp16[0].reset"></direct>
-            <direct name="reset1" input="dsp_pb.reset" output="mac_fp16[1].reset"></direct>
-            <direct name="clk0" input="dsp_pb.clk" output="mac_fp16[0].clk"></direct>
-            <direct name="clk1" input="dsp_pb.clk" output="mac_fp16[1].clk"></direct>
-            <direct name="atoa0" input="dsp_pb.datain[15:0]"  output="mac_fp16[0].a"></direct>
-            <direct name="atoa1" input="dsp_pb.datain[31:16]" output="mac_fp16[1].a"></direct>
-            <direct name="btob0" input="dsp_pb.datain[47:32]" output="mac_fp16[0].b"></direct>
-            <direct name="btob1" input="dsp_pb.datain[63:48]" output="mac_fp16[1].b"></direct>
-            <direct name="sumouttosumout0" input="mac_fp16[0].out" output="dsp_pb.result[15:0]"></direct>
-            <direct name="sumouttosumout1" input="mac_fp16[1].out" output="dsp_pb.result[31:16]"></direct>
-          </interconnect>
-        </mode>
-
-        <!-- floating point fp16 sum-of-2 mult mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b). chainout = third_inp or result-->
-        <mode name="fp16_sum_of_products_mode"> 
-          <pb_type name="fp16_sum_of_2_mult" blif_model=".subckt fp16_mult_add" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="top_a" num_pins="16"/>
-            <input name="top_b" num_pins="16"/>
-            <input name="bot_a" num_pins="16"/>
-            <input name="bot_b" num_pins="16"/>
-            <input name="fp32_in" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.reset" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.mode_sigs" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_a" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_b" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_a" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_b" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.fp32_in" out_port="fp16_sum_of_2_mult.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.reset" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.mode_sigs" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_a" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_b" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_a" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_b" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.fp32_in" out_port="fp16_sum_of_2_mult.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.top_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.top_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.bot_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.bot_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.top_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.top_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.bot_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.bot_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="fp16_sum_of_2_mult.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp16_sum_of_2_mult.clk"/>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp16_sum_of_2_mult.mode_sigs">
-            </direct>
-            <direct name="atoa_top" input="dsp_pb.datain[15:0]" output="fp16_sum_of_2_mult.top_a">
-            </direct>
-            <direct name="btob_top" input="dsp_pb.datain[31:16]" output="fp16_sum_of_2_mult.top_b">
-            </direct>
-            <direct name="result_top" input="fp16_sum_of_2_mult.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="atoa_bot" input="dsp_pb.datain[47:32]" output="fp16_sum_of_2_mult.bot_a">
-            </direct>
-            <direct name="btob_bot" input="dsp_pb.datain[63:48]" output="fp16_sum_of_2_mult.bot_b">
-            </direct>
-            <direct name="result_bot" input="fp16_sum_of_2_mult.result" output="dsp_pb.result[63:32]">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]" output="fp16_sum_of_2_mult.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp16_sum_of_2_mult.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>  
-
-        <!-- floating point fp16 sum-of-2 mult mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b + fp32 chainin or third inp. chainout = third_inp or result)-->
-        <mode name="fp16_sum_of_products_2_mult_mode"> 
-          <pb_type name="fp16_sum_of_2_mult" blif_model=".subckt fp16_sop2_mult" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="top_a" num_pins="16"/>
-            <input name="top_b" num_pins="16"/>
-            <input name="bot_a" num_pins="16"/>
-            <input name="bot_b" num_pins="16"/>
-            <input name="fp32_in" num_pins="32"/>
-            <input name="chainin" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.reset" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.mode_sigs" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_a" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_b" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_a" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_b" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.chainin" out_port="fp16_sum_of_2_mult.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.fp32_in" out_port="fp16_sum_of_2_mult.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.reset" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.mode_sigs" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_a" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.top_b" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_a" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.bot_b" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.chainin" out_port="fp16_sum_of_2_mult.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_mult.fp32_in" out_port="fp16_sum_of_2_mult.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.top_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.top_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.bot_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.bot_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_mult.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.top_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.top_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.bot_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.bot_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_mult.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="fp16_sum_of_2_mult.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp16_sum_of_2_mult.clk"/>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp16_sum_of_2_mult.mode_sigs">
-            </direct>
-            <direct name="atoa_top" input="dsp_pb.datain[15:0]" output="fp16_sum_of_2_mult.top_a">
-            </direct>
-            <direct name="btob_top" input="dsp_pb.datain[31:16]" output="fp16_sum_of_2_mult.top_b">
-            </direct>
-            <direct name="result_top" input="fp16_sum_of_2_mult.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="atoa_bot" input="dsp_pb.datain[47:32]" output="fp16_sum_of_2_mult.bot_a">
-            </direct>
-            <direct name="btob_bot" input="dsp_pb.datain[63:48]" output="fp16_sum_of_2_mult.bot_b">
-            </direct>
-            <direct name="result_bot" input="fp16_sum_of_2_mult.result" output="dsp_pb.result[63:32]">
-            </direct>
-            <direct name="chainin" input="dsp_pb.chainin[31:0]" output="fp16_sum_of_2_mult.chainin">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]" output="fp16_sum_of_2_mult.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp16_sum_of_2_mult.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>        
-
-        <!-- floating point fp16 sum-of-2 accum mode (result = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b + accumulator. chainout = result)-->
-        <mode name="fp16_sum_of_products_2_accum_mode"> 
-          <pb_type name="fp16_sum_of_2_accum" blif_model=".subckt fp16_sop2_accum" num_pb="1">
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="reset" num_pins="1"/>
-            <input name="top_a" num_pins="16"/>
-            <input name="top_b" num_pins="16"/>
-            <input name="bot_a" num_pins="16"/>
-            <input name="bot_b" num_pins="16"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.mode_sigs" out_port="fp16_sum_of_2_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.top_a" out_port="fp16_sum_of_2_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.top_b" out_port="fp16_sum_of_2_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.bot_a" out_port="fp16_sum_of_2_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.bot_b" out_port="fp16_sum_of_2_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.reset" out_port="fp16_sum_of_2_accum.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.mode_sigs" out_port="fp16_sum_of_2_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.top_a" out_port="fp16_sum_of_2_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.top_b" out_port="fp16_sum_of_2_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.bot_a" out_port="fp16_sum_of_2_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.bot_b" out_port="fp16_sum_of_2_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_sum_of_2_accum.reset" out_port="fp16_sum_of_2_accum.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.top_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.top_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.bot_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.bot_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_sum_of_2_accum.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.top_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.top_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.bot_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.bot_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_sum_of_2_accum.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp16_sum_of_2_accum.mode_sigs"/>
-            <direct name="reset" input="dsp_pb.reset" output="fp16_sum_of_2_accum.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp16_sum_of_2_accum.clk"/>
-            <direct name="atoa_top" input="dsp_pb.datain[15:0]" output="fp16_sum_of_2_accum.top_a">
-            </direct>
-            <direct name="btob_top" input="dsp_pb.datain[31:16]" output="fp16_sum_of_2_accum.top_b">
-            </direct>
-            <direct name="result_top" input="fp16_sum_of_2_accum.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="atoa_bot" input="dsp_pb.datain[47:32]" output="fp16_sum_of_2_accum.bot_a">
-            </direct>
-            <direct name="btob_bot" input="dsp_pb.datain[63:48]" output="fp16_sum_of_2_accum.bot_b">
-            </direct>
-            <direct name="result_bot" input="fp16_sum_of_2_accum.result" output="dsp_pb.result[63:32]">
-            </direct>
-            <direct name="chainout" input="fp16_sum_of_2_accum.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>        
-
-        <!-- floating point fp16 mult, fp32 add mode (chainout = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b. result = chainin + third_inp)-->
-        <mode name="fp16_mult_fp32_add"> 
-          <pb_type name="fp16_mult_fp32_add" blif_model=".subckt fp16_mult_fp32_add" num_pb="1">
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="reset" num_pins="1"/>
-            <input name="top_a" num_pins="16"/>
-            <input name="top_b" num_pins="16"/>
-            <input name="bot_a" num_pins="16"/>
-            <input name="bot_b" num_pins="16"/>
-            <input name="fp32_in" num_pins="32"/>
-            <input name="chainin" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.reset" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.mode_sigs" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.top_a" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.top_b" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.bot_a" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.bot_b" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.chainin" out_port="fp16_mult_fp32_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.fp32_in" out_port="fp16_mult_fp32_add.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.reset" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.mode_sigs" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.top_a" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.top_b" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.bot_a" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.bot_b" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.chainin" out_port="fp16_mult_fp32_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_add.fp32_in" out_port="fp16_mult_fp32_add.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.top_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.top_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.bot_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.bot_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_add.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.top_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.top_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.bot_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.bot_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_add.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="clk" input="dsp_pb.clk" output="fp16_mult_fp32_add.clk"/>
-            <direct name="reset" input="dsp_pb.reset" output="fp16_mult_fp32_add.reset"/>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp16_mult_fp32_add.mode_sigs">
-            </direct>
-            <direct name="atoa_top" input="dsp_pb.datain[15:0]" output="fp16_mult_fp32_add.top_a">
-            </direct>
-            <direct name="btob_top" input="dsp_pb.datain[31:16]" output="fp16_mult_fp32_add.top_b">
-            </direct>
-            <direct name="result_top" input="fp16_mult_fp32_add.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="atoa_bot" input="dsp_pb.datain[47:32]" output="fp16_mult_fp32_add.bot_a">
-            </direct>
-            <direct name="btob_bot" input="dsp_pb.datain[63:48]" output="fp16_mult_fp32_add.bot_b">
-            </direct>
-            <direct name="result_bot" input="fp16_mult_fp32_add.result" output="dsp_pb.result[63:32]">
-            </direct>
-            <direct name="chainin" input="dsp_pb.chainin[31:0]" output="fp16_mult_fp32_add.chainin">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]]" output="fp16_mult_fp32_add.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp16_mult_fp32_add.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>      
-
-        <!-- floating point fp16 mult, fp32 accum mode (chainout = fp16_mult_top_a * fp16_mult_top_b + fp16_mult_bot_a * fp16_mult_bot_b. result = third_inp + accumulator)-->
-        <mode name="fp16_mult_fp32_accum"> 
-          <pb_type name="fp16_mult_fp32_accum" blif_model=".subckt fp16_mult_fp32_accum" num_pb="1">
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="reset" num_pins="1"/>
-            <input name="top_a" num_pins="16"/>
-            <input name="top_b" num_pins="16"/>
-            <input name="bot_a" num_pins="16"/>
-            <input name="bot_b" num_pins="16"/>
-            <input name="fp32_in" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.mode_sigs" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.top_a" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.top_b" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.bot_a" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.bot_b" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.fp32_in" out_port="fp16_mult_fp32_accum.result"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.reset" out_port="fp16_mult_fp32_accum.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.mode_sigs" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.top_a" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.top_b" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.bot_a" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.bot_b" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.fp32_in" out_port="fp16_mult_fp32_accum.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp16_mult_fp32_accum.reset" out_port="fp16_mult_fp32_accum.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.top_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.top_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.bot_a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.bot_b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp16_mult_fp32_accum.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.top_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.top_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.bot_a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.bot_b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp16_mult_fp32_accum.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp16_mult_fp32_accum.mode_sigs"/>
-            <direct name="reset" input="dsp_pb.reset" output="fp16_mult_fp32_accum.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp16_mult_fp32_accum.clk"/>
-            <direct name="atoa_top" input="dsp_pb.datain[15:0]" output="fp16_mult_fp32_accum.top_a">
-            </direct>
-            <direct name="btob_top" input="dsp_pb.datain[31:16]" output="fp16_mult_fp32_accum.top_b">
-            </direct>
-            <direct name="result_top" input="fp16_mult_fp32_accum.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="atoa_bot" input="dsp_pb.datain[47:32]" output="fp16_mult_fp32_accum.bot_a">
-            </direct>
-            <direct name="btob_bot" input="dsp_pb.datain[63:48]" output="fp16_mult_fp32_accum.bot_b">
-            </direct>
-            <direct name="result_bot" input="fp16_mult_fp32_accum.result" output="dsp_pb.result[63:32]">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]" output="fp16_mult_fp32_accum.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp16_mult_fp32_accum.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>      
-
-        <!-- floating point fp32 mult_then_add mode (result = fp32_mult_a * fp32_mult_b + chainin. chainout = third_inp or result) -->
-        <mode name="fp32_mult_then_add"> 
-          <pb_type name="fp32_mult_then_add" blif_model=".subckt fp32_mult_then_add" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <input name="fp32_in" num_pins="32"/>
-            <input name="chainin" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.reset" out_port="fp32_mult_then_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.mode_sigs" out_port="fp32_mult_then_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.a" out_port="fp32_mult_then_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.b" out_port="fp32_mult_then_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.chainin" out_port="fp32_mult_then_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.fp32_in" out_port="fp32_mult_then_add.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.reset" out_port="fp32_mult_then_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.mode_sigs" out_port="fp32_mult_then_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.a" out_port="fp32_mult_then_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.b" out_port="fp32_mult_then_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.chainin" out_port="fp32_mult_then_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_then_add.fp32_in" out_port="fp32_mult_then_add.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_then_add.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_then_add.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="fp32_mult_then_add.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp32_mult_then_add.clk"/>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp32_mult_then_add.mode_sigs">
-            </direct>
-            <direct name="atoa" input="dsp_pb.datain[31:0]" output="fp32_mult_then_add.a">
-            </direct>
-            <direct name="btob" input="dsp_pb.datain[63:32]" output="fp32_mult_then_add.b">
-            </direct>
-            <direct name="result" input="fp32_mult_then_add.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="chainin" input="dsp_pb.chainin[31:0]" output="fp32_mult_then_add.chainin">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]]" output="fp32_mult_then_add.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp32_mult_then_add.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>      
-
-        <!-- floating point fp32 mult_add mode (chainout = fp32_mult_a * fp32_mult_b. chainout = third_inp + chainin)-->
-        <mode name="fp32_mult_add"> 
-          <pb_type name="fp32_mult_add" blif_model=".subckt fp32_mult_add" num_pb="1">
-            <input name="reset" num_pins="1"/>
-            <input name="mode_sigs" num_pins="12"/>
-            <input name="a" num_pins="32"/>
-            <input name="b" num_pins="32"/>
-            <input name="fp32_in" num_pins="32"/>
-            <input name="chainin" num_pins="32"/>
-            <output name="result" num_pins="32"/>
-            <output name="chainout" num_pins="32"/>
-            <clock name="clk" num_pins="1"/>
-
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.reset" out_port="fp32_mult_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.mode_sigs" out_port="fp32_mult_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.a" out_port="fp32_mult_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.b" out_port="fp32_mult_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.chainin" out_port="fp32_mult_add.result"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.fp32_in" out_port="fp32_mult_add.result"/>
-
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.reset" out_port="fp32_mult_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.mode_sigs" out_port="fp32_mult_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.a" out_port="fp32_mult_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.b" out_port="fp32_mult_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.chainin" out_port="fp32_mult_add.chainout"/>
-            <delay_constant max="2.56e-9" in_port="fp32_mult_add.fp32_in" out_port="fp32_mult_add.chainout"/>
-
-            <T_setup value="18.91e-12" port="fp32_mult_add.reset" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.mode_sigs" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.a" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.b" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.chainin" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.fp32_in" clock="clk"/>
-            <T_setup value="18.91e-12" port="fp32_mult_add.result" clock="clk"/>
-
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.reset" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.mode_sigs" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.a" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.b" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.chainin" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.fp32_in" clock="clk"/>
-            <T_clock_to_Q max="60.32e-12" min="60.32e-12" port="fp32_mult_add.result" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <direct name="reset" input="dsp_pb.reset" output="fp32_mult_add.reset"/>
-            <direct name="clk" input="dsp_pb.clk" output="fp32_mult_add.clk"/>
-            <direct name="mode_sigs" input="dsp_pb.mode_sigs" output="fp32_mult_add.mode_sigs">
-            </direct>
-            <direct name="atoa" input="dsp_pb.datain[31:0]" output="fp32_mult_add.a">
-            </direct>
-            <direct name="btob" input="dsp_pb.datain[63:32]" output="fp32_mult_add.b">
-            </direct>
-            <direct name="result" input="fp32_mult_add.result" output="dsp_pb.result[31:0]">
-            </direct>
-            <direct name="chainin" input="dsp_pb.chainin[31:0]" output="fp32_mult_add.chainin">
-            </direct>
-            <direct name="fp32in" input="dsp_pb.datain[95:64]]" output="fp32_mult_add.fp32_in">
-            </direct>
-            <direct name="chainout" input="fp32_mult_add.chainout" output="dsp_pb.chainout[31:0]">
-            </direct>
-          </interconnect>
-        </mode>      
-      </pb_type>
-
-      <interconnect>
-        <direct name="mode_sigs" input="dsp.dsp_I1[11:0]" output ="dsp_pb.mode_sigs"/>
-        <direct name="datain1" input="dsp.dsp_I1[63:12]" output ="dsp_pb.datain[51:0]"/>
-        <direct name="datain2" input="dsp.dsp_I2" output ="dsp_pb.datain[115:52]"/>
-        <direct name="reset" input="dsp.reset" output="dsp_pb.reset"></direct>
-        <direct name="chainin" input="dsp.chainin"    output="dsp_pb.chainin"></direct>
-        <direct name="chainout" input="dsp_pb.chainout" output="dsp.chainout"></direct>
-        <direct name="scanin" input="dsp.scanin"    output="dsp_pb.scanin"></direct>
-        <direct name="scanout" input="dsp_pb.scanout" output="dsp.scanout"></direct>
-        <direct name="result" input="dsp_pb.result" output="dsp.result"></direct>
-        <direct name="clk" input="dsp.clk" output="dsp_pb.clk"></direct>
-      </interconnect>  
-
-    </pb_type>
-    <interconnect>
-        <!--50% sparse crossbar means 50% of the lines can reach an actual input of the dsp 
-        We do this by splitting inputs into two buckets and having two full crossbars-->
-        <!--
-       <complete name="first_half" input="dsp_top.dsp_I1" output="dsp.dsp_I1">
-            <delay_constant max="333e-12" in_port="dsp_top.dsp_I1" out_port="dsp.dsp_I1"/>
-       </complete>
-
-        <complete name="second_half" input="dsp_top.dsp_I2" output="dsp.dsp_I2">
-            <delay_constant max="333e-12" in_port="dsp_top.dsp_I2" out_port="dsp.dsp_I2"/>
-        </complete>
-        -->
-        <direct name="enable" input="dsp_top.dsp_I1[0]" output ="dsp.dsp_I1[0]"/>
-        <direct name="loadconst" input="dsp_top.dsp_I1[1]" output ="dsp.dsp_I1[1]"/>
-        <direct name="accumulate" input="dsp_top.dsp_I1[2]" output ="dsp.dsp_I1[2]"/>
-        <direct name="negate" input="dsp_top.dsp_I1[3]" output ="dsp.dsp_I1[3]"/>
-        <direct name="sub" input="dsp_top.dsp_I1[4]" output ="dsp.dsp_I1[4]"/>
-        <direct name="mode" input="dsp_top.dsp_I1[7:5]" output ="dsp.dsp_I1[7:5]"/>
-        <direct name="mux9_select" input="dsp_top.dsp_I1[8]" output ="dsp.dsp_I1[8]"/>
-        <direct name="internal_coeffa" input="dsp_top.dsp_I1[9]" output ="dsp.dsp_I1[9]"/>
-        <direct name="internal_coeffb" input="dsp_top.dsp_I1[10]" output ="dsp.dsp_I1[10]"/>
-        <direct name="datain1" input="dsp_top.dsp_I1[63:11]" output ="dsp.dsp_I1[63:11]"/>
-        <direct name="datain2" input="dsp_top.dsp_I2" output ="dsp.dsp_I2"/>
- 
-        <direct name="reset" input="dsp_top.reset" output="dsp.reset"></direct>
-        <direct name="chainin" input="dsp_top.chainin" output="dsp.chainin">
-            <delay_constant max="1179e-12" in_port="dsp_top.chainin" out_port="dsp.chainin"/>
-        </direct>
-        <direct name="chainout" input="dsp.chainout" output="dsp_top.chainout">
-            <delay_constant max="1179e-12" in_port="dsp.chainout" out_port="dsp_top.chainout"/>
-        </direct>
-        <direct name="scanin" input="dsp_top.scanin" output="dsp.scanin">
-            <delay_constant max="1179e-12" in_port="dsp_top.scanin" out_port="dsp.scanin"/>
-        </direct>
-        <direct name="scanout" input="dsp.scanout" output="dsp_top.scanout">
-            <delay_constant max="1179e-12" in_port="dsp.scanout" out_port="dsp_top.scanout"/>
-        </direct>
-        <direct name="result" input="dsp.result" output="dsp_top.result"></direct>
-        <direct name="clk" input="dsp_top.clk" output="dsp.clk"></direct>
-    </interconnect>
-    </pb_type>
-    <!-- Define DSP slice end -->
-
-
-    <!-- Define fracturable memory begin -->
-    <!-- 
-    RAM blocks always have registered inputs. The input FFs appear before the address decoder & wordline driver,
-    and after the local input crossbar & level shifter.
-    RAM blocks optionally have registered outputs. The output FFs (if present) appear after the output crossbar.
-    If BRAM doesn't have registered outputs, then T_clk_to_q is the whole delay of the read/write operation.
-    If BRAM does have registered output, then T_clk_to_q is just the FF clk_to_q and then delay_constant
-    can be used to specify the whole delay of the read/write operation.
-
-    This RAM block has registered outputs.
-
-    The area and delay values of this RAM block were obtained (indirectly) from COFFE simulations.
-    COFFE only support widths and depths that are powers of 2. For M20K (20 Kilobit BRAM), we need
-    the width to be 40 bits and depth to be 512 (for the logically widest mode: 512x40). We can't
-    simulate these dimensions directly in COFFE. So, we simulated and obtained the results for M32K
-    (32 Kilobits BRAM) and (16 Kilobits BRAM). Then we interpolated the results.
-    For delay, a linear interpolation was used, based on the size of the Memory (16K->20K->32K).
-    For area, the value was calculated using two interpolations: (1) port based (change in number of 
-    ports in going from 16K->20K->32K) and (2) number of bits based (change in number of bits in
-    going from 16K->20K->32K). The interpolation that resulted in the larger area was picked.
-    
-
-    Here are the equations used to calculate the delays based on COFFE results:
-    T_setup (inputs) = T_level_shifter + T_register_micro_setup = 32.3ps + 18.91ps = 51.21ps
-    T_clk_to_q (inputs) = T_register_micro_clk_to_q = 60.32ps
-    T_setup (outputs) = T_register_micro_setup = 18.91ps 
-    T_clk_to_q (outputs) = T_register_micro_clk_to_q = 60.32ps
-
-    (Register setup and clk_to_q timings are actually from the FF used in the logic cluster.)
-
-    T_read = T1 + T2 + T3
-    = max (Row decoder, Pre-charge time) + (Wordline driver + Bit line delay) + (Sense amp + Output crossbar)
-
-    * Bit line delay is included in self.RAM.samp.delay time in COFFE. The Sense amp delay is actually
-    self.RAM.samp_part2.delay
-
-    T_write = T1 + T2 + T3
-    = max (Row decoder, Pre-charge time) + (Wordline driver) + (Write driver)
-
-    delay_constant values model the internal limits of a block (the combinatorial delay).
-    delay_constant = max (T_read, T_write) 
-
-	  Overall internal delay of the RAM is T_clk_to_q (inputs) + delay_constant + T_setup (outputs)
-    -->
-    <pb_type name="memory">
-      <input name="addr1" num_pins="11"/>
-      <input name="addr2" num_pins="11"/>
-      <input name="data" num_pins="40"/>
-      <input name="we1" num_pins="1"/>
-      <input name="we2" num_pins="1"/>
-      <output name="out" num_pins="40"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Specify single port mode first -->
-      <mode name="mem_512x40_sp">
-        <pb_type name="mem_512x40_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="9" port_class="address"/>
-          <input name="data" num_pins="40" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="40" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-
-          <T_setup value="51.12e-12" port="mem_512x40_sp.addr" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_512x40_sp.data" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_512x40_sp.we" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_512x40_sp.out" clock="clk"/>
-
-          <T_clock_to_Q max="60.32e-12" port="mem_512x40_sp.addr" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_512x40_sp.data" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_512x40_sp.we" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_512x40_sp.out" clock="clk"/>
-
-          <delay_constant max="0.852e-9" in_port="mem_512x40_sp.addr" out_port="mem_512x40_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_512x40_sp.data" out_port="mem_512x40_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_512x40_sp.we"   out_port="mem_512x40_sp.out"/>
-
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[8:0]" output="mem_512x40_sp.addr">
-          </direct>
-          <direct name="data1" input="memory.data" output="mem_512x40_sp.data">
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_512x40_sp.we">
-          </direct>
-          <direct name="dataout1" input="mem_512x40_sp.out" output="memory.out">
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_512x40_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-
-      <mode name="mem_1024x20_sp">
-        <pb_type name="mem_1024x20_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="10" port_class="address"/>
-          <input name="data" num_pins="20" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="20" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-
-          <T_setup value="51.12e-12" port="mem_1024x20_sp.addr" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_sp.data" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_sp.we" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_1024x20_sp.out" clock="clk"/>
-
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_sp.addr" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_sp.data" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_sp.we" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_sp.out" clock="clk"/>
-
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_sp.addr" out_port="mem_1024x20_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_sp.data" out_port="mem_1024x20_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_sp.we"   out_port="mem_1024x20_sp.out"/>
-
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x20_sp.addr">
-          </direct>
-          <direct name="data1" input="memory.data[19:0]" output="mem_1024x20_sp.data">
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_1024x20_sp.we">
-          </direct>
-          <direct name="dataout1" input="mem_1024x20_sp.out" output="memory.out[19:0]">
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_1024x20_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-
-      <mode name="mem_2048x10_sp">
-        <pb_type name="mem_2048x10_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="11" port_class="address"/>
-          <input name="data" num_pins="10" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="10" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-
-          <T_setup value="51.12e-12" port="mem_2048x10_sp.addr" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_sp.data" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_sp.we" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_2048x10_sp.out" clock="clk"/>
-
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_sp.addr" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_sp.data" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_sp.we" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_sp.out" clock="clk"/>
-
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_sp.addr" out_port="mem_2048x10_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_sp.data" out_port="mem_2048x10_sp.out"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_sp.we"   out_port="mem_2048x10_sp.out"/>
-
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x10_sp.addr">
-          </direct>
-          <direct name="data1" input="memory.data[9:0]" output="mem_2048x10_sp.data">
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_2048x10_sp.we">
-          </direct>
-          <direct name="dataout1" input="mem_2048x10_sp.out" output="memory.out[9:0]">
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_2048x10_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- Specify true dual port mode next -->
-      <mode name="mem_1024x20_dp">
-        <pb_type name="mem_1024x20_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="addr1" num_pins="10" port_class="address1"/>
-          <input name="addr2" num_pins="10" port_class="address2"/>
-          <input name="data1" num_pins="20" port_class="data_in1"/>
-          <input name="data2" num_pins="20" port_class="data_in2"/>
-          <input name="we1" num_pins="1" port_class="write_en1"/>
-          <input name="we2" num_pins="1" port_class="write_en2"/>
-          <output name="out1" num_pins="20" port_class="data_out1"/>
-          <output name="out2" num_pins="20" port_class="data_out2"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.addr1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.data1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.we1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.addr2" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.data2" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_1024x20_dp.we2" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_1024x20_dp.out1" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_1024x20_dp.out2" clock="clk"/>
-
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.addr1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.data1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.we1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.addr2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.data2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.we2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.out1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_1024x20_dp.out2" clock="clk"/>
-
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.addr1" out_port="mem_1024x20_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.data1" out_port="mem_1024x20_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.we1" out_port="mem_1024x20_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.addr2" out_port="mem_1024x20_dp.out2"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.data2" out_port="mem_1024x20_dp.out2"/>
-          <delay_constant max="0.852e-9" in_port="mem_1024x20_dp.we2" out_port="mem_1024x20_dp.out2"/>
-
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x20_dp.addr1">
-          </direct>
-          <direct name="address2" input="memory.addr2[9:0]" output="mem_1024x20_dp.addr2">
-          </direct>
-          <direct name="data1" input="memory.data[19:0]" output="mem_1024x20_dp.data1">
-          </direct>
-          <direct name="data2" input="memory.data[39:20]" output="mem_1024x20_dp.data2">
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_1024x20_dp.we1">
-          </direct>
-          <direct name="writeen2" input="memory.we2" output="mem_1024x20_dp.we2">
-          </direct>
-          <direct name="dataout1" input="mem_1024x20_dp.out1" output="memory.out[19:0]">
-          </direct>
-          <direct name="dataout2" input="mem_1024x20_dp.out2" output="memory.out[39:20]">
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_1024x20_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-
-      <mode name="mem_2048x10_dp">
-        <pb_type name="mem_2048x10_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="addr1" num_pins="11" port_class="address1"/>
-          <input name="addr2" num_pins="11" port_class="address2"/>
-          <input name="data1" num_pins="10" port_class="data_in1"/>
-          <input name="data2" num_pins="10" port_class="data_in2"/>
-          <input name="we1" num_pins="1" port_class="write_en1"/>
-          <input name="we2" num_pins="1" port_class="write_en2"/>
-          <output name="out1" num_pins="10" port_class="data_out1"/>
-          <output name="out2" num_pins="10" port_class="data_out2"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.addr1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.data1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.we1" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.addr2" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.data2" clock="clk"/>
-          <T_setup value="51.12e-12" port="mem_2048x10_dp.we2" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_2048x10_dp.out1" clock="clk"/>
-          <T_setup value="18.91e-12" port="mem_2048x10_dp.out2" clock="clk"/>
-
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.addr1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.data1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.we1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.addr2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.data2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.we2" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.out1" clock="clk"/>
-          <T_clock_to_Q max="60.32e-12" port="mem_2048x10_dp.out2" clock="clk"/>
-
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.addr1" out_port="mem_2048x10_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.data1" out_port="mem_2048x10_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.we1" out_port="mem_2048x10_dp.out1"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.addr2" out_port="mem_2048x10_dp.out2"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.data2" out_port="mem_2048x10_dp.out2"/>
-          <delay_constant max="0.852e-9" in_port="mem_2048x10_dp.we2" out_port="mem_2048x10_dp.out2"/>
-
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x10_dp.addr1">
-          </direct>
-          <direct name="address2" input="memory.addr2[10:0]" output="mem_2048x10_dp.addr2">
-          </direct>
-          <direct name="data1" input="memory.data[9:0]" output="mem_2048x10_dp.data1">
-          </direct>
-          <direct name="data2" input="memory.data[19:10]" output="mem_2048x10_dp.data2">
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_2048x10_dp.we1">
-          </direct>
-          <direct name="writeen2" input="memory.we2" output="mem_2048x10_dp.we2">
-          </direct>
-          <direct name="dataout1" input="mem_2048x10_dp.out1" output="memory.out[9:0]">
-          </direct>
-          <direct name="dataout2" input="mem_2048x10_dp.out2" output="memory.out[19:10]">
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_2048x10_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-    </pb_type>
-    <!-- Define fracturable memory end -->
-  </complexblocklist>
-
-  <switchblocklist>
-    <!-- Stratix IV uses a uni-directional routing architecture with a Driver Input Mux (DIM) size of 12 (i.e.
-           each wire can be driven by one of 12 block/outputs or wires) for the L4s.
-           
-           In the Stratix IV architecture the long wires (L16 here) are accessible only from the short wires, 
-           and are not connected to the block pins (i.e. connection blocks). Furthermore, they only connect 
-           to switch blocks every 4 LABs (to avoid expensive deep via stacks).
-           We approximate the L16 DIM size as 40:1 (in reality it is a pair of 20:1 (?) muxes with a 2:1 swap mux
-           in front, which has nearly the same connectivity as a full 40:1).
-
-           L4 wires
-           ================
-           At a channel width of 300 there are 260 L4/L4prime wires. At an effective Fc_out of 0.075 
-           and 40 LAB outputs this yeilds:
-
-                40 * 2 = 80 outputs per channel  [2 LABs per-channel]
-
-                80 * 0.075 = 6 outputs drive each L4 wire [output connection block]
-
-           This leaves:
-
-                12 - 6 = 6 inputs to the DIMs from other routing wires [switch block]
-
-           Since L4s connect at every switch block, there are:
-
-                260 L16 wires per channel + direction which can drive wires at a particular switchblock
-                (via switchpoints 0, 1, 2, 3)
-
-           And for each direction (260 wires) only:
-
-               260 / 4 = 65 wires starting/ending per channel + direction at each switch block
-               (i.e. from each direction, north/south/east/west, there are 32 L4s starting, and 32 L4s ending; + 1 wire for the 65th)
-
-           Which we allocate as follows:
-
-                L4
-                =====
-                straight-through connection: 2 (from L4 or L16)
-                clock-wise turn            : 2 (from L4 or L16)
-                counter-clock-wise turn    : 2 (from L4 or L16)
-
-           L16 wires
-           =========
-           At a channel width of 300 there are 40 L16 wires (20 in each direction), which do not connect to the input/output connection blocks.
-           This leaves 40 inputs to the DIM to select from routing wires (long wires use larger DIMs to improve reachability,
-           the area cost is relatively small since they are so rare).
-
-           Since L16s only connect at every 4th switch block there are:
-
-                40 / 4 = 10 L16 wires per channel (5 in each direction) which can drive wires at a particular switchblock
-                (via switchpoints 0, 4, 8, 12)
-
-           And for each direction (20 wires) only:
-
-               40 / 16 = 2.25 => 2 wires starting/ending per channel + direction at each switch block
-               (i.e. from each direction, north/south/east/west, there is one L16 starting, and one L16 ending)
-           
-           We assign the 40 DIM inputs as follows:
-
-                L16
-                =====
-                straight-through connection:  3 (from L16)
-                straight-through connection: 11 (from L4)
-                clock-wise turn            :  3 (from L16)
-                clock-wise turn            : 10 (from L4)
-                counter clock-wise turn    :  3 (from L16)
-                counter clock-wise turn    : 10 (from L4)
-
-           Switch pattern
-           ==============
-           This switch block is based on the Wilton switch block (see Page 103 of Steve Wilton's PhD Thesis 
-           "Architecture and Algorithms for Field-Programmable Gate Arrays with Embedded Memory", 1997):
-
-                left-to-top: W - t
-                top-to-right: t + 1
-                right-to-bottom: 2*W - 2 - t
-                bottom-to-left: t + 1
-                left-to-right: t
-                top-to-bottom: t
-
-           Since Wilton assumed bidirection routing (while we use unidirectional routing),
-           we mirror the clock-wise turns to match the conter-clock-wise specification.
-           -->
-    <switchblock name="wilton_turn_clockwise_core" type="unidir">
-      <switchblock_location type="CORE"/>
-      <switchfuncs>
-        <!-- Clock-wise turns -->
-        <func type="tl" formula="W-t"/>
-        <!-- top to left -->
-        <func type="rt" formula="t+1"/>
-        <!-- right to top -->
-        <func type="br" formula="2*W-2-t"/>
-        <!-- bottom to right -->
-        <func type="lb" formula="t+1"/>
-        <!-- left to bottom -->
-      </switchfuncs>
-      <!-- L16 drivers -->
-      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
-      <wireconn num_conns="10*to" from_type="L4" from_switchpoint="0" to_type="L16" to_switchpoint="0"/>
-      <!-- L4 drivers 
-
-               Driving from L16 (few) to L4 (many) preferr driving from end-point of L16, although since there are many they will
-               all be multiply connected.
-               
-               Driving from L4 (many) to L4 (many) shuffle the switchpoints so the L4's are driven from a variety of switchpoints.
-               Since the actual number L4s starting/ending are equal, using 'fixed' from_order would mean only switchpoint 0 -> 0
-               connections. A 'shuffled' order will mix-up the from switchpoints for more diversity.
-               -->
-      <wireconn num_conns="2*to" from_order="shuffled">
-        <from type="L16" switchpoint="0,12,8,4"/>
-        <from type="L4" switchpoint="0,1,2,3"/>
-        <to type="L4" switchpoint="0"/>
-      </wireconn>
-    </switchblock>
-    <switchblock name="wilton_turn_counter_clockwise_core" type="unidir">
-      <switchblock_location type="CORE"/>
-      <switchfuncs>
-        <!-- Counter-clock-wise turns -->
-        <func type="lt" formula="W-t"/>
-        <!-- left to top -->
-        <func type="tr" formula="t+1"/>
-        <!-- top to right -->
-        <func type="rb" formula="2*W-2-t"/>
-        <!-- right to bottom -->
-        <func type="bl" formula="t+1"/>
-        <!-- bottom to left -->
-      </switchfuncs>
-      <!-- L16 drivers -->
-      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
-      <wireconn num_conns="10*to" from_type="L4" from_switchpoint="0" to_type="L16" to_switchpoint="0"/>
-      <!-- L4 drivers 
-
-               Driving from L16 (few) to L4 (many) preferr driving from end-point of L16, although since there are many they will
-               all be multiply connected.
-               
-               Driving from L4 (many) to L4 (many) shuffle the switchpoints so the L4's are driven from a variety of switchpoints.
-               Since the actual number L4s starting/ending are equal, using 'fixed' from_order would mean only switchpoint 0 -> 0
-               connections. A 'shuffled' order will mix-up the from switchpoints for more diversity.
-
-               Note that a different from_switchpoints ordering is used to ensure a different shuffling occurs compared to 
-               wilton_turn_clockwise_core.
-               -->
-      <wireconn num_conns="2*to" from_order="shuffled">
-        <from type="L16" switchpoint="0,12,8,4"/>
-        <from type="L4" switchpoint="0,1,2,3"/>
-        <to type="L4" switchpoint="0"/>
-      </wireconn>
-    </switchblock>
-    <switchblock name="wilton_straight" type="unidir">
-      <switchblock_location type="EVERYWHERE"/>
-      <switchfuncs>
-        <!-- Straight -->
-        <func type="lr" formula="t"/>
-        <!-- left to right -->
-        <func type="tb" formula="t"/>
-        <!-- top to bottom -->
-        <func type="rl" formula="t"/>
-        <!-- right to left -->
-        <func type="bt" formula="t"/>
-        <!-- bottom to top -->
-      </switchfuncs>
-      <!-- L16 Drivers 
-                Note that we order the switchpoints in order of preference, since VPR currently
-                iterates through the source sets in order, such that we connect first to wires
-                ending at the switchblock (switchpoint 0), and then fallback to switchpoints
-                in decreasing distance from the drive point (if we have more to's than from's
-                it then wraps around).
-
-                Note also that we multiply the number of expected connections by 'to', since while usually
-                there is only one 'to' wire, ocasionally there may be more, and we want to ensure they all
-                get the same number of connections.
-
-                For L16->L16:
-                  We allow any valid switchpoint to be used as the 'from' point.
-                  Allow 'low' switchpoints like '4' may seem counter-intuitive (i.e. why not use a cheaper L4)
-                  this makes it easier to bypass once on the L16 network (e.g. to get around congestion).
-           -->
-      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
-      <wireconn num_conns="11*to" from_type="L4" from_switchpoint="0,3,2,1" to_type="L16" to_switchpoint="0"/>
-      <!-- L4 Drivers -->
-      <wireconn num_conns="2*to" from_order="shuffled">
-        <from type="L16" switchpoint="0,12,8,4"/>
-        <from type="L4" switchpoint="0"/>
-        <to type="L4" switchpoint="0"/>
-      </wireconn>
-      <!--<wireconn num_conns="1*to" from_type="L4" from_switchpoint="0" to_type="L4" to_switchpoint="0"/>-->
-      <!--<wireconn num_conns="1*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L4" to_switchpoint="0"/>-->
-    </switchblock>
-    <switchblock name="wilton_straight_corner" type="unidir">
-      <!-- Same as wilton straight, but turning around a corner -->
-      <switchblock_location type="CORNER"/>
-      <switchfuncs>
-        <!-- Counter-clock-wise turns -->
-        <func type="lt" formula="t"/>
-        <!-- left to top -->
-        <func type="tr" formula="t"/>
-        <!-- top to right -->
-        <func type="rb" formula="t"/>
-        <!-- right to bottom -->
-        <func type="bl" formula="t"/>
-        <!-- bottom to left -->
-        <!-- Clock-wise turns -->
-        <func type="tl" formula="t"/>
-        <!-- top to left -->
-        <func type="rt" formula="t"/>
-        <!-- right to top -->
-        <func type="br" formula="t"/>
-        <!-- bottom to right -->
-        <func type="lb" formula="t"/>
-        <!-- left to bottom -->
-      </switchfuncs>
-      <!-- L16 Drivers -->
-      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
-      <wireconn num_conns="11*to" from_type="L4" from_switchpoint="0,3,2,1" to_type="L16" to_switchpoint="0"/>
-      <!-- L4 Drivers -->
-      <wireconn num_conns="2*to" from_order="shuffled">
-        <from type="L16" switchpoint="0,12,8,4"/>
-        <from type="L4" switchpoint="0"/>
-        <to type="L4" switchpoint="0"/>
-      </wireconn>
-      <!--<wireconn num_conns="1*to" from_type="L4" from_switchpoint="0" to_type="L4" to_switchpoint="0"/>-->
-      <!--<wireconn num_conns="1*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L4" to_switchpoint="0"/>-->
-    </switchblock>
-    <switchblock name="wilton_turn_fringe" type="unidir">
-      <!-- Non-corner perimeter SBs -->
-      <switchblock_location type="FRINGE"/>
-      <switchfuncs>
-        <!-- Counter-clock-wise turns -->
-        <func type="lt" formula="W-t"/>
-        <!-- left to top -->
-        <func type="tr" formula="t+1"/>
-        <!-- top to right -->
-        <func type="rb" formula="2*W-2-t"/>
-        <!-- right to bottom -->
-        <func type="bl" formula="t+1"/>
-        <!-- bottom to left -->
-        <!-- Clock-wise turns -->
-        <func type="tl" formula="W-t"/>
-        <!-- top to left -->
-        <func type="rt" formula="t+1"/>
-        <!-- right to top -->
-        <func type="br" formula="2*W-2-t"/>
-        <!-- bottom to right -->
-        <func type="lb" formula="t+1"/>
-        <!-- left to bottom -->
-      </switchfuncs>
-      <!-- We use 'max' style connections here to ensure there are no dangling wires, otherwise like core turns -->
-      <!-- L16 drivers -->
-      <wireconn num_conns="3*max(from,to)" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
-      <wireconn num_conns="21*max(from,to)" from_type="L4" from_switchpoint="0" to_type="L16" to_switchpoint="0"/>
-      <!-- L4 drivers -->
-      <wireconn num_conns="1*max(from,to)" from_type="L16" from_switchpoint="0,12,8,4" from_order="fixed" to_type="L4" to_switchpoint="0"/>
-      <wireconn num_conns="1*max(from,to)" from_type="L4" from_switchpoint="0,1,2,3" from_order="shuffled" to_type="L4" to_switchpoint="0"/>
-    </switchblock>
-  </switchblocklist>
-
-  <clocks>
-    <clock buffer_size="auto" C_wire="2.5e-10"/>
-  </clocks>
-</architecture>
-
-
diff --git a/vtr_flow/arch/multi_die/aman_3d_coffe.xml b/vtr_flow/arch/multi_die/koios_3d/3d_full_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml
similarity index 90%
rename from vtr_flow/arch/multi_die/aman_3d_coffe.xml
rename to vtr_flow/arch/multi_die/koios_3d/3d_full_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml
index 1825d967a18..8c2edcee01a 100644
--- a/vtr_flow/arch/multi_die/aman_3d_coffe.xml
+++ b/vtr_flow/arch/multi_die/koios_3d/3d_full_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml
@@ -235,7 +235,7 @@
   <!-- ODIN II specific config ends -->
   <layout>
     <!-- Physical descriptions begin -->
-    <fixed_layout name="coffe_7nm" width="328" height="288">
+    <auto_layout aspect_ratio="1.0">
       <layer die="0">
         <perimeter type="io" priority="101"/>
       
@@ -272,8 +272,236 @@
         <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
         
       </layer>
-    </fixed_layout>
+    </auto_layout>
   </layout>
+  <fixed_layout name="sector_1_1" width="41" height="36">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </fixed_layout>
+    <fixed_layout name="sector_2_1" width="82" height="36">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </fixed_layout>
+    <fixed_layout name="sector_2_2" width="82" height="72">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </fixed_layout>
+    <fixed_layout name="sector_4_2" width="164" height="72">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </fixed_layout>
+    <fixed_layout name="sector_4_4" width="164" height="144">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </fixed_layout>
+    <fixed_layout name="coffe_7nm" width="205" height="180">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </fixed_layout>
   <device>
     <sizing R_minW_nmos="13090" R_minW_pmos="19086.83"/>
     <area grid_logic_tile_area="0"/>
@@ -282,7 +510,7 @@
       <y distr="uniform" peak="1.000000"/>
     </chan_width_distr>
     <switch_block type="custom"/>
-    <connection_block input_switch_name="ipin_cblock" input_inter_die_switch_name="die_connection"/>
+    <connection_block input_switch_name="ipin_cblock" input_inter_die_switch_name="ipin_inter_layer_cblock"/>
   </device>
   <switchlist>
     <switch type="mux" name="L4_driver" R="0.0" Cin="0.0" Cout="0.0" Tdel="9.877e-11" mux_trans_size="2.6482996805637553" buf_size="18.744014602932605"/>
@@ -292,7 +520,7 @@
     <switch type="mux" name="L16_driver" R="0.0" Cin="0.0" Cout="0.0" Tdel="2.016e-10" mux_trans_size="3.1851297470059468" buf_size="39.327334265524485"/>
     <switch type="mux" name="L16_inter_layer_driver" R="0.0" Cin="0.0" Cout="0.0" Tdel="2.746e-10" mux_trans_size="3.1851297470059468" buf_size="39.327334265524485"/>
     <switch type="mux" name="ipin_cblock" R="0.0" Cout="0.0" Cin="0.0" Tdel="5.636e-11" mux_trans_size="2.008" buf_size="9.624436045683868"/>
-    <switch type="mux" name="die_connection" R="0.0" Cout="0.0" Cin="0.0" Tdel="130e-12" mux_trans_size="1.508" buf_size="11.71"/>
+    <switch type="mux" name="ipin_inter_layer_cblock" R="0.0" Cout="0.0" Cin="0.0" Tdel="130e-12" mux_trans_size="1.508" buf_size="11.71"/>
   </switchlist>
   <segmentlist>
     <segment name="L4" freq="280" length="4" type="unidir" Rmetal="0.0" Cmetal="0.0">
diff --git a/vtr_flow/arch/multi_die/aman_3d_limited.xml b/vtr_flow/arch/multi_die/koios_3d/3d_limited_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml
similarity index 90%
rename from vtr_flow/arch/multi_die/aman_3d_limited.xml
rename to vtr_flow/arch/multi_die/koios_3d/3d_limited_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml
index 7d67b2c996c..d30fd7d0b09 100644
--- a/vtr_flow/arch/multi_die/aman_3d_limited.xml
+++ b/vtr_flow/arch/multi_die/koios_3d/3d_limited_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml
@@ -226,7 +226,235 @@
   <!-- ODIN II specific config ends -->
   <layout>
     <!-- Physical descriptions begin -->
-    <fixed_layout name="coffe_7nm" width="328" height="288">
+    <auto_layout aspect_ratio="1.0">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </auto_layout>
+    <fixed_layout name="sector_1_1" width="41" height="36">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </fixed_layout>
+    <fixed_layout name="sector_2_1" width="82" height="36">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </fixed_layout>
+    <fixed_layout name="sector_2_2" width="82" height="72">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </fixed_layout>
+    <fixed_layout name="sector_4_2" width="164" height="72">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </fixed_layout>
+    <fixed_layout name="sector_4_4" width="164" height="144">
+      <layer die="0">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+
+        <!-- PW -->
+        <col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
+        
+        <!-- GND -->
+        <col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
+
+      </layer>
+      <layer die="1">
+        <perimeter type="io" priority="101"/>
+      
+        <corners type="EMPTY" priority="102"/>
+
+        <fill type="clb" priority="10"/>
+
+        <col type="memory" startx="11" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="25" starty="1" repeatx="41" priority="20"/>
+        <col type="memory" startx="37" starty="1" repeatx="41" priority="20"/>
+
+        <col type="dsp_top" startx="18" starty="1" repeatx="41" priority="20"/>
+        <col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
+        
+      </layer>
+    </fixed_layout>
+    <fixed_layout name="sector_5_5" width="205" height="180">
       <layer die="0">
         <perimeter type="io" priority="101"/>
       
diff --git a/vtr_flow/arch/multi_die/3d_k4_N4_90nm.xml b/vtr_flow/arch/multi_die/simple_arch/3d_k4_N4_90nm.xml
similarity index 95%
rename from vtr_flow/arch/multi_die/3d_k4_N4_90nm.xml
rename to vtr_flow/arch/multi_die/simple_arch/3d_k4_N4_90nm.xml
index e4ad7876555..0f525323384 100644
--- a/vtr_flow/arch/multi_die/3d_k4_N4_90nm.xml
+++ b/vtr_flow/arch/multi_die/simple_arch/3d_k4_N4_90nm.xml
@@ -87,19 +87,20 @@
       <y distr="uniform" peak="1.000000"/>
     </chan_width_distr>
     <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock" input_inter_die_switch_name="die_connection"/>
+    <connection_block input_switch_name="ipin_cblock" input_inter_die_switch_name="inter_die_ipin_cblock"/>
   </device>
   <switchlist>
     <switch type="mux" name="0" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="6.244000e-11" mux_trans_size="1.835460" buf_size="10.498600"/>
+    <switch type="mux" name="inter_die_seg_driver" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="6.244000e-11" mux_trans_size="1.835460" buf_size="10.498600"/>
     <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
     <switch type="mux" name="ipin_cblock" R="1055.232544" Cout="0." Cin="0.000000e+00" Tdel="8.045000e-11" mux_trans_size="0.983352" buf_size="auto"/>
     <!--switch type for connecting two dices-->
-    <switch type="mux" name="die_connection" R="2000" Cout="0" Cin="0" Tdel="9.045000e-11" mux_trans_size="2.083352" buf_size="auto"/>
+    <switch type="mux" name="inter_die_ipin_cblock" R="1055.232544" Cout="0." Cin="0.000000e+00" Tdel="8.045000e-11" mux_trans_size="0.983352" buf_size="auto"/>
   </switchlist>
   <segmentlist>
     <segment freq="1.000000" length="1" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
       <mux name="0"/>
-      <mux_inter_die name="die_connection"/>
+      <mux_inter_die name="inter_die_seg_driver"/>
       <sb type="pattern">1 1</sb>
       <cb type="pattern">1</cb>
     </segment>
diff --git a/vtr_flow/arch/multi_die/3d_stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml b/vtr_flow/arch/multi_die/stratixiv_3d/3d_10x10_noc_base_stratixiv_up.xml
similarity index 99%
rename from vtr_flow/arch/multi_die/3d_stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml
rename to vtr_flow/arch/multi_die/stratixiv_3d/3d_10x10_noc_base_stratixiv_up.xml
index 041ac93af1a..5c93bd021af 100644
--- a/vtr_flow/arch/multi_die/3d_stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml
+++ b/vtr_flow/arch/multi_die/stratixiv_3d/3d_10x10_noc_base_stratixiv_up.xml
@@ -4828,6 +4828,8 @@
 			to reduce the pin spread of the ports connected to the FPGA fabric. So we will seperate
 			the master and slave interfaces and spread the master ports on the bottom half of the left side of the
 			tile. The slave ports will be spread on the left half of the bottom side of the tile.-->
+		<!-- In this architecture, NoCs are supposed to be connected to the upper layer. Thus, we add a layer offset
+		     to all pins of NoC -->
         <pinlocations pattern="custom">
           <loc side="left" xoffset="0" yoffset="0" layer_offset="1"> noc_router_adapter.master_tready noc_router_adapter.master_tvalid noc_router_adapter.master_tdata[31:0] noc_router_adapter.clk noc_router_adapter.reset</loc>
           <loc side="left" xoffset="0" yoffset="1" layer_offset="1"> noc_router_adapter.master_tstrb[3:0] noc_router_adapter.master_tkeep[3:0] noc_router_adapter.master_tid[7:0] noc_router_adapter.master_tdest[7:0] noc_router_adapter.master_tuser[7:0] noc_router_adapter.master_tlast</loc>
@@ -4838,75 +4840,6 @@
     </tile>
   </tiles>
   <layout>
-    <auto_layout aspect_ratio="1.35">
-      <!-- Stratix IV IO blocks connect to both horizontal and vertical
-             routing channels. We approximate this by placing them one unit
-             'in' from the true perimeter (which is left empty). This means
-             that they are fully surrounded by routing channels, allowing them
-             to connect to both horizontal and vertical channels. This is a
-             minor approximation since on real Stratix IV devices there is no 
-             perimeter-side vertical routing channel -->
-      <perimeter type="EMPTY" priority="5000"/>
-      <col type="io" startx="1" priority="1001"/>
-      <!-- Left side -->
-      <col type="io" startx="W-2" priority="1001"/>
-      <!-- Right side -->
-      <row type="io" starty="1" priority="1000"/>
-      <!-- Bottom side -->
-      <row type="io" starty="H-2" priority="1000"/>
-      <!-- Top side -->
-      <!-- Stratix IV devices support up to 16 Global clocks and 12 PLLs located 
-             around the device perimeter as indicated in Figure 5-1 of Chapter 5 
-             of the Stratix IV handbook.
-
-             Note the use of different priorities to avoid ambiguity on small devices -->
-      <single type="PLL" x="1" y="H-2" priority="1997"/>
-      <!-- L1 -->
-      <single type="PLL" x="1" y="H/2" priority="2000"/>
-      <!-- L2 -->
-      <single type="PLL" x="1" y="H/2 - 1" priority="1999"/>
-      <!-- L3 -->
-      <single type="PLL" x="1" y="1" priority="1998"/>
-      <!-- L4 -->
-      <single type="PLL" x="W - 2" y="H-2" priority="1997"/>
-      <!-- R1 -->
-      <single type="PLL" x="W - 2" y="H/2" priority="2000"/>
-      <!-- R2 -->
-      <single type="PLL" x="W - 2" y="H/2 - 1" priority="1999"/>
-      <!-- R3 -->
-      <single type="PLL" x="W - 2" y="1" priority="1998"/>
-      <!-- R4 -->
-      <single type="PLL" x="W/2" y="H-2" priority="1996"/>
-      <!-- T1 -->
-      <single type="PLL" x="W/2 + 1" y="H-2" priority="1995"/>
-      <!-- T2 -->
-      <single type="PLL" x="W/2 - 1" y="H-2" priority="1996"/>
-      <!-- GCLK -->
-      <single type="PLL" x="W/2 + 2" y="H-2" priority="1995"/>
-      <!-- GCLK -->
-      <single type="PLL" x="W/2" y="1" priority="1994"/>
-      <!-- B1 -->
-      <single type="PLL" x="W/2 + 1" y="1" priority="1993"/>
-      <!-- B2 -->
-      <single type="PLL" x="W/2 - 1" y="1" priority="1994"/>
-      <!-- GCLK -->
-      <single type="PLL" x="W/2 + 2" y="1" priority="1983"/>
-      <!-- GCLK -->
-      <!--Fill with 'LAB'-->
-      <fill type="LAB" priority="10"/>
-      <!--Column of 'DSP' with 'EMPTY' blocks wherever a 'DSP' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="DSP" startx="6" starty="2" repeatx="40" priority="150"/>
-      <col type="EMPTY" startx="6" repeatx="40" starty="1" priority="149"/>
-      <!--Column of 'M9K' with 'EMPTY' blocks wherever a 'M9K' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="M9K" startx="5" starty="2" repeatx="26" priority="50"/>
-      <col type="EMPTY" startx="5" repeatx="26" starty="1" priority="49"/>
-      <!--Column of 'M144K' with 'EMPTY' blocks wherever a 'M144K' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="M144K" startx="33" starty="2" repeatx="43" priority="100"/>
-      <col type="EMPTY" startx="33" repeatx="43" starty="1" priority="99"/>
-
-      <!-- Instantiate a single NoC router within the device (top left corner) -->
-      <region type="noc_router_adapter" startx="4" starty="H-4" incrx="W/20" incry="W/20" priority="2000"/>
-    </auto_layout>
     <fixed_layout name="EP4SE820" width="220" height="162">
       <layer die="1">
         <!-- Stratix IV IO blocks connect to both horizontal and vertical
@@ -4981,20 +4914,6 @@
         <region type="noc_router_adapter" startx="4" starty="4" incrx="W/9 - 1" incry="H/9 - 1" priority="2000"/>
       </layer>
     </fixed_layout>
-    <!--
-        Stratix IV has only 4 unique device dies. 
-        Some devices are 'virtual': based off another die, with utilization limits controlled by Quartus
-
-        Equivalent Devices:
-           EP4SGX110: EP4SGX70
-           EP4SGX230: EP4SGX180
-           EP4SGX530: EP4SGX360 EP4SGX290
-           EP4SGX830:
-       -->
-    <!--<fixed_layout name="EP4SGX110" width="82" height="66"/>-->
-    <!--<fixed_layout name="EP4SGX230" width="120" height="97"/>-->
-    <!--<fixed_layout name="EP4SGX530" width="186" height="129"/>-->
-    <!--<fixed_layout name="EP4SE820" width="220" height="162"/>-->
   </layout>
   <device>
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
@@ -5009,150 +4928,35 @@
       <y distr="uniform" peak="1.000000"/>
     </chan_width_distr>
     <switch_block type="custom"/>
-    <connection_block input_switch_name="ipin_cblock"/>
+    <connection_block input_switch_name="ipin_cblock" input_inter_die_switch_name="ipin_inter_layer_cblock"/>
   </device>
   <switchlist>
-    <!-- KEM: Oct 15, 2013
-         We define two types of drivers, one for each of the segment types (see comment in <segmentlist> section)
-
-         VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-	       book area formula. This means the mux transistors are about 5x minimum drive strength.
-	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-	       (diff of second stage).
-
-         KEM: Based on the above and scaling the PTM model from 45nm to 40nm yields the capacitance values listed for the
-              'seg4_driver'.  The values for 'seg16_driver' are simply 3x those of the 'seg4_driver', since it has 3x the
-              drive strength.  This is very close to the actual values (within 5%) found by performing the look-up procedure
-              described above.
-
-              seg4_driver first stage (Both 3x min):
-                Cg_Nmos: 3.9967e-16 F
-                Cg_Pmos: 2.7652e-16 F
-
-                Cin_45 = Cg_Nmos + Cg_Pmos = 0.676e-15 F
-                Cin_40 = (40/45)(Cin_45) = 0.601e-15 F
-
-              seg4_driver second stage (Nmos 16.2x min, Pmos 29.2x min):
-                Cd_Nmos: 1.4459e-15
-                Cd_Pmos: 3.9751e-15
+    <!-- AM:
+       The delay of switches connecting routing resources on the same die is derived from the capture of the SIV architecture.
 
-                Cout_45 = Cd_Nmos + Cd_Pmos = 5.42e-15 F
-                Cout_40 = (40 nm/45 nm)(Cout_45) = 4.82e-15 F
-
-              The R values and Tdel (intrinsic switch delay) were choosen to correlate the overall wire delay with Quartus II,
-              while keeping the switch delay a reasonable (see comment in <segmentlist>) portion of the overall delay.
+       For inter-layer switches, the delay is obtained by multiplying the ratio between L4 and inter-layer delay from
+       "Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices" by
+       the L4 delay of the SIV capture. This value is considered the delay of the inter-layer connection.
+       Subsequently, this delay is added to the delay of L4 and L16 drivers to determine the inter-layer switch delay.
        -->
     <switch type="mux" name="seg4_driver" R="450" Cin="0.60e-15" Cout="4.82e-15" Tdel="59e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!-- KEM: Since the L16 wires are 4x as long as the L4s, it is not unreasonable to have the L16 drivers be at least 3x as
-         powerful. -->
+    <switch type="mux" name="seg4_inter_layer_driver" R="0.0" Cin="0.0" Cout="0.0" Tdel="138.82e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
     <switch type="mux" name="seg16_driver" R="150" Cin="1.80e-15" Cout="14.5e-15" Tdel="87e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="seg16_inter_layer_driver" R="0.0" Cin="0.0" Cout="0.0" Tdel="166.82e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
     <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="0e0" mux_trans_size="1.222260" buf_size="auto"/>
+    <switch type="mux" name="ipin_inter_layer_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="0e0" mux_trans_size="1.222260" buf_size="auto"/>
   </switchlist>
   <segmentlist>
-    <!-- KEM: Oct 15, 2013
-
-           Wire distribution:
-             In stratix IV there are four types of wires: R4, R20, C4, C12
-             R wires are row wires running horizontally accross the chip
-             C wires are column wires running vertically accross the chip
-
-             The wire counts for Stratix IV channels are:
-                R4 : 272
-                C4 : 160
-                R20:  40
-                C12:  24
-
-             This corresponds to roughly 13% long wires in each horizontal or vertical channel.
-
-             Since VPR can not model non-unifrom channels (both in terms of wire types and channel
-             widths), we model the routing network as follows:
-                - A channel width of 300 wires (provided on the command line)
-                - 13% of wires are long wires of length 16 (average of 20 and 12)
-                - The remainder (87%) of wires are length 4
-
-
-           Metal data:
-             For intermediate wires (from ITRS 2007 for the 2008 year [M1 1/2 pitch of 59nm]):
-                 Resistivity (uohm*cm): 3.63
-                 Capacitance (pF/cm)  : 2.0
-
-             Assuming a (square) Stratix IV LAB is 90um per side.
-
-             Then, for L4 wires assuming:
-              - Intermediate wire half-pitch of 90nm
-              - Wire height is 2x wire width
-
-                 Resistance_L4/meter = (3.63 uOhm*cm)(10^-2 m/cm)(10^-6 ohm/uOhm)/[2*(90e-9 m)^2]
-                 Resistance_L4/meter = 2.25e6 ohm/m
-
-                 Resistance_L4/LAB = (2.25e6 ohm/m)(90e-6 m/LAB) = 201.7 ohm/LAB
-
-                 Capacitance_L4/LAB = (2.0 pF/cm)(10^2 cm/m)(10^-12 F/pF)(90e-6 m/LAB) = 18.0e-15 F/LAB
-
-             L16 wires in contrast, are implemented in the top layers of the metal stack
-             which are significantly less resistive (assuming ~2x vs L4) and are also not implemented
-             at minumum width (assuming ~2x further decrease in resistance).  Therefore, the
-             L16 wires are ~4x less resistive than L4 wires.
-
-                 Resistance_L16/LAB = Resistance_L4/LAB / 4 = 201.7 / 4 = 50.42 ohm/LAB
-
-             Further, according to ITRS global wires are ~15% more capactivie than intermediate
-             wires.
-
-                 Capacitance_L16/LAB = Capacitance_L4/LAB * 1.15 = 18.0e-15 * 1.15 = 20.7e-15 F/LAB
-
-
-           Wire delays:
-
-             Measuring maximum and minimum delays of actual wires using Quartus II resulted in the following average
-             delays:
-                R4:    max: 116 ps  min: 105 ps
-                C4:    max: 245 ps  min: 185 ps
-                R20:   max: 305 ps  min: 269 ps
-                C12:   max: 273 ps  min: 231 ps
-
-             Averaging accross wires of the same type we attempted to make the wires (including
-             drivers) correlate to the following values:
-                L4:    max: 181 ps  min: 145 ps
-                L16:   min: 289 ps  min: 250 ps
-
-             Currently VPR only models the maximum capacitance of the wire. When VPR models the minimum capacitances, 
-             the minimum wire delays should correspond to VPR's result.
-
-             With the maximum capacitance used, current parameters we achieve the following:
-                L4:    131 ps
-                L16:   293 ps
-             which are close to the target maximum values.
-
-             Delay breakdown for each wire type is as follows:
-                L4:
-                  Switch R & Downstream C: 37.8 ps
-                  Intrinsic Switch Delay : 59.0 ps
-                  Wire R & Downstream C  : 33.8 ps
-
-                L16:
-                  Switch R & Downstream C:  55.9 ps
-                  Intrinsic Switch Delay :  87.0 ps
-                  Wire R & Downstream C  : 150.0 ps
-
-                For L4 the intrinsic switch delay is ~45% of the total wire delay.
-                For L16 the intrinsic switch delay is ~30% of the total wire delay.
-                Both of these values are reasonable.
-          -->
     <segment name="L4" freq="260" length="4" type="unidir" Rmetal="201.7" Cmetal="18.0e-15">
       <mux name="seg4_driver"/>
+      <mux_inter_die name="seg4_inter_layer_driver"/>
       <!-- L4 connect to connection block L4 and L4prime -->
       <sb type="pattern">1 1 1 1 1</sb>
       <cb type="pattern">1 1 1 1</cb>
     </segment>
     <segment name="L16" freq="40" length="16" type="unidir" Rmetal="50.42" Cmetal="20.7e-15">
       <mux name="seg16_driver"/>
+      <mux_inter_die name="seg16_inter_layer_driver"/>
       <!-- L16 connect to L16 and L4 -->
       <!-- Vias from the top of the metal stack (global layers, where the long wires are 
            implemented) down to the middle/bottom of the metal stack (semi-global layers, 
diff --git a/vtr_flow/arch/multi_die/stratixiv_arch.timing_OPINs.xml b/vtr_flow/arch/multi_die/stratixiv_3d/3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
similarity index 100%
rename from vtr_flow/arch/multi_die/stratixiv_arch.timing_OPINs.xml
rename to vtr_flow/arch/multi_die/stratixiv_3d/3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
diff --git a/vtr_flow/arch/multi_die/stratixiv_arch.timing.xml b/vtr_flow/arch/multi_die/stratixiv_3d/3d_full_inter_die_stratixiv_arch.timing.xml
similarity index 100%
rename from vtr_flow/arch/multi_die/stratixiv_arch.timing.xml
rename to vtr_flow/arch/multi_die/stratixiv_3d/3d_full_inter_die_stratixiv_arch.timing.xml
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_clique_topology/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_clique_topology/config/config.txt
index 2a773936a9a..1755640e53e 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_clique_topology/config/config.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_clique_topology/config/config.txt
@@ -6,7 +6,7 @@
 circuits_dir=benchmarks/noc/Synthetic_Designs/complex_64_noc_clique/
 
 # Path to directory of architectures to use
-archs_dir=arch/multi_die/
+archs_dir=arch/multi_die/stratixiv_3d/
 
 # Path to directory of NoC Traffic Patterns to use
 noc_traffics_dir=benchmarks/noc/Synthetic_Designs/complex_64_noc_clique
@@ -15,7 +15,7 @@ noc_traffics_dir=benchmarks/noc/Synthetic_Designs/complex_64_noc_clique
 circuit_list_add=complex_64_noc_clique.blif
 
 # Add architectures to list to sweep
-arch_list_add=3d_stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml
+arch_list_add=3d_10x10_noc_base_stratixiv_up.xml
 
 # Add NoC Traffic Patterns to list to sweep
 noc_traffic_list_add=complex_64_noc_clique.flows
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_nearest_neighbor_topology/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_nearest_neighbor_topology/config/config.txt
index e08d2586bc5..84c43939404 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_nearest_neighbor_topology/config/config.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_nearest_neighbor_topology/config/config.txt
@@ -6,7 +6,7 @@
 circuits_dir=benchmarks/noc/Synthetic_Designs/complex_64_noc_nearest_neighbor/
 
 # Path to directory of architectures to use
-archs_dir=arch/multi_die/
+archs_dir=arch/multi_die/stratixiv_3d/
 
 # Path to directory of NoC Traffic Patterns to use
 noc_traffics_dir=benchmarks/noc/Synthetic_Designs/complex_64_noc_nearest_neighbor
@@ -15,7 +15,7 @@ noc_traffics_dir=benchmarks/noc/Synthetic_Designs/complex_64_noc_nearest_neighbo
 circuit_list_add=complex_64_noc_nearest_neighbor.blif
 
 # Add architectures to list to sweep
-arch_list_add=3d_stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml
+arch_list_add=3d_10x10_noc_base_stratixiv_up.xml
 
 # Add NoC Traffic Patterns to list to sweep
 noc_traffic_list_add=complex_64_noc_nearest_neighbor.flows
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_star_topology/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_star_topology/config/config.txt
index 83f46463453..a11fbebb22f 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_star_topology/config/config.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_3d_noc_star_topology/config/config.txt
@@ -6,7 +6,7 @@
 circuits_dir=benchmarks/noc/Synthetic_Designs/complex_64_noc_star/
 
 # Path to directory of architectures to use
-archs_dir=arch/multi_die/
+archs_dir=arch/multi_die/stratixiv_3d/
 
 # Path to directory of NoC Traffic Patterns to use
 noc_traffics_dir=benchmarks/noc/Synthetic_Designs/complex_64_noc_star/
@@ -16,7 +16,7 @@ circuit_list_add=complex_64_noc_star.blif
 
 
 # Add architectures to list to sweep
-arch_list_add=3d_stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml
+arch_list_add=3d_10x10_noc_base_stratixiv_up.xml
 
 # Add NoC Traffic Patterns to list to sweep
 noc_traffic_list_add=complex_64_noc_star_no_constraints.flows
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other/config/config.txt
new file mode 100644
index 00000000000..9f27ebdeae0
--- /dev/null
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other/config/config.txt
@@ -0,0 +1,52 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/titan_blif/other_benchmarks/stratixiv
+
+# Path to directory of SDC files
+sdc_dir=benchmarks/titan_blif/other_benchmarks/stratixiv
+
+# Path to directory of architectures to use
+archs_dir=arch/multi_die/stratixiv_3d
+
+# Add circuits to list to sweep
+circuit_list_add=carpat_stratixiv_arch_timing.blif
+circuit_list_add=CH_DFSIN_stratixiv_arch_timing.blif
+circuit_list_add=CHERI_stratixiv_arch_timing.blif
+circuit_list_add=EKF-SLAM_Jacobians_stratixiv_arch_timing.blif
+circuit_list_add=fir_cascade_stratixiv_arch_timing.blif
+circuit_list_add=jacobi_stratixiv_arch_timing.blif
+circuit_list_add=JPEG_stratixiv_arch_timing.blif
+circuit_list_add=leon2_stratixiv_arch_timing.blif
+circuit_list_add=leon3mp_stratixiv_arch_timing.blif
+circuit_list_add=MCML_stratixiv_arch_timing.blif
+circuit_list_add=MMM_stratixiv_arch_timing.blif
+circuit_list_add=radar20_stratixiv_arch_timing.blif
+circuit_list_add=random_stratixiv_arch_timing.blif
+circuit_list_add=Reed_Solomon_stratixiv_arch_timing.blif
+circuit_list_add=smithwaterman_stratixiv_arch_timing.blif
+circuit_list_add=stap_steering_stratixiv_arch_timing.blif
+circuit_list_add=sudoku_check_stratixiv_arch_timing.blif
+circuit_list_add=SURF_desc_stratixiv_arch_timing.blif
+circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif
+circuit_list_add=uoft_raytracer_stratixiv_arch_timing.blif
+circuit_list_add=wb_conmax_stratixiv_arch_timing.blif
+circuit_list_add=picosoc_stratixiv_arch_timing.blif
+circuit_list_add=murax_stratixiv_arch_timing.blif
+
+# Add architectures to list to sweep
+arch_list_add=3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
+
+# Parse info and how to parse
+parse_file=vpr_titan.txt
+
+# How to parse QoR info
+qor_parse_file=qor_vpr_titan.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements_vpr_titan.txt
+
+script_params=-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map
\ No newline at end of file
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other/config/golden_results.txt
new file mode 100644
index 00000000000..cce235a1c31
--- /dev/null
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other/config/golden_results.txt
@@ -0,0 +1,24 @@
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	num_io	num_LAB	num_DSP	num_M9K	num_M144K	num_PLL	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	routed_wirelength	avg_routed_wirelength	routed_wiresegment	avg_routed_wiresegment	total_nets_routed	total_connections_routed	total_heap_pushes	total_heap_pops	total_internal_heap_pushes	total_internal_heap_pops	total_external_heap_pushes	total_external_heap_pops	total_external_SOURCE_pushes	total_external_SOURCE_pops	total_internal_SOURCE_pushes	total_internal_SOURCE_pops	total_external_SINK_pushes	total_external_SINK_pops	total_internal_SINK_pushes	total_internal_SINK_pops	total_external_IPIN_pushes	total_external_IPIN_pops	total_internal_IPIN_pushes	total_internal_IPIN_pops	total_external_OPIN_pushes	total_external_OPIN_pops	total_internal_OPIN_pushes	total_internal_OPIN_pops	total_external_CHANX_pushes	total_external_CHANX_pops	total_internal_CHANX_pushes	total_internal_CHANX_pops	total_external_CHANY_pushes	total_external_CHANY_pops	total_internal_CHANY_pushes	total_internal_CHANY_pops	rt_node_SOURCE_pushes	rt_node_SINK_pushes	rt_node_IPIN_pushes	rt_node_OPIN_pushes	rt_node_CHANX_pushes	rt_node_CHANY_pushes	rt_node_SOURCE_high_fanout_pushes	rt_node_SINK_high_fanout_pushes	rt_node_IPIN_high_fanout_pushes	rt_node_OPIN_high_fanout_pushes	rt_node_CHANX_high_fanout_pushes	rt_node_CHANY_high_fanout_pushes	rt_node_SOURCE_entire_tree_pushes	rt_node_SINK_entire_tree_pushes	rt_node_IPIN_entire_tree_pushes	rt_node_OPIN_entire_tree_pushes	rt_node_CHANX_entire_tree_pushes	rt_node_CHANY_entire_tree_pushes	adding_all_rt	adding_high_fanout_rt	total_number_of_adding_all_rt_from_calling_high_fanout_rt	logic_block_area_total	logic_block_area_used	routing_area_total	routing_area_per_tile	crit_path_route_success_iteration	num_rr_graph_nodes	num_rr_graph_edges	collapsed_nodes	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	create_rr_graph_time	create_intra_cluster_rr_graph_time	adding_internal_edges	route_mem	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	router_lookahead_mem	tile_lookahead_computation_time	router_lookahead_computation_time	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	carpat_stratixiv_arch_timing.blif	common	371.31	vpr	1.60 GiB		274	964	36	59	0	2	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1673732	22	252	53001	29054	7	24705	1335	54	40	4320	DSP	auto	1246.9 MiB	30.04	205488	794919	209813	478019	107087	1592.9 MiB	114.20	0.71	7.21269	-35874.2	-6.21269	2.91858	26.03	0.101074	0.0916498	16.63	13.9747	306538	12.4235	70534	2.85864	75032	153041	297632124	89620403	0	0	297632124	89620403	153017	134655	0	0	8574405	8523099	0	0	9053439	8765182	0	0	4892435	3599970	0	0	142339315	41550022	0	0	132619513	27047475	0	0	153017	0	0	180373	287801	360594	2051	0	0	24786	56705	84729	150966	0	0	155587	231096	275865	1385503	3893	3490	0	0	9.32958e+07	21596.2	43	1265168	16900788	-1	7.5472	3.10831	-39771	-6.5472	0	0	16.73	-1	-1	1619.5 MiB	79.13	28.4934	24.5063	1592.9 MiB	-1	78.43	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	CH_DFSIN_stratixiv_arch_timing.blif	common	504.64	vpr	1.50 GiB		36	1577	10	10	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1573572	3	33	48977	39238	1	26166	1633	40	30	2400	LAB	auto	1281.6 MiB	80.55	243322	914773	260767	614341	39665	1384.8 MiB	142.46	1.46	74.7044	-66694.2	-73.7044	74.7044	26.10	0.158139	0.138412	13.9676	11.3918	337888	12.9152	81618	3.11972	88834	243998	506251682	304668320	0	0	506251682	304668320	236933	169627	0	0	2637571	2564025	0	0	2976870	2731704	0	0	6763699	5248380	0	0	296115389	197874366	0	0	197521220	96080218	0	0	236933	0	0	333280	722304	1002901	5127	0	0	12996	86678	130814	231806	0	0	320284	635626	872087	5276364	23411	2367	0	0	5.14259e+07	21427.5	26	702232	9285402	-1	68.1458	68.1458	-95784.7	-67.1458	0	0	11.28	-1	-1	1497.0 MiB	176.93	21.8082	18.1079	1384.8 MiB	-1	39.62	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	CHERI_stratixiv_arch_timing.blif	common	1370.69	vpr	1.96 GiB		211	2260	3	210	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	2054300	38	173	62892	59064	3	36091	2684	60	44	5280	M9K	auto	1501.1 MiB	162.37	536798	1848539	624787	1187162	36590	1815.3 MiB	240.52	2.02	11.7873	-306153	-10.7873	6.77664	39.00	0.219279	0.170681	24.8477	19.5334	751301	20.8209	174447	4.83447	141770	501912	1789505148	1370091645	0	0	1789505148	1370091645	456426	349615	0	0	2932470	2774377	0	0	3512780	3144353	0	0	13521236	11186556	0	0	1151152674	945420771	0	0	617929562	407215973	0	0	456426	0	0	724208	3858302	4340157	22387	0	0	68708	619875	742727	434039	0	0	655500	3238427	3597430	21479104	132856	87740	0	0	1.14232e+08	21634.8	44	1553068	20719330	-1	12.4096	7.22798	-339561	-11.4096	0	0	20.59	-1	-1	1922.8 MiB	786.17	46.7522	37.7627	1815.3 MiB	-1	86.50	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	EKF-SLAM_Jacobians_stratixiv_arch_timing.blif	common	1140.40	vpr	1.93 GiB		574	2798	16	0	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	2020084	4	570	66175	54803	2	39719	3388	51	38	3876	LAB	auto	1546.1 MiB	118.05	548937	2419713	797278	1536070	86365	1703.8 MiB	318.87	3.20	27.4657	-101563	-26.4657	6.35626	28.16	0.29534	0.258776	29.6069	23.7197	786553	19.8054	179127	4.51042	178287	695440	1444223474	817887205	0	0	1444223474	817887205	681311	512082	0	0	4591091	4388966	0	0	5060708	4615376	0	0	19559665	16490219	0	0	857249333	552965103	0	0	557081366	238915459	0	0	681311	0	0	930519	2283738	2671775	7516	0	0	32972	217568	251930	673795	0	0	897547	2066170	2419845	13372246	44908	31984	0	0	8.35534e+07	21556.6	20	1135740	15117508	-1	28.4894	6.72576	-110856	-27.4894	0	0	16.10	-1	-1	1887.1 MiB	555.34	43.5197	35.6911	1703.8 MiB	-1	69.69	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	fir_cascade_stratixiv_arch_timing.blif	common	1681.11	vpr	4.13 GiB		40	3678	172	1	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	4335840	19	21	171111	96274	1	73794	3891	129	96	24768	DSP	auto	2032.9 MiB	99.65	724101	3583038	1367291	2199498	16249	4234.2 MiB	214.92	2.13	5.07484	-96672.1	-4.07484	3.39367	602.69	0.316439	0.269883	40.3293	34.8951	857529	11.6211	183706	2.48954	151124	184729	399497864	76698589	0	0	399497864	76698589	181476	172566	0	0	9017240	8962578	0	0	9191616	9087226	0	0	6644481	5012829	0	0	175786304	31136717	0	0	198676747	22326673	0	0	181476	0	0	31469	1155545	1175876	2	0	0	2	31038	30852	181474	0	0	31467	1124507	1145024	5397699	5062	81503	0	0	5.40280e+08	21813.6	12	7186500	97666830	-1	5.42808	3.66174	-133424	-4.42808	0	0	114.87	-1	-1	4234.2 MiB	76.93	53.6658	47.1841	4234.2 MiB	-1	522.02	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	jacobi_stratixiv_arch_timing.blif	common	551.26	vpr	1.63 GiB		536	1962	7	4	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1711228	227	309	49176	40422	1	28220	2509	47	35	3290	io	auto	1347.3 MiB	77.42	269714	1843045	628881	1166910	47254	1521.4 MiB	201.78	2.91	189.671	-110534	-188.671	189.671	18.44	0.232397	0.183141	19.0177	15.5734	370327	13.1247	89084	3.15722	87006	280505	412816608	227509658	0	0	412816608	227509658	270535	174300	0	0	949966	865999	0	0	1233293	1056096	0	0	7027993	5565183	0	0	244336472	153742508	0	0	158998349	66105572	0	0	270535	0	0	421476	879500	1209056	3822	0	0	9085	104137	138117	266713	0	0	412391	775363	1070939	6789137	28050	4944	0	0	7.07120e+07	21493.0	20	956596	12777064	-1	181.369	181.369	-124092	-180.369	0	0	12.85	-1	-1	1613.2 MiB	153.40	29.6609	24.4083	1521.4 MiB	-1	57.14	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	JPEG_stratixiv_arch_timing.blif	common	672.71	vpr	1.68 GiB		36	1338	8	149	2	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1759976	3	33	52402	39411	1	28023	1533	57	42	4788	M9K	auto	1304.7 MiB	63.40	283992	743673	196836	521250	25587	1662.8 MiB	127.35	1.21	15.8776	-289230	-14.8776	15.8776	45.33	0.130811	0.102902	14.8079	11.8071	405442	14.4723	94469	3.37209	86125	215069	522666258	330532434	0	0	522666258	330532434	209286	164065	0	0	2441429	2372198	0	0	2659232	2505853	0	0	6197495	4878795	0	0	317607857	223706890	0	0	193550959	96904633	0	0	209286	0	0	251576	743743	868013	3841	0	0	18775	100255	144653	205445	0	0	232801	643488	723360	3486100	18023	21711	0	0	1.03322e+08	21579.3	34	1396452	18717124	-1	17.6699	17.6699	-315475	-16.6699	0	0	26.26	-1	-1	1682.2 MiB	271.13	27.8671	22.947	1662.8 MiB	-1	111.44	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	leon2_stratixiv_arch_timing.blif	common	254.22	vpr	1.24 GiB		251	954	1	17	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1295648	55	196	20131	19956	1	8402	1223	32	24	1536	LAB	auto	1117.8 MiB	38.25	104642	537257	160230	351830	25197	1204.9 MiB	38.09	0.42	7.03068	-72203.9	-6.03068	7.03068	1.52	0.0686554	0.0605221	7.21891	5.54153	154013	18.3371	37774	4.49744	27913	125355	256686890	148376735	0	0	256686890	148376735	121064	85173	0	0	298402	252467	0	0	368968	309955	0	0	3427665	2969647	0	0	150234045	97118247	0	0	102236746	47641246	0	0	121064	0	0	215656	713930	853018	2583	0	0	7754	56939	68460	118481	0	0	207902	656991	784558	4560453	13664	2840	0	0	3.29330e+07	21440.7	18	447460	5953838	-1	7.48295	7.48295	-80442.6	-6.48295	0	0	9.28	-1	-1	1235.5 MiB	117.22	10.9366	8.72919	1204.9 MiB	-1	31.02	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	leon3mp_stratixiv_arch_timing.blif	common	693.10	vpr	1.54 GiB		255	2097	1	28	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1611712	84	171	36458	36247	3	20325	2381	45	33	2970	LAB	auto	1289.5 MiB	74.60	253881	1432661	479932	883665	69064	1452.9 MiB	77.25	0.78	10.9262	-76682.6	-9.92617	3.98839	18.61	0.121365	0.0944227	11.7911	9.38065	365303	17.9855	83616	4.11678	59131	207839	793704971	644252409	0	0	793704971	644252409	180503	126649	0	0	466697	394300	0	0	568964	479579	0	0	5048682	4269058	0	0	514292410	441040291	0	0	273147715	197942532	0	0	180503	0	0	316310	2047275	2693485	6733	0	0	15866	287479	359081	173770	0	0	300444	1759796	2334404	13436824	66056	81990	0	0	6.38316e+07	21492.1	14	866116	11535668	-1	11.9411	4.40613	-85953.5	-10.9411	0	0	11.86	-1	-1	1530.6 MiB	438.90	17.5977	14.3201	1452.9 MiB	-1	46.96	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	MCML_stratixiv_arch_timing.blif	common	1065.86	vpr	2.16 GiB		69	2109	10	295	16	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	2263124	36	33	57796	49182	1	20302	2499	79	59	9322	M144K	auto	1429.1 MiB	65.52	217516	2223080	853123	1328458	41499	2210.1 MiB	141.83	1.46	9.46871	-78923.4	-8.46871	9.46871	124.92	0.213233	0.163369	22.3003	17.6776	367242	18.0934	85262	4.20072	65984	200815	893541359	651334704	0	0	893541359	651334704	177798	147935	0	0	5646895	5573182	0	0	5961429	5734106	0	0	5674860	4452051	0	0	565144523	446352238	0	0	310935854	189075192	0	0	177798	0	0	206844	2992695	3431138	6255	0	0	19563	344335	460425	171543	0	0	187281	2648360	2970713	13087337	59178	196103	0	0	2.01416e+08	21606.5	46	2701980	36494954	-1	9.54819	9.54819	-116148	-8.54819	0	0	37.13	-1	-1	2210.1 MiB	510.80	41.7284	34.2301	2210.1 MiB	-1	152.80	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	MMM_stratixiv_arch_timing.blif	common	413.26	vpr	1.90 GiB		478	1236	1	300	4	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1996368	202	276	35125	30509	3	21529	2019	73	54	7884	M9K	auto	1234.0 MiB	53.43	219620	1379559	442436	857289	79834	1949.6 MiB	72.51	0.61	8.87456	-29608.2	-7.87456	3.15447	55.72	0.110869	0.0864875	12.9258	10.2006	350076	16.2652	79505	3.69396	63543	186209	254745520	38816766	0	0	254745520	38816766	184682	156746	0	0	3589028	3522559	0	0	3814160	3658467	0	0	6105302	4889196	0	0	121198652	14946794	0	0	119853696	11643004	0	0	184682	0	0	217396	563810	585806	53	0	0	93	13406	14009	184629	0	0	217303	550404	571797	2775776	2247	1618	0	0	1.70850e+08	21670.5	25	2296616	31018276	-1	9.20698	3.54191	-40744.8	-8.20698	0	0	30.40	-1	-1	1949.6 MiB	50.73	23.5068	19.1207	1949.6 MiB	-1	124.48	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	radar20_stratixiv_arch_timing.blif	common	230.70	vpr	1.35 GiB		5	331	31	105	0	2	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1418888	3	2	14862	10304	26	7485	474	49	36	3528	DSP	auto	1051.4 MiB	31.81	98871	146387	33195	97269	15923	1385.6 MiB	12.55	0.16	5.51054	-28688.4	-4.51054	3.51882	36.78	0.0484882	0.0402389	5.53161	4.52425	156504	20.9819	34086	4.56978	20970	46253	68192159	13039367	0	0	68192159	13039367	45452	39101	0	0	1517800	1497745	0	0	1570312	1535418	0	0	1180557	1014286	0	0	31680198	5362999	0	0	32197840	3589818	0	0	45452	0	0	41734	204760	185241	59	0	0	97	5735	6813	45393	0	0	41637	199025	178428	727244	1076	862	0	0	7.61282e+07	21578.3	15	1038076	13775176	-1	5.57945	3.7705	-38287.6	-4.57945	0	0	21.06	-1	-1	1385.6 MiB	20.89	8.94	7.48939	1385.6 MiB	-1	86.74	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	random_stratixiv_arch_timing.blif	common	539.98	vpr	1.74 GiB		693	1763	25	16	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1819288	35	658	51416	37539	1	27797	2497	58	43	4988	io	auto	1339.5 MiB	57.85	224609	1882060	595899	1153115	133046	1711.0 MiB	190.88	1.87	35.6957	-55557.5	-34.6957	35.6957	45.86	0.223739	0.198375	24.8027	20.4596	315275	11.9940	75732	2.88108	82277	245502	261905413	39158496	0	0	261905413	39158496	244065	192794	0	0	3691267	3620444	0	0	3927503	3732056	0	0	7345813	5954806	0	0	124386865	15928263	0	0	122309900	9730133	0	0	244065	0	0	249982	238008	342577	561	0	0	993	12314	13590	243504	0	0	248989	225694	328987	2156089	2247	450	0	0	1.07590e+08	21569.7	22	1452444	19489584	-1	36.8872	36.8872	-60247.3	-35.8872	0	0	30.67	-1	-1	1737.4 MiB	62.20	39.0677	32.8189	1711.0 MiB	-1	123.26	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	Reed_Solomon_stratixiv_arch_timing.blif	common	347.49	vpr	1.66 GiB		753	1119	5	32	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1745044	13	740	25173	25306	1	12707	1909	63	47	5922	io	auto	1169.6 MiB	61.14	128373	1138261	382950	706443	48868	1704.1 MiB	40.63	0.33	8.7936	-26752.4	-7.7936	7.56645	41.85	0.0668516	0.0584289	7.81681	6.41588	176310	13.8827	41856	3.29575	32471	123325	194658634	109300529	0	0	194658634	109300529	112921	86554	0	0	400487	363316	0	0	476081	411930	0	0	3280329	2760829	0	0	114108696	72567822	0	0	76280120	33110078	0	0	112921	0	0	115060	319206	373532	3265	0	0	5158	78124	88704	109656	0	0	109902	241082	284828	1993862	18637	2963	0	0	1.28010e+08	21616.1	23	1733724	23219606	-1	9.43055	7.93598	-31255.8	-8.43055	0	0	29.02	-1	-1	1704.1 MiB	64.01	12.4943	10.4311	1704.1 MiB	-1	85.76	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	smithwaterman_stratixiv_arch_timing.blif	common	998.93	vpr	1.70 GiB		117	2147	0	0	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1779296	79	38	66795	54922	1	36234	2264	46	34	3128	LAB	auto	1411.7 MiB	100.04	234134	1369384	375797	948110	45477	1532.1 MiB	219.02	2.11	9.78496	-165712	-8.78496	9.78496	26.94	0.235409	0.20111	24.0599	19.031	311244	8.59054	74985	2.06964	105789	221563	755264447	613402617	0	0	755264447	613402617	215356	171051	0	0	298059	240075	0	0	487450	318648	0	0	6823548	4677501	0	0	489108302	420278664	0	0	258331732	187716678	0	0	215356	0	0	160707	547991	725875	6171	0	0	14705	128804	155741	209185	0	0	146002	419187	570134	3031712	27246	15235	0	0	6.72077e+07	21485.8	37	910800	12142484	-1	10.3059	10.3059	-183722	-9.30588	0	0	18.34	-1	-1	1678.7 MiB	509.40	42.9779	34.7277	1532.1 MiB	-1	89.32	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	stap_steering_stratixiv_arch_timing.blif	common	392.10	vpr	1.65 GiB		213	1559	26	4	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1730720	139	74	57121	41054	1	24028	1802	49	36	3528	DSP	auto	1347.1 MiB	73.05	151499	1119824	341947	711597	66280	1554.7 MiB	117.09	0.93	5.69597	-17182	-4.69597	5.69597	32.20	0.131073	0.0992389	21.1715	17.2507	218207	9.08288	52931	2.20326	52895	96555	131994243	22590038	0	0	131994243	22590038	94757	79193	0	0	3071337	3040212	0	0	3210039	3129396	0	0	3031664	2365622	0	0	58443466	8084321	0	0	64142980	5891294	0	0	94757	0	0	54792	314159	435955	6	0	0	6	15661	18677	94751	0	0	54786	298498	417278	2046865	2710	759	0	0	7.61282e+07	21578.3	18	1038076	13775176	-1	6.13413	6.13413	-26094	-5.13413	0	0	23.96	-1	-1	1633.2 MiB	39.81	30.1378	25.0385	1554.7 MiB	-1	80.71	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	sudoku_check_stratixiv_arch_timing.blif	common	195.12	vpr	1.22 GiB		54	667	0	40	0	1	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1274036	2	52	16673	16662	2	12034	762	32	24	1536	M9K	auto	1092.2 MiB	42.38	150159	251250	60999	172793	17458	1190.6 MiB	28.34	0.41	5.33675	-17321.7	-4.33675	4.69139	1.68	0.0961119	0.070747	6.43063	4.95744	199192	16.5579	48118	3.99983	47355	144569	171282772	40293327	0	0	171282772	40293327	142902	114790	0	0	650453	603462	0	0	758699	664515	0	0	4381098	3697569	0	0	88096204	23963027	0	0	77253416	11249964	0	0	142902	0	0	150214	223298	372399	832	0	0	3578	15805	28752	142070	0	0	146636	207493	343647	1863433	4443	511	0	0	3.29330e+07	21440.7	18	447460	5953838	-1	5.64717	5.10515	-21351.7	-4.64717	0	0	11.07	-1	-1	1233.9 MiB	52.93	11.3309	9.03413	1190.6 MiB	-1	34.43	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	SURF_desc_stratixiv_arch_timing.blif	common	459.66	vpr	1.78 GiB		445	2165	19	51	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1863752	131	314	57881	45152	1	32949	2680	49	36	3528	DSP	auto	1440.5 MiB	70.66	289875	1937912	630016	1216247	91649	1610.3 MiB	196.67	1.80	185.105	-63305.1	-184.105	185.105	22.28	0.181484	0.15043	20.7503	17.3143	403815	12.2833	99304	3.02065	99848	302258	296106269	81083194	0	0	296106269	81083194	299673	201758	0	0	1581215	1491711	0	0	1793625	1605231	0	0	7807387	6110773	0	0	153313811	49234389	0	0	131310558	22439332	0	0	299673	0	0	400791	706623	873985	1403	0	0	4973	49870	52678	298270	0	0	395818	656753	821307	5223217	6371	1144	0	0	7.61282e+07	21578.3	42	1038076	13775176	-1	179.23	179.23	-74535	-178.23	0	0	13.50	-1	-1	1753.3 MiB	72.28	38.266	32.2437	1610.3 MiB	-1	50.21	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	ucsb_152_tap_fir_stratixiv_arch_timing.blif	common	116.55	vpr	1.18 GiB		42	750	0	0	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1239568	13	29	26295	20086	1	12166	792	29	21	1218	LAB	auto	1085.4 MiB	16.91	67068	202257	28659	157846	15752	1160.9 MiB	20.53	0.39	4.73562	-3961.48	-3.73562	2.43816	1.64	0.061648	0.0465487	3.03006	2.44366	73397	6.03395	18191	1.49548	27121	40222	41691205	14376856	0	0	41691205	14376856	40091	35100	0	0	56151	42804	0	0	79177	56273	0	0	1399913	909885	0	0	22091744	8845427	0	0	18024129	4487367	0	0	40091	0	0	25362	40289	45249	243	0	0	896	3433	3346	39848	0	0	24466	36856	41903	326660	695	58	0	0	2.60090e+07	21353.8	17	354380	4695504	-1	4.98447	2.55101	-4468.31	-3.98447	0	0	6.88	-1	-1	1182.9 MiB	17.61	5.97669	4.95198	1160.9 MiB	-1	28.86	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	uoft_raytracer_stratixiv_arch_timing.blif	common	720.48	vpr	2.01 GiB		964	975	19	34	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	2106376	542	422	37277	26038	1	20638	1992	78	58	9048	io	auto	1187.0 MiB	42.39	183733	1455240	538662	841109	75469	2057.0 MiB	208.67	1.55	7.11394	-33300.6	-6.11394	7.11394	83.23	0.137908	0.121219	15.9164	12.8973	266867	12.9327	63133	3.05951	76191	173085	236726273	71667439	0	0	236726273	71667439	172046	140616	0	0	4646712	4591555	0	0	5047957	4836327	0	0	5363716	3974764	0	0	117101826	36475961	0	0	104394016	21648216	0	0	172046	0	0	220539	383591	505957	1964	0	0	18044	48610	82000	170082	0	0	202495	334981	423957	2427213	4797	911	0	0	1.96212e+08	21685.7	48	2627776	35616532	-1	7.3721	7.24264	-37667.5	-6.3721	0	0	53.18	-1	-1	2057.0 MiB	73.86	26.375	21.945	2057.0 MiB	-1	236.41	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	wb_conmax_stratixiv_arch_timing.blif	common	734.37	vpr	2.19 GiB		1107	721	0	0	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	2301584	403	704	15490	16194	1	8416	1828	88	65	11440	io	auto	1084.8 MiB	41.82	128057	1197232	445931	718466	32835	2247.6 MiB	34.70	0.26	11.4037	-17377.9	-10.4037	5.42126	239.44	0.0457198	0.0408895	6.82671	5.63373	167396	19.8926	34045	4.04575	25334	99358	112324804	53632482	0	0	112324804	53632482	84202	67881	0	0	203693	176286	0	0	274811	218977	0	0	2655608	2336398	0	0	64208220	35351126	0	0	44898270	15481814	0	0	84202	0	0	79422	211978	322314	2365	0	0	4109	89362	120121	81837	0	0	75313	122616	202193	969149	20113	7053	0	0	2.47902e+08	21669.8	14	3325632	44950250	-1	11.9086	5.64111	-21081.7	-10.9086	0	0	69.50	-1	-1	2247.6 MiB	37.04	9.07445	7.61513	2247.6 MiB	-1	292.77	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	picosoc_stratixiv_arch_timing.blif	common	219.40	vpr	1.18 GiB		35	735	0	6	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1232136	18	17	16969	16357	1	6386	776	28	21	1176	LAB	auto	1079.4 MiB	37.51	75549	228872	54280	168966	5626	1154.7 MiB	19.93	0.21	6.60738	-36254.3	-5.60738	6.60738	1.78	0.0403282	0.0312915	4.21205	3.27599	104548	16.3817	25473	3.99138	21091	107999	193327728	112051950	0	0	193327728	112051950	94245	68282	0	0	190700	150845	0	0	243652	196041	0	0	2701629	2107621	0	0	111502687	71727172	0	0	78594815	37801989	0	0	94245	0	0	116281	695408	796456	2720	0	0	4654	132512	147615	91525	0	0	111627	562896	648841	4655232	31263	24066	0	0	2.50919e+07	21336.6	29	342304	4528390	-1	7.13515	7.13515	-40494.2	-6.13515	0	0	6.75	-1	-1	1180.4 MiB	103.10	8.40368	6.77832	1154.7 MiB	-1	32.44	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	murax_stratixiv_arch_timing.blif	common	30.54	vpr	993.04 MiB		35	73	0	8	0	0	success	v8.0.0-9158-g8b57a0365	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-11-17T10:26:55	betzgrp-wintermute.eecg.utoronto.ca	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	1016868	18	17	2291	2142	1	1503	116	13	10	260	LAB	auto	954.4 MiB	5.80	9850	10268	1184	7920	1164	993.0 MiB	0.92	0.02	5.2447	-3308.74	-4.2447	3.92582	0.19	0.00851794	0.00763266	0.422004	0.354326	13127	8.75133	3526	2.35067	3855	9143	8593601	615626	0	0	8593601	615626	9143	7449	0	0	41158	38550	0	0	49306	43362	0	0	285852	224868	0	0	4069130	215521	0	0	4139012	85876	0	0	9143	0	0	7770	8122	9581	0	0	0	0	0	0	9143	0	0	7770	8122	9581	75322	0	0	0	0	5.17734e+06	19912.8	44	69776	911850	-1	5.35381	4.26979	-3592.73	-4.35381	0	0	1.90	-1	-1	993.0 MiB	2.35	1.52031	1.34046	993.0 MiB	-1	1.26	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt
index 1a5f5c6055a..085feec3117 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt
@@ -3,3 +3,4 @@ regression_tests/vtr_reg_nightly_test7/titan_other_run_flat
 #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_depop_run_flat
 #regression_tests/vtr_reg_nightly_test7/verify_router_lookahead_run_flat
 regression_tests/vtr_reg_nightly_test7/verify_rr_graph_run_flat
+regression_tests/vtr_reg_nightly_test7/3d_titan_other