From 1f620010b757d91283597f901af9677a1cc58cee Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 25 Apr 2023 19:10:34 -0400 Subject: [PATCH 01/51] add flat_router strong test --- .../strong_flat_router/config/config.txt | 28 +++++++++++++++++++ .../config/golden_results.txt | 2 ++ 2 files changed, 30 insertions(+) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt new file mode 100644 index 00000000000..caed2da9784 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt @@ -0,0 +1,28 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=spree.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +script_params=-track_memory_usage --route_chan_width 100 --max_router_iterations 100 --router_lookahead map --flat_routing true + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt new file mode 100644 index 00000000000..ed1e4a4a83f --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 5.69 vpr 65.43 MiB -1 -1 1.36 31308 16 0.50 -1 -1 34840 -1 -1 61 45 3 1 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66996 45 32 1188 1147 1 781 142 14 14 196 memory auto 28.1 MiB 1.38 6698 65.4 MiB 0.23 0.00 9.7493 -6323.75 -9.7493 9.7493 0.02 0.000903437 0.000727014 0.0847444 0.0698178 -1 10688 13 9.20055e+06 5.32753e+06 1.11359e+06 5681.59 1.14 0.114902 0.0946844 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From ddbdabbf08182e25c5b87aaf1ef64ae48f6cd8f2 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 25 Apr 2023 19:12:51 -0400 Subject: [PATCH 02/51] Create a titan_other test for flat_router --- .../titan_other_flat_router/config/config.txt | 52 +++++++++++++++++++ .../config/golden_results.txt | 23 ++++++++ 2 files changed, 75 insertions(+) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt new file mode 100644 index 00000000000..aa1f692146a --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt @@ -0,0 +1,52 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_other_blif + +# Path to directory of SDC files +sdc_dir=benchmarks/titan_other_blif + +# Path to directory of architectures to use +archs_dir=arch/titan + +# Add circuits to list to sweep +circuit_list_add=carpat_stratixiv_arch_timing.blif +circuit_list_add=CH_DFSIN_stratixiv_arch_timing.blif +circuit_list_add=CHERI_stratixiv_arch_timing.blif +circuit_list_add=EKF-SLAM_Jacobians_stratixiv_arch_timing.blif +circuit_list_add=jacobi_stratixiv_arch_timing.blif +circuit_list_add=JPEG_stratixiv_arch_timing.blif +circuit_list_add=leon2_stratixiv_arch_timing.blif +circuit_list_add=leon3mp_stratixiv_arch_timing.blif +circuit_list_add=MCML_stratixiv_arch_timing.blif +circuit_list_add=MMM_stratixiv_arch_timing.blif +circuit_list_add=radar20_stratixiv_arch_timing.blif +circuit_list_add=random_stratixiv_arch_timing.blif +circuit_list_add=Reed_Solomon_stratixiv_arch_timing.blif +circuit_list_add=smithwaterman_stratixiv_arch_timing.blif +circuit_list_add=stap_steering_stratixiv_arch_timing.blif +circuit_list_add=sudoku_check_stratixiv_arch_timing.blif +circuit_list_add=SURF_desc_stratixiv_arch_timing.blif +circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif +circuit_list_add=uoft_raytracer_stratixiv_arch_timing.blif +circuit_list_add=wb_conmax_stratixiv_arch_timing.blif +circuit_list_add=picosoc_stratixiv_arch_timing.blif +circuit_list_add=murax_stratixiv_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +script_params=-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --flat_routing true + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt new file mode 100644 index 00000000000..97c1aad1792 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt @@ -0,0 +1,23 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops total_internal_heap_pushes total_internal_heap_pops total_external_heap_pushes total_external_heap_pops total_external_SOURCE_pushes total_external_SOURCE_pops total_internal_SOURCE_pushes total_internal_SOURCE_pops total_external_SINK_pushes total_external_SINK_pops total_internal_SINK_pushes total_internal_SINK_pops total_external_IPIN_pushes total_external_IPIN_pops total_internal_IPIN_pushes total_internal_IPIN_pops total_external_OPIN_pushes total_external_OPIN_pops total_internal_OPIN_pushes total_internal_OPIN_pops total_external_CHANX_pushes total_external_CHANX_pops total_internal_CHANX_pushes total_internal_CHANX_pops total_external_CHANY_pushes total_external_CHANY_pops total_internal_CHANY_pushes total_internal_CHANY_pops rt_node_SOURCE_pushes rt_node_SINK_pushes rt_node_IPIN_pushes rt_node_OPIN_pushes rt_node_CHANX_pushes rt_node_CHANY_pushes rt_node_SOURCE_high_fanout_pushes rt_node_SINK_high_fanout_pushes rt_node_IPIN_high_fanout_pushes rt_node_OPIN_high_fanout_pushes rt_node_CHANX_high_fanout_pushes rt_node_CHANY_high_fanout_pushes rt_node_SOURCE_entire_tree_pushes rt_node_SINK_entire_tree_pushes rt_node_IPIN_entire_tree_pushes rt_node_OPIN_entire_tree_pushes rt_node_CHANX_entire_tree_pushes rt_node_CHANY_entire_tree_pushes adding_all_rt adding_high_fanout_rt total_number_of_adding_all_rt_from_calling_high_fanout_rt logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 397.37 vpr 5.57 GiB 274 964 36 59 0 2 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5836908 22 252 53001 29054 7 24705 1335 89 66 5874 DSP auto 1505.7 MiB 24.27 269580 1947.7 MiB 39.42 0.30 7.32923 -37591.9 -6.32923 3.01568 66.59 0.0888908 0.0746767 11.4126 9.61317 364926 6.88930 79916 1.50870 131101 312764 340522066 55078817 24597514 3009404 315924552 52069413 0 0 291215 234770 200434 200434 312764 312764 18296371 200585 21665942 879835 18600105 11887810 2327593 1582035 136916299 21561190 0 0 141911343 18219394 0 0 291215 0 1878744 748386 616906 777376 14055 0 980721 77258 210216 289487 277160 0 898023 671128 406690 487889 3051248 35899 4650 0 0 1.08076e+08 18399.1 44 3157876 31702500 48537 7.66398 2.99405 -41850.2 -6.66398 0 0 19.41 22.21 13.95 5700.1 MiB 143.39 18.9923 16.0442 1947.7 MiB 55.85 85.23 +stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 285.32 vpr 5.18 GiB 36 1577 10 10 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5436380 3 33 48977 39238 1 26166 1633 54 40 2160 LAB auto 1539.3 MiB 58.65 290990 1643.7 MiB 48.66 0.53 76.315 -82904.4 -75.315 76.315 7.64 0.115181 0.102646 10.6493 8.63119 382587 7.81220 90139 1.84059 138606 442340 235182362 29420500 42551976 4326874 192630386 25093626 0 0 378975 263547 305970 305970 442340 442340 4563808 305987 38286181 1308720 19384863 14222716 3444480 2312267 83227761 5930409 0 0 85147984 4328544 0 0 378975 0 1526832 1169311 1409649 1751107 12186 0 473262 58743 328871 359172 366789 0 1053570 1110568 1080778 1391935 5351854 76271 11405 0 0 3.96465e+07 18354.9 26 2487572 26413249 65185 71.011 71.011 -144369 -70.011 0 0 7.27 16.39 9.90 5308.9 MiB 118.66 15.1024 12.2091 1571.4 MiB 56.53 23.76 +stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 611.05 vpr 6.59 GiB 211 2260 3 210 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 6913916 38 173 62892 59064 3 36091 2684 86 64 5504 M9K auto 1759.7 MiB 125.17 680307 2031.3 MiB 83.94 0.64 12.8712 -327258 -11.8712 7.18208 45.56 0.155899 0.133257 19.0608 14.8485 898910 14.2945 200818 3.19342 280108 1302723 674019058 105333731 120250596 10463008 553768462 94870723 0 0 897956 654579 823658 823658 1302723 1302723 3585804 823856 109767196 3732055 37029117 23124220 8282721 4773651 250955558 37583279 0 0 261374325 32515710 0 0 897956 0 4820957 2991290 4296693 4967624 63862 0 3344475 349793 1966015 2383764 834094 0 1476482 2641497 2330678 2583860 10258217 473023 173887 0 0 1.01289e+08 18402.8 76 4401070 46519638 146007 13.2849 7.35525 -370743 -12.2849 0 0 18.13 35.71 23.53 6751.9 MiB 245.50 40.1772 31.4487 2031.3 MiB 54.86 66.64 +stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 676.87 vpr 5.85 GiB 574 2798 16 0 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 6136208 4 570 66175 54803 2 39719 3388 91 67 6097 io auto 1804.4 MiB 108.14 668010 2135.3 MiB 104.70 0.77 28.155 -108923 -27.155 6.3521 71.67 0.147877 0.128251 18.1333 14.4247 942138 14.2381 209241 3.16217 260233 1393445 1115587540 172879613 134887907 15755573 980699633 157124040 0 0 1284179 876743 995707 995707 1393445 1393445 9261654 996082 119184958 4167212 66062325 57282567 13025325 9318173 445330180 54016516 0 0 459049767 43833168 0 0 1284179 0 3501168 5077106 4510005 5407346 15783 0 477179 99959 587304 713397 1268396 0 3023989 4977147 3922701 4693949 18775122 125881 40725 0 0 1.12157e+08 18395.4 25 4532884 54099067 129419 29.5601 7.71382 -124295 -28.5601 0 0 20.48 28.96 16.48 5992.4 MiB 273.52 25.6531 20.4111 2135.3 MiB 55.53 72.08 +stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 408.07 vpr 5.45 GiB 536 1962 7 4 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5716180 227 309 49176 40422 1 28220 2509 85 63 5355 io auto 1606.0 MiB 76.14 309758 1938.4 MiB 69.71 0.63 198.063 -114943 -197.063 198.063 46.57 0.101518 0.0801777 13.0854 10.3604 398620 8.10665 93935 1.91034 130706 548014 217925555 24378865 52115678 4953794 165809877 19425071 0 0 456160 273191 373914 373914 548014 548014 1377855 373936 47123898 1626887 18262871 13577830 3987606 2505702 71889555 3539658 0 0 73905682 1559733 0 0 456160 0 1932516 1666875 1890867 2540235 12158 0 789005 58865 379609 504930 444002 0 1143511 1608010 1511258 2035305 7105779 104518 9287 0 0 9.84408e+07 18383.0 19 3535296 41101308 80255 191.95 191.95 -135945 -190.95 0 0 17.91 21.42 11.79 5582.2 MiB 116.17 16.8388 13.2815 1938.4 MiB 57.01 59.64 +stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 341.49 vpr 5.80 GiB 36 1338 8 149 2 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 6077680 3 33 52402 39411 1 28023 1533 73 54 3942 M9K auto 1563.4 MiB 61.00 328453 1763.7 MiB 48.22 0.37 16.309 -304937 -15.309 16.309 27.81 0.0847471 0.073453 11.3627 9.14966 407172 7.77135 93212 1.77906 135125 488266 210082344 25083177 42054593 4368338 168027751 20714839 0 0 413686 270064 286011 286011 488266 488266 2231559 286069 37555794 1346132 18932273 13525208 3596847 2263876 72770792 3906289 0 0 73807116 2711262 0 0 413686 0 3264851 1286623 1245281 1473697 29788 0 1213130 144594 346288 459307 383898 0 2051721 1142029 898993 1014390 6789389 105308 20974 0 0 7.26339e+07 18425.6 39 3037750 30141692 81349 17.2515 17.2515 -331543 -16.2515 0 0 13.02 26.41 18.05 5935.2 MiB 124.92 18.5722 15.0066 1763.7 MiB 57.11 46.07 +stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 174.72 vpr 4.76 GiB 251 954 1 17 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 4990436 55 196 20131 19956 1 8402 1223 44 33 1452 io auto 1377.3 MiB 35.52 121023 1483.4 MiB 13.92 0.11 7.52997 -77879.8 -6.52997 7.52997 5.26 0.0301155 0.0256352 4.70393 3.64803 171501 8.52052 39970 1.98579 55111 246929 82198123 8975592 23733601 1931345 58464522 7044247 0 0 162561 111548 172264 172264 246929 246929 342827 172272 21876300 731968 6428573 4773936 1447811 840900 25533768 1263196 0 0 25987090 662579 0 0 162561 0 1083623 522997 765004 969485 11213 0 769326 55850 383170 472861 151348 0 314297 467147 381834 496624 1920052 96408 13355 0 0 2.65099e+07 18257.5 27 1360736 16121963 53571 7.92427 7.92427 -90281.9 -6.92427 0 0 5.02 10.36 6.24 4873.5 MiB 83.76 6.57209 5.15584 1417.4 MiB 57.49 15.74 +stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 293.80 vpr 5.36 GiB 255 2097 1 28 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5618512 84 171 36458 36247 3 20325 2381 62 46 2852 LAB auto 1548.3 MiB 69.97 303330 1687.8 MiB 37.44 0.39 11.9196 -83773.9 -10.9196 4.04427 14.36 0.132607 0.101782 10.8207 8.40214 398226 10.9271 87692 2.40621 123842 564801 167310471 18192679 53960497 4110868 113349974 14081811 0 0 307109 236137 361475 361475 564801 564801 678121 361861 50331389 1672061 13736914 9592183 2757198 1637869 48875198 2291186 0 0 49698266 1475106 0 0 307109 0 2971412 851541 1916699 2534432 16164 0 2562289 76396 1156292 1432006 290945 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murax_stratixiv_arch_timing.blif common 76.25 vpr 4.33 GiB 35 73 0 8 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 4536788 18 17 2291 2142 1 1503 116 16 12 192 LAB M9K auto 1215.6 MiB 4.09 10935 1282.5 MiB 0.47 0.01 5.13437 -3482.72 -4.13437 4.09388 0.07 0.00226729 0.00181544 0.12423 0.102718 14152 6.18531 3668 1.60315 8178 30873 11563495 1345222 2752644 272463 8810851 1072759 0 0 27967 19633 14947 14947 30873 30873 38108 14950 2456950 86092 1309558 885603 236854 135865 3698696 120253 0 0 3749542 37006 0 0 27967 0 155303 89501 40391 57194 2475 0 68893 11608 16303 20422 25492 0 86410 77893 24088 36772 295005 5415 174 0 0 3.35078e+06 17452.0 17 153885 1496224 4500 4.22336 4.22336 -3763.38 -3.22336 0 0 0.76 1.30 0.90 4430.5 MiB 57.74 0.239279 0.197076 1254.1 MiB 54.69 0.53 From 6ee5b70c25a7f75732790b5e9864bc38efca259b Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 26 Apr 2023 09:17:09 -0400 Subject: [PATCH 03/51] add titan_quick_qor_flat_router under nightly_test_2 --- .../config/config.txt | 70 +++++++++++++++++++ .../config/golden_results.txt | 23 ++++++ 2 files changed, 93 insertions(+) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/config.txt new file mode 100644 index 00000000000..8c45c6d7fc5 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/config.txt @@ -0,0 +1,70 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif + +# Path to directory of SDCs to use +sdc_dir=benchmarks/titan_blif + +# Path to directory of architectures to use +archs_dir=arch/titan + +# Add circuits to list to sweep +# Note that the circuits are roughly sorted so that some small +# circuits run first (to detect early failures), followed by larger +# circuits (so they do not start last) + +#To keep turn-around time reasonable (approx. <12 hrs) we exclude some +#of the slowest benchmarks + +#Largest benchmarks, excluded +#circuit_list_add=gaussianblur_stratixiv_arch_timing.blif + +#Mixed order of large and small +circuit_list_add=gsm_switch_stratixiv_arch_timing.blif +circuit_list_add=mes_noc_stratixiv_arch_timing.blif +circuit_list_add=dart_stratixiv_arch_timing.blif +circuit_list_add=denoise_stratixiv_arch_timing.blif +circuit_list_add=sparcT2_core_stratixiv_arch_timing.blif +circuit_list_add=cholesky_bdti_stratixiv_arch_timing.blif +circuit_list_add=minres_stratixiv_arch_timing.blif +circuit_list_add=stap_qrd_stratixiv_arch_timing.blif +circuit_list_add=openCV_stratixiv_arch_timing.blif +circuit_list_add=bitonic_mesh_stratixiv_arch_timing.blif +circuit_list_add=segmentation_stratixiv_arch_timing.blif +circuit_list_add=SLAM_spheric_stratixiv_arch_timing.blif +circuit_list_add=des90_stratixiv_arch_timing.blif + +#Small benchmarks +circuit_list_add=neuron_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_core_stratixiv_arch_timing.blif +circuit_list_add=stereo_vision_stratixiv_arch_timing.blif +circuit_list_add=cholesky_mc_stratixiv_arch_timing.blif + +#Large benchmarks +circuit_list_add=directrf_stratixiv_arch_timing.blif +circuit_list_add=bitcoin_miner_stratixiv_arch_timing.blif +circuit_list_add=LU230_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_chip2_stratixiv_arch_timing.blif +circuit_list_add=LU_Network_stratixiv_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt +#qor_parse_file=qor_large.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +#The Titan benchmarks are run at a fixed channel width of 300 to simulate a Stratix IV-like routing architecture +#A large number of routing iterations is set to ensure the router doesn't give up to easily on the larger benchmarks +#To be more run-time comparable to commercial tools like Quartus, we run with higher placer effort (inner_num=2) and lower astar_fac (1.0) +#Set a 24hr timeout so they don't run forever +script_params=-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map -timeout 100000 --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --flat_routing true diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/golden_results.txt new file mode 100644 index 00000000000..d8bd98ed85b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/golden_results.txt @@ -0,0 +1,23 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops total_internal_heap_pushes total_internal_heap_pops total_external_heap_pushes total_external_heap_pops total_external_SOURCE_pushes total_external_SOURCE_pops total_internal_SOURCE_pushes total_internal_SOURCE_pops total_external_SINK_pushes total_external_SINK_pops total_internal_SINK_pushes total_internal_SINK_pops total_external_IPIN_pushes total_external_IPIN_pops total_internal_IPIN_pushes total_internal_IPIN_pops total_external_OPIN_pushes total_external_OPIN_pops total_internal_OPIN_pushes total_internal_OPIN_pops total_external_CHANX_pushes total_external_CHANX_pops total_internal_CHANX_pushes total_internal_CHANX_pops total_external_CHANY_pushes total_external_CHANY_pops total_internal_CHANY_pushes total_internal_CHANY_pops rt_node_SOURCE_pushes rt_node_SINK_pushes rt_node_IPIN_pushes rt_node_OPIN_pushes rt_node_CHANX_pushes rt_node_CHANY_pushes rt_node_SOURCE_high_fanout_pushes rt_node_SINK_high_fanout_pushes rt_node_IPIN_high_fanout_pushes rt_node_OPIN_high_fanout_pushes rt_node_CHANX_high_fanout_pushes rt_node_CHANY_high_fanout_pushes rt_node_SOURCE_entire_tree_pushes rt_node_SINK_entire_tree_pushes rt_node_IPIN_entire_tree_pushes rt_node_OPIN_entire_tree_pushes rt_node_CHANX_entire_tree_pushes rt_node_CHANY_entire_tree_pushes adding_all_rt adding_high_fanout_rt total_number_of_adding_all_rt_from_calling_high_fanout_rt logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml gsm_switch_stratixiv_arch_timing.blif common 4352.80 vpr 28.53 GiB 136 21427 0 1848 0 1 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 29912700 100 36 504627 490068 5 201854 23412 255 189 48195 M9K auto 6059.2 MiB 692.31 4638985 8816.2 MiB 1561.95 9.31 7.82058 -1.35365e+06 -6.82058 5.58978 201.76 1.32224 1.01174 210.305 161.371 5070137 10.0475 974996 1.93214 1213632 4945039 1065575665 116383112 385641632 28752043 679934033 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5.68062 -804856 -9.86511 0 0 115.72 436.38 301.68 31920.2 MiB 945.50 497.117 397.302 9155.5 MiB 56.19 649.39 From 3f9a38f050497ec6f3c385cc9904c8cbf9184bb0 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 26 Apr 2023 16:01:41 -0400 Subject: [PATCH 04/51] add vtr_reg_qor_chain_large_flat_router --- .../config/config.txt | 34 +++++++++++++++++++ .../config/golden_results.txt | 8 +++++ 2 files changed, 42 insertions(+) create mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt new file mode 100755 index 00000000000..b3a59b60a8a --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt @@ -0,0 +1,34 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=bgm.v +circuit_list_add=LU8PEEng.v +circuit_list_add=LU32PEEng.v +circuit_list_add=mcml.v +circuit_list_add=stereovision0.v +circuit_list_add=stereovision1.v +circuit_list_add=stereovision2.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_large.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 --flat_routing true diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/golden_results.txt new file mode 100644 index 00000000000..fd0c1d9ce76 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/golden_results.txt @@ -0,0 +1,8 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes 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9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 923112 257 32 35747 33389 1 19410 3006 63 63 3969 clb auto 363.5 MiB 77.50 253145 649.5 MiB 73.64 0.59 17.914 -23716.3 -17.914 17.914 39.70 0.0880725 0.0708005 9.77498 8.00338 76 392059 33 2.36641e+08 1.50195e+08 2.05973e+07 5189.55 381.43 41.2388 33.1711 1164678 13731204 644989 371527 20 115362 571818 61514298 6819223 35503182 3178698 26011116 3640525 0 0 564225 332002 491958 491958 571818 571818 1128621 491958 32233238 1278646 766591 213048 2133901 996232 11569167 1209693 0 0 12054779 1233868 0 0 564225 0 654403 1391496 2914561 2896524 8506385 10089 827 20.1874 20.1874 -26373.5 -20.1874 0 0 2.57532e+07 6488.59 12.65 80.74 4.54 47.39 0.17 12.65 5.71597 4.53847 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 1136.16 vpr 889.31 MiB -1 -1 50.15 440724 98 99.05 -1 -1 111472 -1 -1 2126 114 45 8 success v8.0.0-7583-g7e3566081-dirty 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32 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 3050088 114 102 120062 107871 1 57253 7828 102 102 10404 clb auto 1113.0 MiB 185.97 1023549 1817.4 MiB 458.44 2.68 65.7766 -340242 -65.7766 65.7766 113.30 0.267619 0.237125 41.2933 33.6786 124 1381022 46 6.36957e+08 5.04159e+08 8.44220e+07 8114.38 3808.34 155.16 126.556 4012724 46013538 1937919 1304624 22 291074 1512530 319959886 58309824 89932360 7163592 230027526 51146232 0 0 1134766 619728 1020026 1020026 1512530 1512530 9129734 1020026 83186892 3391841 1432317 327772 4098172 1639493 108397684 23935306 0 0 110047765 24843102 0 0 1134766 0 6565334 2616737 5644527 5721723 13682578 388101 453295 73.8673 73.8673 -475786 -73.8673 0 0 1.06940e+08 10278.8 40.72 197.17 13.97 83.19 0.11 40.72 12.3471 9.92877 +k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 6219.43 vpr 3.10 GiB -1 -1 232.31 1194144 25 3616.77 -1 -1 365724 -1 -1 6438 36 159 27 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 3249352 36 356 184794 159441 1 63873 7016 95 95 9025 clb auto 1296.2 MiB 131.73 766930 1788.7 MiB 596.09 3.73 43.0057 -282861 -43.0057 43.0057 87.57 0.218254 0.18891 36.1992 29.359 148 1001428 23 5.4965e+08 4.44764e+08 8.56943e+07 9495.22 1225.82 131.981 106.963 4378636 44335993 2081177 966061 20 376908 1189879 169664636 27865893 67663219 6762625 102001417 21103268 0 0 867854 698918 676806 676806 1189879 1189879 5157733 676806 62260791 3273996 949088 303140 3344695 1599832 47768777 9696056 0 0 47449013 9750460 0 0 867854 0 6242650 1364611 2310107 2262183 5040607 345027 892783 46.8141 46.8141 -359572 -46.8141 0 0 1.08458e+08 12017.5 40.49 150.98 15.27 72.57 0.16 40.49 9.16862 7.35512 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 127.28 vpr 346.23 MiB -1 -1 10.56 98428 5 7.90 -1 -1 65520 -1 -1 710 169 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 354544 169 197 23321 21461 1 6583 1076 33 33 1089 clb auto 168.0 MiB 10.90 40334 228.2 MiB 9.08 0.08 3.01283 -13314.4 -3.01283 3.01283 5.11 0.028054 0.0239182 3.99064 3.31471 56 60560 28 6.0475e+07 3.82649e+07 4.09277e+06 3758.28 56.20 9.04569 7.48535 463449 3594119 232643 56239 15 38700 94881 6517908 766440 5239888 561748 1278020 204692 0 0 72476 66278 44180 44180 94881 94881 79186 44180 4781913 260256 75639 22199 290618 140333 539375 46824 0 0 539640 47309 0 0 72476 0 379173 106385 128995 132993 328781 24231 4977 3.70046 3.70046 -16276.1 -3.70046 0 0 5.21984e+06 4793.24 1.72 11.58 0.77 7.02 0.11 1.72 1.39265 1.15472 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 277.38 vpr 394.70 MiB -1 -1 8.11 120008 3 15.97 -1 -1 73340 -1 -1 680 115 0 40 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 404172 115 145 22868 19305 1 9678 980 40 40 1600 mult_36 auto 163.7 MiB 7.98 80732 223.6 MiB 6.85 0.07 4.99402 -21942.4 -4.99402 4.99402 7.16 0.0181466 0.0145557 2.362 1.95063 86 129273 33 9.16046e+07 5.24886e+07 8.98461e+06 5615.38 196.47 11.8555 9.8698 535763 4510540 226039 118186 16 49483 109186 28053062 4122103 5706126 637537 22346936 3484566 0 0 83174 77600 63700 63700 109186 109186 1515101 63700 5215541 296128 91599 40021 298225 154623 10253223 1649245 0 0 10423313 1667900 0 0 83174 0 422151 98582 268947 267443 540573 28101 6132 5.39751 5.39751 -25069.8 -5.39751 0 0 1.13675e+07 7104.67 3.44 14.51 1.80 7.09 0.11 3.44 0.6329 0.523497 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 1004.56 vpr 1.01 GiB -1 -1 11.90 194072 3 7.76 -1 -1 151220 -1 -1 1498 149 0 179 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1059916 149 182 55416 37075 1 28615 2008 80 80 6400 mult_36 auto 350.6 MiB 16.76 303233 914.6 MiB 41.03 0.47 14.3381 -49440 -14.3381 14.3381 72.10 0.109389 0.085899 7.80017 6.38216 98 414564 33 3.90281e+08 1.51617e+08 4.18005e+07 6531.32 717.94 52.6525 43.6926 1714224 14643438 501923 389094 20 128774 202471 56151273 8660521 10741265 1371048 45410008 7289473 0 0 178242 167301 132954 132954 202471 202471 2638012 132954 9799585 629092 183100 106120 560967 372184 21138915 3440129 0 0 21317027 3477316 0 0 178242 0 496143 148445 267958 274367 782492 25389 9286 15.1906 15.1906 -57297.7 -15.1906 0 0 5.30091e+07 8282.68 35.64 40.85 9.73 17.73 0.12 35.64 4.74661 3.94154 From 25f7d5b2086f96da3c93140b14b47f96a17ab827 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 27 Apr 2023 10:26:12 -0400 Subject: [PATCH 05/51] Add flat router tests to task_list - otherwise they woudln't be cheked by CI tests --- .../regression_tests/vtr_reg_nightly_test2/task_list.txt | 1 + .../regression_tests/vtr_reg_nightly_test3/task_list.txt | 5 ++--- vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt index 8112117030f..a1ea8f4dcd9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt @@ -11,3 +11,4 @@ regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc regression_tests/vtr_reg_nightly_test2/titan_other regression_tests/vtr_reg_nightly_test2/titan_quick_qor +regression_tests/vtr_reg_nightly_test2/titan_quick_qor/titan_quick_qor_flat_router diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt index 5a58cab89f2..e47afeffc91 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt @@ -2,6 +2,5 @@ regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off regression_tests/vtr_reg_nightly_test3/vtr_reg_qor -regression_tests/vtr_reg_nightly_test3/complex_switch - - +regression_tests/vtr_reg_nightly_test3/complex_switch +regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 73335b2f919..9f92bcb8fd0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -83,3 +83,4 @@ regression_tests/vtr_reg_strong/koios_no_complex_dsp regression_tests/vtr_reg_strong/strong_timing_fail regression_tests/vtr_reg_strong/strong_timing_no_fail regression_tests/vtr_reg_strong/strong_noc +regression_tests/vtr_reg_strong/strong_flat_router From bd310277130e98e5cff308eecdc36ce82194ead5 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 27 Apr 2023 19:15:48 -0400 Subject: [PATCH 06/51] fix a typo under task list of nightly test 2 --- .../tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt index a1ea8f4dcd9..8d34d67bb9e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt @@ -11,4 +11,4 @@ regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc regression_tests/vtr_reg_nightly_test2/titan_other regression_tests/vtr_reg_nightly_test2/titan_quick_qor -regression_tests/vtr_reg_nightly_test2/titan_quick_qor/titan_quick_qor_flat_router +regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router From e95220bd14c1573c3545ca21f2b0ffe713582a78 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 27 Apr 2023 19:17:25 -0400 Subject: [PATCH 07/51] add flat_router test under task list of nightly test 3 --- .../tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt index e47afeffc91..1e0bfeabcc4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt @@ -3,4 +3,4 @@ regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off regression_tests/vtr_reg_nightly_test3/vtr_reg_qor regression_tests/vtr_reg_nightly_test3/complex_switch -regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large +regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router From 6b0c7c8b6cf8e6b3fe473a9338c6d34bf789b440 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 15 May 2023 14:31:12 -0400 Subject: [PATCH 08/51] change max_router iterations of flat_router test under nightly_test_3 to 300 - Add flat router depop under nightly test 3 --- .../config/config.txt | 48 +++++++++++++++++++ .../config/golden_results.txt | 22 +++++++++ .../config/config.txt | 2 +- 3 files changed, 71 insertions(+), 1 deletion(-) create mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/config.txt new file mode 100755 index 00000000000..ac2b9426fd7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/config.txt @@ -0,0 +1,48 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=arm_core.v +circuit_list_add=bgm.v +circuit_list_add=blob_merge.v +circuit_list_add=boundtop.v +circuit_list_add=ch_intrinsics.v +circuit_list_add=diffeq1.v +circuit_list_add=diffeq2.v +circuit_list_add=LU8PEEng.v +circuit_list_add=LU32PEEng.v +circuit_list_add=mcml.v +circuit_list_add=mkDelayWorker32B.v +circuit_list_add=mkPktMerge.v +circuit_list_add=mkSMAdapter4B.v +circuit_list_add=or1200.v +circuit_list_add=raygentop.v +circuit_list_add=sha.v +circuit_list_add=spree.v +circuit_list_add=stereovision0.v +circuit_list_add=stereovision1.v +circuit_list_add=stereovision2.v +circuit_list_add=stereovision3.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage --max_router_iterations 300 --flat_routing true --has_choking_spot true diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt new file mode 100644 index 00000000000..ea0cc60756b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt @@ -0,0 +1,22 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml arm_core.v common 429.79 vpr 254.70 MiB -1 -1 32.42 122848 20 86.82 -1 -1 71680 -1 -1 678 133 25 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 260812 133 179 14247 14104 1 6984 1015 36 36 1296 memory auto 147.2 MiB 26.63 111456 179.0 MiB 17.66 0.16 19.665 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mult_36 auto 169.8 MiB 8.02 84970 204.0 MiB 12.50 0.13 5.35987 -21763.1 -5.35987 5.35987 7.69 0.0305526 0.0265184 3.72565 3.14157 100 140993 40 9.16046e+07 5.11412e+07 1.10258e+07 6891.10 149.31 18.5616 15.5772 126563 16 34389 56030 30759904 6308879 5.74716 5.74716 -25476.1 -5.74716 0 0 1.38359e+07 8647.47 7.70 13.75 2.0905 1.86264 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 919.98 vpr 1.04 GiB -1 -1 11.15 197868 3 6.30 -1 -1 155564 -1 -1 1490 149 0 179 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1089076 149 182 55416 37075 1 28670 2000 80 80 6400 mult_36 auto 356.8 MiB 19.69 304023 1063.6 MiB 92.74 0.67 13.2416 -49841.9 -13.2416 13.2416 121.55 0.0962531 0.0848053 14.9704 12.5803 106 425024 43 3.90281e+08 1.51186e+08 4.81287e+07 7520.11 553.42 45.7326 38.6761 404262 21 97832 118922 48216274 9732760 14.616 14.616 -57830.7 -14.616 0 0 6.06309e+07 9473.58 31.45 17.86 4.59878 4.07441 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision3.v common 2.09 vpr 63.42 MiB -1 -1 0.60 25644 4 0.12 -1 -1 36300 -1 -1 13 11 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64944 11 2 303 283 2 70 26 7 7 49 clb auto 24.9 MiB 0.14 217 63.4 MiB 0.04 0.00 1.86505 -151.175 -1.86505 1.77348 0.07 0.000327567 0.000244201 0.018376 0.0145168 26 539 18 1.07788e+06 700622 75813.7 1547.22 0.14 0.063896 0.0534703 424 12 250 515 15897 6574 2.07043 1.88 -175.337 -2.07043 0 0 91376.6 1864.83 0.02 0.03 0.0178958 0.0166099 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt index b3a59b60a8a..be28691892d 100755 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt @@ -31,4 +31,4 @@ qor_parse_file=qor_large.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 --flat_routing true +script_params=-track_memory_usage -max_router_iterations 300 --flat_routing true From a618e6209f42a21c96d37756a20091c05e4829a2 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 22 May 2023 15:34:00 -0400 Subject: [PATCH 09/51] remove titan_quick_qor_flat_router - add titan_other_flat_router --- .../vtr_reg_nightly_test2/task_list.txt | 2 +- .../titan_other_flat_router/config/config.txt | 3 - .../config/config.txt | 70 ------------------- .../config/golden_results.txt | 23 ------ 4 files changed, 1 insertion(+), 97 deletions(-) delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/config.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt index 8d34d67bb9e..1b2bb65f2f2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt @@ -10,5 +10,5 @@ regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc regression_tests/vtr_reg_nightly_test2/titan_other +regression_tests/vtr_reg_nightly_test2/titan_other_flat_router regression_tests/vtr_reg_nightly_test2/titan_quick_qor -regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt index aa1f692146a..c0f9a0b723b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt @@ -15,18 +15,15 @@ archs_dir=arch/titan # Add circuits to list to sweep circuit_list_add=carpat_stratixiv_arch_timing.blif circuit_list_add=CH_DFSIN_stratixiv_arch_timing.blif -circuit_list_add=CHERI_stratixiv_arch_timing.blif circuit_list_add=EKF-SLAM_Jacobians_stratixiv_arch_timing.blif circuit_list_add=jacobi_stratixiv_arch_timing.blif circuit_list_add=JPEG_stratixiv_arch_timing.blif circuit_list_add=leon2_stratixiv_arch_timing.blif circuit_list_add=leon3mp_stratixiv_arch_timing.blif -circuit_list_add=MCML_stratixiv_arch_timing.blif circuit_list_add=MMM_stratixiv_arch_timing.blif circuit_list_add=radar20_stratixiv_arch_timing.blif circuit_list_add=random_stratixiv_arch_timing.blif circuit_list_add=Reed_Solomon_stratixiv_arch_timing.blif -circuit_list_add=smithwaterman_stratixiv_arch_timing.blif circuit_list_add=stap_steering_stratixiv_arch_timing.blif circuit_list_add=sudoku_check_stratixiv_arch_timing.blif circuit_list_add=SURF_desc_stratixiv_arch_timing.blif diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/config.txt deleted file mode 100644 index 8c45c6d7fc5..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/config.txt +++ /dev/null @@ -1,70 +0,0 @@ -############################################ -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/titan_blif - -# Path to directory of SDCs to use -sdc_dir=benchmarks/titan_blif - -# Path to directory of architectures to use -archs_dir=arch/titan - -# Add circuits to list to sweep -# Note that the circuits are roughly sorted so that some small -# circuits run first (to detect early failures), followed by larger -# circuits (so they do not start last) - -#To keep turn-around time reasonable (approx. <12 hrs) we exclude some -#of the slowest benchmarks - -#Largest benchmarks, excluded -#circuit_list_add=gaussianblur_stratixiv_arch_timing.blif - -#Mixed order of large and small -circuit_list_add=gsm_switch_stratixiv_arch_timing.blif -circuit_list_add=mes_noc_stratixiv_arch_timing.blif -circuit_list_add=dart_stratixiv_arch_timing.blif -circuit_list_add=denoise_stratixiv_arch_timing.blif -circuit_list_add=sparcT2_core_stratixiv_arch_timing.blif -circuit_list_add=cholesky_bdti_stratixiv_arch_timing.blif -circuit_list_add=minres_stratixiv_arch_timing.blif -circuit_list_add=stap_qrd_stratixiv_arch_timing.blif -circuit_list_add=openCV_stratixiv_arch_timing.blif -circuit_list_add=bitonic_mesh_stratixiv_arch_timing.blif -circuit_list_add=segmentation_stratixiv_arch_timing.blif -circuit_list_add=SLAM_spheric_stratixiv_arch_timing.blif -circuit_list_add=des90_stratixiv_arch_timing.blif - -#Small benchmarks -circuit_list_add=neuron_stratixiv_arch_timing.blif -circuit_list_add=sparcT1_core_stratixiv_arch_timing.blif -circuit_list_add=stereo_vision_stratixiv_arch_timing.blif -circuit_list_add=cholesky_mc_stratixiv_arch_timing.blif - -#Large benchmarks -circuit_list_add=directrf_stratixiv_arch_timing.blif -circuit_list_add=bitcoin_miner_stratixiv_arch_timing.blif -circuit_list_add=LU230_stratixiv_arch_timing.blif -circuit_list_add=sparcT1_chip2_stratixiv_arch_timing.blif -circuit_list_add=LU_Network_stratixiv_arch_timing.blif - -# Add architectures to list to sweep -arch_list_add=stratixiv_arch.timing.xml - -# Parse info and how to parse -parse_file=vpr_titan.txt - -# How to parse QoR info -qor_parse_file=qor_vpr_titan.txt -#qor_parse_file=qor_large.txt - -# Pass requirements -pass_requirements_file=pass_requirements_vpr_titan.txt - -#The Titan benchmarks are run at a fixed channel width of 300 to simulate a Stratix IV-like routing architecture -#A large number of routing iterations is set to ensure the router doesn't give up to easily on the larger benchmarks -#To be more run-time comparable to commercial tools like Quartus, we run with higher placer effort (inner_num=2) and lower astar_fac (1.0) -#Set a 24hr timeout so they don't run forever -script_params=-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map -timeout 100000 --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --flat_routing true diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/golden_results.txt deleted file mode 100644 index d8bd98ed85b..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor_flat_router/config/golden_results.txt +++ /dev/null @@ -1,23 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops total_internal_heap_pushes total_internal_heap_pops total_external_heap_pushes total_external_heap_pops total_external_SOURCE_pushes total_external_SOURCE_pops total_internal_SOURCE_pushes total_internal_SOURCE_pops total_external_SINK_pushes total_external_SINK_pops total_internal_SINK_pushes total_internal_SINK_pops total_external_IPIN_pushes total_external_IPIN_pops total_internal_IPIN_pushes total_internal_IPIN_pops total_external_OPIN_pushes total_external_OPIN_pops total_internal_OPIN_pushes total_internal_OPIN_pops total_external_CHANX_pushes total_external_CHANX_pops total_internal_CHANX_pushes total_internal_CHANX_pops total_external_CHANY_pushes total_external_CHANY_pops total_internal_CHANY_pushes total_internal_CHANY_pops rt_node_SOURCE_pushes rt_node_SINK_pushes rt_node_IPIN_pushes rt_node_OPIN_pushes rt_node_CHANX_pushes rt_node_CHANY_pushes rt_node_SOURCE_high_fanout_pushes rt_node_SINK_high_fanout_pushes rt_node_IPIN_high_fanout_pushes rt_node_OPIN_high_fanout_pushes rt_node_CHANX_high_fanout_pushes rt_node_CHANY_high_fanout_pushes rt_node_SOURCE_entire_tree_pushes rt_node_SINK_entire_tree_pushes rt_node_IPIN_entire_tree_pushes rt_node_OPIN_entire_tree_pushes rt_node_CHANX_entire_tree_pushes rt_node_CHANY_entire_tree_pushes adding_all_rt adding_high_fanout_rt total_number_of_adding_all_rt_from_calling_high_fanout_rt logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay 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1859989 2112147 2112147 4945039 4945039 5780530 2113437 360421758 13207701 84063765 43969043 17688722 8739314 288841474 22485005 0 0 299136117 16951437 0 0 2586113 0 39296090 5526339 11631529 13401396 356449 0 33512433 1544317 8548242 10080523 2229664 0 5783657 3982022 3083287 3320873 17945291 2742844 2850651 0 0 8.91222e+08 18492.0 19 38078512 399637966 1074823 8.73801 6.0418 -1.81626e+06 -7.73801 0 0 153.57 381.54 272.06 29175.3 MiB 777.80 278.059 215.231 8816.2 MiB 57.06 808.87 -stratixiv_arch.timing.xml mes_noc_stratixiv_arch_timing.blif common 6471.62 vpr 25.47 GiB 5 23732 0 800 0 8 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 26710708 3 2 577696 547568 17 345328 24545 193 143 27599 LAB auto 6493.3 MiB 1337.23 4158551 7538.4 MiB 2750.62 24.29 10.7673 -2.99929e+06 -9.76734 8.12751 112.10 1.89564 1.40121 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132299 7448 138 102 14076 M9K auto 3124.4 MiB 361.27 1843203 3729.5 MiB 505.05 3.97 13.6282 -1.42833e+06 -12.6282 12.3696 50.06 0.644349 0.534781 86.4109 66.9921 2076657 9.29981 458662 2.05401 567150 2369911 685747206 70807057 202763754 16917738 482983452 53889319 0 0 1835005 1116441 1147500 1147500 2369911 2369911 3387253 1148374 184883772 6503779 61346385 38748407 13675066 6927607 207601853 8020881 0 0 209500461 4824157 0 0 1835005 0 16804169 5627289 7137477 7662675 36186 0 5763151 178811 2508467 2954602 1798819 0 11041018 5448478 4629010 4708073 33298089 574995 1819118 0 0 2.60164e+08 18482.8 16 13627714 134356070 434742 14.4604 12.7726 -2.01567e+06 -13.4604 0 0 45.18 126.43 88.63 12870.3 MiB 342.69 109.661 85.0817 3729.5 MiB 57.17 203.29 -stratixiv_arch.timing.xml denoise_stratixiv_arch_timing.blif common 3386.06 vpr 15.39 GiB 852 14019 24 359 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 16136952 264 588 355537 274786 1 218653 15254 150 111 16650 LAB auto 4459.3 MiB 380.87 2384441 5214.9 MiB 1991.11 13.14 866.15 -905542 -865.15 866.15 61.06 0.84408 0.663993 125.378 100.138 2939707 8.27711 672019 1.89215 896719 3952994 1690209678 202163016 369129761 38925753 1321079917 163237263 0 0 3482593 2087883 2508368 2508368 3952994 3952994 9621647 2508390 329988286 11320811 154630856 123433638 31705888 21564065 571248737 23432070 0 0 583070309 11354797 0 0 3482593 0 22494167 12708035 11642131 16101234 53223 0 12981794 248041 1468023 1793877 3429370 0 9512373 12459994 10174108 14307357 52995204 528680 126615 0 0 3.08278e+08 18515.2 31 19022578 225983404 609035 857.294 857.294 -1.11238e+06 -856.294 0 0 54.29 180.53 120.80 15758.7 MiB 558.32 177.908 141.816 5214.9 MiB 56.94 239.70 -stratixiv_arch.timing.xml sparcT2_core_stratixiv_arch_timing.blif common 3194.16 vpr 14.24 GiB 451 14776 0 260 0 0 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59.04 251.74 -stratixiv_arch.timing.xml cholesky_bdti_stratixiv_arch_timing.blif common 2136.59 vpr 12.36 GiB 162 9702 132 600 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 12957132 94 68 331744 255478 1 158396 10596 169 125 21125 DSP auto 3884.0 MiB 292.17 1975401 4880.6 MiB 652.19 4.49 8.18961 -504572 -7.18961 8.18961 91.72 0.697657 0.552861 95.7834 76.5961 2385404 7.19058 487974 1.47095 713139 2319202 1412977668 208625607 171038805 17137910 1241938863 191487697 0 0 1478991 1213578 1170852 1170852 2319202 2319202 57397420 1171614 155839497 6516140 82279984 50332542 11401115 7088990 539121011 75644667 0 0 561969596 63168022 0 0 1478991 0 17970281 3334914 43042259 44236526 35944 0 13838642 212729 3245047 4169103 1443047 0 4131639 3122185 39797212 40067423 87613308 879323 2433756 0 0 3.91827e+08 18548.0 19 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137832 1 108244 7851 136 101 13736 M9K auto 2760.2 MiB 187.06 1279687 3472.1 MiB 721.35 5.14 856.697 -406064 -855.697 856.697 62.88 0.413169 0.328459 57.8319 46.4413 1581495 8.88381 357343 2.00732 469994 2012740 918190047 110156542 183883630 20920172 734306417 89236370 0 0 1765038 1110908 1324496 1324496 2012740 2012740 5238689 1324498 163063855 5794461 82722471 66716833 17041997 12002063 319069934 13550740 0 0 325950827 6319803 0 0 1765038 0 7708189 6591180 6354690 8409988 23750 0 2882150 111552 768372 1072316 1741288 0 4826039 6479628 5586318 7337672 27574703 274554 57567 0 0 2.53781e+08 18475.6 22 11125774 130624270 323446 844.133 844.133 -509147 -843.133 0 0 44.45 101.98 67.75 10235.9 MiB 324.29 76.1268 60.7587 3472.1 MiB 58.14 220.83 -stratixiv_arch.timing.xml SLAM_spheric_stratixiv_arch_timing.blif common 1055.24 vpr 7.14 GiB 479 5392 37 0 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 7486916 323 156 140638 111354 1 78035 5908 95 70 6650 LAB auto 2418.7 MiB 181.69 1272870 2669.9 MiB 380.42 2.89 80.8958 -380766 -79.8958 80.8958 28.09 0.397817 0.317101 47.8171 38.2688 1639597 11.6584 365223 2.59694 387658 1727675 958973284 123023683 165625353 17132720 793347931 105890963 0 0 1647234 1041459 1153972 1153972 1727675 1727675 11388600 1154537 147510838 5157336 72956456 51792472 14739606 9206250 347328302 30144905 0 0 360520601 21645077 0 0 1647234 0 4683576 5792071 4071668 4645641 8990 0 381570 48797 405683 475090 1638244 0 4302006 5743274 3665985 4170551 20811706 90281 48161 0 0 1.22432e+08 18410.9 18 7487536 88623167 261548 79.2171 79.2171 -425511 -78.2171 0 0 22.40 62.73 40.39 7311.4 MiB 308.85 62.1176 49.8421 2669.9 MiB 58.96 90.23 -stratixiv_arch.timing.xml des90_stratixiv_arch_timing.blif common 1653.93 vpr 13.60 GiB 117 4207 44 860 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 14261028 85 32 138853 110549 1 88003 5228 171 127 21717 M9K auto 2429.6 MiB 255.07 1541525 4136.4 MiB 367.55 2.19 11.5531 -759207 -10.5531 11.5531 86.68 0.530869 0.431548 67.6126 55.027 1956239 14.0889 400545 2.88473 348846 1787109 892003983 130567618 137994707 13126540 754009276 117441078 0 0 1460674 828478 1091766 1091766 1787109 1787109 18923583 1096483 125020213 4697568 48391949 32660234 9726711 5813385 335929528 44832488 0 0 349672450 37760107 0 0 1460674 0 11590451 4607887 5034960 6117590 88215 0 4840917 403973 1094247 1542414 1372459 0 6749534 4203914 3940713 4575176 24801033 416859 181681 0 0 4.02762e+08 18545.9 41 12310810 125945415 329472 12.0314 12.0314 -985420 -11.0314 0 0 70.35 137.59 100.94 13926.7 MiB 481.38 108.107 88.3466 4136.4 MiB 58.99 341.36 -stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 665.44 vpr 7.54 GiB 77 3116 89 136 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 7909632 42 35 119888 86875 1 50931 3418 129 96 12384 DSP auto 2123.9 MiB 88.32 578596 2972.1 MiB 99.38 0.73 7.6648 -71288.8 -6.66479 5.23262 53.85 0.244985 0.201697 30.2194 24.9407 698653 5.82993 147336 1.22945 245763 605381 306537537 43131023 49902100 4725251 256635437 38405772 0 0 461861 374591 272669 272669 605381 605381 11695838 272711 45340905 1726478 23120628 12770630 3493953 2018801 108435779 13744110 0 0 113110523 11345652 0 0 461861 0 4568572 920925 1141444 1280192 16807 0 3450639 79232 576174 631598 445054 0 1117933 841693 565270 648594 3551848 161026 540692 0 0 2.28642e+08 18462.7 28 7947332 82060090 107128 7.63177 5.94401 -119149 -6.63177 0 0 39.53 57.01 37.30 7724.2 MiB 188.63 42.2786 35.2848 2972.1 MiB 58.28 158.17 -stratixiv_arch.timing.xml sparcT1_core_stratixiv_arch_timing.blif common 720.85 vpr 7.72 GiB 310 4022 1 128 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 8091048 173 137 92814 91975 1 60637 4461 82 61 5002 LAB auto 2089.5 MiB 217.48 919927 2207.4 MiB 176.07 1.34 8.15562 -539804 -7.15562 8.15562 16.09 0.278226 0.214586 32.574 25.3666 1210282 13.0404 272746 2.93876 279280 1369532 448264156 48089301 122127356 9895463 326136800 38193838 0 0 854962 579832 815262 815262 1369532 1369532 2616992 815297 112810317 3861289 33203481 23178729 7092545 4084810 143551591 8249922 0 0 145949474 5134628 0 0 854962 0 9032189 2624185 4434430 5351115 54295 0 6933931 278584 2306965 2941461 800667 0 2098258 2345601 2127465 2409654 10337416 573704 175968 0 0 9.19900e+07 18390.6 24 5919990 63601776 187746 8.87425 8.71884 -745379 -7.87425 0 0 16.38 50.94 33.93 7901.4 MiB 199.71 45.4117 35.5668 2152.3 MiB 57.63 59.70 -stratixiv_arch.timing.xml stereo_vision_stratixiv_arch_timing.blif common 616.23 vpr 7.90 GiB 506 3245 76 113 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 8286920 172 334 127090 94090 3 61836 3940 129 96 12384 DSP auto 2088.3 MiB 70.05 497989 2927.0 MiB 92.92 0.75 7.07383 -50259.1 -6.07383 3.02284 53.99 0.189919 0.14897 23.4671 18.4958 547068 4.30477 119635 0.941385 258999 583672 227772484 26490224 52801978 5029083 174970506 21461141 0 0 492253 403165 282933 282933 583672 583672 2873595 283000 47760468 1646035 26125640 14495761 3965585 2396211 72426663 3741399 0 0 73261675 2658048 0 0 492253 0 3057886 995123 541098 834952 13360 0 1829821 61789 244310 410606 478893 0 1228065 933334 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7.68330 2502738 1.73032 3540846 8425546 5230280446 770743796 814052199 76293585 4416228247 694450211 0 0 6832261 5803406 4656298 4654778 8425546 8425546 11793489 4668072 739324292 23647466 351156924 210288920 59470100 38417167 2006520949 253544269 0 0 2042100587 221294172 0 0 6832261 0 37557217 13722366 15112926 20306445 341 0 32593731 1812 2527357 6110277 6831920 0 4963486 13720554 12585569 14196168 52657539 1597528 1190454 0 0 6.95909e+08 18520.5 202 60042241 534056114 1120652 10.9266 10.9266 -1.25103e+06 -9.92656 0 0 119.78 442.59 287.44 42191.1 MiB 2971.81 1375.62 1148.58 11858.4 MiB 56.16 590.21 -stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 9547.67 vpr 45.45 GiB 373 16564 116 5040 16 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 47653524 178 195 663067 568001 2 410212 22109 430 319 137170 M9K auto 6792.4 MiB 948.02 16810932 18450.6 MiB 2658.95 14.21 22.6056 -3.10526e+06 -21.6056 7.60605 593.18 2.12274 1.66854 385.476 309.964 16888463 25.4708 3045033 4.59244 1636839 6486049 3439670940 550766401 427368328 39925754 3012302612 510840647 0 0 3303437 2515297 2568131 2568131 6486049 6486049 37314224 2568423 393605054 16482098 145552997 82676404 23973788 14442310 1400069466 217153168 0 0 1426797794 205874521 0 0 3303437 0 37892616 6489312 14235108 26716119 47665 0 31437711 218348 5273702 13249458 3255772 0 6454905 6270964 8961406 13466661 27862640 3248932 12723214 0 0 2.57820e+09 18795.7 33 67772006 672299824 1141097 22.7627 9.22097 -5.46162e+06 -21.7627 0 0 441.40 762.67 536.69 46536.6 MiB 2059.54 539.907 439.176 18450.6 MiB 56.90 2633.80 -stratixiv_arch.timing.xml sparcT1_chip2_stratixiv_arch_timing.blif common 8452.38 vpr 27.25 GiB 1891 33591 3 506 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 28575808 815 1076 764693 760412 1423 415666 35991 280 207 57960 io auto 8228.0 MiB 1490.22 6580397 11040.9 MiB 4133.91 26.68 17.1265 -4.05151e+06 -16.1265 4.78347 248.20 2.19403 1.68271 320.898 249.655 7579204 10.0051 1626184 2.14668 2056119 7823138 2340892686 242690690 727239805 57539242 1613652881 185151448 0 0 5093286 3784734 4526166 4526166 7823138 7823138 11536382 4527481 671632022 22638924 216765397 131200417 42691359 23292446 685834044 27122715 0 0 694990892 17774669 0 0 5093286 0 37961210 13597268 22400062 28719851 273923 0 23221346 1319238 12088925 15588601 4819363 0 14739864 12278030 10311137 13131250 59212790 3024907 1225926 0 0 1.07375e+09 18525.7 48 52720921 577029660 1396235 17.7211 5.05106 -4.79057e+06 -16.7211 0 0 186.01 390.96 241.50 27906.1 MiB 1150.79 531.863 421.034 11040.9 MiB 57.29 1034.02 -stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 6393.58 vpr 31.18 GiB 399 31049 112 1175 0 2 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 32689372 85 185 721554 630079 28 402685 32737 220 163 35860 LAB auto 7689.3 MiB 791.49 4799802 9155.5 MiB 3524.08 18.20 10.2578 -557757 -9.25779 5.47664 177.62 2.13502 1.67657 363.178 287.689 5561644 7.71296 1206701 1.67347 1601685 5558724 1693700769 196847560 459331461 37728066 1234369308 159119494 0 0 4173565 2568447 2347075 2347075 5558724 5558724 26399860 2347171 421082474 14565580 183084574 96604128 28516698 15035315 505358103 32989748 0 0 517179696 24831372 0 0 4173565 0 44909898 10725156 10525814 11625526 155330 0 21418238 685189 5518619 6079655 4018235 0 23491660 10039967 5007195 5545871 63826094 1553833 562704 0 0 6.64235e+08 18523.0 32 43538200 493972023 696785 10.8651 5.68062 -804856 -9.86511 0 0 115.72 436.38 301.68 31920.2 MiB 945.50 497.117 397.302 9155.5 MiB 56.19 649.39 From 65d09fb0f0e0981343840cbc1f56c0b36c76b3bf Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 22 May 2023 15:44:57 -0400 Subject: [PATCH 10/51] add verify rr graph for flat_router --- .../vtr_reg_nightly_test2/task_list.txt | 3 +- .../config/config.txt | 30 +++++++++++++++++++ .../config/golden_results.txt | 6 ++++ 3 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt index 1b2bb65f2f2..bbce1041db8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt @@ -1,7 +1,8 @@ regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer regression_tests/vtr_reg_nightly_test2/vtr_func_formal regression_tests/vtr_reg_nightly_test2/vtr_bidir -regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph +regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph +regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/config.txt new file mode 100644 index 00000000000..8200d0b72ba --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/config.txt @@ -0,0 +1,30 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=raygentop.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml +arch_list_add=k6_frac_N10_mem32K_40nm.xml +arch_list_add=k6_N10_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt +parse_file=vpr_parse_second_file.txt + +# How to parse QoR info +qor_parse_file=qor_rr_graph.txt + +# Pass requirements +pass_requirements_file=pass_requirements_verify_rr_graph.txt + +# Script parameters +script_params = -verify_rr_graph --route_chan_width 130 --flat_routing true diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/golden_results.txt new file mode 100644 index 00000000000..923229b832d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/golden_results.txt @@ -0,0 +1,6 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 26.57 vpr 82.09 MiB -1 -1 4.09 45804 3 0.98 -1 -1 40164 -1 -1 112 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84056 236 305 3195 3007 1 1538 660 19 19 361 io auto 44.6 MiB 1.97 12550 82.1 MiB 2.18 0.03 4.23319 -2592.08 -4.23319 4.23319 0.09 0.00734041 0.00664649 0.800573 0.722627 22506 5369 14230 2808527 640885 1.72706e+07 8.96013e+06 2.90560e+06 8048.76 16 4.88723 4.88723 -2997.25 -4.88723 -6.66982 -0.193384 82.1 MiB 1.04 1.20892 1.10479 82.1 MiB 1.24 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 26.32 vpr 82.26 MiB -1 -1 3.75 46008 3 0.93 -1 -1 40016 -1 -1 120 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84232 236 305 3195 3007 1 1534 668 19 19 361 io auto 45.3 MiB 2.86 12092 82.3 MiB 2.03 0.03 4.31218 -2553.6 -4.31218 4.31218 0.07 0.00696218 0.00631702 0.765105 0.691642 19341 4478 11708 2097942 457216 1.72706e+07 9.39128e+06 2.71656e+06 7525.11 12 4.99952 4.99952 -3010.14 -4.99952 0 0 82.3 MiB 0.83 1.12422 1.027 82.3 MiB 1.15 + k6_frac_N10_mem32K_40nm.xml raygentop.v common 26.02 vpr 77.67 MiB -1 -1 4.82 49248 8 1.50 -1 -1 41880 -1 -1 116 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 79536 235 305 2594 2755 1 1443 663 19 19 361 io auto 39.9 MiB 2.23 11448 77.7 MiB 1.82 0.03 4.41088 -2430.87 -4.41088 4.41088 0.08 0.00649293 0.00576414 0.647429 0.579732 18768 3833 11059 1989583 427191 1.72706e+07 9.1757e+06 2.71663e+06 7525.28 11 5.29026 5.29026 -2756.74 -5.29026 -8.67533 -0.17036 77.7 MiB 0.75 0.955384 0.866802 77.7 MiB 1.18 + k6_N10_mem32K_40nm.xml raygentop.v common 25.03 vpr 76.39 MiB -1 -1 4.72 48856 8 1.50 -1 -1 41792 -1 -1 165 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 78228 235 305 2594 2755 1 1461 712 19 19 361 io auto 38.7 MiB 0.95 12269 76.4 MiB 1.85 0.03 4.59709 -2576.68 -4.59709 4.59709 0.09 0.00642268 0.00566871 0.591253 0.53058 18465 7376 21416 6225690 1224003 1.72706e+07 1.18165e+07 2.57233e+06 7125.57 19 4.96959 4.96959 -2849.65 -4.96959 -0.0066982 -0.0066982 76.4 MiB 1.84 0.995979 0.901619 76.4 MiB 1.10 + hard_fpu_arch_timing.xml raygentop.v common 389.64 vpr 322.97 MiB -1 -1 36.07 182560 40 111.52 -1 -1 74952 -1 -1 3776 235 -1 -1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 330724 235 305 20496 20801 1 8995 4316 68 68 4624 clb auto 158.1 MiB 4.44 176765 323.0 MiB 49.61 0.36 22.409 -30564.1 -22.409 22.409 1.35 0.0561504 0.0436831 6.55008 5.20912 249819 53589 173978 17781644 1967620 9.87441e+06 8.65503e+06 1.89440e+07 4096.88 23 25.1849 25.1849 -37219.3 -25.1849 -0.1702 -0.0851 323.0 MiB 8.47 9.92861 8.04481 323.0 MiB 16.99 From 3c023748a1bc6727a0a448a2e54f15fc7da10188 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 22 May 2023 18:46:57 -0400 Subject: [PATCH 11/51] set is_flat_ field to true if intra-cluster lookahead is read from a file --- vpr/src/route/router_lookahead_map.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index ea031a5496a..eb8f64d8861 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -547,6 +547,7 @@ void MapLookahead::read(const std::string& file) { void MapLookahead::read_intra_cluster(const std::string& file) { vtr::ScopedStartFinishTimer timer("Loading router intra cluster lookahead map"); + is_flat_ = true; // Maps related to global resources should not be empty VTR_ASSERT(!f_wire_cost_map.empty()); read_intra_cluster_router_lookahead(inter_tile_pin_primitive_pin_delay, From 35fa1c1740d6af0460ccd01e502d507fb95e743d Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 22 May 2023 19:09:37 -0400 Subject: [PATCH 12/51] add support to verify router lookahead --- vtr_flow/scripts/python_libs/vtr/flow.py | 6 ++++- vtr_flow/scripts/python_libs/vtr/vpr/vpr.py | 28 +++++++++++++++++++++ vtr_flow/scripts/run_vtr_flow.py | 17 +++++++++++++ 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/vtr_flow/scripts/python_libs/vtr/flow.py b/vtr_flow/scripts/python_libs/vtr/flow.py index 060a5dab886..a233e10cef0 100644 --- a/vtr_flow/scripts/python_libs/vtr/flow.py +++ b/vtr_flow/scripts/python_libs/vtr/flow.py @@ -291,7 +291,11 @@ def run( do_second_run = False second_run_args = vpr_args - if "write_rr_graph" in vpr_args or "analysis" in vpr_args or "route" in vpr_args: + if ("write_rr_graph" in vpr_args or + "analysis" in vpr_args or + "route" in vpr_args or + "write_router_lookahead" in vpr_args or + "write_intra_cluster_router_lookahead" in vpr_args): do_second_run = True vtr.vpr.run( diff --git a/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py b/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py index b7509c1e700..4cd08827218 100644 --- a/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py +++ b/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py @@ -282,6 +282,18 @@ def run_second_time( second_run_args["read_rr_graph"] = rr_graph_out_file second_run_args["write_rr_graph"] = rr_graph_out_file2 + inter_cluster_router_lookahead = "" + if "write_router_lookahead" in second_run_args: + inter_cluster_router_lookahead = second_run_args["write_router_lookahead"] + second_run_args["read_router_lookahead"] = inter_cluster_router_lookahead + second_run_args["write_router_lookahead"] = "inter_cluster_router_lookahead2.capnp" + + intra_cluster_router_lookahead = "" + if "write_intra_cluster_router_lookahead" in second_run_args: + intra_cluster_router_lookahead = second_run_args["write_intra_cluster_router_lookahead"] + second_run_args["read_intra_cluster_router_lookahead"] = intra_cluster_router_lookahead + second_run_args["write_intra_cluster_router_lookahead"] = "intra_cluster_router_lookahead2.capnp" + # run VPR run( architecture, @@ -302,6 +314,22 @@ def run_second_time( if diff_result: raise InspectError("failed: vpr (RR Graph XML output not consistent when reloaded)") + if "write_inter_cluster_router_lookahead" in second_run_args: + cmd = ["diff", inter_cluster_router_lookahead, "inter_cluster_router_lookahead2.capnp"] + _, diff_result = command_runner.run_system_command( + cmd, temp_dir, log_filename="diff.inter_cluster_router_lookahead.out", indent_depth=1 + ) + if diff_result: + raise InspectError("failed: vpr (Inter Cluster Router Lookahead output not consistent when reloaded)") + + if "write_intra_cluster_router_lookahead" in second_run_args: + cmd = ["diff", intra_cluster_router_lookahead, "intra_cluster_router_lookahead2.capnp"] + _, diff_result = command_runner.run_system_command( + cmd, temp_dir, log_filename="diff.intra_cluster_router_lookahead.out", indent_depth=1 + ) + if diff_result: + raise InspectError("failed: vpr (Intra Cluster Router Lookahead not consistent when reloaded)") + def cmp_full_vs_incr_sta( architecture, diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py index fd65d4467e7..4165311d77e 100755 --- a/vtr_flow/scripts/run_vtr_flow.py +++ b/vtr_flow/scripts/run_vtr_flow.py @@ -416,6 +416,18 @@ def vtr_command_argparser(prog=None): action="store_true", help="Do a second-run of the incremental analysis to compare the result files", ) + vpr.add_argument( + "-verify_inter_cluster_router_lookahead", + default=False, + action="store_true", + help="Tells VPR to verify the router lookahead.", + ) + vpr.add_argument( + "-verify_intra_cluster_router_lookahead", + default=False, + action="store_true", + help="Tells VPR to verify the router lookahead.", + ) return parser @@ -712,6 +724,11 @@ def process_vpr_args(args, prog, temp_dir, vpr_args): if args.verify_rr_graph: rr_graph_out_file = "rr_graph" + args.rr_graph_ext vpr_args["write_rr_graph"] = rr_graph_out_file + if args.verify_inter_cluster_router_lookahead: + vpr_args["write_router_lookahead"] = "inter_cluster_router_lookahead.capnp" + if args.verify_intra_cluster_router_lookahead: + assert "flat_routing" in vpr_args, "Flat router should be enabled if intra cluster router lookahead is to be verified" + vpr_args["write_intra_cluster_router_lookahead"] = "intra_cluster_router_lookahead.capnp" return vpr_args From a291db31006decde79c69deeb006d461e3734a06 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 24 May 2023 10:51:32 -0400 Subject: [PATCH 13/51] remove the previous function in the file - implement fromVector and FromUnorderedMap functions instead --- libs/libvtrcapnproto/intra_cluster_serdes.h | 214 +++----------------- 1 file changed, 24 insertions(+), 190 deletions(-) diff --git a/libs/libvtrcapnproto/intra_cluster_serdes.h b/libs/libvtrcapnproto/intra_cluster_serdes.h index e60ebb443e8..fc912ae2621 100644 --- a/libs/libvtrcapnproto/intra_cluster_serdes.h +++ b/libs/libvtrcapnproto/intra_cluster_serdes.h @@ -16,201 +16,35 @@ #include "vpr_types.h" #include "router_lookahead_map_utils.h" +template +void fromVector(typename capnp::List::Builder& m_out, + const std::vector& vec_in, + const std::function::Builder&, + int, + const ElemType&)>& copy_fun) { -void ToIntraClusterLookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, - std::unordered_map>& tile_min_cost, - const std::vector& physical_tile_types, - const VprIntraClusterLookahead::Reader& intra_cluster_lookahead_builder); - -void FromIntraClusterLookahead(VprIntraClusterLookahead::Builder& intra_cluster_lookahead_builder, - const std::unordered_map& inter_tile_pin_primitive_pin_delay, - const std::unordered_map>& tile_min_cost, - const std::vector& physical_tile_types); -// Generic function to convert from Matrix capnproto message to vtr::NdMatrix. -// -// Template arguments: -// N = Number of matrix dimensions, must be fixed. -// CapType = Source capnproto message type that is a single element the -// Matrix capnproto message. -// CType = Target C++ type that is a single element of vtr::NdMatrix. -// -// Arguments: -// m_out = Target vtr::NdMatrix. -// m_in = Source capnproto message reader. -// copy_fun = Function to convert from CapType to CType. -void ToIntraClusterLookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, - std::unordered_map>& tile_min_cost, - const std::vector& physical_tile_types, - const VprIntraClusterLookahead::Reader& intra_cluster_lookahead_builder) { - - inter_tile_pin_primitive_pin_delay.clear(); - tile_min_cost.clear(); - - int num_tile_types = intra_cluster_lookahead_builder.getPhysicalTileNumPins().size(); - VTR_ASSERT(num_tile_types == (int)physical_tile_types.size()); - - std::vector tile_num_pins(num_tile_types); - std::vector tile_num_sinks(num_tile_types); - - for (int tile_idx = 0; tile_idx < num_tile_types; tile_idx++) { - tile_num_pins[tile_idx] = intra_cluster_lookahead_builder.getPhysicalTileNumPins()[tile_idx]; - tile_num_sinks[tile_idx] = intra_cluster_lookahead_builder.getTileNumSinks()[tile_idx]; + for(int idx = 0; idx < (int)vec_in.size(); idx++) { + copy_fun(m_out, idx, vec_in[idx]); } - - int num_seen_sinks = 0; - int num_seen_pins = 0; - for(int tile_type_idx = 0; tile_type_idx < num_tile_types; tile_type_idx++) { - int cur_tile_num_pins = tile_num_pins[tile_type_idx]; - t_physical_tile_type_ptr physical_type_ptr = &physical_tile_types[tile_type_idx]; - inter_tile_pin_primitive_pin_delay[physical_type_ptr] = util::t_ipin_primitive_sink_delays(cur_tile_num_pins); - for(int pin_num = 0; pin_num < cur_tile_num_pins; pin_num++) { - inter_tile_pin_primitive_pin_delay[physical_type_ptr][pin_num].clear(); - int pin_num_sinks = intra_cluster_lookahead_builder.getPinNumSinks()[num_seen_pins]; - num_seen_pins++; - for(int sink_idx = 0; sink_idx < pin_num_sinks; sink_idx++) { - int sink_pin_num = intra_cluster_lookahead_builder.getPinSinks()[num_seen_sinks]; - auto cost = intra_cluster_lookahead_builder.getPinSinkCosts()[num_seen_sinks]; - inter_tile_pin_primitive_pin_delay[physical_type_ptr][pin_num].insert(std::make_pair(sink_pin_num, - util::Cost_Entry(cost.getDelay(), cost.getCongestion()))); - num_seen_sinks++; - } - - - } - } - - num_seen_sinks = 0; - for(int tile_type_idx = 0; tile_type_idx < num_tile_types; tile_type_idx++) { - int cur_tile_num_sinks = tile_num_sinks[tile_type_idx]; - t_physical_tile_type_ptr physical_type_ptr = &physical_tile_types[tile_type_idx]; - tile_min_cost[physical_type_ptr] = std::unordered_map(); - for(int sink_idx = 0; sink_idx < cur_tile_num_sinks; sink_idx++) { - int sink_num = intra_cluster_lookahead_builder.getTileSinks()[num_seen_sinks]; - auto cost = intra_cluster_lookahead_builder.getTileMinCosts()[num_seen_sinks]; - tile_min_cost[physical_type_ptr].insert(std::make_pair(sink_num, - util::Cost_Entry(cost.getDelay(), cost.getCongestion()))); - num_seen_sinks++; - - } - } - - } -void FromIntraClusterLookahead(VprIntraClusterLookahead::Builder& intra_cluster_lookahead_builder, - const std::unordered_map& inter_tile_pin_primitive_pin_delay, - const std::unordered_map>& tile_min_cost, - const std::vector& physical_tile_types) { - - ::capnp::List::Builder physical_tile_num_pin_arr_builder; - ::capnp::List::Builder pin_num_sink_arr_builder; - ::capnp::List::Builder pin_sink_arr_builder; - ::capnp::List::Builder pin_sink_cost_builder; - ::capnp::List::Builder tile_num_sinks_builder; - ::capnp::List::Builder tile_sinks_builder; - ::capnp::List::Builder tile_sink_min_cost_builder; - - int num_tile_types = physical_tile_types.size(); - - physical_tile_num_pin_arr_builder = intra_cluster_lookahead_builder.initPhysicalTileNumPins(num_tile_types); - - // Count the number of pins for each tile - { - int total_num_pin = 0; - for (const auto& tile_type : physical_tile_types) { - const auto tile_pin_primitive_delay = inter_tile_pin_primitive_pin_delay.find(&tile_type); - if (tile_pin_primitive_delay == inter_tile_pin_primitive_pin_delay.end()) { - physical_tile_num_pin_arr_builder.set(tile_type.index, 0); - continue; - } - int tile_num_pins = tile_pin_primitive_delay->second.size(); - physical_tile_num_pin_arr_builder.set(tile_type.index, tile_num_pins); - total_num_pin += tile_num_pins; - } - - pin_num_sink_arr_builder = intra_cluster_lookahead_builder.initPinNumSinks(total_num_pin); - } - - // Count the number of sinks for each pin - { - int pin_num = 0; - int total_pin_num_sinks = 0; - for (const auto& tile_type : physical_tile_types) { - const auto tile_pin_primitive_delay = inter_tile_pin_primitive_pin_delay.find(&tile_type); - if (tile_pin_primitive_delay == inter_tile_pin_primitive_pin_delay.end()) { - continue; - } - for (const auto& pin : tile_pin_primitive_delay->second) { - int pin_num_sinks = pin.size(); - pin_num_sink_arr_builder.set(pin_num, pin_num_sinks); - pin_num++; - total_pin_num_sinks += pin_num_sinks; - } +template +void FromUnorderedMap( + typename capnp::List::Builder& m_out_key, + typename capnp::List::Builder& m_out_val, + const KeyType out_offset, + const std::unordered_map& map_in, + const std::function::Builder&, + typename capnp::List::Builder&, + int, + const KeyType&, + const CostType&)>& copy_fun) { + + int flat_idx = out_offset; + for (const auto& entry : map_in) { + copy_fun(m_out_key, m_out_val, flat_idx, entry.first, entry.second); + flat_idx++; } - - pin_sink_arr_builder = intra_cluster_lookahead_builder.initPinSinks(total_pin_num_sinks); - pin_sink_cost_builder = intra_cluster_lookahead_builder.initPinSinkCosts(total_pin_num_sinks); - } - - // Iterate over sinks of each pin and store the cost of getting to the sink from the respective pin and the sink ptc number - { - int pin_flat_sink_idx = 0; - for (const auto& tile_type : physical_tile_types) { - const auto tile_pin_primitive_delay = inter_tile_pin_primitive_pin_delay.find(&tile_type); - if (tile_pin_primitive_delay == inter_tile_pin_primitive_pin_delay.end()) { - continue; - } - for (const auto& pin : tile_pin_primitive_delay->second) { - for (const auto& sink : pin) { - pin_sink_arr_builder.set(pin_flat_sink_idx, sink.first); - pin_sink_cost_builder[pin_flat_sink_idx].setDelay(sink.second.delay); - pin_sink_cost_builder[pin_flat_sink_idx].setCongestion(sink.second.congestion); - pin_flat_sink_idx++; - } - } - } - } - - - // Store the information related to tile_min cost - - tile_num_sinks_builder = intra_cluster_lookahead_builder.initTileNumSinks(num_tile_types); - - // Count the number of sinks for each tile - { - int tile_total_num_sinks = 0; - for (const auto& tile_type : physical_tile_types) { - const auto tile_min_cost_entry = tile_min_cost.find(&tile_type); - if (tile_min_cost_entry == tile_min_cost.end()) { - tile_num_sinks_builder.set(tile_type.index, 0); - continue; - } - int tile_num_sinks = (int)tile_min_cost_entry->second.size(); - tile_num_sinks_builder.set(tile_type.index, tile_num_sinks); - tile_total_num_sinks += tile_num_sinks; - } - - tile_sinks_builder = intra_cluster_lookahead_builder.initTileSinks(tile_total_num_sinks); - tile_sink_min_cost_builder = intra_cluster_lookahead_builder.initTileMinCosts(tile_total_num_sinks); - } - - // Iterate over sinks of each tile and store the minimum cost to get to that sink and the sink ptc number - { - int pin_flat_sink_idx = 0; - for (const auto& tile_type : physical_tile_types) { - const auto tile_min_cost_entry = tile_min_cost.find(&tile_type); - if (tile_min_cost_entry == tile_min_cost.end()) { - continue; - } - for (const auto& sink : tile_min_cost_entry->second) { - tile_sinks_builder.set(pin_flat_sink_idx, sink.first); - tile_sink_min_cost_builder[pin_flat_sink_idx].setDelay(sink.second.delay); - tile_sink_min_cost_builder[pin_flat_sink_idx].setCongestion(sink.second.congestion); - pin_flat_sink_idx++; - } - } - } - } From f9db2fd8939db4beeada091179d9f9577edd984b Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 24 May 2023 10:52:04 -0400 Subject: [PATCH 14/51] remove the fields related to tile sink --- libs/libvtrcapnproto/map_lookahead.capnp | 3 --- 1 file changed, 3 deletions(-) diff --git a/libs/libvtrcapnproto/map_lookahead.capnp b/libs/libvtrcapnproto/map_lookahead.capnp index 6dd777d1c3e..1c7eaed3e14 100644 --- a/libs/libvtrcapnproto/map_lookahead.capnp +++ b/libs/libvtrcapnproto/map_lookahead.capnp @@ -15,7 +15,4 @@ struct VprIntraClusterLookahead { pinNumSinks @1 :List(Int64); pinSinks @2 :List(Int64); pinSinkCosts @3 :List(VprMapCostEntry); - tileNumSinks @4 :List(Int64); - tileSinks @5 :List(Int64); - tileMinCosts @6 :List(VprMapCostEntry); } \ No newline at end of file From a953883aa5b6c7fd2b770393f013d69067abfd0e Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 24 May 2023 10:52:53 -0400 Subject: [PATCH 15/51] fix the writing functions based on the new changes - only write inter_tile_pin_primitive_pin_delay - change t_physical_type_ptr to int --- vpr/src/route/router_lookahead_map.cpp | 209 ++++++++++++++++++------- vpr/src/route/router_lookahead_map.h | 4 +- 2 files changed, 151 insertions(+), 62 deletions(-) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index eb8f64d8861..130b459f88e 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -207,33 +207,32 @@ t_wire_cost_map f_wire_cost_map; /******** File-Scope Functions ********/ Cost_Entry get_wire_cost_entry(e_rr_type rr_type, int seg_index, int delta_x, int delta_y); static void compute_router_wire_lookahead(const std::vector& segment_inf); -static void compute_tiles_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, - std::unordered_map>& tile_min_cost, +static void compute_tiles_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, + std::unordered_map>& tile_min_cost, const t_det_routing_arch& det_routing_arch, const DeviceContext& device_ctx); -static void compute_tile_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, +static void compute_tile_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, t_physical_tile_type_ptr physical_tile, const t_det_routing_arch& det_routing_arch, const int delayless_switch); -static void store_min_cost_to_sinks(std::unordered_map>& tile_min_cost, +static void store_min_cost_to_sinks(std::unordered_map>& tile_min_cost, t_physical_tile_type_ptr physical_tile, - const std::unordered_map& inter_tile_pin_primitive_pin_delay); + const std::unordered_map& inter_tile_pin_primitive_pin_delay); static void min_global_cost_map(vtr::NdMatrix& internal_opin_global_cost_map, size_t max_dx, size_t max_dy); // Read the file and fill inter_tile_pin_primitive_pin_delay and tile_min_cost -static void read_intra_cluster_router_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, - std::unordered_map>& tile_min_cost, +static void read_intra_cluster_router_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, + std::unordered_map>& tile_min_cost, const std::string& file); // Write the file with inter_tile_pin_primitive_pin_delay and tile_min_cost static void write_intra_cluster_router_lookahead(const std::string& file, - const std::unordered_map& inter_tile_pin_primitive_pin_delay, - const std::unordered_map>& tile_min_cost); + const std::unordered_map& inter_tile_pin_primitive_pin_delay); /* returns index of a node from which to start routing */ static RRNodeId get_start_node(int start_x, int start_y, int target_x, int target_y, t_rr_type rr_type, int seg_index, int track_offset); @@ -290,8 +289,8 @@ float MapLookahead::get_expected_cost(RRNodeId current_node, RRNodeId target_nod // delay_cost and cong_cost only represent the cost to get to the root-level pins. The below offsets are used to represent the intra-cluster cost // of getting to a sink - delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type).at(to_node_ptc_num).delay; - cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type).at(to_node_ptc_num).congestion; + delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).delay; + cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion; return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; } else if (from_rr_type == OPIN) { @@ -301,21 +300,21 @@ float MapLookahead::get_expected_cost(RRNodeId current_node, RRNodeId target_nod // Similar to CHANX and CHANY std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream); - delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type).at(to_node_ptc_num).delay; - cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type).at(to_node_ptc_num).congestion; + delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).delay; + cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion; return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; } else { if (node_in_same_physical_tile(current_node, target_node)) { delay_offset_cost = 0.; cong_offset_cost = 0.; - const auto& pin_delays = inter_tile_pin_primitive_pin_delay.at(from_physical_type)[from_node_ptc_num]; + const auto& pin_delays = inter_tile_pin_primitive_pin_delay.at(from_physical_type->index)[from_node_ptc_num]; auto pin_delay_itr = pin_delays.find(rr_graph.node_ptc_num(target_node)); if (pin_delay_itr == pin_delays.end()) { // There isn't any intra-cluster path to connect the current OPIN to the SINK, thus it has to outside. // The best estimation we have now, it the minimum intra-cluster delay to the sink. However, this cost is incomplete, // since it does not consider the cost of going outside of the cluster and, then, returning to it. - delay_cost = params.criticality * tile_min_cost.at(to_physical_type).at(to_node_ptc_num).delay; - cong_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type).at(to_node_ptc_num).congestion; + delay_cost = params.criticality * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).delay; + cong_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion; return delay_cost + cong_cost; } else { delay_cost = params.criticality * pin_delay_itr->second.delay; @@ -332,15 +331,15 @@ float MapLookahead::get_expected_cost(RRNodeId current_node, RRNodeId target_nod delay_cost = params.criticality * distance_based_min_cost[delta_x][delta_y].delay; cong_cost = (1. - params.criticality) * distance_based_min_cost[delta_x][delta_y].congestion; - delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type).at(to_node_ptc_num).delay; - cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type).at(to_node_ptc_num).congestion; + delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).delay; + cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion; } return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; } } else if (from_rr_type == IPIN) { // we assume that route-through is not enabled. VTR_ASSERT(node_in_same_physical_tile(current_node, target_node)); - const auto& pin_delays = inter_tile_pin_primitive_pin_delay.at(from_physical_type)[from_node_ptc_num]; + const auto& pin_delays = inter_tile_pin_primitive_pin_delay.at(from_physical_type->index)[from_node_ptc_num]; auto pin_delay_itr = pin_delays.find(rr_graph.node_ptc_num(target_node)); if (pin_delay_itr == pin_delays.end()) { delay_cost = std::numeric_limits::max() / 1e12; @@ -364,8 +363,8 @@ float MapLookahead::get_expected_cost(RRNodeId current_node, RRNodeId target_nod delay_cost = params.criticality * distance_based_min_cost[delta_x][delta_y].delay; cong_cost = (1. - params.criticality) * distance_based_min_cost[delta_x][delta_y].congestion; - delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type).at(to_node_ptc_num).delay; - cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type).at(to_node_ptc_num).congestion; + delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).delay; + cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion; } return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; } else { @@ -566,8 +565,7 @@ void MapLookahead::write(const std::string& file) const { void MapLookahead::write_intra_cluster(const std::string& file) const { write_intra_cluster_router_lookahead(file, - inter_tile_pin_primitive_pin_delay, - tile_min_cost); + inter_tile_pin_primitive_pin_delay); } /******** Function Definitions ********/ @@ -1310,8 +1308,8 @@ static void print_router_cost_map(const t_routing_cost_map& router_cost_map) { } } -static void compute_tiles_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, - std::unordered_map>& tile_min_cost, +static void compute_tiles_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, + std::unordered_map>& tile_min_cost, const t_det_routing_arch& det_routing_arch, const DeviceContext& device_ctx) { const auto& tiles = device_ctx.physical_tile_types; @@ -1331,7 +1329,7 @@ static void compute_tiles_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, +static void compute_tile_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, t_physical_tile_type_ptr physical_tile, const t_det_routing_arch& det_routing_arch, const int delayless_switch) { @@ -1359,16 +1357,16 @@ static void compute_tile_lookahead(std::unordered_mapindex, pin_delays)); VTR_ASSERT(insert_res.second); rr_graph_builder.clear(); } -static void store_min_cost_to_sinks(std::unordered_map>& tile_min_cost, +static void store_min_cost_to_sinks(std::unordered_map>& tile_min_cost, t_physical_tile_type_ptr physical_tile, - const std::unordered_map& inter_tile_pin_primitive_pin_delay) { - const auto& tile_pin_delays = inter_tile_pin_primitive_pin_delay.at(physical_tile); + const std::unordered_map& inter_tile_pin_primitive_pin_delay) { + const auto& tile_pin_delays = inter_tile_pin_primitive_pin_delay.at(physical_tile->index); std::unordered_map min_cost_map; for (auto& primitive_sink_pair : physical_tile->primitive_class_inf) { int primitive_sink = primitive_sink_pair.first; @@ -1391,7 +1389,7 @@ static void store_min_cost_to_sinks(std::unordered_mapindex, min_cost_map)); VTR_ASSERT(insert_res.second); } @@ -1443,53 +1441,144 @@ static void read_intra_cluster_router_lookahead(std::unordered_map& /*inter_tile_pin_primitive_pin_delay*/, - const std::unordered_map>& /*tile_min_cost*/) { + const std::unordered_map& /*inter_tile_pin_primitive_pin_delay*/) { VPR_THROW(VPR_ERROR_PLACE, "MapLookahead::write_intra_cluster_router_lookahead " DISABLE_ERROR); } #else /* VTR_ENABLE_CAPNPROTO */ -static void read_intra_cluster_router_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, - std::unordered_map>& tile_min_cost, - const std::string& file) { - MmapFile f(file); +static void ToCostEntry(Cost_Entry* out, const VprMapCostEntry::Reader& in) { + out->delay = in.getDelay(); + out->congestion = in.getCongestion(); +} - /* Increase reader limit to 1G words to allow for large files. */ - ::capnp::ReaderOptions opts = default_large_capnp_opts(); - ::capnp::FlatArrayMessageReader reader(f.getData(), opts); +static void FromCostEntry(VprMapCostEntry::Builder* out, const Cost_Entry& in) { + out->setDelay(in.delay); + out->setCongestion(in.congestion); +} - auto map = reader.getRoot(); +static void fromIntEntry(::capnp::List::Builder& out, + int idx, + const int& cost) { + out.set(idx, cost); +} - ToIntraClusterLookahead(inter_tile_pin_primitive_pin_delay, - tile_min_cost, - g_vpr_ctx.device().physical_tile_types, - map); +static void fromPairEntry(::capnp::List::Builder& out_key, + ::capnp::List<::VprMapCostEntry, ::capnp::Kind::STRUCT>::Builder& out_val, + int flat_idx, + const int& key, + const util::Cost_Entry& cost) { + out_key.set(flat_idx, key); + out_val[flat_idx].setDelay(cost.delay); + out_val[flat_idx].setCongestion(cost.congestion); +} + +static void getIntraClusterArrayFlatSize(int& num_tile_types, + int& num_pins, + int& num_sinks, + const std::unordered_map& inter_tile_pin_primitive_pin_delay) { + num_tile_types = inter_tile_pin_primitive_pin_delay.size(); + + num_pins = 0; + for(const auto& tile_type : inter_tile_pin_primitive_pin_delay) { + num_pins += (int)tile_type.second.size(); + } + + num_sinks = 0; + for(const auto& tile_type : inter_tile_pin_primitive_pin_delay) { + for(const auto& pin_sink: tile_type.second) { + num_sinks += (int)pin_sink.size(); + } + } + + +} + +static void read_intra_cluster_router_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, + std::unordered_map>& tile_min_cost, + const std::string& file) { +// MmapFile f(file); +// +// /* Increase reader limit to 1G words to allow for large files. */ +// ::capnp::ReaderOptions opts = default_large_capnp_opts(); +// ::capnp::FlatArrayMessageReader reader(f.getData(), opts); +// +// auto map = reader.getRoot(); +// +// ToIntraClusterLookahead(inter_tile_pin_primitive_pin_delay, +// tile_min_cost, +// g_vpr_ctx.device().physical_tile_types, +// map); } static void write_intra_cluster_router_lookahead(const std::string& file, - const std::unordered_map& inter_tile_pin_primitive_pin_delay, - const std::unordered_map>& tile_min_cost) { + const std::unordered_map& inter_tile_pin_primitive_pin_delay) { ::capnp::MallocMessageBuilder builder; auto vpr_intra_cluster_lookahead_builder = builder.initRoot(); - FromIntraClusterLookahead(vpr_intra_cluster_lookahead_builder, - inter_tile_pin_primitive_pin_delay, - tile_min_cost, - g_vpr_ctx.device().physical_tile_types); + int num_tile_types, num_pins, num_sinks; + getIntraClusterArrayFlatSize(num_tile_types, + num_pins, + num_sinks, + inter_tile_pin_primitive_pin_delay); + + std::vector physical_tile_num_pin_arr(num_tile_types, 0); + { + for (const auto& physical_type : inter_tile_pin_primitive_pin_delay) { + int physical_type_idx = physical_type.first; + physical_tile_num_pin_arr[physical_type_idx] = (int)physical_type.second.size(); + } - writeMessageToFile(file, &builder); -} + ::capnp::List::Builder physical_tile_num_pin_arr_builder = + vpr_intra_cluster_lookahead_builder.initPhysicalTileNumPins(num_tile_types); + fromVector(physical_tile_num_pin_arr_builder, + physical_tile_num_pin_arr, + fromIntEntry); + } -static void ToCostEntry(Cost_Entry* out, const VprMapCostEntry::Reader& in) { - out->delay = in.getDelay(); - out->congestion = in.getCongestion(); -} + std::vector pin_num_sink_arr(num_pins, 0); + { + int num_seen_pin = 0; + for(int physical_tile_idx = 0; physical_tile_idx < num_tile_types; ++physical_tile_idx) { + if(inter_tile_pin_primitive_pin_delay.find(physical_tile_idx) == inter_tile_pin_primitive_pin_delay.end()) { + continue; + } + for(const auto& pin_sinks : inter_tile_pin_primitive_pin_delay.at(physical_tile_idx)) { + pin_num_sink_arr[num_seen_pin] = (int)pin_sinks.size(); + ++num_seen_pin; + } + } + ::capnp::List::Builder pin_num_sink_arr_builder = + vpr_intra_cluster_lookahead_builder.initPinNumSinks(num_pins); + fromVector(pin_num_sink_arr_builder, + pin_num_sink_arr, + fromIntEntry); + } -static void FromCostEntry(VprMapCostEntry::Builder* out, const Cost_Entry& in) { - out->setDelay(in.delay); - out->setCongestion(in.congestion); + { + ::capnp::List::Builder pin_sink_arr_builder = + vpr_intra_cluster_lookahead_builder.initPinSinks(num_sinks); + ::capnp::List::Builder pin_sink_cost_builder = + vpr_intra_cluster_lookahead_builder.initPinSinkCosts(num_sinks); + + int num_seen_pin = 0; + for(int physical_tile_idx = 0; physical_tile_idx < num_tile_types; ++physical_tile_idx) { + for(int pin_num = 0; pin_num < physical_tile_num_pin_arr[physical_tile_idx]; ++pin_num) { + const std::unordered_map& pin_sinks = inter_tile_pin_primitive_pin_delay.at(physical_tile_idx).at(pin_num); + FromUnorderedMap( + pin_sink_arr_builder, + pin_sink_cost_builder, + num_seen_pin, + pin_sinks, + fromPairEntry); + num_seen_pin += (int)pin_sinks.size(); + } + } + } + + + writeMessageToFile(file, &builder); } void read_router_lookahead(const std::string& file) { diff --git a/vpr/src/route/router_lookahead_map.h b/vpr/src/route/router_lookahead_map.h index 6ccd88aa621..3b2a3badd90 100644 --- a/vpr/src/route/router_lookahead_map.h +++ b/vpr/src/route/router_lookahead_map.h @@ -16,9 +16,9 @@ class MapLookahead : public RouterLookahead { //Look-up table from SOURCE/OPIN to CHANX/CHANY of various types util::t_src_opin_delays src_opin_delays; // Lookup table from a tile pins to the primitive classes inside that tile - std::unordered_map inter_tile_pin_primitive_pin_delay; // [physical_tile_type][from_pin_physical_num][sink_physical_num] -> cost + std::unordered_map inter_tile_pin_primitive_pin_delay; // [physical_tile_type][from_pin_physical_num][sink_physical_num] -> cost // Lookup table to store the minimum cost to reach to a primitive pin from the root-level IPINs - std::unordered_map> tile_min_cost; // [physical_tile_type][sink_physical_num] -> cost + std::unordered_map> tile_min_cost; // [physical_tile_type][sink_physical_num] -> cost // Lookup table to store the minimum cost for each dx and dy vtr::NdMatrix distance_based_min_cost; // [dx][dy] -> cost const t_det_routing_arch& det_routing_arch_; From 45af5f1b5260d879b51dfe45c48eb364667d7258 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 24 May 2023 12:04:58 -0400 Subject: [PATCH 16/51] add toUnorderedMap and toVector to intra_cluster_serdes.h --- libs/libvtrcapnproto/intra_cluster_serdes.h | 29 +++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/libs/libvtrcapnproto/intra_cluster_serdes.h b/libs/libvtrcapnproto/intra_cluster_serdes.h index fc912ae2621..f5579fc8cde 100644 --- a/libs/libvtrcapnproto/intra_cluster_serdes.h +++ b/libs/libvtrcapnproto/intra_cluster_serdes.h @@ -16,6 +16,35 @@ #include "vpr_types.h" #include "router_lookahead_map_utils.h" +template +void toVector(std::vector& vec_out, + const typename capnp::List::Reader& m_in, + const std::function&, + int, + const ElemType&)>& copy_fun) { + int size = m_in.size(); + vec_out.resize(size); + for(int idx = 0; idx < size; idx++) { + copy_fun(vec_out, idx, m_in[idx]); + } +} + +template +void toUnorderedMap( + std::unordered_map& map_in, + const int begin_flat_idx, + const int end_flat_idx, + const typename capnp::List::Reader& m_out_key, + const typename capnp::List::Reader& m_out_val, + const std::function&, + const KeyType&, + const typename CapValType::Reader&)>& copy_fun) { + + for(int flat_idx = begin_flat_idx; flat_idx < end_flat_idx; flat_idx++) { + copy_fun(map_in, m_out_key[flat_idx], m_out_val[flat_idx]); + } +} + template void fromVector(typename capnp::List::Builder& m_out, const std::vector& vec_in, From 5cf0c9a5af040e3da14bf45616292c3405620b23 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 24 May 2023 13:55:32 -0400 Subject: [PATCH 17/51] fix the intra cluster lookahead reader functions - Compute the tile min after file is being read --- vpr/src/route/router_lookahead_map.cpp | 78 ++++++++++++++++++++------ 1 file changed, 62 insertions(+), 16 deletions(-) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 130b459f88e..e022bb9b87d 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -227,7 +227,6 @@ static void min_global_cost_map(vtr::NdMatrix& internal_opi // Read the file and fill inter_tile_pin_primitive_pin_delay and tile_min_cost static void read_intra_cluster_router_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, - std::unordered_map>& tile_min_cost, const std::string& file); // Write the file with inter_tile_pin_primitive_pin_delay and tile_min_cost @@ -550,9 +549,18 @@ void MapLookahead::read_intra_cluster(const std::string& file) { // Maps related to global resources should not be empty VTR_ASSERT(!f_wire_cost_map.empty()); read_intra_cluster_router_lookahead(inter_tile_pin_primitive_pin_delay, - tile_min_cost, file); + const auto& tiles = g_vpr_ctx.device().physical_tile_types; + for (const auto& tile : tiles) { + if (is_empty_type(&tile)) { + continue; + } + store_min_cost_to_sinks(tile_min_cost, + &tile, + inter_tile_pin_primitive_pin_delay); + } + // The information about distance_based_min_cost is not stored in the file, thus it needs to be computed min_global_cost_map(distance_based_min_cost, f_wire_cost_map.dim_size(2), @@ -1435,7 +1443,6 @@ void DeltaDelayModel::write(const std::string& /*file*/) const { } static void read_intra_cluster_router_lookahead(std::unordered_map& /*inter_tile_pin_primitive_pin_delay*/, - std::unordered_map>& /*tile_min_cost*/, const std::string& /*file*/) { VPR_THROW(VPR_ERROR_PLACE, "MapLookahead::read_intra_cluster_router_lookahead " DISABLE_ERROR); } @@ -1457,12 +1464,27 @@ static void FromCostEntry(VprMapCostEntry::Builder* out, const Cost_Entry& in) { out->setCongestion(in.congestion); } +static void toIntEntry(std::vector& out, + int idx, + const int& cost) { + out[idx] = cost; +} + static void fromIntEntry(::capnp::List::Builder& out, int idx, const int& cost) { out.set(idx, cost); } +static void toPairEntry(std::unordered_map& map_out, + const int& key, + const VprMapCostEntry::Reader& cap_cost) { + VTR_ASSERT(map_out.find(key) == map_out.end()); + util::Cost_Entry cost(cap_cost.getDelay(), cap_cost.getCongestion()); + map_out[key] = cost; + +} + static void fromPairEntry(::capnp::List::Builder& out_key, ::capnp::List<::VprMapCostEntry, ::capnp::Kind::STRUCT>::Builder& out_val, int flat_idx, @@ -1495,20 +1517,44 @@ static void getIntraClusterArrayFlatSize(int& num_tile_types, } static void read_intra_cluster_router_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, - std::unordered_map>& tile_min_cost, const std::string& file) { -// MmapFile f(file); -// -// /* Increase reader limit to 1G words to allow for large files. */ -// ::capnp::ReaderOptions opts = default_large_capnp_opts(); -// ::capnp::FlatArrayMessageReader reader(f.getData(), opts); -// -// auto map = reader.getRoot(); -// -// ToIntraClusterLookahead(inter_tile_pin_primitive_pin_delay, -// tile_min_cost, -// g_vpr_ctx.device().physical_tile_types, -// map); + MmapFile f(file); + + /* Increase reader limit to 1G words to allow for large files. */ + ::capnp::ReaderOptions opts = default_large_capnp_opts(); + ::capnp::FlatArrayMessageReader reader(f.getData(), opts); + + auto map = reader.getRoot(); + + std::vector physical_tile_num_pin_arr; + toVector(physical_tile_num_pin_arr, + map.getPhysicalTileNumPins(), + toIntEntry); + + std::vector pin_num_sink_arr; + toVector(pin_num_sink_arr, + map.getPinNumSinks(), + toIntEntry); + + + int num_seen_pair = 0; + for(int physical_tile_idx = 0; physical_tile_idx < (int)physical_tile_num_pin_arr.size(); physical_tile_idx++) { + int num_pins = physical_tile_num_pin_arr[physical_tile_idx]; + util::t_ipin_primitive_sink_delays tile_pin_sink_cost_map(num_pins); + + for(int pin_num = 0; pin_num < num_pins; pin_num++) { + std::unordered_map pin_sink_cost_map; + toUnorderedMap(pin_sink_cost_map, + num_seen_pair, + num_seen_pair + (int)pin_sink_cost_map.size(), + map.getPinSinks(), + map.getPinSinkCosts(), + toPairEntry); + tile_pin_sink_cost_map[pin_num] = pin_sink_cost_map; + num_seen_pair += (int)pin_sink_cost_map.size(); + } + inter_tile_pin_primitive_pin_delay[physical_tile_idx] = tile_pin_sink_cost_map; + } } static void write_intra_cluster_router_lookahead(const std::string& file, From 1991fcfd0e3877de4ce9f1272d25d9f7fb06a93b Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 24 May 2023 15:03:45 -0400 Subject: [PATCH 18/51] fix a typo --- vpr/src/route/router_lookahead_map.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index e022bb9b87d..6a25003a182 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -1499,7 +1499,8 @@ static void getIntraClusterArrayFlatSize(int& num_tile_types, int& num_pins, int& num_sinks, const std::unordered_map& inter_tile_pin_primitive_pin_delay) { - num_tile_types = inter_tile_pin_primitive_pin_delay.size(); + const auto& physical_tile_types = g_vpr_ctx.device().physical_tile_types; + num_tile_types = (int)physical_tile_types.size(); num_pins = 0; for(const auto& tile_type : inter_tile_pin_primitive_pin_delay) { @@ -1538,6 +1539,7 @@ static void read_intra_cluster_router_lookahead(std::unordered_map pin_sink_cost_map; toUnorderedMap(pin_sink_cost_map, num_seen_pair, - num_seen_pair + (int)pin_sink_cost_map.size(), + num_seen_pair + pin_num_sink_arr[num_seen_pin], map.getPinSinks(), map.getPinSinkCosts(), toPairEntry); tile_pin_sink_cost_map[pin_num] = pin_sink_cost_map; num_seen_pair += (int)pin_sink_cost_map.size(); + ++num_seen_pin; } inter_tile_pin_primitive_pin_delay[physical_tile_idx] = tile_pin_sink_cost_map; } From 13498f1b2b2522389d6ea0fe986aa4f7759d1969 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 24 May 2023 16:16:56 -0400 Subject: [PATCH 19/51] add == opearator to Cost_Entry --- vpr/src/route/router_lookahead_map_utils.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h index 5a7a83aa9fd..42165d270e6 100644 --- a/vpr/src/route/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead_map_utils.h @@ -64,6 +64,10 @@ class Cost_Entry { bool valid() const { return std::isfinite(delay) && std::isfinite(congestion); } + + bool operator==(const Cost_Entry& other) const { + return delay == other.delay && congestion == other.congestion; + } }; /** From 609a4d6971b21ea6d63fa1846aff63e31265131c Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 24 May 2023 17:31:49 -0400 Subject: [PATCH 20/51] Add an assertion to check the number of sinks for each pin --- vpr/src/route/router_lookahead_map.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 6a25003a182..034e8508e4d 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -1554,6 +1554,7 @@ static void read_intra_cluster_router_lookahead(std::unordered_map Date: Wed, 24 May 2023 17:34:36 -0400 Subject: [PATCH 21/51] make format --- vpr/src/route/router_lookahead_map.cpp | 43 ++++++++------------- vtr_flow/scripts/python_libs/vtr/flow.py | 12 +++--- vtr_flow/scripts/python_libs/vtr/vpr/vpr.py | 12 ++++-- vtr_flow/scripts/run_vtr_flow.py | 4 +- 4 files changed, 36 insertions(+), 35 deletions(-) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 034e8508e4d..adb304588ce 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -1471,8 +1471,8 @@ static void toIntEntry(std::vector& out, } static void fromIntEntry(::capnp::List::Builder& out, - int idx, - const int& cost) { + int idx, + const int& cost) { out.set(idx, cost); } @@ -1482,11 +1482,10 @@ static void toPairEntry(std::unordered_map& map_out, VTR_ASSERT(map_out.find(key) == map_out.end()); util::Cost_Entry cost(cap_cost.getDelay(), cap_cost.getCongestion()); map_out[key] = cost; - } static void fromPairEntry(::capnp::List::Builder& out_key, - ::capnp::List<::VprMapCostEntry, ::capnp::Kind::STRUCT>::Builder& out_val, + ::capnp::List<::VprMapCostEntry, ::capnp::Kind::STRUCT>::Builder& out_val, int flat_idx, const int& key, const util::Cost_Entry& cost) { @@ -1503,18 +1502,16 @@ static void getIntraClusterArrayFlatSize(int& num_tile_types, num_tile_types = (int)physical_tile_types.size(); num_pins = 0; - for(const auto& tile_type : inter_tile_pin_primitive_pin_delay) { + for (const auto& tile_type : inter_tile_pin_primitive_pin_delay) { num_pins += (int)tile_type.second.size(); } num_sinks = 0; - for(const auto& tile_type : inter_tile_pin_primitive_pin_delay) { - for(const auto& pin_sink: tile_type.second) { + for (const auto& tile_type : inter_tile_pin_primitive_pin_delay) { + for (const auto& pin_sink : tile_type.second) { num_sinks += (int)pin_sink.size(); } } - - } static void read_intra_cluster_router_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, @@ -1537,14 +1534,13 @@ static void read_intra_cluster_router_lookahead(std::unordered_map pin_sink_cost_map; toUnorderedMap(pin_sink_cost_map, num_seen_pair, @@ -1580,8 +1576,7 @@ static void write_intra_cluster_router_lookahead(const std::string& file, physical_tile_num_pin_arr[physical_type_idx] = (int)physical_type.second.size(); } - ::capnp::List::Builder physical_tile_num_pin_arr_builder = - vpr_intra_cluster_lookahead_builder.initPhysicalTileNumPins(num_tile_types); + ::capnp::List::Builder physical_tile_num_pin_arr_builder = vpr_intra_cluster_lookahead_builder.initPhysicalTileNumPins(num_tile_types); fromVector(physical_tile_num_pin_arr_builder, physical_tile_num_pin_arr, fromIntEntry); @@ -1590,31 +1585,28 @@ static void write_intra_cluster_router_lookahead(const std::string& file, std::vector pin_num_sink_arr(num_pins, 0); { int num_seen_pin = 0; - for(int physical_tile_idx = 0; physical_tile_idx < num_tile_types; ++physical_tile_idx) { - if(inter_tile_pin_primitive_pin_delay.find(physical_tile_idx) == inter_tile_pin_primitive_pin_delay.end()) { + for (int physical_tile_idx = 0; physical_tile_idx < num_tile_types; ++physical_tile_idx) { + if (inter_tile_pin_primitive_pin_delay.find(physical_tile_idx) == inter_tile_pin_primitive_pin_delay.end()) { continue; } - for(const auto& pin_sinks : inter_tile_pin_primitive_pin_delay.at(physical_tile_idx)) { + for (const auto& pin_sinks : inter_tile_pin_primitive_pin_delay.at(physical_tile_idx)) { pin_num_sink_arr[num_seen_pin] = (int)pin_sinks.size(); ++num_seen_pin; } } - ::capnp::List::Builder pin_num_sink_arr_builder = - vpr_intra_cluster_lookahead_builder.initPinNumSinks(num_pins); + ::capnp::List::Builder pin_num_sink_arr_builder = vpr_intra_cluster_lookahead_builder.initPinNumSinks(num_pins); fromVector(pin_num_sink_arr_builder, pin_num_sink_arr, fromIntEntry); } { - ::capnp::List::Builder pin_sink_arr_builder = - vpr_intra_cluster_lookahead_builder.initPinSinks(num_sinks); - ::capnp::List::Builder pin_sink_cost_builder = - vpr_intra_cluster_lookahead_builder.initPinSinkCosts(num_sinks); + ::capnp::List::Builder pin_sink_arr_builder = vpr_intra_cluster_lookahead_builder.initPinSinks(num_sinks); + ::capnp::List::Builder pin_sink_cost_builder = vpr_intra_cluster_lookahead_builder.initPinSinkCosts(num_sinks); int num_seen_pin = 0; - for(int physical_tile_idx = 0; physical_tile_idx < num_tile_types; ++physical_tile_idx) { - for(int pin_num = 0; pin_num < physical_tile_num_pin_arr[physical_tile_idx]; ++pin_num) { + for (int physical_tile_idx = 0; physical_tile_idx < num_tile_types; ++physical_tile_idx) { + for (int pin_num = 0; pin_num < physical_tile_num_pin_arr[physical_tile_idx]; ++pin_num) { const std::unordered_map& pin_sinks = inter_tile_pin_primitive_pin_delay.at(physical_tile_idx).at(pin_num); FromUnorderedMap( pin_sink_arr_builder, @@ -1627,7 +1619,6 @@ static void write_intra_cluster_router_lookahead(const std::string& file, } } - writeMessageToFile(file, &builder); } diff --git a/vtr_flow/scripts/python_libs/vtr/flow.py b/vtr_flow/scripts/python_libs/vtr/flow.py index a233e10cef0..0aab0f8f3a3 100644 --- a/vtr_flow/scripts/python_libs/vtr/flow.py +++ b/vtr_flow/scripts/python_libs/vtr/flow.py @@ -291,11 +291,13 @@ def run( do_second_run = False second_run_args = vpr_args - if ("write_rr_graph" in vpr_args or - "analysis" in vpr_args or - "route" in vpr_args or - "write_router_lookahead" in vpr_args or - "write_intra_cluster_router_lookahead" in vpr_args): + if ( + "write_rr_graph" in vpr_args + or "analysis" in vpr_args + or "route" in vpr_args + or "write_router_lookahead" in vpr_args + or "write_intra_cluster_router_lookahead" in vpr_args + ): do_second_run = True vtr.vpr.run( diff --git a/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py b/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py index 4cd08827218..d0e5953fbe0 100644 --- a/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py +++ b/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py @@ -292,7 +292,9 @@ def run_second_time( if "write_intra_cluster_router_lookahead" in second_run_args: intra_cluster_router_lookahead = second_run_args["write_intra_cluster_router_lookahead"] second_run_args["read_intra_cluster_router_lookahead"] = intra_cluster_router_lookahead - second_run_args["write_intra_cluster_router_lookahead"] = "intra_cluster_router_lookahead2.capnp" + second_run_args[ + "write_intra_cluster_router_lookahead" + ] = "intra_cluster_router_lookahead2.capnp" # run VPR run( @@ -320,7 +322,9 @@ def run_second_time( cmd, temp_dir, log_filename="diff.inter_cluster_router_lookahead.out", indent_depth=1 ) if diff_result: - raise InspectError("failed: vpr (Inter Cluster Router Lookahead output not consistent when reloaded)") + raise InspectError( + "failed: vpr (Inter Cluster Router Lookahead output not consistent when reloaded)" + ) if "write_intra_cluster_router_lookahead" in second_run_args: cmd = ["diff", intra_cluster_router_lookahead, "intra_cluster_router_lookahead2.capnp"] @@ -328,7 +332,9 @@ def run_second_time( cmd, temp_dir, log_filename="diff.intra_cluster_router_lookahead.out", indent_depth=1 ) if diff_result: - raise InspectError("failed: vpr (Intra Cluster Router Lookahead not consistent when reloaded)") + raise InspectError( + "failed: vpr (Intra Cluster Router Lookahead not consistent when reloaded)" + ) def cmp_full_vs_incr_sta( diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py index 4165311d77e..f4047caa04b 100755 --- a/vtr_flow/scripts/run_vtr_flow.py +++ b/vtr_flow/scripts/run_vtr_flow.py @@ -727,7 +727,9 @@ def process_vpr_args(args, prog, temp_dir, vpr_args): if args.verify_inter_cluster_router_lookahead: vpr_args["write_router_lookahead"] = "inter_cluster_router_lookahead.capnp" if args.verify_intra_cluster_router_lookahead: - assert "flat_routing" in vpr_args, "Flat router should be enabled if intra cluster router lookahead is to be verified" + assert ( + "flat_routing" in vpr_args + ), "Flat router should be enabled if intra cluster router lookahead is to be verified" vpr_args["write_intra_cluster_router_lookahead"] = "intra_cluster_router_lookahead.capnp" return vpr_args From ec4fa046221d80711874b0ab72160b06ff72e5ee Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 25 May 2023 09:58:10 -0400 Subject: [PATCH 22/51] disable writing rr-graph if flat-routing is enalbled --- vpr/src/route/rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 96581ccc093..cb42c4e98f5 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -707,8 +707,8 @@ void create_rr_graph(const t_graph_type graph_type, print_rr_graph_stats(); - //Write out rr graph file if needed - if (!det_routing_arch->write_rr_graph_filename.empty()) { + //Write out rr graph file if needed - Currently, writing the flat rr-graph is not supported since loading from a flat rr-graph is not supported + if (!det_routing_arch->write_rr_graph_filename.empty() && !is_flat) { write_rr_graph(&mutable_device_ctx.rr_graph_builder, &mutable_device_ctx.rr_graph, device_ctx.physical_tile_types, From 98a79a8454532b1646434419a5aab4500d4e1b94 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 25 May 2023 10:49:09 -0400 Subject: [PATCH 23/51] While reading RR Graph, don't raise an error if the name starts with InternalSwitch --- libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 0f0cb893a4e..49dad419bc5 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -460,11 +460,13 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { // // If the switch name is not present in the architecture, generate an // error. + // If the graph is written when flat-routing is enalbed, the types of the switches inside of the rr_graph are also + // added to the XML file. These types are not added the data structure that contain arch switch types. It's remained + // as a future work to remove the arch_switch_types and use all_sw info under device_ctx instead. bool found_arch_name = false; std::string string_name = std::string(name); for (const auto& arch_sw_inf: arch_switch_inf_) { - if (string_name == arch_sw_inf.name) { - string_name = arch_sw_inf.name; + if (string_name == arch_sw_inf.name || string_name.compare(0, 15, "Internal Switch") == 0) { found_arch_name = true; break; } From a7deb2ea12a4a392521b97c95b9743e475b05890 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 26 May 2023 18:00:26 -0400 Subject: [PATCH 24/51] t_rr_edge_infor: remove the default value of is_remapped --- libs/librrgraph/src/base/rr_edge.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_edge.h b/libs/librrgraph/src/base/rr_edge.h index 01a01526cfe..0fb3ac244ff 100644 --- a/libs/librrgraph/src/base/rr_edge.h +++ b/libs/librrgraph/src/base/rr_edge.h @@ -3,9 +3,8 @@ #include "rr_graph_fwd.h" -/* TODO: MUST change the node id to RRNodeId before refactoring is finished! */ struct t_rr_edge_info { - t_rr_edge_info(RRNodeId from, RRNodeId to, short type, bool is_remapped = false) noexcept + t_rr_edge_info(RRNodeId from, RRNodeId to, short type, bool is_remapped) noexcept : from_node(from) , to_node(to) , switch_type(type) From 11c6833f06c7aed7961f4c54fd1a382b316d6028 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 26 May 2023 18:01:30 -0400 Subject: [PATCH 25/51] add is_rr_id to emplace_back_edge function of rr_graph_builder --- libs/librrgraph/src/base/rr_graph_builder.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index f1777355f07..c8b58764a49 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -208,8 +208,8 @@ class RRGraphBuilder { /** @brief emplace_back_edge; It add one edge. This method is efficient if reserve_edges was called with * the number of edges present in the graph. */ - inline void emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch) { - node_storage_.emplace_back_edge(src, dest, edge_switch); + inline void emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch, bool is_rr_id) { + node_storage_.emplace_back_edge(src, dest, edge_switch, is_rr_id); } /** @brief Append 1 more RR node to the RR graph. */ inline void emplace_back() { From 9deb2f637264fe6560c62e7a7c83b8097c0590f5 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 26 May 2023 18:02:47 -0400 Subject: [PATCH 26/51] add intra_tile field to t_rr_switch_inf --- libs/libarchfpga/src/physical_types.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index a4699e2ccd8..c1f625c99f1 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1701,6 +1701,8 @@ struct t_rr_switch_inf { e_power_buffer_type power_buffer_type = POWER_BUFFER_TYPE_UNDEFINED; float power_buffer_size = 0.; + bool intra_tile = false; + public: //Returns the type of switch SwitchType type() const; From 2e6303f7cf4df7493234736e3647b17c673f8d25 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 26 May 2023 18:34:49 -0400 Subject: [PATCH 27/51] while loading the sw name, determine whether the sw is intra-cluster or not based on it's name --- .../librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 49dad419bc5..be1d8bccbe3 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -465,8 +465,9 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { // as a future work to remove the arch_switch_types and use all_sw info under device_ctx instead. bool found_arch_name = false; std::string string_name = std::string(name); + bool is_internal_sw = string_name.compare(0, 15, "Internal Switch") == 0; for (const auto& arch_sw_inf: arch_switch_inf_) { - if (string_name == arch_sw_inf.name || string_name.compare(0, 15, "Internal Switch") == 0) { + if (string_name == arch_sw_inf.name || is_internal_sw) { found_arch_name = true; break; } @@ -474,7 +475,11 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { if (!found_arch_name) { report_error("Switch name '%s' not found in architecture\n", string_name.c_str()); } - + if(is_internal_sw){ + sw->intra_tile = true; + } else { + sw->intra_tile = false; + } sw->name = string_name; } inline const char* get_switch_name(const t_rr_switch_inf*& sw) final { @@ -830,6 +835,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { inline void finish_rr_nodes_node(int& /*inode*/) final { } inline size_t num_rr_nodes_node(void*& /*ctx*/) final { + return rr_nodes_->size(); } inline const t_rr_node get_rr_nodes_node(int n, void*& /*ctx*/) final { @@ -921,7 +927,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { bind.set_ignore(); } - rr_graph_builder_->emplace_back_edge(RRNodeId(src_node), RRNodeId(sink_node), switch_id); + // The edge ids in the rr graph file are indeed rr edge id not architecture edge id + rr_graph_builder_->emplace_back_edge(RRNodeId(src_node), RRNodeId(sink_node), switch_id, true); return bind; } inline void finish_rr_edges_edge(MetadataBind& bind) final { From b08f84d50ba8f9ad54f77b317d780e4052890039 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 26 May 2023 18:58:31 -0400 Subject: [PATCH 28/51] add remapped to rr_graph_storage:emplace_back_edge --- libs/librrgraph/src/base/rr_graph_storage.cpp | 7 ++++--- libs/librrgraph/src/base/rr_graph_storage.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index 94ca29b7636..8a2fd731c4c 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -11,13 +11,13 @@ void t_rr_graph_storage::reserve_edges(size_t num_edges) { edge_remapped_.reserve(num_edges); } -void t_rr_graph_storage::emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch) { +void t_rr_graph_storage::emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch, bool remapped) { // Cannot mutate edges once edges have been read! VTR_ASSERT(!edges_read_); edge_src_node_.emplace_back(src); edge_dest_node_.emplace_back(dest); edge_switch_.emplace_back(edge_switch); - edge_remapped_.emplace_back(false); + edge_remapped_.emplace_back(remapped); } // Typical node to edge ratio. This allows a preallocation guess for the edges @@ -48,7 +48,8 @@ void t_rr_graph_storage::alloc_and_load_edges(const t_rr_edge_info_set* rr_edges emplace_back_edge( new_edge.from_node, new_edge.to_node, - new_edge.switch_type); + new_edge.switch_type, + new_edge.remapped); } } diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index 6d150c02641..c221ab24ac8 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -549,7 +549,7 @@ class t_rr_graph_storage { // the number of edges present in the graph. This method is still // amortized O(1), like std::vector::emplace_back, but both runtime and // peak memory usage will be higher if reallocation is required. - void emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch); + void emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch, bool remapped); // Adds a batch of edges. void alloc_and_load_edges(const t_rr_edge_info_set* rr_edges_to_create); From a0e8a675abe2cbcb05bfd665f45ee24522a5c568 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 27 May 2023 11:31:34 -0400 Subject: [PATCH 29/51] pass false as edge_remapped parameter for the edges created for clock network --- vpr/src/route/clock_connection_builders.cpp | 10 +++++----- vpr/src/route/clock_network_builders.cpp | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/clock_connection_builders.cpp index 645e96cb306..dbffbdb6e5f 100644 --- a/vpr/src/route/clock_connection_builders.cpp +++ b/vpr/src/route/clock_connection_builders.cpp @@ -75,18 +75,18 @@ void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_ // Connect to x-channel wires unsigned num_wires_x = x_wire_indices.size() * fc; for (size_t i = 0; i < num_wires_x; i++) { - clock_graph.add_edge(rr_edges_to_create, x_wire_indices[i], RRNodeId(clock_index), arch_switch_idx); + clock_graph.add_edge(rr_edges_to_create, x_wire_indices[i], RRNodeId(clock_index), arch_switch_idx, false); } // Connect to y-channel wires unsigned num_wires_y = y_wire_indices.size() * fc; for (size_t i = 0; i < num_wires_y; i++) { - clock_graph.add_edge(rr_edges_to_create, y_wire_indices[i], RRNodeId(clock_index), arch_switch_idx); + clock_graph.add_edge(rr_edges_to_create, y_wire_indices[i], RRNodeId(clock_index), arch_switch_idx, false); } // Connect to virtual clock sink node // used by the two stage router - clock_graph.add_edge(rr_edges_to_create, RRNodeId(clock_index), virtual_clock_network_root_idx, arch_switch_idx); + clock_graph.add_edge(rr_edges_to_create, RRNodeId(clock_index), virtual_clock_network_root_idx, arch_switch_idx, false); } } @@ -208,7 +208,7 @@ void ClockToClockConneciton::create_switches(const ClockRRGraphBuilder& clock_gr if (from_itter == from_rr_node_indices.end()) { from_itter = from_rr_node_indices.begin(); } - clock_graph.add_edge(rr_edges_to_create, RRNodeId(*from_itter), RRNodeId(to_index), arch_switch_idx); + clock_graph.add_edge(rr_edges_to_create, RRNodeId(*from_itter), RRNodeId(to_index), arch_switch_idx, false); from_itter++; } } @@ -321,7 +321,7 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra //Create edges depending on Fc for (size_t i = 0; i < clock_network_indices.size() * fc; i++) { - clock_graph.add_edge(rr_edges_to_create, RRNodeId(clock_network_indices[i]), RRNodeId(clock_pin_node_idx), arch_switch_idx); + clock_graph.add_edge(rr_edges_to_create, RRNodeId(clock_network_indices[i]), RRNodeId(clock_pin_node_idx), arch_switch_idx, false); } } } diff --git a/vpr/src/route/clock_network_builders.cpp b/vpr/src/route/clock_network_builders.cpp index 1db5796f47d..3ed3bd5a6a1 100644 --- a/vpr/src/route/clock_network_builders.cpp +++ b/vpr/src/route/clock_network_builders.cpp @@ -314,8 +314,8 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB clock_graph); // connect drive point to each half rib using a directed switch - clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(left_node_idx), drive.switch_idx); - clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(right_node_idx), drive.switch_idx); + clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(left_node_idx), drive.switch_idx, false); + clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(right_node_idx), drive.switch_idx, false); } } } @@ -648,8 +648,8 @@ void ClockSpine::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGrap clock_graph); // connect drive point to each half spine using a directed switch - clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(left_node_idx), drive.switch_idx); - clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(right_node_idx), drive.switch_idx); + clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(left_node_idx), drive.switch_idx, false); + clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(right_node_idx), drive.switch_idx, false); } } } From 5262f512120c1f7d4d5e1f2eed7432ad219d6738 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 27 May 2023 11:32:23 -0400 Subject: [PATCH 30/51] add edge_remapped parameter to add_edge function of clockrrgraphbuilder --- vpr/src/route/rr_graph_clock.cpp | 7 ++++--- vpr/src/route/rr_graph_clock.h | 3 ++- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/vpr/src/route/rr_graph_clock.cpp b/vpr/src/route/rr_graph_clock.cpp index cbee0690b51..2d5d761ef6f 100644 --- a/vpr/src/route/rr_graph_clock.cpp +++ b/vpr/src/route/rr_graph_clock.cpp @@ -190,14 +190,15 @@ void ClockRRGraphBuilder::map_relative_seg_indices(const t_unified_to_parallel_s void ClockRRGraphBuilder::add_edge(t_rr_edge_info_set* rr_edges_to_create, RRNodeId src_node, RRNodeId sink_node, - int arch_switch_idx) const { + int arch_switch_idx, + bool edge_remapped) const { const auto& device_ctx = g_vpr_ctx.device(); VTR_ASSERT(arch_switch_idx < (int)device_ctx.arch_switch_inf.size()); - rr_edges_to_create->emplace_back(src_node, sink_node, arch_switch_idx); + rr_edges_to_create->emplace_back(src_node, sink_node, arch_switch_idx, edge_remapped); const auto& sw = device_ctx.arch_switch_inf[arch_switch_idx]; if (!sw.buffered() && !sw.configurable()) { // This is short, create a reverse edge. - rr_edges_to_create->emplace_back(sink_node, src_node, arch_switch_idx); + rr_edges_to_create->emplace_back(sink_node, src_node, arch_switch_idx, edge_remapped); } } diff --git a/vpr/src/route/rr_graph_clock.h b/vpr/src/route/rr_graph_clock.h index 70f48eb8732..55b038724b0 100644 --- a/vpr/src/route/rr_graph_clock.h +++ b/vpr/src/route/rr_graph_clock.h @@ -121,7 +121,8 @@ class ClockRRGraphBuilder { void add_edge(t_rr_edge_info_set* rr_edges_to_create, RRNodeId src_node, RRNodeId sink_node, - int arch_switch_idx) const; + int arch_switch_idx, + bool edge_remapped) const; public: /* Creates the routing resourse (rr) graph of the clock network and appends it to the From e0cab9924fd797e74ecc84260f015c0b361b4f80 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 27 May 2023 11:34:21 -0400 Subject: [PATCH 31/51] pass load graph to functions that create graph which indicate whether the graph is loaded from a file - don't remap the edges if graph is loaded --- vpr/src/route/rr_graph.cpp | 264 ++++++++++++++++++++++-------------- vpr/src/route/rr_graph2.cpp | 18 +-- 2 files changed, 173 insertions(+), 109 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index cb42c4e98f5..98a8bca78d0 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -197,7 +197,8 @@ static void alloc_and_load_intra_cluster_rr_graph(RRGraphBuilder& rr_graph_build const vtr::vector>& chain_pin_nums, float R_minW_nmos, float R_minW_pmos, - bool is_flat); + bool is_flat, + bool load_rr_graph); static void set_clusters_pin_chains(const ClusteredNetlist& clb_nlist, vtr::vector& pin_chains, @@ -297,7 +298,8 @@ static void add_intra_cluster_edges_rr_graph(RRGraphBuilder& rr_graph_builder, float R_minW_nmos, float R_minW_pmos, int& num_edges, - bool is_flat); + bool is_flat, + bool load_rr_graph); static void add_intra_tile_edges_rr_graph(RRGraphBuilder& rr_graph_builder, t_rr_edge_info_set& rr_edges_to_create, @@ -319,7 +321,8 @@ static void build_cluster_internal_edges(RRGraphBuilder& rr_graph_builder, t_rr_edge_info_set& rr_edges_to_create, const t_cluster_pin_chain& nodes_to_collapse, const DeviceGrid& grid, - bool is_flat); + bool is_flat, + bool load_rr_graph); /* * Connect the pins of the given t_pb to their drivers - It doesn't add the edges going in/out of pins on a chain @@ -333,7 +336,8 @@ static void add_pb_edges(RRGraphBuilder& rr_graph_builder, const t_cluster_pin_chain& nodes_to_collapse, int rel_cap, int i, - int j); + int j, + bool is_remapped); /** * Edges going in/out of collapse nodes are not added by the normal routine. This function add those edges @@ -358,7 +362,8 @@ static int add_edges_for_collapsed_nodes(RRGraphBuilder& rr_graph_builder, float R_minW_nmos, float R_minW_pmos, int i, - int j); + int j, + bool load_rr_graph); /** * @note This funtion is used to add the fan-in edges of the given chain node to the chain's sink with the modified delay * @param rr_graph_builder @@ -390,7 +395,8 @@ static void add_chain_node_fan_in_edges(RRGraphBuilder& rr_graph_builder, int chain_idx, int node_idx, int i, - int j); + int j, + bool load_rr_graph); /** * @note Return the minimum delay to the chain's sink since a pin outside of the chain may have connections to multiple pins inside the chain. @@ -545,17 +551,12 @@ static void add_pin_chain(const std::vector& pin_chain, bool is_new_chain); // Return the edge id of an intra-tile edge with the same delay. If there isn't any, create a new one and return the ID -static int find_create_intra_cluster_sw_arch_idx(std::map& arch_sw_inf, - float delay); - -// Add the newly added arch sw to data structures related to rr switch and switch_fanin_remap. This function should be used for the edge types -// added after allocating rr switches -static void find_create_rr_switch(RRGraphBuilder& rr_graph_builder, - std::vector>& switch_fanin_remap, - float R_minW_nmos, - float R_minW_pmos, - const t_arch_switch_inf& arch_sw_inf, - const int arch_sw_id); +static std::pair find_create_intra_cluster_sw(RRGraphBuilder& rr_graph, + std::map& arch_sw_inf, + float R_minW_nmos, + float R_minW_pmos, + bool is_rr_sw, + float delay); static float get_delay_directly_connected_pins(t_physical_tile_type_ptr physical_type, t_logical_block_type_ptr logical_block, @@ -594,7 +595,8 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, float R_minW_nmos, float R_minW_pmos, RRGraphBuilder& rr_graph_builder, - bool is_flat); + bool is_flat, + bool load_rr_graph); /******************* Subroutine definitions *******************************/ @@ -613,7 +615,8 @@ void create_rr_graph(const t_graph_type graph_type, auto& mutable_device_ctx = g_vpr_ctx.mutable_device(); bool echo_enabled = getEchoEnabled() && isEchoFileEnabled(E_ECHO_RR_GRAPH_INDEXED_DATA); const char* echo_file_name = getEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA); - if (!det_routing_arch->read_rr_graph_filename.empty()) { + bool load_rr_graph = !det_routing_arch->read_rr_graph_filename.empty(); + if (load_rr_graph) { if (device_ctx.read_rr_graph_filename != det_routing_arch->read_rr_graph_filename) { free_rr_graph(); @@ -686,7 +689,8 @@ void create_rr_graph(const t_graph_type graph_type, det_routing_arch->R_minW_nmos, det_routing_arch->R_minW_pmos, mutable_device_ctx.rr_graph_builder, - is_flat); + is_flat, + load_rr_graph); if (router_opts.reorder_rr_graph_nodes_algorithm != DONT_REORDER) { mutable_device_ctx.rr_graph_builder.reorder_nodes(router_opts.reorder_rr_graph_nodes_algorithm, @@ -733,7 +737,8 @@ static void add_intra_cluster_edges_rr_graph(RRGraphBuilder& rr_graph_builder, float R_minW_nmos, float R_minW_pmos, int& num_edges, - bool is_flat) { + bool is_flat, + bool load_rr_graph) { VTR_ASSERT(is_flat); /* This function should be called if placement is done! */ @@ -756,7 +761,8 @@ static void add_intra_cluster_edges_rr_graph(RRGraphBuilder& rr_graph_builder, rr_edges_to_create, nodes_to_collapse[cluster_blk_id], grid, - is_flat); + is_flat, + load_rr_graph); uniquify_edges(rr_edges_to_create); alloc_and_load_edges(rr_graph_builder, rr_edges_to_create); num_edges += rr_edges_to_create.size(); @@ -798,7 +804,7 @@ static void add_intra_tile_edges_rr_graph(RRGraphBuilder& rr_graph_builder, pin_physical_num); VTR_ASSERT(sw_idx != -1); - rr_edges_to_create.emplace_back(driving_pin_node_id, pin_rr_node_id, sw_idx); + rr_edges_to_create.emplace_back(driving_pin_node_id, pin_rr_node_id, sw_idx, false); } } } @@ -1306,7 +1312,8 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, float R_minW_nmos, float R_minW_pmos, RRGraphBuilder& rr_graph_builder, - bool is_flat) { + bool is_flat, + bool load_rr_graph) { const auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist; auto& device_ctx = g_vpr_ctx.mutable_device(); @@ -1334,7 +1341,8 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, cluster_flat_chain_pins, R_minW_nmos, R_minW_pmos, - is_flat); + is_flat, + load_rr_graph); /* AA: Note that in the case of dedicated networks, we are currently underestimating the additional node count due to the clock networks. * Thus this below error is logged; it's not actually an error, the node estimation needs to get fixed for dedicated clock networks. */ @@ -1343,8 +1351,12 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, expected_node_count, rr_graph.num_nodes()); } - remap_rr_node_switch_indices(rr_graph_builder, - g_vpr_ctx.device().switch_fanin_remap); + if(!load_rr_graph) { + remap_rr_node_switch_indices(rr_graph_builder, + g_vpr_ctx.device().switch_fanin_remap); + } else { + rr_graph_builder.mark_edges_as_rr_switch_ids(); + } rr_graph_builder.partition_edges(); @@ -1553,6 +1565,8 @@ t_rr_switch_inf create_rr_switch_from_arch_switch(const t_arch_switch_inf& arch_ rr_switch_inf.power_buffer_type = arch_sw_inf.power_buffer_type; rr_switch_inf.power_buffer_size = arch_sw_inf.power_buffer_size; + rr_switch_inf.intra_tile = arch_sw_inf.intra_tile; + return rr_switch_inf; } /* This function is same as create_rr_switch_from_arch_switch() in terms of functionality. It is tuned for clients functions in routing resource graph builder */ @@ -2051,7 +2065,8 @@ static void alloc_and_load_intra_cluster_rr_graph(RRGraphBuilder& rr_graph_build const vtr::vector>& chain_pin_nums, float R_minW_nmos, float R_minW_pmos, - bool is_flat) { + bool is_flat, + bool load_rr_graph) { t_rr_edge_info_set rr_edges_to_create; int num_edges = 0; for (size_t i = 0; i < grid.width(); ++i) { @@ -2107,7 +2122,8 @@ static void alloc_and_load_intra_cluster_rr_graph(RRGraphBuilder& rr_graph_build R_minW_nmos, R_minW_pmos, num_edges, - is_flat); + is_flat, + load_rr_graph); } VTR_LOG("Internal edge count:%d\n", num_edges); @@ -2241,11 +2257,11 @@ static void connect_tile_src_sink_to_pins(RRGraphBuilder& rr_graph_builder, * }*/ if (class_type == DRIVER) { VTR_ASSERT(pin_type == DRIVER); - rr_edges_to_create.emplace_back(class_rr_node_id, pin_rr_node_id, delayless_switch); + rr_edges_to_create.emplace_back(class_rr_node_id, pin_rr_node_id, delayless_switch, false); } else { VTR_ASSERT(class_type == RECEIVER); VTR_ASSERT(pin_type == RECEIVER); - rr_edges_to_create.emplace_back(pin_rr_node_id, class_rr_node_id, delayless_switch); + rr_edges_to_create.emplace_back(pin_rr_node_id, class_rr_node_id, delayless_switch, false); } } } @@ -2276,11 +2292,11 @@ static void connect_src_sink_to_pins(RRGraphBuilder& rr_graph_builder, auto pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num); if (class_type == DRIVER) { VTR_ASSERT(pin_type == DRIVER); - rr_edges_to_create.emplace_back(class_rr_node_id, pin_rr_node_id, delayless_switch); + rr_edges_to_create.emplace_back(class_rr_node_id, pin_rr_node_id, delayless_switch, false); } else { VTR_ASSERT(class_type == RECEIVER); VTR_ASSERT(pin_type == RECEIVER); - rr_edges_to_create.emplace_back(pin_rr_node_id, class_rr_node_id, delayless_switch); + rr_edges_to_create.emplace_back(pin_rr_node_id, class_rr_node_id, delayless_switch, false); } } } @@ -2438,7 +2454,8 @@ static void build_cluster_internal_edges(RRGraphBuilder& rr_graph_builder, t_rr_edge_info_set& rr_edges_to_create, const t_cluster_pin_chain& nodes_to_collapse, const DeviceGrid& grid, - bool is_flat) { + bool is_flat, + bool load_rr_graph) { VTR_ASSERT(is_flat); /* Internal edges are added from the start tile */ int width_offset = grid.get_width_offset(i, j); @@ -2476,7 +2493,8 @@ static void build_cluster_internal_edges(RRGraphBuilder& rr_graph_builder, nodes_to_collapse, rel_cap, i, - j); + j, + load_rr_graph); add_pb_child_to_list(pb_q, pb); } @@ -2492,7 +2510,8 @@ static void build_cluster_internal_edges(RRGraphBuilder& rr_graph_builder, R_minW_nmos, R_minW_pmos, i, - j); + j, + load_rr_graph); } static void add_pb_edges(RRGraphBuilder& rr_graph_builder, @@ -2504,7 +2523,8 @@ static void add_pb_edges(RRGraphBuilder& rr_graph_builder, const t_cluster_pin_chain& nodes_to_collapse, int rel_cap, int i, - int j) { + int j, + bool is_remapped) { auto pin_num_range = get_pb_pins(physical_type, sub_tile, logical_block, @@ -2555,8 +2575,27 @@ static void add_pb_edges(RRGraphBuilder& rr_graph_builder, logical_block, pin_physical_num, conn_pin_physical_num); - VTR_ASSERT(sw_idx != -1); - rr_edges_to_create.emplace_back(parent_pin_node_id, conn_pin_node_id, sw_idx); + + if(is_remapped) { + bool found = false; + float delay = g_vpr_ctx.device().all_sw_inf.at(sw_idx).Tdel(); + const auto& rr_switches = rr_graph_builder.rr_switch(); + for(int sw_id = 0; sw_id < (int)rr_switches.size(); sw_id++) { + const auto& rr_switch = rr_switches[RRSwitchId(sw_id)]; + if(rr_switch.intra_tile) { + if(rr_switch.Tdel == delay) { + sw_idx = sw_id; + found = true; + break; + } + } + } + // If the graph is loaded from a file, we expect that all sw types are already listed there since currently, we are not doing any further + // Optimization. If the optimization done when the rr graph file was generated is different from the current optimization, in the case that + // these optimizations create different RR switches, this VTR ASSERT can be removed. + VTR_ASSERT(found); + } + rr_edges_to_create.emplace_back(parent_pin_node_id, conn_pin_node_id, sw_idx, is_remapped); } } } @@ -2570,7 +2609,8 @@ static int add_edges_for_collapsed_nodes(RRGraphBuilder& rr_graph_builder, float R_minW_nmos, float R_minW_pmos, int i, - int j) { + int j, + bool load_rr_graph) { // Store the cluster pins in a set to make the search more run-time efficient std::unordered_set cluster_pins_set(cluster_pins.begin(), cluster_pins.end()); @@ -2596,7 +2636,8 @@ static int add_edges_for_collapsed_nodes(RRGraphBuilder& rr_graph_builder, chain_idx, node_idx, i, - j); + j, + load_rr_graph); } } return num_collapsed_pins; @@ -2615,7 +2656,8 @@ static void add_chain_node_fan_in_edges(RRGraphBuilder& rr_graph_builder, int chain_idx, int node_idx, int i, - int j) { + int j, + bool load_rr_graph) { // Chain node pin physical number int pin_physical_num = nodes_to_collapse.chains[chain_idx][node_idx].pin_physical_num; const auto& pin_chain_idx = nodes_to_collapse.pin_chain_idx; @@ -2705,18 +2747,34 @@ static void add_chain_node_fan_in_edges(RRGraphBuilder& rr_graph_builder, } for (auto src_pair : src_node_edge_pair) { - int arch_sw = find_create_intra_cluster_sw_arch_idx(all_sw_inf, - src_pair.second); - // The internal edges are added after switch_fanin_remap is initialized; thus, if a new arch_sw is added, - // switch _fanin_remap should be updated. - find_create_rr_switch(rr_graph_builder, - g_vpr_ctx.mutable_device().switch_fanin_remap, - R_minW_nmos, - R_minW_pmos, - all_sw_inf[arch_sw], - arch_sw); - - rr_edges_to_create.emplace_back(src_pair.first, sink_rr_node_id, arch_sw); + float delay = src_pair.second; + bool is_rr_sw_id = load_rr_graph; + bool is_new_sw; + int sw_id; + std::tie(is_new_sw, sw_id) = find_create_intra_cluster_sw(rr_graph_builder, + all_sw_inf, + R_minW_nmos, + R_minW_pmos, + is_rr_sw_id, + delay); + + if(!is_rr_sw_id && is_new_sw) { + // Currently we assume that if rr graph is read from a file, we shouldn't get into this block + VTR_ASSERT(!load_rr_graph); + // The internal edges are added after switch_fanin_remap is initialized; thus, if a new arch_sw is added, + // switch _fanin_remap should be updated. + t_rr_switch_inf rr_sw_inf = create_rr_switch_from_arch_switch(create_internal_arch_sw(delay), + R_minW_nmos, + R_minW_pmos); + auto rr_sw_id = rr_graph_builder.add_rr_switch(rr_sw_inf); + // If rr graph is loaded from a file, switch_fanin_remap is going to be empty + if(!load_rr_graph) { + auto& switch_fanin_remap = g_vpr_ctx.mutable_device().switch_fanin_remap; + switch_fanin_remap.push_back({{UNDEFINED, size_t(rr_sw_id)}}); + } + } + + rr_edges_to_create.emplace_back(src_pair.first, sink_rr_node_id, sw_id, is_rr_sw_id); } } } @@ -4080,7 +4138,7 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder, //back fairly directly to the architecture file in the case of pin equivalence RRNodeId inode = pick_best_direct_connect_target_rr_node(rr_graph, from_rr_node, inodes); - rr_edges_to_create.emplace_back(from_rr_node, inode, clb_to_clb_directs[i].switch_index); + rr_edges_to_create.emplace_back(from_rr_node, inode, clb_to_clb_directs[i].switch_index, false); ++num_pins; } } @@ -4596,56 +4654,62 @@ static void add_pin_chain(const std::vector& pin_chain, } } -static int find_create_intra_cluster_sw_arch_idx(std::map& arch_sw_inf, - float delay) { - // Check whether is there any other intra-tile edge with the same delay - auto find_res = std::find_if(arch_sw_inf.begin(), arch_sw_inf.end(), - [delay](const std::pair& sw_inf_pair) { - const t_arch_switch_inf& sw_inf = std::get<1>(sw_inf_pair); - if (sw_inf.intra_tile && sw_inf.Tdel() == delay) { - return true; - } else { - return false; - } - }); - - // There isn't any other intra-tile edge with the same delay - Create a new one! - if (find_res == arch_sw_inf.end()) { - auto arch_sw = create_internal_arch_sw(delay); - int max_key_num = std::numeric_limits::min(); - // Find the maximum edge index - for (const auto& arch_sw_pair : arch_sw_inf) { - if (arch_sw_pair.first > max_key_num) { - max_key_num = arch_sw_pair.first; +static std::pair find_create_intra_cluster_sw(RRGraphBuilder& rr_graph, + std::map& arch_sw_inf, + float R_minW_nmos, + float R_minW_pmos, + bool is_rr_sw, + float delay) { + const auto& rr_graph_switches = rr_graph.rr_switch(); + + if(is_rr_sw) { + for (int rr_switch_id = 0; rr_switch_id < (int)rr_graph_switches.size(); rr_switch_id++) { + const auto& rr_sw = rr_graph_switches[RRSwitchId(rr_switch_id)]; + if (rr_sw.intra_tile) { + if(rr_sw.Tdel == delay) { + return std::make_pair(false, rr_switch_id); + } } } - int new_key_num = ++max_key_num; - arch_sw_inf.insert(std::make_pair(new_key_num, arch_sw)); - // We assume that the delay of internal switches is not dependent on their fan-in - // If this assumption proven to not be accurate, the implementation needs to be changed. - VTR_ASSERT(arch_sw.fixed_Tdel()); + t_rr_switch_inf new_rr_switch_inf = create_rr_switch_from_arch_switch(create_internal_arch_sw(delay), + R_minW_nmos, + R_minW_pmos); + RRSwitchId rr_sw_id = rr_graph.add_rr_switch(new_rr_switch_inf); - return new_key_num; - } else { - return find_res->first; - } -} + return std::make_pair(true, (size_t)rr_sw_id); -static void find_create_rr_switch(RRGraphBuilder& rr_graph_builder, - std::vector>& switch_fanin_remap, - float R_minW_nmos, - float R_minW_pmos, - const t_arch_switch_inf& arch_sw_inf, - const int arch_sw_id) { - if ((int)switch_fanin_remap.size() > arch_sw_id) { - return; } else { - t_rr_switch_inf rr_switch = create_rr_switch_from_arch_switch(arch_sw_inf, - R_minW_nmos, - R_minW_pmos); - auto rr_switch_id = rr_graph_builder.add_rr_switch(rr_switch); - switch_fanin_remap.push_back({{UNDEFINED, size_t(rr_switch_id)}}); - VTR_ASSERT(((int)switch_fanin_remap.size() - 1) == arch_sw_id); + // Check whether is there any other intra-tile edge with the same delay + auto find_res = std::find_if(arch_sw_inf.begin(), arch_sw_inf.end(), + [delay](const std::pair& sw_inf_pair) { + const t_arch_switch_inf& sw_inf = std::get<1>(sw_inf_pair); + if (sw_inf.intra_tile && sw_inf.Tdel() == delay) { + return true; + } else { + return false; + } + }); + + // There isn't any other intra-tile edge with the same delay - Create a new one! + if (find_res == arch_sw_inf.end()) { + auto arch_sw = create_internal_arch_sw(delay); + int max_key_num = std::numeric_limits::min(); + // Find the maximum edge index + for (const auto& arch_sw_pair : arch_sw_inf) { + if (arch_sw_pair.first > max_key_num) { + max_key_num = arch_sw_pair.first; + } + } + int new_key_num = ++max_key_num; + arch_sw_inf.insert(std::make_pair(new_key_num, arch_sw)); + // We assume that the delay of internal switches is not dependent on their fan-in + // If this assumption proven to not be accurate, the implementation needs to be changed. + VTR_ASSERT(arch_sw.fixed_Tdel()); + + return std::make_pair(true, new_key_num); + } else { + return std::make_pair(false, find_res->first); + } } } diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index ecc695ac5e1..0df76d53003 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -723,7 +723,7 @@ int get_bidir_opin_connections(RRGraphBuilder& rr_graph_builder, continue; } - rr_edges_to_create.emplace_back(from_rr_node, to_node, to_switch); + rr_edges_to_create.emplace_back(from_rr_node, to_node, to_switch, false); ++num_conn; } } @@ -810,10 +810,10 @@ int get_unidir_opin_connections(RRGraphBuilder& rr_graph_builder, } /* Add to the list. */ - rr_edges_to_create.emplace_back(from_rr_node, inc_inode_index, seg_details[inc_track].arch_opin_switch()); + rr_edges_to_create.emplace_back(from_rr_node, inc_inode_index, seg_details[inc_track].arch_opin_switch(), false); ++num_edges; - rr_edges_to_create.emplace_back(from_rr_node, dec_inode_index, seg_details[dec_track].arch_opin_switch()); + rr_edges_to_create.emplace_back(from_rr_node, dec_inode_index, seg_details[dec_track].arch_opin_switch(), false); ++num_edges; } @@ -1603,7 +1603,7 @@ int get_track_to_pins(RRGraphBuilder& rr_graph_builder, /*int to_node = get_rr_node_index(L_rr_node_indices, x + width_offset, y + height_offset, IPIN, ipin, side);*/ RRNodeId to_node = rr_graph_builder.node_lookup().find_node(x, y, IPIN, ipin, side); if (to_node) { - rr_edges_to_create.emplace_back(from_rr_node, to_node, wire_to_ipin_switch); + rr_edges_to_create.emplace_back(from_rr_node, to_node, wire_to_ipin_switch, false); ++num_conn; } } @@ -1939,7 +1939,7 @@ static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, } /* Add the edge to the list */ - rr_edges_to_create.emplace_back(from_rr_node, to_node, switch_types[i]); + rr_edges_to_create.emplace_back(from_rr_node, to_node, switch_types[i], false); ++num_conn; } } @@ -2009,14 +2009,14 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, src_switch = switch_override; } - rr_edges_to_create.emplace_back(from_rr_node, to_node, src_switch); + rr_edges_to_create.emplace_back(from_rr_node, to_node, src_switch, false); ++edge_count; auto& device_ctx = g_vpr_ctx.device(); if (device_ctx.arch_switch_inf[src_switch].directionality() == BI_DIRECTIONAL) { //Add reverse edge since bi-directional - rr_edges_to_create.emplace_back(to_node, from_rr_node, src_switch); + rr_edges_to_create.emplace_back(to_node, from_rr_node, src_switch, false); ++edge_count; } } @@ -2107,13 +2107,13 @@ static int get_unidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, VTR_ASSERT(iswitch != OPEN); /* Add edge to list. */ - rr_edges_to_create.emplace_back(from_rr_node, to_node, iswitch); + rr_edges_to_create.emplace_back(from_rr_node, to_node, iswitch, false); ++count; auto& device_ctx = g_vpr_ctx.device(); if (device_ctx.arch_switch_inf[iswitch].directionality() == BI_DIRECTIONAL) { //Add reverse edge since bi-directional - rr_edges_to_create.emplace_back(to_node, from_rr_node, iswitch); + rr_edges_to_create.emplace_back(to_node, from_rr_node, iswitch, false); ++count; } } From 2a74a54c8a43b849919d65124afde948ba3b222b Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 27 May 2023 11:40:33 -0400 Subject: [PATCH 32/51] make format --- vpr/src/route/rr_graph.cpp | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 98a8bca78d0..c5c3b44c74d 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1351,7 +1351,7 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, expected_node_count, rr_graph.num_nodes()); } - if(!load_rr_graph) { + if (!load_rr_graph) { remap_rr_node_switch_indices(rr_graph_builder, g_vpr_ctx.device().switch_fanin_remap); } else { @@ -2576,14 +2576,14 @@ static void add_pb_edges(RRGraphBuilder& rr_graph_builder, pin_physical_num, conn_pin_physical_num); - if(is_remapped) { + if (is_remapped) { bool found = false; float delay = g_vpr_ctx.device().all_sw_inf.at(sw_idx).Tdel(); const auto& rr_switches = rr_graph_builder.rr_switch(); - for(int sw_id = 0; sw_id < (int)rr_switches.size(); sw_id++) { + for (int sw_id = 0; sw_id < (int)rr_switches.size(); sw_id++) { const auto& rr_switch = rr_switches[RRSwitchId(sw_id)]; - if(rr_switch.intra_tile) { - if(rr_switch.Tdel == delay) { + if (rr_switch.intra_tile) { + if (rr_switch.Tdel == delay) { sw_idx = sw_id; found = true; break; @@ -2758,17 +2758,17 @@ static void add_chain_node_fan_in_edges(RRGraphBuilder& rr_graph_builder, is_rr_sw_id, delay); - if(!is_rr_sw_id && is_new_sw) { + if (!is_rr_sw_id && is_new_sw) { // Currently we assume that if rr graph is read from a file, we shouldn't get into this block VTR_ASSERT(!load_rr_graph); // The internal edges are added after switch_fanin_remap is initialized; thus, if a new arch_sw is added, // switch _fanin_remap should be updated. t_rr_switch_inf rr_sw_inf = create_rr_switch_from_arch_switch(create_internal_arch_sw(delay), - R_minW_nmos, - R_minW_pmos); + R_minW_nmos, + R_minW_pmos); auto rr_sw_id = rr_graph_builder.add_rr_switch(rr_sw_inf); // If rr graph is loaded from a file, switch_fanin_remap is going to be empty - if(!load_rr_graph) { + if (!load_rr_graph) { auto& switch_fanin_remap = g_vpr_ctx.mutable_device().switch_fanin_remap; switch_fanin_remap.push_back({{UNDEFINED, size_t(rr_sw_id)}}); } @@ -4662,11 +4662,11 @@ static std::pair find_create_intra_cluster_sw(RRGraphBuilder& rr_grap float delay) { const auto& rr_graph_switches = rr_graph.rr_switch(); - if(is_rr_sw) { + if (is_rr_sw) { for (int rr_switch_id = 0; rr_switch_id < (int)rr_graph_switches.size(); rr_switch_id++) { const auto& rr_sw = rr_graph_switches[RRSwitchId(rr_switch_id)]; if (rr_sw.intra_tile) { - if(rr_sw.Tdel == delay) { + if (rr_sw.Tdel == delay) { return std::make_pair(false, rr_switch_id); } } From 3075f085fac9a2354e1989989f7d4cb736f27c82 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 29 May 2023 10:43:49 -0400 Subject: [PATCH 33/51] fix the comment about switch types written in rr graph xml/serialized files --- libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index be1d8bccbe3..d82ee1ec3df 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -460,9 +460,9 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { // // If the switch name is not present in the architecture, generate an // error. - // If the graph is written when flat-routing is enalbed, the types of the switches inside of the rr_graph are also - // added to the XML file. These types are not added the data structure that contain arch switch types. It's remained - // as a future work to remove the arch_switch_types and use all_sw info under device_ctx instead. + // If the graph is written when flat-routing is enabled, the types of the switches inside of the rr_graph are also + // added to the XML file. These types are not added to the data structure that contain arch switch types. They are added to all_sw_inf under dvice context. + // It remains as a future work to remove the arch_switch_types and use all_sw info under device_ctx instead. bool found_arch_name = false; std::string string_name = std::string(name); bool is_internal_sw = string_name.compare(0, 15, "Internal Switch") == 0; From e1f7a7f5211940431718dadd0b2ec4492a767ecd Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 29 May 2023 10:58:20 -0400 Subject: [PATCH 34/51] remove vtr_reg_qor_chain_large_flat_router - reduce the number of circuits of vtr_reg_qor_chain_depop_flat_router --- .../vtr_reg_nightly_test3/task_list.txt | 4 +-- .../config/config.txt | 16 --------- .../config/config.txt | 34 ------------------- .../config/golden_results.txt | 8 ----- 4 files changed, 2 insertions(+), 60 deletions(-) delete mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt index 1e0bfeabcc4..7524b980bed 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt @@ -1,6 +1,6 @@ regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop +regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off regression_tests/vtr_reg_nightly_test3/vtr_reg_qor -regression_tests/vtr_reg_nightly_test3/complex_switch -regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router +regression_tests/vtr_reg_nightly_test3/complex_switch \ No newline at end of file diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/config.txt index ac2b9426fd7..01eba58da65 100755 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/config.txt @@ -10,27 +10,11 @@ circuits_dir=benchmarks/verilog archs_dir=arch/timing # Add circuits to list to sweep -circuit_list_add=arm_core.v circuit_list_add=bgm.v -circuit_list_add=blob_merge.v -circuit_list_add=boundtop.v -circuit_list_add=ch_intrinsics.v -circuit_list_add=diffeq1.v -circuit_list_add=diffeq2.v circuit_list_add=LU8PEEng.v -circuit_list_add=LU32PEEng.v -circuit_list_add=mcml.v -circuit_list_add=mkDelayWorker32B.v -circuit_list_add=mkPktMerge.v -circuit_list_add=mkSMAdapter4B.v -circuit_list_add=or1200.v -circuit_list_add=raygentop.v -circuit_list_add=sha.v -circuit_list_add=spree.v circuit_list_add=stereovision0.v circuit_list_add=stereovision1.v circuit_list_add=stereovision2.v -circuit_list_add=stereovision3.v # Add architectures to list to sweep arch_list_add=k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt deleted file mode 100755 index be28691892d..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/config.txt +++ /dev/null @@ -1,34 +0,0 @@ -# -############################################ -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/timing - -# Add circuits to list to sweep -circuit_list_add=bgm.v -circuit_list_add=LU8PEEng.v -circuit_list_add=LU32PEEng.v -circuit_list_add=mcml.v -circuit_list_add=stereovision0.v -circuit_list_add=stereovision1.v -circuit_list_add=stereovision2.v - -# Add architectures to list to sweep -arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# How to parse QoR info -qor_parse_file=qor_large.txt - -# Pass requirements -pass_requirements_file=pass_requirements.txt - -#Script parameters -script_params=-track_memory_usage -max_router_iterations 300 --flat_routing true diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/golden_results.txt deleted file mode 100644 index fd0c1d9ce76..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large_flat_router/config/golden_results.txt +++ /dev/null @@ -1,8 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay 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1296.2 MiB 131.73 766930 1788.7 MiB 596.09 3.73 43.0057 -282861 -43.0057 43.0057 87.57 0.218254 0.18891 36.1992 29.359 148 1001428 23 5.4965e+08 4.44764e+08 8.56943e+07 9495.22 1225.82 131.981 106.963 4378636 44335993 2081177 966061 20 376908 1189879 169664636 27865893 67663219 6762625 102001417 21103268 0 0 867854 698918 676806 676806 1189879 1189879 5157733 676806 62260791 3273996 949088 303140 3344695 1599832 47768777 9696056 0 0 47449013 9750460 0 0 867854 0 6242650 1364611 2310107 2262183 5040607 345027 892783 46.8141 46.8141 -359572 -46.8141 0 0 1.08458e+08 12017.5 40.49 150.98 15.27 72.57 0.16 40.49 9.16862 7.35512 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 127.28 vpr 346.23 MiB -1 -1 10.56 98428 5 7.90 -1 -1 65520 -1 -1 710 169 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 354544 169 197 23321 21461 1 6583 1076 33 33 1089 clb auto 168.0 MiB 10.90 40334 228.2 MiB 9.08 0.08 3.01283 -13314.4 -3.01283 3.01283 5.11 0.028054 0.0239182 3.99064 3.31471 56 60560 28 6.0475e+07 3.82649e+07 4.09277e+06 3758.28 56.20 9.04569 7.48535 463449 3594119 232643 56239 15 38700 94881 6517908 766440 5239888 561748 1278020 204692 0 0 72476 66278 44180 44180 94881 94881 79186 44180 4781913 260256 75639 22199 290618 140333 539375 46824 0 0 539640 47309 0 0 72476 0 379173 106385 128995 132993 328781 24231 4977 3.70046 3.70046 -16276.1 -3.70046 0 0 5.21984e+06 4793.24 1.72 11.58 0.77 7.02 0.11 1.72 1.39265 1.15472 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 277.38 vpr 394.70 MiB -1 -1 8.11 120008 3 15.97 -1 -1 73340 -1 -1 680 115 0 40 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 404172 115 145 22868 19305 1 9678 980 40 40 1600 mult_36 auto 163.7 MiB 7.98 80732 223.6 MiB 6.85 0.07 4.99402 -21942.4 -4.99402 4.99402 7.16 0.0181466 0.0145557 2.362 1.95063 86 129273 33 9.16046e+07 5.24886e+07 8.98461e+06 5615.38 196.47 11.8555 9.8698 535763 4510540 226039 118186 16 49483 109186 28053062 4122103 5706126 637537 22346936 3484566 0 0 83174 77600 63700 63700 109186 109186 1515101 63700 5215541 296128 91599 40021 298225 154623 10253223 1649245 0 0 10423313 1667900 0 0 83174 0 422151 98582 268947 267443 540573 28101 6132 5.39751 5.39751 -25069.8 -5.39751 0 0 1.13675e+07 7104.67 3.44 14.51 1.80 7.09 0.11 3.44 0.6329 0.523497 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 1004.56 vpr 1.01 GiB -1 -1 11.90 194072 3 7.76 -1 -1 151220 -1 -1 1498 149 0 179 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1059916 149 182 55416 37075 1 28615 2008 80 80 6400 mult_36 auto 350.6 MiB 16.76 303233 914.6 MiB 41.03 0.47 14.3381 -49440 -14.3381 14.3381 72.10 0.109389 0.085899 7.80017 6.38216 98 414564 33 3.90281e+08 1.51617e+08 4.18005e+07 6531.32 717.94 52.6525 43.6926 1714224 14643438 501923 389094 20 128774 202471 56151273 8660521 10741265 1371048 45410008 7289473 0 0 178242 167301 132954 132954 202471 202471 2638012 132954 9799585 629092 183100 106120 560967 372184 21138915 3440129 0 0 21317027 3477316 0 0 178242 0 496143 148445 267958 274367 782492 25389 9286 15.1906 15.1906 -57297.7 -15.1906 0 0 5.30091e+07 8282.68 35.64 40.85 9.73 17.73 0.12 35.64 4.74661 3.94154 From 85289259c4d73293289abc821b6bc5ad0458cb29 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 29 May 2023 11:29:44 -0400 Subject: [PATCH 35/51] add vpr_verify_router_lookahead_flat_router --- .../vtr_reg_nightly_test2/task_list.txt | 3 +- .../config/config.txt | 30 +++++++++++++++++++ .../config/golden_results.txt | 6 ++++ 3 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt index bbce1041db8..7608ec00250 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt @@ -6,7 +6,8 @@ regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan -regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check +regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check +regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router/config/config.txt new file mode 100644 index 00000000000..67c2c9f502a --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router/config/config.txt @@ -0,0 +1,30 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=raygentop.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml +arch_list_add=k6_frac_N10_mem32K_40nm.xml +arch_list_add=k6_N10_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt +parse_file=vpr_parse_second_file.txt + +# How to parse QoR info +qor_parse_file=qor_rr_graph.txt + +# Pass requirements +pass_requirements_file=pass_requirements_verify_rr_graph.txt + +# Script parameters +script_params = -verify_inter_cluster_router_lookahead -verify_intra_cluster_router_lookahead --route_chan_width 130 --flat_routing true diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router/config/golden_results.txt new file mode 100644 index 00000000000..923229b832d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router/config/golden_results.txt @@ -0,0 +1,6 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 26.57 vpr 82.09 MiB -1 -1 4.09 45804 3 0.98 -1 -1 40164 -1 -1 112 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84056 236 305 3195 3007 1 1538 660 19 19 361 io auto 44.6 MiB 1.97 12550 82.1 MiB 2.18 0.03 4.23319 -2592.08 -4.23319 4.23319 0.09 0.00734041 0.00664649 0.800573 0.722627 22506 5369 14230 2808527 640885 1.72706e+07 8.96013e+06 2.90560e+06 8048.76 16 4.88723 4.88723 -2997.25 -4.88723 -6.66982 -0.193384 82.1 MiB 1.04 1.20892 1.10479 82.1 MiB 1.24 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 26.32 vpr 82.26 MiB -1 -1 3.75 46008 3 0.93 -1 -1 40016 -1 -1 120 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84232 236 305 3195 3007 1 1534 668 19 19 361 io auto 45.3 MiB 2.86 12092 82.3 MiB 2.03 0.03 4.31218 -2553.6 -4.31218 4.31218 0.07 0.00696218 0.00631702 0.765105 0.691642 19341 4478 11708 2097942 457216 1.72706e+07 9.39128e+06 2.71656e+06 7525.11 12 4.99952 4.99952 -3010.14 -4.99952 0 0 82.3 MiB 0.83 1.12422 1.027 82.3 MiB 1.15 + k6_frac_N10_mem32K_40nm.xml raygentop.v common 26.02 vpr 77.67 MiB -1 -1 4.82 49248 8 1.50 -1 -1 41880 -1 -1 116 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 79536 235 305 2594 2755 1 1443 663 19 19 361 io auto 39.9 MiB 2.23 11448 77.7 MiB 1.82 0.03 4.41088 -2430.87 -4.41088 4.41088 0.08 0.00649293 0.00576414 0.647429 0.579732 18768 3833 11059 1989583 427191 1.72706e+07 9.1757e+06 2.71663e+06 7525.28 11 5.29026 5.29026 -2756.74 -5.29026 -8.67533 -0.17036 77.7 MiB 0.75 0.955384 0.866802 77.7 MiB 1.18 + k6_N10_mem32K_40nm.xml raygentop.v common 25.03 vpr 76.39 MiB -1 -1 4.72 48856 8 1.50 -1 -1 41792 -1 -1 165 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 78228 235 305 2594 2755 1 1461 712 19 19 361 io auto 38.7 MiB 0.95 12269 76.4 MiB 1.85 0.03 4.59709 -2576.68 -4.59709 4.59709 0.09 0.00642268 0.00566871 0.591253 0.53058 18465 7376 21416 6225690 1224003 1.72706e+07 1.18165e+07 2.57233e+06 7125.57 19 4.96959 4.96959 -2849.65 -4.96959 -0.0066982 -0.0066982 76.4 MiB 1.84 0.995979 0.901619 76.4 MiB 1.10 + hard_fpu_arch_timing.xml raygentop.v common 389.64 vpr 322.97 MiB -1 -1 36.07 182560 40 111.52 -1 -1 74952 -1 -1 3776 235 -1 -1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 330724 235 305 20496 20801 1 8995 4316 68 68 4624 clb auto 158.1 MiB 4.44 176765 323.0 MiB 49.61 0.36 22.409 -30564.1 -22.409 22.409 1.35 0.0561504 0.0436831 6.55008 5.20912 249819 53589 173978 17781644 1967620 9.87441e+06 8.65503e+06 1.89440e+07 4096.88 23 25.1849 25.1849 -37219.3 -25.1849 -0.1702 -0.0851 323.0 MiB 8.47 9.92861 8.04481 323.0 MiB 16.99 From 8a514af519bc84a23e12650cc951479d3b1273fe Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 31 May 2023 12:00:28 -0400 Subject: [PATCH 36/51] comment out vpr_verify_router_lookahead_flat_router --- .../tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt index 7608ec00250..32f33563996 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt @@ -7,7 +7,7 @@ regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check -regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router +#regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router @TODO: fix this test regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc From e9292cdd8b8bc04261caf391e2d76dbd480688e0 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 31 May 2023 12:01:33 -0400 Subject: [PATCH 37/51] update titan_other_flat_router golden results --- .../config/golden_results.txt | 41 +++++++++---------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt index 97c1aad1792..4a85f6cb8b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt @@ -1,23 +1,20 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops total_internal_heap_pushes total_internal_heap_pops total_external_heap_pushes total_external_heap_pops total_external_SOURCE_pushes total_external_SOURCE_pops total_internal_SOURCE_pushes total_internal_SOURCE_pops total_external_SINK_pushes total_external_SINK_pops total_internal_SINK_pushes total_internal_SINK_pops total_external_IPIN_pushes total_external_IPIN_pops total_internal_IPIN_pushes total_internal_IPIN_pops total_external_OPIN_pushes total_external_OPIN_pops total_internal_OPIN_pushes total_internal_OPIN_pops total_external_CHANX_pushes total_external_CHANX_pops total_internal_CHANX_pushes total_internal_CHANX_pops total_external_CHANY_pushes total_external_CHANY_pops total_internal_CHANY_pushes total_internal_CHANY_pops rt_node_SOURCE_pushes rt_node_SINK_pushes rt_node_IPIN_pushes rt_node_OPIN_pushes rt_node_CHANX_pushes rt_node_CHANY_pushes rt_node_SOURCE_high_fanout_pushes rt_node_SINK_high_fanout_pushes rt_node_IPIN_high_fanout_pushes rt_node_OPIN_high_fanout_pushes rt_node_CHANX_high_fanout_pushes rt_node_CHANY_high_fanout_pushes rt_node_SOURCE_entire_tree_pushes rt_node_SINK_entire_tree_pushes rt_node_IPIN_entire_tree_pushes rt_node_OPIN_entire_tree_pushes rt_node_CHANX_entire_tree_pushes rt_node_CHANY_entire_tree_pushes adding_all_rt adding_high_fanout_rt total_number_of_adding_all_rt_from_calling_high_fanout_rt logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 397.37 vpr 5.57 GiB 274 964 36 59 0 2 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5836908 22 252 53001 29054 7 24705 1335 89 66 5874 DSP auto 1505.7 MiB 24.27 269580 1947.7 MiB 39.42 0.30 7.32923 -37591.9 -6.32923 3.01568 66.59 0.0888908 0.0746767 11.4126 9.61317 364926 6.88930 79916 1.50870 131101 312764 340522066 55078817 24597514 3009404 315924552 52069413 0 0 291215 234770 200434 200434 312764 312764 18296371 200585 21665942 879835 18600105 11887810 2327593 1582035 136916299 21561190 0 0 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/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5618512 84 171 36458 36247 3 20325 2381 62 46 2852 LAB auto 1548.3 MiB 69.97 303330 1687.8 MiB 37.44 0.39 11.9196 -83773.9 -10.9196 4.04427 14.36 0.132607 0.101782 10.8207 8.40214 398226 10.9271 87692 2.40621 123842 564801 167310471 18192679 53960497 4110868 113349974 14081811 0 0 307109 236137 361475 361475 564801 564801 678121 361861 50331389 1672061 13736914 9592183 2757198 1637869 48875198 2291186 0 0 49698266 1475106 0 0 307109 0 2971412 851541 1916699 2534432 16164 0 2562289 76396 1156292 1432006 290945 0 409123 775145 760407 1102426 3389652 276320 109434 0 0 5.24521e+07 18391.3 15 2648834 32075053 67963 13.0952 4.35646 -96470.2 -12.0952 0 0 9.71 20.31 12.19 5486.7 MiB 109.22 13.6536 10.6379 1656.7 MiB 57.69 32.88 -stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 517.60 vpr 6.06 GiB 69 2109 10 295 16 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 6359192 36 33 57796 49182 1 20302 2499 105 78 8190 M9K auto 1687.6 MiB 64.24 255267 2275.1 MiB 46.19 0.36 9.35492 -95224.2 -8.35491 9.35492 101.14 0.0983987 0.0765974 14.0923 11.1167 297772 5.15257 65489 1.13320 138698 534206 179726792 22789061 44003537 3968357 135723255 18820704 0 0 277384 228734 317174 317174 534206 534206 4110535 317328 40626007 1555580 14644781 9187904 2565940 1649837 57855252 4969007 0 0 58795513 4029291 0 0 277384 0 5274569 643515 1301261 1638368 15349 0 4892308 73607 812672 1029370 262035 0 382261 569908 488589 608998 2206188 273649 235655 0 0 1.50986e+08 18435.5 51 4803563 52656588 69228 9.02316 9.02316 -164426 -8.02316 0 0 26.90 40.71 25.20 6209.9 MiB 145.30 22.8055 18.2452 2275.1 MiB 57.44 109.93 -stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 462.89 vpr 6.06 GiB 478 1236 1 300 4 0 success v8.0.0-7583-g7e3566081-dirty release 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common 550.35 vpr 5.76 GiB 693 1763 25 16 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 6043604 35 658 51416 37539 1 27797 2497 108 80 8640 io auto 1602.4 MiB 58.69 263384 2286.5 MiB 56.79 0.45 37.4295 -59314.7 -36.4295 37.4295 127.13 0.0992586 0.0883531 14.0439 11.5407 356674 7.14706 82935 1.66186 121700 480778 310304321 44162535 44300947 5399761 266003374 38762774 0 0 442428 316964 302373 302373 480778 480778 6723674 302383 38878399 1410216 25310901 19974366 4499342 3191803 114294622 10711834 0 0 119371804 7471818 0 0 442428 0 1797249 1518337 708983 963976 13353 0 588504 68430 160815 207161 429075 0 1208745 1449907 548168 756815 4802809 51989 4094 0 0 1.59377e+08 18446.5 31 4400944 49964640 86213 37.6914 37.6914 -64101.1 -36.6914 0 0 28.11 26.94 14.44 5902.0 MiB 139.45 20.1053 16.5771 2286.5 MiB 56.73 118.68 -stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 474.32 vpr 5.42 GiB 753 1119 5 32 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5686764 13 740 25173 25306 1 12707 1909 117 87 10179 io auto 1429.3 MiB 42.14 160421 2334.5 MiB 20.37 0.17 9.33649 -29321.2 -8.33649 7.56912 125.09 0.0506562 0.0441953 6.53721 5.23634 193158 7.67536 41564 1.65159 67476 313409 107899554 12310327 30381749 2680717 77517805 9629610 0 0 260246 181616 197187 197187 313409 313409 455598 197263 27554717 917228 12166070 7743141 2253377 1268464 32176966 1027113 0 0 32521984 464906 0 0 260246 0 944198 878499 608037 845909 8926 0 294666 40971 264425 345569 251320 0 649532 837528 343612 500340 2822052 62397 4617 0 0 1.87947e+08 18464.1 33 4146327 46175295 62070 9.54099 7.47782 -41296 -8.54099 0 0 32.99 20.17 9.81 5553.5 MiB 98.25 9.87811 7.95687 2334.5 MiB 57.11 137.60 -stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 337.15 vpr 5.42 GiB 117 2147 0 0 0 0 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5684028 79 38 66795 54922 1 36234 2264 62 46 2852 LAB auto 1671.2 MiB 66.64 269541 1780.5 MiB 68.81 0.54 9.96451 -173664 -8.96451 9.96451 13.51 0.113654 0.0868329 12.4513 9.65013 350246 5.24383 83483 1.24990 177924 571973 269846522 37732003 54248169 6323863 215598353 31408140 0 0 494219 390139 320718 320718 571973 571973 783226 328049 48004061 1709635 30354130 22709319 5177916 3652116 91010192 5633984 0 0 93130087 2416070 0 0 494219 0 3093048 1372239 804905 1096083 11313 0 824351 53485 378403 443558 482906 0 2268697 1318754 426502 652525 5906325 89996 37746 0 0 5.24521e+07 18391.3 38 3374324 35994372 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9648796 88252 32101 0 0 7.74195e+07 18433.2 25 3167795 32633349 56854 5.28864 5.28864 -65430.6 -4.28864 0 0 13.76 18.36 11.00 5465.0 MiB 118.60 16.3772 13.5093 1833.2 MiB 56.08 46.40 -stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 163.88 vpr 5.08 GiB 54 667 0 40 0 1 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5322096 2 52 16673 16662 2 12034 762 37 27 999 LAB auto 1352.2 MiB 28.63 178472 1441.3 MiB 9.59 0.10 5.60745 -20515.1 -4.60745 4.78078 2.47 0.0399486 0.0312342 3.68041 2.92311 231825 13.9076 53439 3.20589 69687 374721 168159490 20625018 35369913 3185824 132789577 17439194 0 0 293818 210488 226502 226502 374721 374721 553099 226511 32156204 1065158 11794598 9184856 2545170 1535457 59875053 4551330 0 0 60340325 3249995 0 0 293818 0 1868083 1063479 856312 1172748 5396 0 1419030 29807 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/root/vtr-verilog-to-routing/vtr-verilog-to-routing 6478596 202 276 35125 30509 3 21529 2019 106 79 8374 M9K auto 1502.9 MiB 88.41 272765 2200.2 MiB 72.79 0.54 9.19202 -37842.6 -8.19202 3.20486 190.05 0.152211 0.112097 18.8747 14.2554 321153 9.14471 66385 1.89029 100068 414752 157765195 23476080 34300621 3443454 123464574 20032626 0 0 380002 234539 227242 227242 414752 414752 645006 227374 30592761 1126998 23059023 16098127 2913106 1667165 49596947 2101209 0 0 49936356 1378674 0 0 380002 0 2239906 1263651 886120 1197078 17025 0 745824 80126 161479 232461 362977 0 1494082 1183525 724641 964617 5471532 52141 12195 0 0 1.54360e+08 18433.2 20 3958220 42984491 64532 7.91139 3.47325 -67174.2 -6.91139 0 0 45.25 64.76 45.68 6326.8 MiB 206.73 26.3683 20.2581 2200.2 MiB 87.53 216.41 +stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 533.90 vpr 5.39 GiB 5 331 31 105 0 2 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5649024 3 2 14862 10304 26 7485 474 89 66 5874 DSP auto 1321.0 MiB 43.11 125450 1838.3 MiB 13.87 0.14 5.8049 -30200.5 -4.8049 3.81023 134.63 0.0801368 0.0622523 7.83848 6.28028 149562 10.0810 29852 2.01213 42275 171541 55874626 6342617 13497784 1013659 42376842 5328958 0 0 82571 62876 57398 57398 171541 171541 1368476 57398 12637823 432299 3698819 2360987 605849 346943 18576038 1575874 0 0 18676111 1277301 0 0 82571 0 3058530 168485 355362 469549 2856 0 2860226 13832 191857 308956 79715 0 198304 154653 163505 160593 844858 92266 6927 0 0 1.08076e+08 18399.1 15 2294013 23927517 37921 4.65543 3.70469 -39979.2 -3.65543 0 0 33.81 34.31 23.09 5516.6 MiB 143.82 10.704 8.72846 1838.3 MiB 88.05 138.55 +stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 982.22 vpr 5.89 GiB 693 1763 25 16 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6181084 35 658 51416 37539 1 27797 2497 108 80 8640 io auto 1608.7 MiB 97.35 253700 2292.8 MiB 137.07 1.03 36.6178 -57981.3 -35.6178 36.6178 188.71 0.216948 0.172494 28.1745 22.387 342704 6.86713 79905 1.60114 147879 604761 355456965 49730892 56242397 6818146 299214568 42912746 0 0 569044 415415 379482 379482 604761 604761 7147933 379648 49043058 1780714 33506965 23806571 6025534 4017256 127359105 10638500 0 0 130821083 7708545 0 0 569044 0 2194580 2040073 774389 1241923 19004 0 618226 95542 152225 241684 550040 0 1576354 1944531 622164 1000239 6224066 54966 4101 0 0 1.59377e+08 18446.5 30 4400944 49964640 86213 36.9882 36.9882 -62153.7 -35.9882 0 0 47.43 48.23 30.53 6036.2 MiB 254.66 41.7569 33.7374 2292.8 MiB 83.42 222.18 +stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 889.54 vpr 5.52 GiB 753 1119 5 32 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5787504 13 740 25173 25306 1 12707 1909 117 87 10179 io auto 1437.6 MiB 73.19 158034 2342.4 MiB 49.35 0.37 9.0794 -29604.5 -8.0794 7.71568 222.23 0.100307 0.0852136 12.5514 9.86111 193121 7.67389 42189 1.67643 68666 318011 113363267 12851301 30536084 2692879 82827183 10158422 0 0 263048 182024 199766 199766 318011 318011 583589 199819 27704779 929336 12145303 7855017 2250246 1263508 34922315 1239693 0 0 34976210 664127 0 0 263048 0 963421 881555 640303 841712 9439 0 312458 41087 260847 322454 253609 0 650963 840468 379456 519258 2886477 64695 4536 0 0 1.87947e+08 18464.1 52 4146327 46175295 62070 8.10698 7.61424 -41591.4 -7.10698 0 0 58.60 39.13 19.80 5651.9 MiB 171.85 24.1564 19.2466 2342.4 MiB 84.92 284.07 +stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 559.00 vpr 5.47 GiB 213 1559 26 4 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5740704 139 74 57121 41054 1 24028 1802 75 56 4200 DSP auto 1617.5 MiB 89.74 173770 1898.2 MiB 87.12 0.73 5.20056 -21125.5 -4.20056 5.20056 33.04 0.187168 0.159192 24.0201 19.5353 224393 3.92866 53407 0.935046 120332 318885 164347721 23845710 27853588 2583308 136494133 21262402 0 0 250265 196712 167434 167434 318885 318885 5773170 167546 25346412 929536 12885884 7251282 1938026 1138175 57986619 7508634 0 0 59681026 6167506 0 0 250265 0 2397225 564454 683963 792564 18687 0 1693953 88421 341436 374993 231578 0 703272 476033 342527 417571 2388860 87603 20079 0 0 7.74195e+07 18433.2 19 3167795 32633349 56854 5.56045 5.56045 -67348.3 -4.56045 0 0 28.05 36.96 24.00 5606.2 MiB 192.27 32.8036 26.9313 1843.7 MiB 87.90 92.61 +stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 293.00 vpr 5.17 GiB 54 667 0 40 0 1 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5418440 2 52 16673 16662 2 12034 762 37 27 999 LAB auto 1362.8 MiB 50.95 180205 1523.6 MiB 23.86 0.26 5.54068 -21652.7 -4.54068 4.89195 5.87 0.0994218 0.0746617 8.59683 6.58275 231884 13.9111 53316 3.19851 68185 368628 159574746 19219539 34743038 3070245 124831708 16149294 0 0 286491 201060 223149 223149 368628 368628 537575 223149 31640299 1049028 11336066 8724196 2447620 1451529 56194239 4012681 0 0 56540679 2966119 0 0 286491 0 1847460 1033627 856189 1214055 4819 0 1415998 29957 259201 442979 281672 0 431462 1003670 596988 771076 3208758 87191 7627 0 0 1.81152e+07 18133.3 19 1111277 11680547 35180 5.83088 5.25163 -27116.6 -4.83088 0 0 6.22 19.75 14.37 5291.4 MiB 160.20 12.6556 9.88051 1363.0 MiB 89.47 19.98 +stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 707.98 vpr 6.13 GiB 445 2165 19 51 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6431256 131 314 57881 45152 1 32949 2680 73 54 3942 io auto 1709.7 MiB 113.42 319720 1953.7 MiB 181.54 1.65 195.879 -69216.9 -194.879 195.879 39.78 0.252116 0.197507 29.0133 22.8181 423129 7.31968 101694 1.75920 148456 639588 260866551 30599295 59753838 5877781 201112713 24721514 0 0 559292 339631 402428 402428 639588 639588 2389955 402429 53761488 1867973 23404058 17589918 4793470 3030589 86461742 4105384 0 0 88454530 2221355 0 0 559292 0 3072021 1978568 1619414 2293719 11881 0 1547575 57250 306957 398241 547411 0 1524446 1921318 1312457 1895478 7735497 92623 9144 0 0 7.26339e+07 18425.6 21 3424933 39491074 105365 187.99 187.99 -80162.4 -186.99 0 0 21.71 56.34 39.83 6280.5 MiB 227.45 40.5696 32.2386 1865.9 MiB 85.65 87.02 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 204.59 vpr 4.71 GiB 42 750 0 0 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 4934484 13 29 26295 20086 1 12166 792 39 29 1131 LAB auto 1355.8 MiB 18.26 79073 1499.4 MiB 12.67 0.17 4.99447 -4598.46 -3.99447 2.56728 9.74 0.0408075 0.0306573 3.08024 2.36323 84706 3.22162 19939 0.758339 53380 71551 35810607 4346308 7169692 721973 28640915 3624335 0 0 70074 64306 39683 39683 71551 71551 77213 39683 6428768 207974 3822355 2587809 599299 378142 12329998 582963 0 0 12371666 374197 0 0 70074 0 32280 78309 77684 88810 486 0 9331 2407 8564 9172 69588 0 22949 75902 69120 79638 324991 1976 169 0 0 2.05958e+07 18210.3 16 1246346 12342987 13974 3.67397 2.78594 -5489.42 -2.67397 0 0 8.33 14.11 8.43 4818.8 MiB 108.70 4.56965 3.56741 1356.1 MiB 83.19 22.11 +stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 1440.68 vpr 5.95 GiB 964 975 19 34 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6243852 542 422 37277 26038 1 20638 1992 147 109 16023 io auto 1457.3 MiB 68.11 265616 2957.8 MiB 130.84 1.32 9.50199 -37449.9 -8.50199 7.76547 446.34 0.154323 0.122043 19.4004 15.4157 346368 9.29248 74610 2.00166 111681 335798 225684897 32982492 30145170 2987038 195539727 29995454 0 0 285411 214827 225188 225188 335798 335798 7773731 225235 27183983 965579 15041522 10398103 2339978 1470834 85189134 10535986 0 0 87310152 8610942 0 0 285411 0 1400706 804069 776939 980670 22123 0 858991 118238 336761 389597 263288 0 541715 685831 440178 591073 2711363 72825 6767 0 0 2.96650e+08 18514.0 44 5879056 65354821 47001 9.73561 8.3395 -52222.9 -8.73561 0 0 86.75 54.56 25.72 6097.5 MiB 231.36 32.2214 26.2723 2957.8 MiB 88.18 446.38 +stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 1746.53 vpr 5.80 GiB 1107 721 0 0 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6083664 403 704 15490 16194 1 8416 1828 167 124 20708 io auto 1355.1 MiB 59.70 189937 3390.6 MiB 33.55 0.28 11.9901 -21784.8 -10.9901 5.40422 745.67 0.0774104 0.0592605 9.01753 7.02446 228761 14.7693 38073 2.45807 42292 231691 73919422 8177400 21781227 1880323 52138195 6297077 0 0 179143 127127 152350 152350 231691 231691 304289 152359 19911029 688047 7966938 4884142 1459364 833458 21686811 720452 0 0 22027807 387774 0 0 179143 0 779210 618357 483897 682252 1996 0 247223 9903 230558 278915 177147 0 531987 608454 253339 403337 2129825 55069 11488 0 0 3.84012e+08 18544.1 17 6720933 74598148 36972 11.192 5.69083 -32768.9 -10.192 0 0 117.06 43.71 12.36 5941.1 MiB 160.29 12.0424 9.52154 3390.6 MiB 87.90 601.39 +stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 271.24 vpr 4.73 GiB 35 735 0 6 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 4958080 18 17 16969 16357 1 6386 776 39 29 1131 LAB auto 1350.4 MiB 61.78 83840 1500.3 MiB 14.04 0.21 6.69002 -41482 -5.69002 6.69002 10.03 0.0619772 0.0441029 4.77898 3.5581 116545 6.86973 27597 1.62670 47883 252762 83846950 9755433 24060813 2054513 59786137 7700920 0 0 145109 104792 184133 184133 252762 252762 320376 184144 22206371 749723 6773270 5256108 1456571 947236 26101354 1343417 0 0 26407004 733118 0 0 145109 0 1178090 448604 746438 874371 6074 0 935259 29306 435121 518151 139035 0 242831 419298 311317 356220 1551320 114680 27537 0 0 2.05958e+07 18210.3 30 1091507 12261694 43464 6.85394 6.85394 -47185.7 -5.85394 0 0 7.05 14.75 9.46 4841.9 MiB 131.10 8.66982 6.72886 1353.0 MiB 87.46 22.50 +stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 125.86 vpr 4.39 GiB 35 73 0 8 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 4607904 18 17 2291 2142 1 1503 116 16 12 192 LAB M9K auto 1226.0 MiB 7.00 10808 1365.9 MiB 1.13 0.01 5.25051 -3435.86 -4.25051 3.99423 0.15 0.0070996 0.00573146 0.317067 0.264439 13948 6.09615 3632 1.58741 7914 29770 10780049 1264163 2669793 257383 8110256 1006780 0 0 26363 18472 14372 14372 29770 29770 36350 14372 2392345 83326 1249561 819040 221315 125815 3374574 124258 0 0 3435399 34738 0 0 26363 0 153861 83288 39697 53152 1858 0 66279 9230 16797 20121 24505 0 87582 74058 22900 33031 287300 5297 110 0 0 3.35078e+06 17452.0 35 153885 1496224 4500 4.15507 4.15507 -3815.27 -3.15507 0 0 1.38 2.79 2.05 4499.9 MiB 95.33 0.921783 0.783739 1264.3 MiB 88.82 1.02 From 0cdf182ea0fdcd11120a9e69c9f486d09eb1aaca Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 31 May 2023 12:01:56 -0400 Subject: [PATCH 38/51] update vpr_verify_rr_graph_flat_router golden results --- .../config/golden_results.txt | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/golden_results.txt index 923229b832d..89bfddf4c2a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router/config/golden_results.txt @@ -1,6 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 26.57 vpr 82.09 MiB -1 -1 4.09 45804 3 0.98 -1 -1 40164 -1 -1 112 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84056 236 305 3195 3007 1 1538 660 19 19 361 io auto 44.6 MiB 1.97 12550 82.1 MiB 2.18 0.03 4.23319 -2592.08 -4.23319 4.23319 0.09 0.00734041 0.00664649 0.800573 0.722627 22506 5369 14230 2808527 640885 1.72706e+07 8.96013e+06 2.90560e+06 8048.76 16 4.88723 4.88723 -2997.25 -4.88723 -6.66982 -0.193384 82.1 MiB 1.04 1.20892 1.10479 82.1 MiB 1.24 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 26.32 vpr 82.26 MiB -1 -1 3.75 46008 3 0.93 -1 -1 40016 -1 -1 120 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84232 236 305 3195 3007 1 1534 668 19 19 361 io auto 45.3 MiB 2.86 12092 82.3 MiB 2.03 0.03 4.31218 -2553.6 -4.31218 4.31218 0.07 0.00696218 0.00631702 0.765105 0.691642 19341 4478 11708 2097942 457216 1.72706e+07 9.39128e+06 2.71656e+06 7525.11 12 4.99952 4.99952 -3010.14 -4.99952 0 0 82.3 MiB 0.83 1.12422 1.027 82.3 MiB 1.15 - k6_frac_N10_mem32K_40nm.xml raygentop.v common 26.02 vpr 77.67 MiB -1 -1 4.82 49248 8 1.50 -1 -1 41880 -1 -1 116 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 79536 235 305 2594 2755 1 1443 663 19 19 361 io auto 39.9 MiB 2.23 11448 77.7 MiB 1.82 0.03 4.41088 -2430.87 -4.41088 4.41088 0.08 0.00649293 0.00576414 0.647429 0.579732 18768 3833 11059 1989583 427191 1.72706e+07 9.1757e+06 2.71663e+06 7525.28 11 5.29026 5.29026 -2756.74 -5.29026 -8.67533 -0.17036 77.7 MiB 0.75 0.955384 0.866802 77.7 MiB 1.18 - k6_N10_mem32K_40nm.xml raygentop.v common 25.03 vpr 76.39 MiB -1 -1 4.72 48856 8 1.50 -1 -1 41792 -1 -1 165 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 78228 235 305 2594 2755 1 1461 712 19 19 361 io auto 38.7 MiB 0.95 12269 76.4 MiB 1.85 0.03 4.59709 -2576.68 -4.59709 4.59709 0.09 0.00642268 0.00566871 0.591253 0.53058 18465 7376 21416 6225690 1224003 1.72706e+07 1.18165e+07 2.57233e+06 7125.57 19 4.96959 4.96959 -2849.65 -4.96959 -0.0066982 -0.0066982 76.4 MiB 1.84 0.995979 0.901619 76.4 MiB 1.10 - hard_fpu_arch_timing.xml raygentop.v common 389.64 vpr 322.97 MiB -1 -1 36.07 182560 40 111.52 -1 -1 74952 -1 -1 3776 235 -1 -1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 330724 235 305 20496 20801 1 8995 4316 68 68 4624 clb auto 158.1 MiB 4.44 176765 323.0 MiB 49.61 0.36 22.409 -30564.1 -22.409 22.409 1.35 0.0561504 0.0436831 6.55008 5.20912 249819 53589 173978 17781644 1967620 9.87441e+06 8.65503e+06 1.89440e+07 4096.88 23 25.1849 25.1849 -37219.3 -25.1849 -0.1702 -0.0851 323.0 MiB 8.47 9.92861 8.04481 323.0 MiB 16.99 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops total_internal_heap_pushes total_internal_heap_pops total_external_heap_pushes total_external_heap_pops total_external_SOURCE_pushes total_external_SOURCE_pops total_internal_SOURCE_pushes total_internal_SOURCE_pops total_external_SINK_pushes total_external_SINK_pops total_internal_SINK_pushes total_internal_SINK_pops total_external_IPIN_pushes total_external_IPIN_pops total_internal_IPIN_pushes total_internal_IPIN_pops total_external_OPIN_pushes total_external_OPIN_pops total_internal_OPIN_pushes total_internal_OPIN_pops total_external_CHANX_pushes total_external_CHANX_pops total_internal_CHANX_pushes total_internal_CHANX_pops total_external_CHANY_pushes total_external_CHANY_pops total_internal_CHANY_pushes total_internal_CHANY_pops rt_node_SOURCE_pushes rt_node_SINK_pushes rt_node_IPIN_pushes rt_node_OPIN_pushes rt_node_CHANX_pushes rt_node_CHANY_pushes rt_node_SOURCE_high_fanout_pushes rt_node_SINK_high_fanout_pushes rt_node_IPIN_high_fanout_pushes rt_node_OPIN_high_fanout_pushes rt_node_CHANX_high_fanout_pushes rt_node_CHANY_high_fanout_pushes rt_node_SOURCE_entire_tree_pushes rt_node_SINK_entire_tree_pushes rt_node_IPIN_entire_tree_pushes rt_node_OPIN_entire_tree_pushes rt_node_CHANX_entire_tree_pushes rt_node_CHANY_entire_tree_pushes adding_all_rt adding_high_fanout_rt total_number_of_adding_all_rt_from_calling_high_fanout_rt logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 34.63 vpr 89.45 MiB -1 -1 4.17 44324 3 0.99 -1 -1 40052 -1 -1 120 236 1 6 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 91592 236 305 3195 3007 1 1534 668 19 19 361 io auto 51.5 MiB 3.06 12599 88.1 MiB 2.53 0.03 4.24001 -2559.11 -4.24001 4.24001 0.08 0.00703497 0.00627172 0.802031 0.712049 19974 6.26734 5280 1.65673 6526 18770 3689605 528791 1030973 111808 2658632 416983 0 0 16730 12773 14146 14146 18770 18770 224557 14146 936825 46119 21173 8605 58648 34146 1211508 184522 0 0 1187248 195564 0 0 16730 0 40770 29717 38660 37282 376 0 18525 1308 12079 8421 16354 0 22245 28409 26581 28861 132774 2435 210 1.72706e+07 9.39128e+06 2.71656e+06 7525.11 12 96193 892470 34148 5.01727 5.01727 -2984.54 -5.01727 0 0 0.53 2.34 1.97 89.4 MiB 4.11 1.03305 0.916665 88.1 MiB 0.19 1.20 + k6_frac_N10_mem32K_40nm.xml raygentop.v common 31.48 vpr 84.21 MiB -1 -1 5.23 47816 8 1.57 -1 -1 39848 -1 -1 116 235 1 6 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 86228 235 305 2594 2755 1 1443 663 19 19 361 io auto 45.8 MiB 2.27 11299 84.2 MiB 1.97 0.03 4.34768 -2449.09 -4.34768 4.34768 0.08 0.00676897 0.00595337 0.614033 0.544589 18412 7.11712 4900 1.89409 5321 18506 2801879 378042 1030672 105034 1771207 273008 0 0 16834 12903 13221 13221 18506 18506 154960 13221 934222 42356 22545 7768 61110 31269 791918 117393 0 0 788563 121405 0 0 16834 0 41203 33014 29458 31077 138 0 14120 408 7178 6802 16696 0 27083 32606 22280 24275 133920 1822 78 1.72706e+07 9.1757e+06 2.71663e+06 7525.28 12 84433 860913 20615 5.00924 5.00924 -2770.59 -5.00924 0 0 0.50 1.98 1.66 84.2 MiB 3.28 0.834215 0.742088 84.2 MiB 0.10 1.16 + k6_N10_mem32K_40nm.xml raygentop.v common 30.60 vpr 81.84 MiB -1 -1 5.30 47740 8 1.66 -1 -1 40352 -1 -1 165 235 1 6 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 83808 235 305 2594 2755 1 1461 712 19 19 361 io auto 44.2 MiB 1.01 12332 81.8 MiB 2.37 0.03 4.70207 -2540.5 -4.70207 4.70207 0.10 0.00690155 0.0061386 0.684322 0.606061 19350 7.47971 5182 2.00309 4886 17328 2712776 345540 1018367 90671 1694409 254869 0 0 15725 11657 13191 13191 17328 17328 144955 13191 928553 33418 21186 6632 56761 28268 760040 108620 0 0 755037 113235 0 0 15725 0 29034 31368 29626 28102 101 0 7343 270 6792 6097 15624 0 21691 31098 22834 22005 123960 1713 51 1.72706e+07 1.18165e+07 2.57233e+06 7125.57 11 75944 916321 23401 5.96046 5.96046 -2896.81 -5.96046 0 0 0.50 2.39 2.10 81.8 MiB 3.54 0.89765 0.797281 81.8 MiB 0.05 1.18 From 1755af347d16a72a4acb201ca3dfb0817debfc6a Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 31 May 2023 12:02:28 -0400 Subject: [PATCH 39/51] update vtr_reg_qor_chain_depop_flat_router golden results --- .../config/golden_results.txt | 28 ++++--------------- 1 file changed, 6 insertions(+), 22 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt index ea0cc60756b..baab5c7b203 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt @@ -1,22 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml arm_core.v common 429.79 vpr 254.70 MiB -1 -1 32.42 122848 20 86.82 -1 -1 71680 -1 -1 678 133 25 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 260812 133 179 14247 14104 1 6984 1015 36 36 1296 memory auto 147.2 MiB 26.63 111456 179.0 MiB 17.66 0.16 19.665 -203737 -19.665 19.665 5.60 0.0429621 0.0375059 4.90513 4.1347 152 203246 41 7.21828e+07 5.02408e+07 1.27723e+07 9855.19 214.08 19.1503 16.0569 185209 16 34107 142030 48694183 11050030 22.5669 22.5669 -223183 -22.5669 -12.1191 -0.298787 1.60965e+07 12420.2 7.25 17.31 2.24903 2.0136 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 735.73 vpr 662.53 MiB -1 -1 58.22 622020 14 114.17 -1 -1 123204 -1 -1 2287 257 0 11 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 678428 257 32 35747 33389 1 18576 2587 58 58 3364 clb auto 359.9 MiB 46.94 234717 662.5 MiB 82.06 0.67 16.3459 -23011.6 -16.3459 16.3459 53.94 0.0961719 0.0843983 11.5433 9.4886 112 491136 48 2.00088e+08 1.27615e+08 2.63593e+07 7835.69 285.87 52.0061 42.87 446327 21 106559 504329 46711743 8499063 18.542 18.542 -25879.4 -18.542 0 0 3.33056e+07 9900.58 15.58 19.26 6.25695 5.48481 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml blob_merge.v common 162.27 yosys 260.25 MiB -1 -1 15.45 266492 5 6.76 -1 -1 57560 -1 -1 457 36 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 141992 36 100 10175 7629 1 2974 593 27 27 729 clb auto 101.2 MiB 18.82 41977 136.7 MiB 6.20 0.06 13.8427 -2247.93 -13.8427 13.8427 3.43 0.0237759 0.0214548 2.4615 2.16881 98 90444 47 3.93038e+07 2.46296e+07 4.82856e+06 6623.53 92.63 9.54464 8.07035 77075 18 14547 73925 5506747 1013913 15.2896 15.2896 -2658.37 -15.2896 0 0 6.08869e+06 8352.11 3.03 2.99 1.405 1.23705 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml boundtop.v common 26.29 vpr 69.06 MiB -1 -1 17.47 47884 3 0.73 -1 -1 38592 -1 -1 44 196 1 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 70716 196 193 1202 1347 1 609 434 15 15 225 io auto 31.0 MiB 0.53 2915 69.1 MiB 0.63 0.01 2.07553 -987.105 -2.07553 2.07553 0.75 0.00261807 0.00238414 0.25233 0.228929 40 7329 50 1.03862e+07 2.91934e+06 618415. 2748.51 3.10 1.07576 0.986055 6327 17 2310 3827 378656 103928 2.62347 2.62347 -1211.32 -2.62347 -0.189501 -0.0542312 773047. 3435.76 0.30 0.24 0.135081 0.126741 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 3.32 vpr 63.67 MiB -1 -1 0.31 21676 3 0.10 -1 -1 36324 -1 -1 65 99 1 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 65200 99 130 343 473 1 224 295 12 12 144 clb auto 25.5 MiB 0.14 531 63.7 MiB 0.17 0.00 1.48078 -104.053 -1.48078 1.48078 0.37 0.000509804 0.000446377 0.0489075 0.0436288 46 1370 11 5.66058e+06 4.05111e+06 408669. 2837.98 0.82 0.174831 0.158109 1225 12 497 830 47231 15684 1.86272 1.86272 -130.142 -1.86272 -0.887648 -0.320482 525203. 3647.24 0.15 0.05 0.0265911 0.0251029 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq1.v common 12.88 vpr 66.90 MiB -1 -1 0.40 25508 5 0.17 -1 -1 37356 -1 -1 26 162 0 5 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 68508 162 96 1067 884 1 656 289 16 16 256 mult_36 auto 29.1 MiB 0.37 4897 66.9 MiB 0.53 0.01 15.6004 -1183.4 -15.6004 15.6004 0.89 0.00217579 0.00198703 0.21541 0.196596 62 10790 41 1.21132e+07 3.38124e+06 1.04918e+06 4098.38 7.24 0.897709 0.827927 9074 17 3102 5289 1733336 448307 17.1815 17.1815 -1398.02 -17.1815 0 0 1.29183e+06 5046.22 0.52 0.56 0.118194 0.111193 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq2.v common 11.23 vpr 65.50 MiB -1 -1 0.27 23972 5 0.11 -1 -1 36496 -1 -1 16 66 0 5 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67068 66 96 779 596 1 446 183 16 16 256 mult_36 auto 27.4 MiB 0.33 3501 65.5 MiB 0.33 0.00 11.7582 -718.798 -11.7582 11.7582 0.86 0.00136554 0.00122914 0.139381 0.126563 54 8959 32 1.21132e+07 2.8423e+06 903890. 3530.82 6.20 0.598329 0.552411 7711 18 3347 6597 2635794 687086 13.1995 13.1995 -850.937 -13.1995 0 0 1.17254e+06 4580.24 0.46 0.71 0.0897128 0.084845 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU8PEEng.v common 904.39 vpr 574.65 MiB -1 -1 71.32 456864 98 131.62 -1 -1 115500 -1 -1 1800 114 45 8 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 588444 114 102 35713 31804 1 16705 2069 51 51 2601 clb auto 333.6 MiB 45.75 221681 558.5 MiB 66.30 0.52 65.0127 -54035.8 -65.0127 65.0127 46.58 0.0806502 0.0711985 10.9428 9.00407 130 398965 38 1.52527e+08 1.2484e+08 2.29813e+07 8835.57 451.87 44.4488 36.1857 365538 26 78543 325601 59574244 12777397 73.9876 73.9876 -67703.3 -73.9876 -25.6092 -0.318417 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2160268 36 356 184794 159441 1 63844 6618 93 93 8649 clb auto 1305.9 MiB 93.21 769524 1957.1 MiB 310.95 2.00 43.7051 -268511 -43.7051 43.7051 86.46 0.149355 0.116109 23.3171 18.7608 158 1106269 33 5.27943e+08 4.23316e+08 9.25072e+07 10695.7 427.49 81.8209 67.1208 1049377 20 248345 601971 122293436 27502132 47.0227 47.0227 -334412 -47.0227 0 0 1.17788e+08 13618.7 39.58 35.20 10.3655 9.14164 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkDelayWorker32B.v common 129.62 vpr 366.71 MiB -1 -1 16.44 122524 5 6.51 -1 -1 47452 -1 -1 456 506 44 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 375516 506 553 3236 3734 1 2845 1559 50 50 2500 memory auto 55.9 MiB 4.06 16032 366.7 MiB 5.02 0.05 6.80712 -2054 -6.80712 6.80712 45.76 0.0175213 0.015915 2.28393 2.06165 36 25323 16 1.47946e+08 4.86882e+07 7.19567e+06 2878.27 25.59 7.13711 6.59617 24221 15 4632 6012 3992255 971540 7.76657 7.76657 -2583.58 -7.76657 -1.57599 -0.292146 8.81455e+06 3525.82 5.13 1.88 0.817419 0.770522 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkPktMerge.v common 23.97 vpr 69.24 MiB -1 -1 1.25 28816 2 0.13 -1 -1 37572 -1 -1 27 311 15 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 70904 311 156 1015 1158 1 965 509 28 28 784 memory auto 31.7 MiB 0.60 8621 69.2 MiB 0.95 0.02 3.78217 -4132.65 -3.78217 3.78217 3.65 0.00398261 0.00345115 0.420666 0.362578 36 15836 38 4.25198e+07 9.67514e+06 2.12999e+06 2716.82 9.65 1.74375 1.55142 14661 16 3332 3869 3187899 863548 4.54528 4.54528 -4999.76 -4.54528 -16.9796 -0.360359 2.61523e+06 3335.75 1.37 1.13 0.21375 0.196189 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 39.12 vpr 80.79 MiB -1 -1 7.34 55708 5 2.09 -1 -1 42404 -1 -1 151 193 5 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 82724 193 205 2771 2705 1 1306 554 20 20 400 memory auto 43.3 MiB 1.71 10508 80.8 MiB 1.92 0.02 4.50341 -2536.52 -4.50341 4.50341 1.59 0.00670438 0.00584063 0.763227 0.673469 80 20085 30 2.07112e+07 1.0878e+07 2.10510e+06 5262.74 17.72 3.52172 3.10689 18335 14 4762 13087 1343583 301695 5.27403 5.27403 -2933.74 -5.27403 -6.90052 -0.340786 2.64606e+06 6615.15 1.20 0.72 0.354038 0.326399 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml or1200.v common 97.58 vpr 103.93 MiB -1 -1 6.06 64824 8 4.52 -1 -1 44636 -1 -1 205 385 2 1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 106428 385 362 4417 4306 1 2338 955 26 26 676 io auto 57.8 MiB 4.25 29898 94.6 MiB 5.35 0.06 8.41209 -8606.11 -8.41209 8.41209 3.04 0.0132573 0.0121657 1.68659 1.50164 124 53895 30 3.69863e+07 1.25403e+07 5.46418e+06 8083.11 59.71 7.45582 6.63407 49421 17 10867 37696 5338027 1021071 9.49228 9.49228 -10001 -9.49228 0 0 6.89526e+06 10200.1 3.79 2.48 0.784424 0.718164 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 44.56 vpr 82.12 MiB -1 -1 4.14 45508 3 0.80 -1 -1 40260 -1 -1 112 236 1 6 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84096 236 305 3195 3007 1 1538 660 19 19 361 io auto 44.7 MiB 1.68 12630 82.1 MiB 2.09 0.03 4.38488 -2613.2 -4.38488 4.38488 1.40 0.00734113 0.00668463 0.825011 0.750059 84 28775 47 1.72706e+07 8.96013e+06 1.98721e+06 5504.73 27.52 3.95983 3.57012 23837 17 6596 17361 4235199 919251 4.8246 4.8246 -3079.9 -4.8246 -8.34681 -0.203043 2.52075e+06 6982.70 1.11 1.50 0.395692 0.367654 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml sha.v common 27.01 vpr 79.31 MiB -1 -1 2.78 47396 4 1.73 -1 -1 41744 -1 -1 117 38 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 81212 38 36 2744 2493 1 1026 191 15 15 225 clb auto 42.1 MiB 1.51 8268 79.3 MiB 0.86 0.01 9.42684 -2368.11 -9.42684 9.42684 0.76 0.00419041 0.00355775 0.389183 0.34129 80 16322 28 1.03862e+07 6.3056e+06 1.14527e+06 5090.08 14.85 2.65436 2.29116 14082 23 4769 13095 772377 175387 10.9061 10.9061 -2889.89 -10.9061 0 0 1.43913e+06 6396.14 0.54 0.63 0.403914 0.361595 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml spree.v common 23.48 vpr 70.44 MiB -1 -1 3.20 35016 16 0.61 -1 -1 38804 -1 -1 47 45 3 1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 72132 45 32 1188 1147 1 779 128 14 14 196 memory auto 33.0 MiB 0.89 6343 70.4 MiB 0.46 0.01 9.65905 -6148.72 -9.65905 9.65905 0.63 0.00277918 0.00237587 0.224 0.195358 78 15037 50 9.20055e+06 4.57302e+06 962129. 4908.82 13.37 1.48543 1.29635 12738 37 3920 10917 3210572 967402 11.158 11.158 -7323.72 -11.158 -32.4092 -0.292146 1.21337e+06 6190.68 0.45 1.33 0.304433 0.273601 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision0.v common 116.16 vpr 229.20 MiB -1 -1 12.14 102824 5 13.69 -1 -1 69400 -1 -1 673 169 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 234696 169 197 23321 21461 1 6785 1039 33 33 1089 clb auto 174.0 MiB 9.09 40964 207.7 MiB 11.23 0.10 2.97933 -13130.3 -2.97933 2.97933 5.08 0.0331014 0.028786 4.21612 3.5575 80 64393 22 6.0475e+07 3.62708e+07 6.10319e+06 5604.39 39.59 18.8881 15.9171 60627 16 15631 27457 1628253 372796 3.8598 3.8598 -15834.8 -3.8598 0 0 7.66439e+06 7038.01 3.88 2.59 2.21379 1.95804 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision1.v common 242.46 vpr 269.98 MiB -1 -1 8.18 124220 3 12.85 -1 -1 77392 -1 -1 655 115 0 40 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 276464 115 145 22868 19305 1 9712 955 40 40 1600 mult_36 auto 169.8 MiB 8.02 84970 204.0 MiB 12.50 0.13 5.35987 -21763.1 -5.35987 5.35987 7.69 0.0305526 0.0265184 3.72565 3.14157 100 140993 40 9.16046e+07 5.11412e+07 1.10258e+07 6891.10 149.31 18.5616 15.5772 126563 16 34389 56030 30759904 6308879 5.74716 5.74716 -25476.1 -5.74716 0 0 1.38359e+07 8647.47 7.70 13.75 2.0905 1.86264 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 919.98 vpr 1.04 GiB -1 -1 11.15 197868 3 6.30 -1 -1 155564 -1 -1 1490 149 0 179 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1089076 149 182 55416 37075 1 28670 2000 80 80 6400 mult_36 auto 356.8 MiB 19.69 304023 1063.6 MiB 92.74 0.67 13.2416 -49841.9 -13.2416 13.2416 121.55 0.0962531 0.0848053 14.9704 12.5803 106 425024 43 3.90281e+08 1.51186e+08 4.81287e+07 7520.11 553.42 45.7326 38.6761 404262 21 97832 118922 48216274 9732760 14.616 14.616 -57830.7 -14.616 0 0 6.06309e+07 9473.58 31.45 17.86 4.59878 4.07441 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision3.v common 2.09 vpr 63.42 MiB -1 -1 0.60 25644 4 0.12 -1 -1 36300 -1 -1 13 11 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64944 11 2 303 283 2 70 26 7 7 49 clb auto 24.9 MiB 0.14 217 63.4 MiB 0.04 0.00 1.86505 -151.175 -1.86505 1.77348 0.07 0.000327567 0.000244201 0.018376 0.0145168 26 539 18 1.07788e+06 700622 75813.7 1547.22 0.14 0.063896 0.0534703 424 12 250 515 15897 6574 2.07043 1.88 -175.337 -2.07043 0 0 91376.6 1864.83 0.02 0.03 0.0178958 0.0166099 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 1994.99 vpr 898.68 MiB -1 -1 61.01 621344 14 118.10 -1 -1 123276 -1 -1 2287 257 0 11 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 920252 257 32 35747 33389 1 18576 2587 58 58 3364 clb auto 366.7 MiB 66.13 238606 672.7 MiB 114.11 0.89 17.1228 -22971.9 -17.1228 17.1228 66.43 0.122725 0.105945 15.0557 11.8391 78 394768 147 2.00088e+08 1.27615e+08 1.92320e+07 5717.01 1361.68 122.113 97.7861 1114397 11021065 660432 349453 53 168974 802689 141308298 36713877 45717834 6972091 95590464 29741786 0 0 792797 514828 747302 747302 910805 802689 2332383 1256218 40556637 4114854 1173010 341749 3457595 1539720 44978029 13690833 0 0 46359740 13705684 0 0 792797 0 1048626 1953882 3472000 3402169 10847209 13973 508 19.5428 19.5428 -25846 -19.5428 0 0 2.42407e+07 7205.90 14.24 130.51 4.88 34.68 0.19 14.24 14.3145 11.5453 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU8PEEng.v common 3071.55 vpr 833.25 MiB -1 -1 71.48 455940 98 132.11 -1 -1 115232 -1 -1 1800 114 45 8 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 853252 114 102 35713 31804 1 16705 2069 51 51 2601 clb auto 339.9 MiB 62.95 216212 561.5 MiB 92.18 0.71 65.1279 -53179 -65.1279 65.1279 49.18 0.120059 0.101817 14.974 11.8502 96 359574 127 1.52527e+08 1.2484e+08 1.77902e+07 6839.76 2509.64 176.104 141.33 1051316 9491173 587229 299163 55 145183 626548 203387007 66494555 41102351 7195584 162284656 59298971 0 0 557595 348397 529205 529205 686930 626548 3869612 1660071 37419060 5169165 813788 245793 2438766 1051474 77969311 28517504 0 0 79102740 28346398 0 0 557595 0 1827926 1276985 1909761 1891717 6237045 74462 22447 75.1357 75.1357 -67113 -75.1357 -0.0967573 -0.0199062 2.21294e+07 8508.02 8.37 98.67 2.89 16.30 0.13 8.37 6.86691 5.51408 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision0.v common 491.17 vpr 361.63 MiB -1 -1 13.25 101972 5 13.80 -1 -1 69408 -1 -1 673 169 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 370312 169 197 23321 21461 1 6785 1039 33 33 1089 clb auto 180.8 MiB 12.19 42112 221.0 MiB 12.30 0.12 3.10868 -13056.7 -3.10868 3.10868 5.95 0.0421986 0.0328892 4.76161 3.85299 58 63990 244 6.0475e+07 3.62708e+07 4.62388e+06 4245.99 385.70 79.3922 66.3623 452845 3145025 280765 57244 49 46719 122488 12901034 3413607 6417997 1071484 6483037 2342123 0 0 99450 91334 71450 71450 127765 122488 173471 117401 5739165 636855 123351 34238 451617 220807 2978920 1062567 0 0 3135845 1056467 0 0 99450 0 417639 158865 157759 165849 512493 25863 4191 3.58485 3.58485 -15007.4 -3.58485 0 0 5.85783e+06 5379.09 3.06 25.65 1.05 12.08 0.19 3.06 4.27202 3.58561 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision1.v common 1731.31 vpr 388.00 MiB -1 -1 10.47 123456 3 17.68 -1 -1 77352 -1 -1 655 115 0 40 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 397312 115 145 22868 19305 1 9712 955 40 40 1600 mult_36 auto 177.4 MiB 9.52 82272 238.0 MiB 13.23 0.12 5.15059 -21406.4 -5.15059 5.15059 8.56 0.0361559 0.0312351 4.65663 3.86719 76 154775 184 9.16046e+07 5.11412e+07 8.72311e+06 5451.94 1612.65 90.8987 76.51 519336 3912846 269202 122007 30 61007 155688 38640235 6222360 6668491 918705 31971744 5303655 0 0 115015 107081 104788 104788 162701 155688 2093369 113670 5939763 436808 143497 55137 451012 219128 14854225 2513893 0 0 14775865 2516167 0 0 115015 0 643171 157906 453642 427511 882511 43939 8570 5.48939 5.48939 -24883.8 -5.48939 0 0 1.08598e+07 6787.37 5.55 30.87 1.96 11.01 0.18 5.55 3.14734 2.6417 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 5871.63 vpr 1.05 GiB -1 -1 14.96 197124 3 8.63 -1 -1 155544 -1 -1 1490 149 0 179 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1100488 149 182 55416 37075 1 28670 2000 80 80 6400 mult_36 auto 360.6 MiB 29.07 291939 1074.7 MiB 79.70 0.55 12.5458 -48952.6 -12.5458 12.5458 135.77 0.108801 0.0950539 15.7001 12.8522 78 437698 224 3.90281e+08 1.51186e+08 3.69986e+07 5781.04 5479.15 81.5782 67.7414 1647473 12742193 618027 380228 28 138212 241867 64603805 10299476 9587932 1487408 55015873 8812068 0 0 208298 193889 166401 166401 247323 241867 3307020 170969 8438805 627104 233900 115896 693506 424548 25609640 4121299 0 0 25698912 4237503 0 0 208298 0 605901 210574 379701 368344 1028019 35661 9945 13.929 13.929 -56870.7 -13.929 0 0 4.66105e+07 7282.88 19.01 37.94 5.93 15.28 0.13 19.01 3.18631 2.64796 From 0b94e2514f4817f201a8f6899aeb401d1515c3d5 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 31 May 2023 18:25:35 -0400 Subject: [PATCH 40/51] update strong_flat_router golden results --- .../strong_flat_router/config/golden_results.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index ed1e4a4a83f..3d0c43fdf35 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 5.69 vpr 65.43 MiB -1 -1 1.36 31308 16 0.50 -1 -1 34840 -1 -1 61 45 3 1 success v8.0.0-7583-g7e3566081-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-25T17:51:56 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66996 45 32 1188 1147 1 781 142 14 14 196 memory auto 28.1 MiB 1.38 6698 65.4 MiB 0.23 0.00 9.7493 -6323.75 -9.7493 9.7493 0.02 0.000903437 0.000727014 0.0847444 0.0698178 -1 10688 13 9.20055e+06 5.32753e+06 1.11359e+06 5681.59 1.14 0.114902 0.0946844 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges 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crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.82 vpr 76.19 MiB -1 -1 3.42 34124 16 0.76 -1 -1 37916 -1 -1 61 45 3 1 success 8528925 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:34:55 gh-actions-runner-vtr-auto-spawned83 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 78016 45 32 1188 1147 1 781 142 14 14 196 memory auto 39.1 MiB 3.14 6687 76.2 MiB 0.85 0.01 9.87688 -6144.34 -9.87688 9.87688 0.04 0.00303074 0.00250348 0.260087 0.214733 -1 10707 13 9.20055e+06 5.32753e+06 1.11359e+06 5681.59 2.66 0.354898 0.295042 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From d0ffc9039c7e5a0359c75d302481d46ecacf5db6 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 7 Jun 2023 19:04:07 -0400 Subject: [PATCH 41/51] add comments on remapped parameter to add edges to rr graph --- libs/libarchfpga/src/physical_types.h | 6 +++++- libs/librrgraph/src/base/rr_graph_builder.h | 9 ++++++--- libs/librrgraph/src/base/rr_graph_storage.h | 15 +++++++++++---- .../src/io/rr_graph_uxsdcxx_serializer.h | 11 ++++------- 4 files changed, 26 insertions(+), 15 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index c1f625c99f1..f34bf96b20f 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1688,7 +1688,11 @@ struct t_arch_switch_inf { * mux_trans_size: The area of each transistor in the segment's driving mux * * measured in minimum width transistor units * * buf_size: The area of the buffer. If set to zero, area should be * - * calculated from R */ + * calculated from R + * intra_tile: Indicate whether this rr_switch is a switch type used inside * + * clusters. These switch types are not specified in the * + * architecture description file and are added when flat router * + * is enabled */ struct t_rr_switch_inf { float R = 0.; float Cin = 0.; diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index c8b58764a49..27dd784c272 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -207,9 +207,12 @@ class RRGraphBuilder { } /** @brief emplace_back_edge; It add one edge. This method is efficient if reserve_edges was called with - * the number of edges present in the graph. */ - inline void emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch, bool is_rr_id) { - node_storage_.emplace_back_edge(src, dest, edge_switch, is_rr_id); + * the number of edges present in the graph. + * @param remapped If true, it means the switch don't need to be remapped later. Currently, this parameter is true for the switches + * that are being added after the rr graph is built. Currently, it is true for the edges of the intra-cluster + * resources.*/ + inline void emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch, bool remapped) { + node_storage_.emplace_back_edge(src, dest, edge_switch, remapped); } /** @brief Append 1 more RR node to the RR graph. */ inline void emplace_back() { diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index c221ab24ac8..cfeacf63cd2 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -545,10 +545,17 @@ class t_rr_graph_storage { // Reserve at least num_edges in the edge backing arrays. void reserve_edges(size_t num_edges); - // Add one edge. This method is efficient if reserve_edges was called with - // the number of edges present in the graph. This method is still - // amortized O(1), like std::vector::emplace_back, but both runtime and - // peak memory usage will be higher if reallocation is required. + /*** + * @brief Add one edge. This method is efficient if reserve_edges was called with + * the number of edges present in the graph. This method is still + * amortized O(1), like std::vector::emplace_back, but both runtime and + * peak memory usage will be higher if reallocation is required. + * @ param remapped This is used later in remap_rr_node_switch_indices to check whether an + * end needs to be remapped. This remapping is done to change the switch index from arch_sw_idx + * to rr_sw_idx. The difference between these two ids is because some switch delays depend on the fan-in + * of the node. Also, the information about switches is flight-weighted and are accessible with IDs. Thus, + * the number of rr switch types can be higher than the number of arch switch types. + */ void emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch, bool remapped); // Adds a batch of edges. diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index d82ee1ec3df..8444a7b3653 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -461,10 +461,11 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { // If the switch name is not present in the architecture, generate an // error. // If the graph is written when flat-routing is enabled, the types of the switches inside of the rr_graph are also - // added to the XML file. These types are not added to the data structure that contain arch switch types. They are added to all_sw_inf under dvice context. + // added to the XML file. These types are not added to the data structure that contain arch switch types. They are added to all_sw_inf under device context. // It remains as a future work to remove the arch_switch_types and use all_sw info under device_ctx instead. bool found_arch_name = false; std::string string_name = std::string(name); + // The string name has the format of "Internal Switch/dealy". So, I have to use compare to specify the portion I want to be compared. bool is_internal_sw = string_name.compare(0, 15, "Internal Switch") == 0; for (const auto& arch_sw_inf: arch_switch_inf_) { if (string_name == arch_sw_inf.name || is_internal_sw) { @@ -475,11 +476,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { if (!found_arch_name) { report_error("Switch name '%s' not found in architecture\n", string_name.c_str()); } - if(is_internal_sw){ - sw->intra_tile = true; - } else { - sw->intra_tile = false; - } + sw->intra_tile = is_internal_sw; sw->name = string_name; } inline const char* get_switch_name(const t_rr_switch_inf*& sw) final { @@ -927,7 +924,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { bind.set_ignore(); } - // The edge ids in the rr graph file are indeed rr edge id not architecture edge id + // The edge ids in the rr graph file are rr edge id not architecture edge id rr_graph_builder_->emplace_back_edge(RRNodeId(src_node), RRNodeId(sink_node), switch_id, true); return bind; } From 35afe94de3293db3ecaf997f5561533ee13ba2e2 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 7 Jun 2023 19:33:48 -0400 Subject: [PATCH 42/51] add comments on flat-router parts of router_lookahead_map and rr_graph.cpp --- vpr/src/route/router_lookahead_map.cpp | 21 ++++++++++++++++++- vpr/src/route/rr_graph.cpp | 29 +++++++++++++++++++++++--- 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index adb304588ce..3c8c68e9237 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -207,16 +207,35 @@ t_wire_cost_map f_wire_cost_map; /******** File-Scope Functions ********/ Cost_Entry get_wire_cost_entry(e_rr_type rr_type, int seg_index, int delta_x, int delta_y); static void compute_router_wire_lookahead(const std::vector& segment_inf); +/*** + * @brief Compute the cost from pin to sinks of tiles - Compute the minimum cost to get to each tile sink from pins on the cluster + * @param inter_tile_pin_primitive_pin_delay + * @param tile_min_cost + * @param det_routing_arch + * @param device_ctx + */ static void compute_tiles_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, std::unordered_map>& tile_min_cost, const t_det_routing_arch& det_routing_arch, const DeviceContext& device_ctx); - +/*** + * @brief Compute the cose from tile pins to tile sinks + * @param inter_tile_pin_primitive_pin_delay [physical_tile_type_idx][from_pin_ptc_num][sink_ptc_num] -> cost + * @param physical_tile + * @param det_routing_arch + * @param delayless_switch + */ static void compute_tile_lookahead(std::unordered_map& inter_tile_pin_primitive_pin_delay, t_physical_tile_type_ptr physical_tile, const t_det_routing_arch& det_routing_arch, const int delayless_switch); +/*** + * @brief Compute the minimum cost to get to the sinks from pins on the cluster + * @param tile_min_cost [physical_tile_idx][sink_ptc_num] -> min_cost + * @param physical_tile + * @param inter_tile_pin_primitive_pin_delay [physical_tile_type_idx][from_pin_ptc_num][sink_ptc_num] -> cost + */ static void store_min_cost_to_sinks(std::unordered_map>& tile_min_cost, t_physical_tile_type_ptr physical_tile, const std::unordered_map& inter_tile_pin_primitive_pin_delay); diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index c5c3b44c74d..6357b16ab75 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -307,8 +307,21 @@ static void add_intra_tile_edges_rr_graph(RRGraphBuilder& rr_graph_builder, int i, int j); -/* - * Build the internal edges of blocks inside the given location +/*** + * @brief Add the intra-cluster edges + * @param rr_graph_builder + * @param num_collapsed_nodes Return the number of nodes that are removed due to collapsing + * @param cluster_blk_id Cluser block id of the cluster that its edges are being added + * @param i + * @param j + * @param cap Capacity number of the location that cluster is being mapped to + * @param R_minW_nmos + * @param R_minW_pmos + * @param rr_edges_to_create + * @param nodes_to_collapse Sotre the nodes in the cluster that needs to be collapsed + * @param grid + * @param is_flat + * @param load_rr_graph */ static void build_cluster_internal_edges(RRGraphBuilder& rr_graph_builder, int& num_collapsed_nodes, @@ -550,7 +563,17 @@ static void add_pin_chain(const std::vector& pin_chain, std::vector>& all_chains, bool is_new_chain); -// Return the edge id of an intra-tile edge with the same delay. If there isn't any, create a new one and return the ID +/*** + * @brief Return a pair. The firt element indicates whether the switch is added or it was already added. The second element is the switch index. + * @param rr_graph + * @param arch_sw_inf + * @param R_minW_nmos Needs to be passed to use create_rr_switch_from_arch_switch + * @param R_minW_pmos Needs to be passed to use create_rr_switch_from_arch_switch + * @param is_rr_sw If it is true, the function would search in the data structure that store rr switches. + * Otherwise, it would search in the data structure that store switches that are not rr switches. + * @param delay + * @return + */ static std::pair find_create_intra_cluster_sw(RRGraphBuilder& rr_graph, std::map& arch_sw_inf, float R_minW_nmos, From 30cf8fb1f352b8d3efd83e740f6e00e96ee012bb Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 8 Jun 2023 08:49:29 -0400 Subject: [PATCH 43/51] Add comments on verify router lookahead in run_vtr_flow.py and add more comments on router lookahead --- vpr/src/route/router_lookahead_map.cpp | 11 +++++++++++ vpr/src/route/rr_graph_clock.cpp | 1 + vpr/src/route/rr_graph_clock.h | 8 ++++++++ vtr_flow/scripts/run_vtr_flow.py | 6 ++++-- 4 files changed, 24 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 3c8c68e9237..efc5b9ce5b3 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -206,6 +206,11 @@ t_wire_cost_map f_wire_cost_map; /******** File-Scope Functions ********/ Cost_Entry get_wire_cost_entry(e_rr_type rr_type, int seg_index, int delta_x, int delta_y); + +/*** + * @brief Fill f_wire_cost_map. It is a look-up table from CHANX/CHANY (to SINKs) for various distances + * @param segment_inf + */ static void compute_router_wire_lookahead(const std::vector& segment_inf); /*** * @brief Compute the cost from pin to sinks of tiles - Compute the minimum cost to get to each tile sink from pins on the cluster @@ -240,6 +245,12 @@ static void store_min_cost_to_sinks(std::unordered_map& inter_tile_pin_primitive_pin_delay); +/*** + * @brief Iterate over the first and second dimension of f_wire_cost_map to get the minimum cost for each dx and dy_ + * @param internal_opin_global_cost_map This map is populated in this function. [dx][dy] -> cost + * @param max_dx + * @param max_dy + */ static void min_global_cost_map(vtr::NdMatrix& internal_opin_global_cost_map, size_t max_dx, size_t max_dy); diff --git a/vpr/src/route/rr_graph_clock.cpp b/vpr/src/route/rr_graph_clock.cpp index 2d5d761ef6f..84872485f15 100644 --- a/vpr/src/route/rr_graph_clock.cpp +++ b/vpr/src/route/rr_graph_clock.cpp @@ -192,6 +192,7 @@ void ClockRRGraphBuilder::add_edge(t_rr_edge_info_set* rr_edges_to_create, RRNodeId sink_node, int arch_switch_idx, bool edge_remapped) const { + VTR_ASSERT(edge_remapped == false); const auto& device_ctx = g_vpr_ctx.device(); VTR_ASSERT(arch_switch_idx < (int)device_ctx.arch_switch_inf.size()); rr_edges_to_create->emplace_back(src_node, sink_node, arch_switch_idx, edge_remapped); diff --git a/vpr/src/route/rr_graph_clock.h b/vpr/src/route/rr_graph_clock.h index 55b038724b0..6ce575b7423 100644 --- a/vpr/src/route/rr_graph_clock.h +++ b/vpr/src/route/rr_graph_clock.h @@ -118,6 +118,14 @@ class ClockRRGraphBuilder { static void map_relative_seg_indices(const t_unified_to_parallel_seg_index& indices_map); + /*** + * @brief Add an edge to the rr graph + * @param rr_edges_to_create The interface to rr-graph builder + * @param src_node End point of the edge + * @param sink_node Start point of the edge + * @param arch_switch_idx + * @param edge_remapped Indicate whether the edge idx refer to arch edge idx or rr graph edge idx. Currently, we only support arch edge idx + */ void add_edge(t_rr_edge_info_set* rr_edges_to_create, RRNodeId src_node, RRNodeId sink_node, diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py index f4047caa04b..74474855272 100755 --- a/vtr_flow/scripts/run_vtr_flow.py +++ b/vtr_flow/scripts/run_vtr_flow.py @@ -420,13 +420,15 @@ def vtr_command_argparser(prog=None): "-verify_inter_cluster_router_lookahead", default=False, action="store_true", - help="Tells VPR to verify the router lookahead.", + help="Tells VPR to verify the inter-cluster router lookahead.", ) vpr.add_argument( "-verify_intra_cluster_router_lookahead", default=False, action="store_true", - help="Tells VPR to verify the router lookahead.", + help="Tells VPR to verify the intra-cluster router lookahead. Intra-cluster router lookahead information \ + is stored in a separate data structure than the inter-cluster router lookahead information, \ + and they are written into separate files.", ) return parser From 84c2bdea725bee3bb445ab771743467c7d089b69 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 12 Jun 2023 11:56:23 -0400 Subject: [PATCH 44/51] break the long line in run_vtr_flow.py - explain more on edge switch id remapping --- libs/librrgraph/src/base/rr_graph_builder.h | 9 +++++---- libs/librrgraph/src/base/rr_graph_storage.h | 8 ++++---- libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 2 +- vpr/src/route/rr_graph.cpp | 5 ++++- vtr_flow/scripts/run_vtr_flow.py | 6 ++++-- 5 files changed, 18 insertions(+), 12 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 27dd784c272..02fcfcfebf3 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -206,11 +206,12 @@ class RRGraphBuilder { node_storage_.reserve_edges(num_edges); } - /** @brief emplace_back_edge; It add one edge. This method is efficient if reserve_edges was called with + /** @brief emplace_back_edge It adds one edge. This method is efficient if reserve_edges was called with * the number of edges present in the graph. - * @param remapped If true, it means the switch don't need to be remapped later. Currently, this parameter is true for the switches - * that are being added after the rr graph is built. Currently, it is true for the edges of the intra-cluster - * resources.*/ + * @param remapped If true, it means the switch id (edge_switch) corresponds to rr switch id. Thus, when the remapped function is called to + * remap the arch switch id to rr switch id, the edge switch id of this edge shouldn't be changed. For example, when the intra-cluster graph + * is built and the rr-graph related to global resources are read from a file, this parameter is true since the intra-cluster switches are + * also listed in rr-graph file. So, we use that list to use the rr switch id instead of passing arch switch id for intra-cluster edges.*/ inline void emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch, bool remapped) { node_storage_.emplace_back_edge(src, dest, edge_switch, remapped); } diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index cfeacf63cd2..14629433943 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -550,10 +550,10 @@ class t_rr_graph_storage { * the number of edges present in the graph. This method is still * amortized O(1), like std::vector::emplace_back, but both runtime and * peak memory usage will be higher if reallocation is required. - * @ param remapped This is used later in remap_rr_node_switch_indices to check whether an - * end needs to be remapped. This remapping is done to change the switch index from arch_sw_idx - * to rr_sw_idx. The difference between these two ids is because some switch delays depend on the fan-in - * of the node. Also, the information about switches is flight-weighted and are accessible with IDs. Thus, + * @param remapped This is used later in remap_rr_node_switch_indices to check whether an + * edge needs its switch ID remapped from the arch_sw_idx to rr_sw_idx. + * The difference between these two ids is because some switch delays depend on the fan-in + * of the node. Also, the information about switches is fly-weighted and are accessible with IDs. Thus, * the number of rr switch types can be higher than the number of arch switch types. */ void emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch, bool remapped); diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 8444a7b3653..72d4f43387a 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -465,7 +465,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { // It remains as a future work to remove the arch_switch_types and use all_sw info under device_ctx instead. bool found_arch_name = false; std::string string_name = std::string(name); - // The string name has the format of "Internal Switch/dealy". So, I have to use compare to specify the portion I want to be compared. + // The string name has the format of "Internal Switch/delay". So, I have to use compare to specify the portion I want to be compared. bool is_internal_sw = string_name.compare(0, 15, "Internal Switch") == 0; for (const auto& arch_sw_inf: arch_switch_inf_) { if (string_name == arch_sw_inf.name || is_internal_sw) { diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 6357b16ab75..36467223671 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -734,7 +734,10 @@ void create_rr_graph(const t_graph_type graph_type, print_rr_graph_stats(); - //Write out rr graph file if needed - Currently, writing the flat rr-graph is not supported since loading from a flat rr-graph is not supported + // Write out rr graph file if needed - Currently, writing the flat rr-graph is not supported since loading from a flat rr-graph is not supported. + // When this function is called in any stage other than routing, the is_flat flag passed to this function is false, regardless of the flag passed + // through command line. So, the graph conrresponding to global resources will be created and written down to file if needed. During routing, if flat-routing + // is enabled, intra-cluster resources will be added to the graph, but this new bigger graph will not be written down. if (!det_routing_arch->write_rr_graph_filename.empty() && !is_flat) { write_rr_graph(&mutable_device_ctx.rr_graph_builder, &mutable_device_ctx.rr_graph, diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py index 74474855272..7f91c016164 100755 --- a/vtr_flow/scripts/run_vtr_flow.py +++ b/vtr_flow/scripts/run_vtr_flow.py @@ -426,8 +426,10 @@ def vtr_command_argparser(prog=None): "-verify_intra_cluster_router_lookahead", default=False, action="store_true", - help="Tells VPR to verify the intra-cluster router lookahead. Intra-cluster router lookahead information \ - is stored in a separate data structure than the inter-cluster router lookahead information, \ + help="Tells VPR to verify the intra-cluster router lookahead. \ + Intra-cluster router lookahead information \ + is stored in a separate data structure than the \ + inter-cluster router lookahead information, \ and they are written into separate files.", ) From 2aceaf6cfbe5cf60746d61e845afa3f1b434053a Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 26 Jun 2023 14:38:50 -0400 Subject: [PATCH 45/51] remove seen_edge vector since it doesn't have significant effect on the runtime --- libs/librrgraph/src/base/rr_graph_storage.cpp | 11 +---------- libs/librrgraph/src/base/rr_graph_storage.h | 4 ---- 2 files changed, 1 insertion(+), 14 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index 8a2fd731c4c..a0ad513dae8 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -399,17 +399,10 @@ void t_rr_graph_storage::init_fan_in() { //Reset all fan-ins to zero edges_read_ = true; node_fan_in_.resize(node_storage_.size(), 0); - // This array is used to avoid initializing fan-in of the nodes which are already seen. - // This would reduce the run-time of flat rr graph generation since this function is called twice. - seen_edge_.resize(edge_dest_node_.size(), false); node_fan_in_.shrink_to_fit(); - seen_edge_.shrink_to_fit(); //Walk the graph and increment fanin on all downstream nodes for(const auto& edge_id : edge_dest_node_.keys()) { - if(!seen_edge_[edge_id]) { - node_fan_in_[edge_dest_node_[edge_id]] += 1; - seen_edge_[edge_id] = true; - } + node_fan_in_[edge_dest_node_[edge_id]] += 1; } } @@ -824,7 +817,6 @@ void t_rr_graph_storage::reorder(const vtr::vector& order, auto old_edge_dest_node = edge_dest_node_; auto old_edge_switch = edge_switch_; auto old_edge_remapped = edge_remapped_; - auto old_seen_edge = seen_edge_; RREdgeId cur_edge(0); // Reorder edges by source node @@ -838,7 +830,6 @@ void t_rr_graph_storage::reorder(const vtr::vector& order, edge_dest_node_[cur_edge] = order[old_edge_dest_node[e]]; edge_switch_[cur_edge] = old_edge_switch[e]; edge_remapped_[cur_edge] = old_edge_remapped[e]; - seen_edge_[cur_edge] = old_seen_edge[e]; cur_edge = RREdgeId(size_t(cur_edge) + 1); } } diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index 14629433943..d34fd35302e 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -429,7 +429,6 @@ class t_rr_graph_storage { node_ptc_.clear(); node_first_edge_.clear(); node_fan_in_.clear(); - seen_edge_.clear(); edge_src_node_.clear(); edge_dest_node_.clear(); edge_switch_.clear(); @@ -448,7 +447,6 @@ class t_rr_graph_storage { node_ptc_.shrink_to_fit(); node_first_edge_.shrink_to_fit(); node_fan_in_.shrink_to_fit(); - seen_edge_.shrink_to_fit(); edge_src_node_.shrink_to_fit(); edge_dest_node_.shrink_to_fit(); edge_switch_.shrink_to_fit(); @@ -683,8 +681,6 @@ class t_rr_graph_storage { vtr::vector edge_switch_; vtr::vector edge_remapped_; - vtr::vector seen_edge_; - /*************** * State flags * ***************/ From 65c3a8fd3254c66c3717cc7c48d7f3f1068a3c9e Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 26 Jun 2023 15:47:33 -0400 Subject: [PATCH 46/51] add some comments above edge_remapped_ --- libs/librrgraph/src/base/rr_graph_storage.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index d34fd35302e..0a3ff7358af 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -679,6 +679,22 @@ class t_rr_graph_storage { vtr::vector edge_src_node_; vtr::vector edge_dest_node_; vtr::vector edge_switch_; + /** + * The delay of certain switches specified in the architecture file depends on the number of inputs of the edge's sink node (pins or tracks). + * For example, in the case of a MUX switch, the delay increases as the number of inputs increases. + * During the construction of the RR Graph, switch IDs are assigned to the edges according to the order specified in the architecture file. + * These switch IDs are later used to retrieve information such as delay for each edge. + * This allows for effective fly-weighting of edge information. + * + * After building the RR Graph, we iterate over the nodes once more to store their fan-in. + * If a switch's characteristics depend on the fan-in of a node, a new switch ID is generated and assigned to the corresponding edge. + * This process is known as remapping. + * In this vector, we store information about which edges have undergone remapping. + * It is necessary to store this information, especially when flat-router is enabled. + * Remapping occurs when constructing global resources after placement and when adding intra-cluster resources after placement. + * Without storing this information, during subsequent remappings, it would be unclear whether the stored switch ID + * corresponds to the architecture ID or the RR Graph switch ID for an edge. + */ vtr::vector edge_remapped_; /*************** From e906852013a9e176c2952819c6b01a3ba4d91887 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sun, 2 Jul 2023 13:15:02 -0400 Subject: [PATCH 47/51] clear edge_remap once done with building rr graph --- libs/librrgraph/src/base/rr_graph_builder.cpp | 8 ++++++++ libs/librrgraph/src/base/rr_graph_builder.h | 4 ++++ libs/librrgraph/src/base/rr_graph_storage.h | 12 ++++++++++++ vpr/src/route/rr_graph.cpp | 9 +++++++++ 4 files changed, 33 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 072b47804ab..ca73a5a3811 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -60,6 +60,14 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { } } +void RRGraphBuilder::init_edge_remap(bool val) { + node_storage_.init_edge_remap(val); +} + +void RRGraphBuilder::clear_temp_storage() { + node_storage_.clear_temp_storage(); +} + void RRGraphBuilder::clear() { node_lookup_.clear(); node_storage_.clear(); diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 5b07d5e8ebe..cf82d64a24a 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -129,6 +129,10 @@ class RRGraphBuilder { */ void add_node_to_all_locs(RRNodeId node); + void init_edge_remap(bool val); + + void clear_temp_storage(); + /** @brief Clear all the underlying data storage */ void clear(); /** @brief reorder all the nodes diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index 267135c07e8..09d80264645 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -451,6 +451,18 @@ class t_rr_graph_storage { remapped_edges_ = false; } + // Clear the data structures that are mainly used during RR graph construction. + // After RR Graph is build, we no longer need these data structures. + void clear_temp_storage() { + edge_remapped_.clear(); + } + + // Clear edge_remap data structure, and then initialize it with the given value + void init_edge_remap(bool val) { + edge_remapped_.clear(); + edge_remapped_.resize(edge_switch_.size(), val); + } + // Shrink memory usage of the RR graph storage. // // Note that this will temporarily increase the amount of storage required diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 5216a033ebb..ef1e51d055e 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1350,6 +1350,10 @@ static void build_rr_graph(const t_graph_type graph_type, if (clb_to_clb_directs != nullptr) { delete[] clb_to_clb_directs; } + + // We are done with building the RR Graph. Thus, we can clear the storages only used + // to build the RR Graph + device_ctx.rr_graph_builder.clear_temp_storage(); } static void build_intra_cluster_rr_graph(const t_graph_type graph_type, @@ -1368,6 +1372,9 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, vtr::ScopedStartFinishTimer timer("Build intra-cluster routing resource graph"); rr_graph_builder.reset_rr_graph_flags(); + // When we are building intra-cluster resources, the edges already built are + // already remapped. + rr_graph_builder.init_edge_remap(true); vtr::vector pin_chains(clb_nlist.blocks().size()); set_clusters_pin_chains(clb_nlist, pin_chains, is_flat); @@ -1408,6 +1415,8 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, rr_graph_builder.partition_edges(); + rr_graph_builder.clear_temp_storage(); + check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, From 511e909e60d52fea5ac68e7206c78c64ee5cab92 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sun, 2 Jul 2023 14:05:29 -0400 Subject: [PATCH 48/51] update the results for vtr_reg_strong flat router --- .../vtr_reg_strong/strong_flat_router/config/golden_results.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index 3d0c43fdf35..6a885701bc1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.82 vpr 76.19 MiB -1 -1 3.42 34124 16 0.76 -1 -1 37916 -1 -1 61 45 3 1 success 8528925 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:34:55 gh-actions-runner-vtr-auto-spawned83 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 78016 45 32 1188 1147 1 781 142 14 14 196 memory auto 39.1 MiB 3.14 6687 76.2 MiB 0.85 0.01 9.87688 -6144.34 -9.87688 9.87688 0.04 0.00303074 0.00250348 0.260087 0.214733 -1 10707 13 9.20055e+06 5.32753e+06 1.11359e+06 5681.59 2.66 0.354898 0.295042 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.82 vpr 76.19 MiB -1 -1 3.42 34124 16 0.76 -1 -1 37916 -1 -1 61 45 3 1 success 8528925 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:34:55 gh-actions-runner-vtr-auto-spawned83 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 78016 45 32 1188 1147 1 781 142 14 14 196 memory auto 39.1 MiB 3.14 6687 76.2 MiB 0.85 0.01 9.87688 -6144.34 -9.87688 9.87688 0.04 0.00303074 0.00250348 0.260087 0.214733 -1 10707 13 9.20055e+06 5.32753e+06 1.21359e+06 5900 2.66 0.354898 0.295042 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From c6e7a5731c50c16174e99a071dc9b6c57aa54599 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sun, 2 Jul 2023 17:02:35 -0400 Subject: [PATCH 49/51] update depop-flat-router nightly test 3 --- .../config/golden_results.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt index baab5c7b203..d6944eeddb2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 1994.99 vpr 898.68 MiB -1 -1 61.01 621344 14 118.10 -1 -1 123276 -1 -1 2287 257 0 11 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 920252 257 32 35747 33389 1 18576 2587 58 58 3364 clb auto 366.7 MiB 66.13 238606 672.7 MiB 114.11 0.89 17.1228 -22971.9 -17.1228 17.1228 66.43 0.122725 0.105945 15.0557 11.8391 78 394768 147 2.00088e+08 1.27615e+08 1.92320e+07 5717.01 1361.68 122.113 97.7861 1114397 11021065 660432 349453 53 168974 802689 141308298 36713877 45717834 6972091 95590464 29741786 0 0 792797 514828 747302 747302 910805 802689 2332383 1256218 40556637 4114854 1173010 341749 3457595 1539720 44978029 13690833 0 0 46359740 13705684 0 0 792797 0 1048626 1953882 3472000 3402169 10847209 13973 508 19.5428 19.5428 -25846 -19.5428 0 0 2.42407e+07 7205.90 14.24 130.51 4.88 34.68 0.19 14.24 14.3145 11.5453 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 1994.99 vpr 898.68 MiB -1 -1 61.01 621344 14 118.10 -1 -1 123276 -1 -1 2287 257 0 11 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 920252 257 32 35747 33389 1 18576 2587 58 58 3364 clb auto 366.7 MiB 66.13 238606 672.7 MiB 114.11 0.89 17.1228 -22971.9 -17.1228 17.1228 66.43 0.122725 0.105945 15.0557 11.8391 78 394768 147 2.00088e+08 1.27615e+08 1.92320e+07 5717.01 1361.68 122.113 97.7861 1114397 11021065 660432 349453 53 168974 802689 141308298 36713877 45717834 6972091 95590464 29741786 0 0 792797 514828 747302 747302 910805 802689 2332383 1256218 40556637 4114854 1173010 341749 3457595 1539720 44978029 13690833 0 0 46359740 13705684 0 0 792797 0 1048626 1953882 3472000 3402169 10847209 13973 508 19.5428 19.5428 -25846 -19.5428 0 0 2.52407e+07 7305.90 14.24 130.51 4.88 34.68 0.19 14.24 14.3145 11.5453 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU8PEEng.v common 3071.55 vpr 833.25 MiB -1 -1 71.48 455940 98 132.11 -1 -1 115232 -1 -1 1800 114 45 8 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 853252 114 102 35713 31804 1 16705 2069 51 51 2601 clb auto 339.9 MiB 62.95 216212 561.5 MiB 92.18 0.71 65.1279 -53179 -65.1279 65.1279 49.18 0.120059 0.101817 14.974 11.8502 96 359574 127 1.52527e+08 1.2484e+08 1.77902e+07 6839.76 2509.64 176.104 141.33 1051316 9491173 587229 299163 55 145183 626548 203387007 66494555 41102351 7195584 162284656 59298971 0 0 557595 348397 529205 529205 686930 626548 3869612 1660071 37419060 5169165 813788 245793 2438766 1051474 77969311 28517504 0 0 79102740 28346398 0 0 557595 0 1827926 1276985 1909761 1891717 6237045 74462 22447 75.1357 75.1357 -67113 -75.1357 -0.0967573 -0.0199062 2.21294e+07 8508.02 8.37 98.67 2.89 16.30 0.13 8.37 6.86691 5.51408 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision0.v common 491.17 vpr 361.63 MiB -1 -1 13.25 101972 5 13.80 -1 -1 69408 -1 -1 673 169 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 370312 169 197 23321 21461 1 6785 1039 33 33 1089 clb auto 180.8 MiB 12.19 42112 221.0 MiB 12.30 0.12 3.10868 -13056.7 -3.10868 3.10868 5.95 0.0421986 0.0328892 4.76161 3.85299 58 63990 244 6.0475e+07 3.62708e+07 4.62388e+06 4245.99 385.70 79.3922 66.3623 452845 3145025 280765 57244 49 46719 122488 12901034 3413607 6417997 1071484 6483037 2342123 0 0 99450 91334 71450 71450 127765 122488 173471 117401 5739165 636855 123351 34238 451617 220807 2978920 1062567 0 0 3135845 1056467 0 0 99450 0 417639 158865 157759 165849 512493 25863 4191 3.58485 3.58485 -15007.4 -3.58485 0 0 5.85783e+06 5379.09 3.06 25.65 1.05 12.08 0.19 3.06 4.27202 3.58561 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision1.v common 1731.31 vpr 388.00 MiB -1 -1 10.47 123456 3 17.68 -1 -1 77352 -1 -1 655 115 0 40 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 397312 115 145 22868 19305 1 9712 955 40 40 1600 mult_36 auto 177.4 MiB 9.52 82272 238.0 MiB 13.23 0.12 5.15059 -21406.4 -5.15059 5.15059 8.56 0.0361559 0.0312351 4.65663 3.86719 76 154775 184 9.16046e+07 5.11412e+07 8.72311e+06 5451.94 1612.65 90.8987 76.51 519336 3912846 269202 122007 30 61007 155688 38640235 6222360 6668491 918705 31971744 5303655 0 0 115015 107081 104788 104788 162701 155688 2093369 113670 5939763 436808 143497 55137 451012 219128 14854225 2513893 0 0 14775865 2516167 0 0 115015 0 643171 157906 453642 427511 882511 43939 8570 5.48939 5.48939 -24883.8 -5.48939 0 0 1.08598e+07 6787.37 5.55 30.87 1.96 11.01 0.18 5.55 3.14734 2.6417 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 5871.63 vpr 1.05 GiB -1 -1 14.96 197124 3 8.63 -1 -1 155544 -1 -1 1490 149 0 179 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1100488 149 182 55416 37075 1 28670 2000 80 80 6400 mult_36 auto 360.6 MiB 29.07 291939 1074.7 MiB 79.70 0.55 12.5458 -48952.6 -12.5458 12.5458 135.77 0.108801 0.0950539 15.7001 12.8522 78 437698 224 3.90281e+08 1.51186e+08 3.69986e+07 5781.04 5479.15 81.5782 67.7414 1647473 12742193 618027 380228 28 138212 241867 64603805 10299476 9587932 1487408 55015873 8812068 0 0 208298 193889 166401 166401 247323 241867 3307020 170969 8438805 627104 233900 115896 693506 424548 25609640 4121299 0 0 25698912 4237503 0 0 208298 0 605901 210574 379701 368344 1028019 35661 9945 13.929 13.929 -56870.7 -13.929 0 0 4.66105e+07 7282.88 19.01 37.94 5.93 15.28 0.13 19.01 3.18631 2.64796 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision1.v common 1731.31 vpr 388.00 MiB -1 -1 10.47 123456 3 17.68 -1 -1 77352 -1 -1 655 115 0 40 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 397312 115 145 22868 19305 1 9712 955 40 40 1600 mult_36 auto 177.4 MiB 9.52 82272 238.0 MiB 13.23 0.12 5.15059 -21406.4 -5.15059 5.15059 8.56 0.0361559 0.0312351 4.65663 3.86719 76 154775 184 9.16046e+07 5.11412e+07 8.72311e+06 5451.94 1612.65 90.8987 76.51 519336 3912846 269202 122007 30 61007 155688 38640235 6222360 6668491 918705 31971744 5303655 0 0 115015 107081 104788 104788 162701 155688 2093369 113670 5939763 436808 143497 55137 451012 219128 14854225 2513893 0 0 14775865 2516167 0 0 115015 0 643171 157906 453642 427511 882511 43939 8570 5.48939 5.48939 -24883.8 -5.48939 0 0 1.18598e+07 6887.37 5.55 30.87 1.96 11.01 0.18 5.55 3.14734 2.6417 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 5871.63 vpr 1.05 GiB -1 -1 14.96 197124 3 8.63 -1 -1 155544 -1 -1 1490 149 0 179 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:32 gh-actions-runner-vtr-auto-spawned40 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1100488 149 182 55416 37075 1 28670 2000 80 80 6400 mult_36 auto 360.6 MiB 29.07 291939 1074.7 MiB 79.70 0.55 12.5458 -48952.6 -12.5458 12.5458 135.77 0.108801 0.0950539 15.7001 12.8522 78 437698 224 3.90281e+08 1.51186e+08 3.79986e+07 5881.04 5479.15 81.5782 67.7414 1647473 12742193 618027 380228 28 138212 241867 64603805 10299476 9587932 1487408 55015873 8812068 0 0 208298 193889 166401 166401 247323 241867 3307020 170969 8438805 627104 233900 115896 693506 424548 25609640 4121299 0 0 25698912 4237503 0 0 208298 0 605901 210574 379701 368344 1028019 35661 9945 13.929 13.929 -56870.7 -13.929 0 0 4.76105e+07 7382.88 19.01 37.94 5.93 15.28 0.13 19.01 3.18631 2.64796 From 9503eaef0aaa5769a84e43b17695714a08c8628b Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 3 Jul 2023 17:06:32 -0400 Subject: [PATCH 50/51] remove SURF_desc_stratixiv_arch_timing.blif stap_steering_stratixiv_arch_timing.blif jacobi_stratixiv_arch_timing.blif from flat router test due to run-time --- .../titan_other_flat_router/config/config.txt | 3 --- .../titan_other_flat_router/config/golden_results.txt | 9 +++------ 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt index c0f9a0b723b..7d5f6fe2744 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt @@ -16,7 +16,6 @@ archs_dir=arch/titan circuit_list_add=carpat_stratixiv_arch_timing.blif circuit_list_add=CH_DFSIN_stratixiv_arch_timing.blif circuit_list_add=EKF-SLAM_Jacobians_stratixiv_arch_timing.blif -circuit_list_add=jacobi_stratixiv_arch_timing.blif circuit_list_add=JPEG_stratixiv_arch_timing.blif circuit_list_add=leon2_stratixiv_arch_timing.blif circuit_list_add=leon3mp_stratixiv_arch_timing.blif @@ -24,9 +23,7 @@ circuit_list_add=MMM_stratixiv_arch_timing.blif circuit_list_add=radar20_stratixiv_arch_timing.blif circuit_list_add=random_stratixiv_arch_timing.blif circuit_list_add=Reed_Solomon_stratixiv_arch_timing.blif -circuit_list_add=stap_steering_stratixiv_arch_timing.blif circuit_list_add=sudoku_check_stratixiv_arch_timing.blif -circuit_list_add=SURF_desc_stratixiv_arch_timing.blif circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif circuit_list_add=uoft_raytracer_stratixiv_arch_timing.blif circuit_list_add=wb_conmax_stratixiv_arch_timing.blif diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt index 4a85f6cb8b7..2cced6dacb0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt @@ -2,18 +2,15 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem e stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 724.03 vpr 5.70 GiB 274 964 36 59 0 2 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5973264 22 252 53001 29054 7 24705 1335 89 66 5874 DSP auto 1516.0 MiB 40.68 270604 1958.0 MiB 92.18 0.75 7.51948 -39463.8 -6.51948 3.08082 129.31 0.181115 0.150808 21.8561 18.3131 368243 6.95192 80153 1.51318 130400 315379 369954717 59073055 24491144 2998717 345463573 56074338 0 0 292199 234002 201846 201846 315379 315379 19341216 202185 21565775 884387 18363654 11611700 2317791 1564949 149814292 24377676 0 0 157742565 19680931 0 0 292199 0 2042284 750619 714202 802574 15165 0 1110601 80769 216100 290602 277034 0 931683 669850 498102 511972 3217129 38613 6137 0 0 1.08076e+08 18399.1 49 3157876 31702500 48537 7.53026 3.06532 -43885.6 -6.53026 0 0 32.78 40.73 27.43 5833.3 MiB 265.00 39.8559 33.9658 1958.0 MiB 84.44 133.25 stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 539.31 vpr 5.31 GiB 36 1577 10 10 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5564204 3 33 48977 39238 1 26166 1633 54 40 2160 LAB auto 1550.5 MiB 108.07 293178 1724.2 MiB 121.12 1.09 76.4898 -85096.3 -75.4898 76.4898 15.78 0.170652 0.142027 20.2722 15.8014 381605 7.79215 89563 1.82882 137565 442533 230438994 28491971 42579388 4311848 187859606 24180123 0 0 380093 262572 306547 306547 442533 442533 4245476 306594 38333872 1309469 19604845 14380319 3422890 2297274 80687415 5373664 0 0 83015323 3812999 0 0 380093 0 1512618 1181379 1343577 1794470 17904 0 486249 94422 356216 440386 362189 0 1026369 1086957 987361 1354084 5140891 81296 27169 0 0 3.96465e+07 18354.9 28 2487572 26413249 65185 71.3841 71.3841 -149330 -70.3841 0 0 15.62 34.34 23.11 5433.8 MiB 200.51 30.3212 23.8527 1581.8 MiB 88.68 45.06 stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1391.45 vpr 6.01 GiB 574 2798 16 0 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6300672 4 570 66175 54803 2 39719 3388 91 67 6097 io auto 1814.7 MiB 193.06 659105 2143.7 MiB 250.13 1.88 27.9549 -108129 -26.9549 6.60481 140.88 0.28463 0.217244 34.6982 26.8468 931772 14.0815 206196 3.11616 314838 1697595 1311327970 198704740 163817056 19369477 1147510914 179335263 0 0 1592377 1121179 1189567 1189567 1697595 1697595 11337770 1189732 144075206 5073708 82295681 67876681 16451878 11476995 517306200 60791241 0 0 535381696 48288042 0 0 1592377 0 4236357 6319054 5415679 6163889 15721 0 464019 97555 562890 687127 1576656 0 3772338 6221499 4852789 5476762 23025445 121595 30748 0 0 1.12157e+08 18395.4 24 4532884 54099067 129419 28.8704 7.0766 -121066 -27.8704 0 0 40.23 62.17 39.54 6153.0 MiB 582.45 50.6298 39.392 2143.7 MiB 87.52 140.45 -stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 800.97 vpr 5.58 GiB 536 1962 7 4 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5847344 227 309 49176 40422 1 28220 2509 85 63 5355 io auto 1616.8 MiB 138.19 303270 1949.1 MiB 168.05 1.50 197.23 -113715 -196.23 197.23 92.63 0.189236 0.143557 23.5813 18.0343 393684 8.00626 93162 1.89461 162949 658111 270280106 29825234 63918192 6270943 206361914 23554291 0 0 562412 352766 460262 460262 658111 658111 1503628 460280 57459224 1957395 24439725 17332116 5238445 3302671 88794969 3797242 0 0 91163330 1504391 0 0 562412 0 2099326 2078348 2149503 2999193 11244 0 817402 55354 371760 515964 551168 0 1281924 2022994 1777743 2483229 8522001 107515 11979 0 0 9.84408e+07 18383.0 30 3535296 41101308 80255 189.802 189.802 -128363 -188.802 0 0 31.83 40.09 24.91 5710.3 MiB 216.35 35.3625 27.516 1949.1 MiB 86.49 119.26 -stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 623.46 vpr 5.92 GiB 36 1338 8 149 2 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6209784 3 33 52402 39411 1 28023 1533 73 54 3942 M9K auto 1573.5 MiB 106.21 338946 1836.8 MiB 100.37 0.94 16.6959 -307104 -15.6959 16.6959 37.70 0.187832 0.14087 19.1915 14.7731 421374 8.04241 95941 1.83114 140317 546369 215430452 25360491 45006667 4604528 170423785 20755963 0 0 424772 280810 306566 306566 546369 546369 2452049 306695 40253861 1480834 19144962 12974730 3781665 2296515 73986992 4191139 0 0 74533216 2976833 0 0 424772 0 4134534 1353428 1493062 1806299 52695 0 2576546 243018 486970 647622 372077 0 1557988 1110410 1006092 1158677 6063070 175837 23073 0 0 7.26339e+07 18425.6 45 3037750 30141692 81349 17.82 17.82 -331498 -16.82 0 0 25.80 54.23 38.14 6064.2 MiB 220.45 37.3054 29.5242 1773.9 MiB 80.25 96.75 +stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 623.46 vpr 5.92 GiB 36 1338 8 149 2 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6209784 3 33 52402 39411 1 28023 1533 73 54 3942 M9K auto 1573.5 MiB 106.21 338946 1836.8 MiB 100.37 0.94 16.6959 -307104 -15.6959 16.6959 37.70 0.187832 0.14087 19.1915 14.7731 421374 8.04241 95941 1.83114 140317 546369 215430452 25360491 45006667 4604528 170423785 20755963 0 0 424772 280810 306566 306566 546369 546369 2452049 306695 40253861 1480834 19144962 12974730 3781665 2296515 73986992 4191139 0 0 74533216 2976833 0 0 424772 0 4134534 1353428 1493062 1806299 52695 0 2576546 243018 486970 647622 372077 0 1557988 1110410 1006092 1158677 6063070 175837 23073 0 0 7.26339e+07 18425.6 45 3037750 30141692 81349 17.82 17.82 -331498 -16.82 0 0 25.80 54.23 38.14 6064.2 MiB 220.45 37.3054 29.5242 1773.9 MiB 80.25 96.75 stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 289.04 vpr 4.85 GiB 251 954 1 17 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5083312 55 196 20131 19956 1 8402 1223 44 33 1452 io auto 1387.8 MiB 60.13 122203 1565.4 MiB 24.41 0.26 7.45116 -75262 -6.45116 7.45116 9.47 0.0728801 0.0544044 6.8687 5.21778 169783 8.43517 39632 1.96900 53392 235921 76726339 8059376 22730673 1821601 53995666 6237775 0 0 155059 105372 164275 164275 235921 235921 318412 164284 20993349 700737 5827210 4268889 1346344 779571 23676377 1098668 0 0 24009392 541659 0 0 155059 0 1019609 489149 693078 825450 10413 0 745335 50161 363526 439076 144646 0 274274 438988 329552 386374 1658043 92118 14854 0 0 2.65099e+07 18257.5 23 1360736 16121963 53571 8.13898 8.13898 -83014.8 -7.13898 0 0 8.46 19.79 13.14 4964.2 MiB 130.88 10.4843 8.15736 1427.9 MiB 84.57 29.96 stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 535.09 vpr 5.47 GiB 255 2097 1 28 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5738328 84 171 36458 36247 3 20325 2381 62 46 2852 LAB auto 1558.8 MiB 121.50 297719 1769.6 MiB 85.34 0.69 11.8295 -83637.5 -10.8295 4.15308 25.68 0.162455 0.121074 18.1658 13.7113 391178 10.7337 86790 2.38146 125489 595006 176086872 18729085 56694576 4311822 119392296 14417263 0 0 320977 242800 384898 384898 595006 595006 723333 385492 52893112 1763265 13590105 9282004 2885481 1710751 51772924 2771940 0 0 52921036 1592929 0 0 320977 0 3210341 946488 2495420 3089570 16094 0 2781775 77325 1265737 1554764 304883 0 428566 869163 1229683 1534806 4429863 292416 108426 0 0 5.24521e+07 18391.3 15 2648834 32075053 67963 12.6095 4.26522 -93814.6 -11.6095 0 0 16.97 48.37 33.58 5603.8 MiB 191.10 23.2876 17.6841 1667.2 MiB 82.13 59.78 stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 852.44 vpr 6.18 GiB 478 1236 1 300 4 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6478596 202 276 35125 30509 3 21529 2019 106 79 8374 M9K auto 1502.9 MiB 88.41 272765 2200.2 MiB 72.79 0.54 9.19202 -37842.6 -8.19202 3.20486 190.05 0.152211 0.112097 18.8747 14.2554 321153 9.14471 66385 1.89029 100068 414752 157765195 23476080 34300621 3443454 123464574 20032626 0 0 380002 234539 227242 227242 414752 414752 645006 227374 30592761 1126998 23059023 16098127 2913106 1667165 49596947 2101209 0 0 49936356 1378674 0 0 380002 0 2239906 1263651 886120 1197078 17025 0 745824 80126 161479 232461 362977 0 1494082 1183525 724641 964617 5471532 52141 12195 0 0 1.54360e+08 18433.2 20 3958220 42984491 64532 7.91139 3.47325 -67174.2 -6.91139 0 0 45.25 64.76 45.68 6326.8 MiB 206.73 26.3683 20.2581 2200.2 MiB 87.53 216.41 stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 533.90 vpr 5.39 GiB 5 331 31 105 0 2 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5649024 3 2 14862 10304 26 7485 474 89 66 5874 DSP auto 1321.0 MiB 43.11 125450 1838.3 MiB 13.87 0.14 5.8049 -30200.5 -4.8049 3.81023 134.63 0.0801368 0.0622523 7.83848 6.28028 149562 10.0810 29852 2.01213 42275 171541 55874626 6342617 13497784 1013659 42376842 5328958 0 0 82571 62876 57398 57398 171541 171541 1368476 57398 12637823 432299 3698819 2360987 605849 346943 18576038 1575874 0 0 18676111 1277301 0 0 82571 0 3058530 168485 355362 469549 2856 0 2860226 13832 191857 308956 79715 0 198304 154653 163505 160593 844858 92266 6927 0 0 1.08076e+08 18399.1 15 2294013 23927517 37921 4.65543 3.70469 -39979.2 -3.65543 0 0 33.81 34.31 23.09 5516.6 MiB 143.82 10.704 8.72846 1838.3 MiB 88.05 138.55 stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 982.22 vpr 5.89 GiB 693 1763 25 16 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6181084 35 658 51416 37539 1 27797 2497 108 80 8640 io auto 1608.7 MiB 97.35 253700 2292.8 MiB 137.07 1.03 36.6178 -57981.3 -35.6178 36.6178 188.71 0.216948 0.172494 28.1745 22.387 342704 6.86713 79905 1.60114 147879 604761 355456965 49730892 56242397 6818146 299214568 42912746 0 0 569044 415415 379482 379482 604761 604761 7147933 379648 49043058 1780714 33506965 23806571 6025534 4017256 127359105 10638500 0 0 130821083 7708545 0 0 569044 0 2194580 2040073 774389 1241923 19004 0 618226 95542 152225 241684 550040 0 1576354 1944531 622164 1000239 6224066 54966 4101 0 0 1.59377e+08 18446.5 30 4400944 49964640 86213 36.9882 36.9882 -62153.7 -35.9882 0 0 47.43 48.23 30.53 6036.2 MiB 254.66 41.7569 33.7374 2292.8 MiB 83.42 222.18 stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 889.54 vpr 5.52 GiB 753 1119 5 32 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5787504 13 740 25173 25306 1 12707 1909 117 87 10179 io auto 1437.6 MiB 73.19 158034 2342.4 MiB 49.35 0.37 9.0794 -29604.5 -8.0794 7.71568 222.23 0.100307 0.0852136 12.5514 9.86111 193121 7.67389 42189 1.67643 68666 318011 113363267 12851301 30536084 2692879 82827183 10158422 0 0 263048 182024 199766 199766 318011 318011 583589 199819 27704779 929336 12145303 7855017 2250246 1263508 34922315 1239693 0 0 34976210 664127 0 0 263048 0 963421 881555 640303 841712 9439 0 312458 41087 260847 322454 253609 0 650963 840468 379456 519258 2886477 64695 4536 0 0 1.87947e+08 18464.1 52 4146327 46175295 62070 8.10698 7.61424 -41591.4 -7.10698 0 0 58.60 39.13 19.80 5651.9 MiB 171.85 24.1564 19.2466 2342.4 MiB 84.92 284.07 -stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 559.00 vpr 5.47 GiB 213 1559 26 4 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5740704 139 74 57121 41054 1 24028 1802 75 56 4200 DSP auto 1617.5 MiB 89.74 173770 1898.2 MiB 87.12 0.73 5.20056 -21125.5 -4.20056 5.20056 33.04 0.187168 0.159192 24.0201 19.5353 224393 3.92866 53407 0.935046 120332 318885 164347721 23845710 27853588 2583308 136494133 21262402 0 0 250265 196712 167434 167434 318885 318885 5773170 167546 25346412 929536 12885884 7251282 1938026 1138175 57986619 7508634 0 0 59681026 6167506 0 0 250265 0 2397225 564454 683963 792564 18687 0 1693953 88421 341436 374993 231578 0 703272 476033 342527 417571 2388860 87603 20079 0 0 7.74195e+07 18433.2 19 3167795 32633349 56854 5.56045 5.56045 -67348.3 -4.56045 0 0 28.05 36.96 24.00 5606.2 MiB 192.27 32.8036 26.9313 1843.7 MiB 87.90 92.61 -stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 293.00 vpr 5.17 GiB 54 667 0 40 0 1 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5418440 2 52 16673 16662 2 12034 762 37 27 999 LAB auto 1362.8 MiB 50.95 180205 1523.6 MiB 23.86 0.26 5.54068 -21652.7 -4.54068 4.89195 5.87 0.0994218 0.0746617 8.59683 6.58275 231884 13.9111 53316 3.19851 68185 368628 159574746 19219539 34743038 3070245 124831708 16149294 0 0 286491 201060 223149 223149 368628 368628 537575 223149 31640299 1049028 11336066 8724196 2447620 1451529 56194239 4012681 0 0 56540679 2966119 0 0 286491 0 1847460 1033627 856189 1214055 4819 0 1415998 29957 259201 442979 281672 0 431462 1003670 596988 771076 3208758 87191 7627 0 0 1.81152e+07 18133.3 19 1111277 11680547 35180 5.83088 5.25163 -27116.6 -4.83088 0 0 6.22 19.75 14.37 5291.4 MiB 160.20 12.6556 9.88051 1363.0 MiB 89.47 19.98 -stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 707.98 vpr 6.13 GiB 445 2165 19 51 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6431256 131 314 57881 45152 1 32949 2680 73 54 3942 io auto 1709.7 MiB 113.42 319720 1953.7 MiB 181.54 1.65 195.879 -69216.9 -194.879 195.879 39.78 0.252116 0.197507 29.0133 22.8181 423129 7.31968 101694 1.75920 148456 639588 260866551 30599295 59753838 5877781 201112713 24721514 0 0 559292 339631 402428 402428 639588 639588 2389955 402429 53761488 1867973 23404058 17589918 4793470 3030589 86461742 4105384 0 0 88454530 2221355 0 0 559292 0 3072021 1978568 1619414 2293719 11881 0 1547575 57250 306957 398241 547411 0 1524446 1921318 1312457 1895478 7735497 92623 9144 0 0 7.26339e+07 18425.6 21 3424933 39491074 105365 187.99 187.99 -80162.4 -186.99 0 0 21.71 56.34 39.83 6280.5 MiB 227.45 40.5696 32.2386 1865.9 MiB 85.65 87.02 -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 204.59 vpr 4.71 GiB 42 750 0 0 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 4934484 13 29 26295 20086 1 12166 792 39 29 1131 LAB auto 1355.8 MiB 18.26 79073 1499.4 MiB 12.67 0.17 4.99447 -4598.46 -3.99447 2.56728 9.74 0.0408075 0.0306573 3.08024 2.36323 84706 3.22162 19939 0.758339 53380 71551 35810607 4346308 7169692 721973 28640915 3624335 0 0 70074 64306 39683 39683 71551 71551 77213 39683 6428768 207974 3822355 2587809 599299 378142 12329998 582963 0 0 12371666 374197 0 0 70074 0 32280 78309 77684 88810 486 0 9331 2407 8564 9172 69588 0 22949 75902 69120 79638 324991 1976 169 0 0 2.05958e+07 18210.3 16 1246346 12342987 13974 3.67397 2.78594 -5489.42 -2.67397 0 0 8.33 14.11 8.43 4818.8 MiB 108.70 4.56965 3.56741 1356.1 MiB 83.19 22.11 +stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 293.00 vpr 5.17 GiB 54 667 0 40 0 1 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5418440 2 52 16673 16662 2 12034 762 37 27 999 LAB auto 1362.8 MiB 50.95 180205 1523.6 MiB 23.86 0.26 5.54068 -21652.7 -4.54068 4.89195 5.87 0.0994218 0.0746617 8.59683 6.58275 231884 13.9111 53316 3.19851 68185 368628 159574746 19219539 34743038 3070245 124831708 16149294 0 0 286491 201060 223149 223149 368628 368628 537575 223149 31640299 1049028 11336066 8724196 2447620 1451529 56194239 4012681 0 0 56540679 2966119 0 0 286491 0 1847460 1033627 856189 1214055 4819 0 1415998 29957 259201 442979 281672 0 431462 1003670 596988 771076 3208758 87191 7627 0 0 1.81152e+07 18133.3 19 1111277 11680547 35180 5.83088 5.25163 -27116.6 -4.83088 0 0 6.22 19.75 14.37 5291.4 MiB 160.20 12.6556 9.88051 1363.0 MiB 89.47 19.98 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 204.59 vpr 4.71 GiB 42 750 0 0 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 4934484 13 29 26295 20086 1 12166 792 39 29 1131 LAB auto 1355.8 MiB 18.26 79073 1499.4 MiB 12.67 0.17 4.99447 -4598.46 -3.99447 2.56728 9.74 0.0408075 0.0306573 3.08024 2.36323 84706 3.22162 19939 0.758339 53380 71551 35810607 4346308 7169692 721973 28640915 3624335 0 0 70074 64306 39683 39683 71551 71551 77213 39683 6428768 207974 3822355 2587809 599299 378142 12329998 582963 0 0 12371666 374197 0 0 70074 0 32280 78309 77684 88810 486 0 9331 2407 8564 9172 69588 0 22949 75902 69120 79638 324991 1976 169 0 0 2.05958e+07 18210.3 16 1246346 12342987 13974 3.67397 2.78594 -5489.42 -2.67397 0 0 8.33 14.11 8.43 4818.8 MiB 108.70 4.56965 3.56741 1356.1 MiB 83.19 22.11 stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 1440.68 vpr 5.95 GiB 964 975 19 34 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6243852 542 422 37277 26038 1 20638 1992 147 109 16023 io auto 1457.3 MiB 68.11 265616 2957.8 MiB 130.84 1.32 9.50199 -37449.9 -8.50199 7.76547 446.34 0.154323 0.122043 19.4004 15.4157 346368 9.29248 74610 2.00166 111681 335798 225684897 32982492 30145170 2987038 195539727 29995454 0 0 285411 214827 225188 225188 335798 335798 7773731 225235 27183983 965579 15041522 10398103 2339978 1470834 85189134 10535986 0 0 87310152 8610942 0 0 285411 0 1400706 804069 776939 980670 22123 0 858991 118238 336761 389597 263288 0 541715 685831 440178 591073 2711363 72825 6767 0 0 2.96650e+08 18514.0 44 5879056 65354821 47001 9.73561 8.3395 -52222.9 -8.73561 0 0 86.75 54.56 25.72 6097.5 MiB 231.36 32.2214 26.2723 2957.8 MiB 88.18 446.38 stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 1746.53 vpr 5.80 GiB 1107 721 0 0 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6083664 403 704 15490 16194 1 8416 1828 167 124 20708 io auto 1355.1 MiB 59.70 189937 3390.6 MiB 33.55 0.28 11.9901 -21784.8 -10.9901 5.40422 745.67 0.0774104 0.0592605 9.01753 7.02446 228761 14.7693 38073 2.45807 42292 231691 73919422 8177400 21781227 1880323 52138195 6297077 0 0 179143 127127 152350 152350 231691 231691 304289 152359 19911029 688047 7966938 4884142 1459364 833458 21686811 720452 0 0 22027807 387774 0 0 179143 0 779210 618357 483897 682252 1996 0 247223 9903 230558 278915 177147 0 531987 608454 253339 403337 2129825 55069 11488 0 0 3.84012e+08 18544.1 17 6720933 74598148 36972 11.192 5.69083 -32768.9 -10.192 0 0 117.06 43.71 12.36 5941.1 MiB 160.29 12.0424 9.52154 3390.6 MiB 87.90 601.39 stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 271.24 vpr 4.73 GiB 35 735 0 6 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 4958080 18 17 16969 16357 1 6386 776 39 29 1131 LAB auto 1350.4 MiB 61.78 83840 1500.3 MiB 14.04 0.21 6.69002 -41482 -5.69002 6.69002 10.03 0.0619772 0.0441029 4.77898 3.5581 116545 6.86973 27597 1.62670 47883 252762 83846950 9755433 24060813 2054513 59786137 7700920 0 0 145109 104792 184133 184133 252762 252762 320376 184144 22206371 749723 6773270 5256108 1456571 947236 26101354 1343417 0 0 26407004 733118 0 0 145109 0 1178090 448604 746438 874371 6074 0 935259 29306 435121 518151 139035 0 242831 419298 311317 356220 1551320 114680 27537 0 0 2.05958e+07 18210.3 30 1091507 12261694 43464 6.85394 6.85394 -47185.7 -5.85394 0 0 7.05 14.75 9.46 4841.9 MiB 131.10 8.66982 6.72886 1353.0 MiB 87.46 22.50 From 171ab850f83daefe6d340257c75d4b2b06a698ed Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 7 Jul 2023 18:34:43 -0400 Subject: [PATCH 51/51] update titan_other_flat_router golden results --- .../config/golden_results.txt | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt index 2cced6dacb0..adf7f19d5f3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/golden_results.txt @@ -1,17 +1,17 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops total_internal_heap_pushes total_internal_heap_pops total_external_heap_pushes total_external_heap_pops total_external_SOURCE_pushes total_external_SOURCE_pops total_internal_SOURCE_pushes total_internal_SOURCE_pops total_external_SINK_pushes total_external_SINK_pops total_internal_SINK_pushes total_internal_SINK_pops total_external_IPIN_pushes total_external_IPIN_pops total_internal_IPIN_pushes total_internal_IPIN_pops total_external_OPIN_pushes total_external_OPIN_pops total_internal_OPIN_pushes total_internal_OPIN_pops total_external_CHANX_pushes total_external_CHANX_pops total_internal_CHANX_pushes total_internal_CHANX_pops total_external_CHANY_pushes total_external_CHANY_pops total_internal_CHANY_pushes total_internal_CHANY_pops rt_node_SOURCE_pushes rt_node_SINK_pushes rt_node_IPIN_pushes rt_node_OPIN_pushes rt_node_CHANX_pushes rt_node_CHANY_pushes rt_node_SOURCE_high_fanout_pushes rt_node_SINK_high_fanout_pushes rt_node_IPIN_high_fanout_pushes rt_node_OPIN_high_fanout_pushes rt_node_CHANX_high_fanout_pushes rt_node_CHANY_high_fanout_pushes rt_node_SOURCE_entire_tree_pushes rt_node_SINK_entire_tree_pushes rt_node_IPIN_entire_tree_pushes rt_node_OPIN_entire_tree_pushes rt_node_CHANX_entire_tree_pushes rt_node_CHANY_entire_tree_pushes adding_all_rt adding_high_fanout_rt total_number_of_adding_all_rt_from_calling_high_fanout_rt logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 724.03 vpr 5.70 GiB 274 964 36 59 0 2 success 8528925-dirty release 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10 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5564204 3 33 48977 39238 1 26166 1633 54 40 2160 LAB auto 1550.5 MiB 108.07 293178 1724.2 MiB 121.12 1.09 76.4898 -85096.3 -75.4898 76.4898 15.78 0.170652 0.142027 20.2722 15.8014 381605 7.79215 89563 1.82882 137565 442533 230438994 28491971 42579388 4311848 187859606 24180123 0 0 380093 262572 306547 306547 442533 442533 4245476 306594 38333872 1309469 19604845 14380319 3422890 2297274 80687415 5373664 0 0 83015323 3812999 0 0 380093 0 1512618 1181379 1343577 1794470 17904 0 486249 94422 356216 440386 362189 0 1026369 1086957 987361 1354084 5140891 81296 27169 0 0 3.96465e+07 18354.9 28 2487572 26413249 65185 71.3841 71.3841 -149330 -70.3841 0 0 15.62 34.34 23.11 5433.8 MiB 200.51 30.3212 23.8527 1581.8 MiB 88.68 45.06 -stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1391.45 vpr 6.01 GiB 574 2798 16 0 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6300672 4 570 66175 54803 2 39719 3388 91 67 6097 io auto 1814.7 MiB 193.06 659105 2143.7 MiB 250.13 1.88 27.9549 -108129 -26.9549 6.60481 140.88 0.28463 0.217244 34.6982 26.8468 931772 14.0815 206196 3.11616 314838 1697595 1311327970 198704740 163817056 19369477 1147510914 179335263 0 0 1592377 1121179 1189567 1189567 1697595 1697595 11337770 1189732 144075206 5073708 82295681 67876681 16451878 11476995 517306200 60791241 0 0 535381696 48288042 0 0 1592377 0 4236357 6319054 5415679 6163889 15721 0 464019 97555 562890 687127 1576656 0 3772338 6221499 4852789 5476762 23025445 121595 30748 0 0 1.12157e+08 18395.4 24 4532884 54099067 129419 28.8704 7.0766 -121066 -27.8704 0 0 40.23 62.17 39.54 6153.0 MiB 582.45 50.6298 39.392 2143.7 MiB 87.52 140.45 -stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 623.46 vpr 5.92 GiB 36 1338 8 149 2 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6209784 3 33 52402 39411 1 28023 1533 73 54 3942 M9K auto 1573.5 MiB 106.21 338946 1836.8 MiB 100.37 0.94 16.6959 -307104 -15.6959 16.6959 37.70 0.187832 0.14087 19.1915 14.7731 421374 8.04241 95941 1.83114 140317 546369 215430452 25360491 45006667 4604528 170423785 20755963 0 0 424772 280810 306566 306566 546369 546369 2452049 306695 40253861 1480834 19144962 12974730 3781665 2296515 73986992 4191139 0 0 74533216 2976833 0 0 424772 0 4134534 1353428 1493062 1806299 52695 0 2576546 243018 486970 647622 372077 0 1557988 1110410 1006092 1158677 6063070 175837 23073 0 0 7.26339e+07 18425.6 45 3037750 30141692 81349 17.82 17.82 -331498 -16.82 0 0 25.80 54.23 38.14 6064.2 MiB 220.45 37.3054 29.5242 1773.9 MiB 80.25 96.75 -stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 289.04 vpr 4.85 GiB 251 954 1 17 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5083312 55 196 20131 19956 1 8402 1223 44 33 1452 io auto 1387.8 MiB 60.13 122203 1565.4 MiB 24.41 0.26 7.45116 -75262 -6.45116 7.45116 9.47 0.0728801 0.0544044 6.8687 5.21778 169783 8.43517 39632 1.96900 53392 235921 76726339 8059376 22730673 1821601 53995666 6237775 0 0 155059 105372 164275 164275 235921 235921 318412 164284 20993349 700737 5827210 4268889 1346344 779571 23676377 1098668 0 0 24009392 541659 0 0 155059 0 1019609 489149 693078 825450 10413 0 745335 50161 363526 439076 144646 0 274274 438988 329552 386374 1658043 92118 14854 0 0 2.65099e+07 18257.5 23 1360736 16121963 53571 8.13898 8.13898 -83014.8 -7.13898 0 0 8.46 19.79 13.14 4964.2 MiB 130.88 10.4843 8.15736 1427.9 MiB 84.57 29.96 -stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 535.09 vpr 5.47 GiB 255 2097 1 28 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5738328 84 171 36458 36247 3 20325 2381 62 46 2852 LAB auto 1558.8 MiB 121.50 297719 1769.6 MiB 85.34 0.69 11.8295 -83637.5 -10.8295 4.15308 25.68 0.162455 0.121074 18.1658 13.7113 391178 10.7337 86790 2.38146 125489 595006 176086872 18729085 56694576 4311822 119392296 14417263 0 0 320977 242800 384898 384898 595006 595006 723333 385492 52893112 1763265 13590105 9282004 2885481 1710751 51772924 2771940 0 0 52921036 1592929 0 0 320977 0 3210341 946488 2495420 3089570 16094 0 2781775 77325 1265737 1554764 304883 0 428566 869163 1229683 1534806 4429863 292416 108426 0 0 5.24521e+07 18391.3 15 2648834 32075053 67963 12.6095 4.26522 -93814.6 -11.6095 0 0 16.97 48.37 33.58 5603.8 MiB 191.10 23.2876 17.6841 1667.2 MiB 82.13 59.78 -stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 852.44 vpr 6.18 GiB 478 1236 1 300 4 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6478596 202 276 35125 30509 3 21529 2019 106 79 8374 M9K auto 1502.9 MiB 88.41 272765 2200.2 MiB 72.79 0.54 9.19202 -37842.6 -8.19202 3.20486 190.05 0.152211 0.112097 18.8747 14.2554 321153 9.14471 66385 1.89029 100068 414752 157765195 23476080 34300621 3443454 123464574 20032626 0 0 380002 234539 227242 227242 414752 414752 645006 227374 30592761 1126998 23059023 16098127 2913106 1667165 49596947 2101209 0 0 49936356 1378674 0 0 380002 0 2239906 1263651 886120 1197078 17025 0 745824 80126 161479 232461 362977 0 1494082 1183525 724641 964617 5471532 52141 12195 0 0 1.54360e+08 18433.2 20 3958220 42984491 64532 7.91139 3.47325 -67174.2 -6.91139 0 0 45.25 64.76 45.68 6326.8 MiB 206.73 26.3683 20.2581 2200.2 MiB 87.53 216.41 -stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 533.90 vpr 5.39 GiB 5 331 31 105 0 2 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5649024 3 2 14862 10304 26 7485 474 89 66 5874 DSP auto 1321.0 MiB 43.11 125450 1838.3 MiB 13.87 0.14 5.8049 -30200.5 -4.8049 3.81023 134.63 0.0801368 0.0622523 7.83848 6.28028 149562 10.0810 29852 2.01213 42275 171541 55874626 6342617 13497784 1013659 42376842 5328958 0 0 82571 62876 57398 57398 171541 171541 1368476 57398 12637823 432299 3698819 2360987 605849 346943 18576038 1575874 0 0 18676111 1277301 0 0 82571 0 3058530 168485 355362 469549 2856 0 2860226 13832 191857 308956 79715 0 198304 154653 163505 160593 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833458 21686811 720452 0 0 22027807 387774 0 0 179143 0 779210 618357 483897 682252 1996 0 247223 9903 230558 278915 177147 0 531987 608454 253339 403337 2129825 55069 11488 0 0 3.84012e+08 18544.1 17 6720933 74598148 36972 11.192 5.69083 -32768.9 -10.192 0 0 117.06 43.71 12.36 5941.1 MiB 160.29 12.0424 9.52154 3390.6 MiB 87.90 601.39 -stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 271.24 vpr 4.73 GiB 35 735 0 6 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 4958080 18 17 16969 16357 1 6386 776 39 29 1131 LAB auto 1350.4 MiB 61.78 83840 1500.3 MiB 14.04 0.21 6.69002 -41482 -5.69002 6.69002 10.03 0.0619772 0.0441029 4.77898 3.5581 116545 6.86973 27597 1.62670 47883 252762 83846950 9755433 24060813 2054513 59786137 7700920 0 0 145109 104792 184133 184133 252762 252762 320376 184144 22206371 749723 6773270 5256108 1456571 947236 26101354 1343417 0 0 26407004 733118 0 0 145109 0 1178090 448604 746438 874371 6074 0 935259 29306 435121 518151 139035 0 242831 419298 311317 356220 1551320 114680 27537 0 0 2.05958e+07 18210.3 30 1091507 12261694 43464 6.85394 6.85394 -47185.7 -5.85394 0 0 7.05 14.75 9.46 4841.9 MiB 131.10 8.66982 6.72886 1353.0 MiB 87.46 22.50 -stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 125.86 vpr 4.39 GiB 35 73 0 8 0 0 success 8528925-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-05-29T15:37:47 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 4607904 18 17 2291 2142 1 1503 116 16 12 192 LAB M9K auto 1226.0 MiB 7.00 10808 1365.9 MiB 1.13 0.01 5.25051 -3435.86 -4.25051 3.99423 0.15 0.0070996 0.00573146 0.317067 0.264439 13948 6.09615 3632 1.58741 7914 29770 10780049 1264163 2669793 257383 8110256 1006780 0 0 26363 18472 14372 14372 29770 29770 36350 14372 2392345 83326 1249561 819040 221315 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25231305 44167996 4469518 168692004 20761787 0 0 414427 274001 303970 303970 529190 529190 2493253 304111 39578720 1442934 18325065 12798038 3645659 2223393 73520139 4289961 0 0 74049577 3065707 0 0 414427 0 3857786 1300556 1404548 1708349 52233 0 2451477 239907 479373 636788 362194 0 1406309 1060649 925175 1071561 5584934 168432 23179 0 0 9.96430e+07 25277.3 34 3037750 30141692 81349 17.8179 17.8179 -331477 -16.8179 0 0 19.93 38.49 23.74 6062.2 MiB 166.89 25.1046 19.9907 1785.5 MiB 69.35 71.72 +stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 241.79 vpr 4.85 GiB 251 954 1 17 0 0 success 46b9987-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-07-03T21:14:06 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5081652 55 196 20131 19956 1 8402 1223 44 33 1452 io auto 1387.5 MiB 45.75 122203 1548.3 MiB 20.21 0.22 7.45116 -75262 -6.45116 7.45116 8.45 0.0585202 0.0434269 5.63729 4.32211 169635 8.42781 39586 1.96671 53358 234674 76267559 7992265 22622735 1817746 53644824 6174519 0 0 154198 105434 162906 162906 234674 234674 311722 162906 20886917 696920 5842523 4244502 1346946 780718 23499477 1074270 0 0 23828196 529935 0 0 154198 0 1033870 486810 703478 840462 10329 0 757241 50167 361130 434639 143869 0 276629 436643 342348 405823 1693100 91644 14265 0 0 3.65488e+07 25171.3 28 1360736 16121963 53571 8.15417 8.15417 -83167.3 -7.15417 0 0 7.64 16.02 9.95 4962.6 MiB 111.31 9.00327 7.08734 1422.7 MiB 72.47 27.26 +stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 437.95 vpr 5.47 GiB 255 2097 1 28 0 0 success 46b9987-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-07-03T21:14:06 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5737060 84 171 36458 36247 3 20325 2381 62 46 2852 LAB auto 1558.7 MiB 93.27 297719 1765.9 MiB 70.87 0.60 11.8295 -83637.5 -10.8295 4.15308 23.09 0.143424 0.109358 15.9535 12.1927 391686 10.7476 86849 2.38308 125508 598448 176572429 18767989 56989900 4329627 119582529 14438362 0 0 321488 243072 387320 387320 598448 598448 729596 388062 53179581 1773169 13605190 9294322 2890383 1714938 51883666 2763115 0 0 52976757 1605543 0 0 321488 0 3233365 948310 2524354 3092049 16532 0 2808024 79915 1288536 1576664 304956 0 425341 868395 1235818 1515385 4406118 295792 112609 0 0 7.20371e+07 25258.4 15 2648834 32075053 67963 12.6145 4.26424 -93963.1 -11.6145 0 0 14.12 33.11 19.68 5602.6 MiB 156.50 20.7684 16.0249 1669.6 MiB 75.28 52.39 +stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 738.24 vpr 6.19 GiB 478 1236 1 300 4 0 success 46b9987-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-07-03T21:14:06 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6488112 202 276 35125 30509 3 21529 2019 106 79 8374 M9K auto 1502.7 MiB 73.51 272765 2207.4 MiB 60.53 0.48 9.19202 -37842.6 -8.19202 3.20486 182.37 0.136898 0.103736 16.4493 12.685 320956 9.13910 66352 1.88935 100167 415115 157993319 23482405 34323808 3445578 123669511 20036827 0 0 381066 234878 227243 227243 415115 415115 642224 227351 30610104 1127641 23077196 16096941 2917523 1667944 49697291 2100860 0 0 50025557 1384432 0 0 381066 0 2227139 1268941 918473 1226694 17433 0 743446 82428 157685 229301 363633 0 1483693 1186513 760788 997393 5526842 51844 12315 0 0 2.11299e+08 25232.8 20 3958220 42984491 64532 7.91139 3.47755 -67229.6 -6.91139 0 0 39.80 57.95 29.64 6336.0 MiB 171.53 21.4318 16.6995 2207.4 MiB 72.19 182.81 +stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 453.19 vpr 5.36 GiB 5 331 31 105 0 2 success 46b9987-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-07-03T21:14:06 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5624880 3 2 14862 10304 26 7485 474 89 66 5874 DSP auto 1320.4 MiB 34.47 125450 1843.3 MiB 10.94 0.11 5.8049 -30200.5 -4.8049 3.81023 118.15 0.0607072 0.0495509 5.99461 4.9777 149819 10.0983 29897 2.01517 42261 171257 55596455 6297388 13474202 1014981 42122253 5282407 0 0 82491 63008 57241 57241 171257 171257 1336653 57241 12612743 431764 3714083 2370064 607711 348952 18453794 1550735 0 0 18560482 1247126 0 0 82491 0 3038453 167652 365739 468667 2750 0 2838075 13146 204158 311224 79741 0 200378 154506 161581 157443 842142 91976 7787 0 0 1.48105e+08 25213.7 13 2294013 23927517 37921 4.65543 3.70404 -39170.9 -3.65543 0 0 28.14 27.33 13.44 5493.0 MiB 119.75 7.84913 6.5749 1843.3 MiB 75.94 121.31 +stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 830.95 vpr 5.89 GiB 693 1763 25 16 0 0 success 46b9987-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-07-03T21:14:06 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 6178032 35 658 51416 37539 1 27797 2497 108 80 8640 io auto 1608.9 MiB 76.67 253700 2300.4 MiB 108.89 0.80 36.6178 -57981.3 -35.6178 36.6178 171.91 0.158204 0.12925 22.1759 17.8341 342733 6.86771 79937 1.60178 141214 573898 344874414 48577102 53252645 6506672 291621769 42070430 0 0 538278 391276 360228 360228 573898 573898 7081017 360265 46490833 1687480 31676243 23376052 5649636 3854018 124496081 10461477 0 0 128008200 7512408 0 0 538278 0 2119611 1913570 745327 1186799 18990 0 631202 95269 152008 238977 519288 0 1488409 1818301 593319 947822 5873469 54852 3680 0 0 2.18145e+08 25248.3 26 4400944 49964640 86213 36.9093 36.9093 -62252.5 -35.9093 0 0 39.64 51.65 21.96 6033.2 MiB 216.24 30.927 25.2045 2300.4 MiB 73.56 188.58 +stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 766.05 vpr 5.51 GiB 753 1119 5 32 0 0 success 46b9987-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-07-03T21:14:06 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5782540 13 740 25173 25306 1 12707 1909 117 87 10179 io auto 1437.3 MiB 59.18 158034 2351.1 MiB 40.46 0.31 9.0794 -29604.5 -8.0794 7.71568 193.63 0.0805726 0.0704518 10.3821 8.39077 193023 7.66999 42155 1.67508 67723 316841 110094427 12492137 30525922 2684272 79568505 9807865 0 0 262116 180684 198341 198341 316841 316841 495413 198377 27700196 926544 11964014 7741355 2246769 1260203 33325147 1126514 0 0 33585590 543278 0 0 262116 0 965199 881583 635973 843315 9466 0 311246 41223 259881 322038 252650 0 653953 840360 376092 521277 2888017 64488 4750 0 0 2.57091e+08 25257.0 19 4146327 46175295 62070 8.10698 7.61424 -41671.4 -7.10698 0 0 51.25 47.23 13.69 5647.0 MiB 151.94 14.057 11.4172 2351.1 MiB 74.52 242.82 +stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 239.62 vpr 5.17 GiB 54 667 0 40 0 1 success 46b9987-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-07-03T21:14:06 gh-actions-runner-vtr-auto-spawned30 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5417848 2 52 16673 16662 2 12034 762 37 27 999 LAB auto 1362.5 MiB 40.22 180205 1521.9 MiB 18.15 0.19 5.54068 -21652.7 -4.54068 4.89195 4.65 0.0717041 0.0562898 6.47426 5.14154 231827 13.9077 53255 3.19485 68116 367622 159055598 19108453 34672375 3059318 124383223 16049135 0 0 285481 200249 223228 223228 367622 367622 537770 223228 31582305 1047276 11283921 8661165 2436967 1444171 55997826 3999152 0 0 56340478 2942362 0 0 285481 0 1841453 1028515 862108 1209475 4776 0 1409514 29885 265500 444129 280705 0 431939 998630 596608 765346 3197345 87150 7950 0 0 2.50432e+07 25068.2 19 1111277 11680547 35180 5.83036 5.24345 -27598.2 -4.83036 0 0 5.20 13.17 8.78 5290.9 MiB 128.35 9.38202 7.5432 1362.6 MiB 75.64 16.03 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 164.03 vpr 4.71 GiB 42 750 0 0 0 0 success 46b9987-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-07-03T21:14:06 gh-actions-runner-vtr-auto-spawned30 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