diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 28de7e0de7c..1c2d7a536dc 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -155,7 +155,7 @@ jobs: include: [ { name: 'Basic', - params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on', + params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DODIN_USE_YOSYS=ON', suite: 'vtr_reg_basic' }, { diff --git a/.gitignore b/.gitignore index 1cb9b37d357..2ed34f461fb 100644 --- a/.gitignore +++ b/.gitignore @@ -100,6 +100,11 @@ ODIN_II/usefull_tools/**/track_completed *.o *.a +# +#Yosys exec dir +# +Yosys + # #Python # diff --git a/doc/src/vtr/tasks.rst b/doc/src/vtr/tasks.rst index f1c501f4e80..d819c3d7af5 100644 --- a/doc/src/vtr/tasks.rst +++ b/doc/src/vtr/tasks.rst @@ -144,15 +144,17 @@ Optional Fields Absolute path or relative to ``$VTR_ROOT/vtr_flow/``. - Note: Multiple _includes_dir_ are NOT allowed in a task config file. + Note: Multiple `includes_dir` are NOT allowed in a task config file. -* **include_list_add**: A path to an _include_ file, which is relative to _includes_dir_ +* **include_list_add**: A path to an `include` file, which is relative to `includes_dir` - Multiple _include_list_add_ can be provided. + Multiple `include_list_add` can be provided. - _include_ files could act as the top module complementary, like definitions, macros or sub-modules. + `include` files could act as the top module complementary, like definitions, memory initialization files, macros or sub-modules. + + Note: Only `include` files, written in supported HDLs by each frontend, are synthesized. The others are only copied to the destination folder. - Note: _include_ files will be shared among all benchmark circuits in the task config file. + Note: `include` files will be shared among all benchmark circuits in the task config file. * **pass_requirements_file**: :ref:`vtr_pass_requirements` file. diff --git a/doc/src/yosys/dev_guide.rst b/doc/src/yosys/dev_guide.rst index 702febc4b29..bd301432f49 100644 --- a/doc/src/yosys/dev_guide.rst +++ b/doc/src/yosys/dev_guide.rst @@ -32,8 +32,8 @@ How to add new changes? ----------------------- The Yosys synthesis commands, including the generic synthesis and additional VTR specific configurations, are provided -in `synthesis.ys `_. To make changes in the overall Yosys synthesis flow, the `synthesis.ys `_ -script is perhaps the first file developers may require to change. +in `synthesis.tcl `_. To make changes in the overall Yosys synthesis flow, the `synthesis.tcl `_ +script is perhaps the first file developers may be required to change. Moreover, the `yosys_models.v `_ file includes the required definitions for Yosys to how it should infer implicit memories and instantiate arithmetic operations, such as addition, subtraction, and multiplication. Therefore, to alter these diff --git a/doc/src/yosys/structure.rst b/doc/src/yosys/structure.rst index 48b84a5d669..9cd7f82d4db 100644 --- a/doc/src/yosys/structure.rst +++ b/doc/src/yosys/structure.rst @@ -18,7 +18,7 @@ Structure of Yosys Synthesis Files and the Yosys External Library Library │ ├── multiply.v │ ├── single_port_ram.v │ ├── spram_rename.v - │ ├── synthesis.ys + │ ├── synthesis.tcl │ └── yosys_models.v └── libs └── EXTERNAL diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index c8a0c5671bd..d47f9beb7eb 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -18,6 +18,20 @@ endif() # Yosys is compiled only if the user ask for it if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS}) add_subdirectory(libyosys) + + # In addition to libyosys in the build folder, we copy the libyosys directory + # into a temporary folder in the VTR root, name Yosys, to have access to Yosys + # execs for using in VTR scripts (similar to VPR/vpr or ODIN_II/odin_II) + add_custom_target(vtr-yosys ALL + DEPENDS yosys + COMMAND ${CMAKE_COMMAND} -E + remove_directory ${VTR_SOURCE_DIR}/Yosys/ + COMMAND ${CMAKE_COMMAND} -E + make_directory ${VTR_SOURCE_DIR}/Yosys/ + COMMAND ${CMAKE_COMMAND} -E + copy_directory ${CMAKE_CURRENT_BINARY_DIR}/libyosys ${VTR_SOURCE_DIR}/Yosys/ + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}) + endif() if(${VTR_ENABLE_CAPNPROTO}) diff --git a/libs/EXTERNAL/libyosys/CMakeLists.txt b/libs/EXTERNAL/libyosys/CMakeLists.txt index a6321247a68..97251a453eb 100644 --- a/libs/EXTERNAL/libyosys/CMakeLists.txt +++ b/libs/EXTERNAL/libyosys/CMakeLists.txt @@ -44,7 +44,7 @@ add_dependencies(libyosys yosys) # specify where the library is and where to find the headers set_target_properties(libyosys PROPERTIES PREFIX "" #Avoid extra 'lib' prefix - IMPORTED_LOCATION ${LIB_FILE} + IMPORTED_LOCATION ${BINARY_LIB_FILE} INTERFACE_INCLUDE_DIRECTORIES ${YOSYS_INCLUDE_DIRS}) diff --git a/vtr_flow/benchmarks/hdl_include/include/memory_controller.v b/vtr_flow/benchmarks/hdl_include/include/memory_controller.v index 81988fe8e10..7339a457787 100755 --- a/vtr_flow/benchmarks/hdl_include/include/memory_controller.v +++ b/vtr_flow/benchmarks/hdl_include/include/memory_controller.v @@ -24,6 +24,8 @@ reg str_write_enable; reg [7:0] str_in; wire [7:0] str_out; +defparam _str.ADDR_WIDTH = 5; +defparam _str.DATA_WIDTH = 8; single_port_ram _str ( .clk( clk ), .addr( str_address ), diff --git a/vtr_flow/misc/yosyslib/synthesis.ys b/vtr_flow/misc/yosyslib/synthesis.tcl similarity index 62% rename from vtr_flow/misc/yosyslib/synthesis.ys rename to vtr_flow/misc/yosyslib/synthesis.tcl index 726e7e54732..0b7f7af2c09 100644 --- a/vtr_flow/misc/yosyslib/synthesis.ys +++ b/vtr_flow/misc/yosyslib/synthesis.tcl @@ -1,18 +1,19 @@ ################################################################# -# Yosys synthesis script, including generic 'synth' commands, # -# in addition to techmap asynchronous FFs and VTR hard blocks. # +# Yosys synthesis script, including generic 'synth' commands, # +# in addition to techmap asynchronous FFs and VTR hard blocks. # # Once the VTR flow runs with the Yosys front-end, Yosys # -# synthesizes the input design using the following commands. # -# # -# NOTE: the script is adapted from the one Eddie Hung proposed # -# for VTR-to-Bitstream[1]. However, a few minor changes to make # -# it adaptable with the current VTR flow have been made. # -# # -# [1] http://eddiehung.github.io/vtb.html # -# # -# Author: Eddie Hung # -# Co-author: Seyed Alireza Damghani (sdamghann@gmail.com) # +# synthesizes the input design using the following commands. # +# # +# NOTE: the script is adapted from the one Eddie Hung proposed # +# for VTR-to-Bitstream[1]. However, a few minor changes to make # +# it adaptable with the current VTR flow have been made. # +# # +# [1] http://eddiehung.github.io/vtb.html # +# # +# Author: Eddie Hung # +# Co-author: Seyed Alireza Damghani (sdamghann@gmail.com) # ################################################################# +yosys -import # XXX (input circuit) is replaced with filename by the run_vtr_flow script read_verilog -sv -nolatches XXX @@ -23,7 +24,7 @@ read_verilog -sv -nolatches XXX # directory for any definitions to modules it doesn't know # about, such as hand-instantiated (not inferred) memories hierarchy -check -auto-top -libdir . -proc +procs # Check that there are no combinational loops scc -select @@ -50,7 +51,7 @@ techmap -map +/adff2dff.v techmap -map TTT/../../../ODIN_II/techlib/adffe2dff.v # Map multipliers, DSPs, and add/subtracts according to yosys_models.v -techmap -map YYY */t:$mul */t:$mem */t:$sub */t:$add +techmap -map YYY */t:\$mul */t:\$mem */t:\$sub */t:\$add opt -fast -full memory_map @@ -67,15 +68,19 @@ opt -fast # as blackboxes read_verilog -lib TTT/adder.v read_verilog -lib TTT/multiply.v -read_verilog -lib SSS #(SSS) will be replaced by single_port_ram.v by python script -read_verilog -lib DDD #(DDD) will be replaced by dual_port_ram.v by python script +#(SSS) will be replaced by single_port_ram.v by python script +read_verilog -lib SSS +#(DDD) will be replaced by dual_port_ram.v by python script +read_verilog -lib DDD # Rename singlePortRam to single_port_ram -# Rename dualPortRam to dualZ_port_ram +# Rename dualPortRam to dual_port_ram # rename function of Yosys not work here # since it may outcome hierarchy error -read_verilog SSR #(SSR) will be replaced by spram_rename.v by python script -read_verilog DDR #(DDR) will be replaced by dpram_rename.v by python script +#(SSR) will be replaced by spram_rename.v by python script +read_verilog SSR +#(DDR) will be replaced by dpram_rename.v by python script +read_verilog DDR # Flatten the netlist flatten diff --git a/vtr_flow/scripts/python_libs/vtr/odin/odin.py b/vtr_flow/scripts/python_libs/vtr/odin/odin.py index 1b156e4792a..7b8243aa427 100644 --- a/vtr_flow/scripts/python_libs/vtr/odin/odin.py +++ b/vtr_flow/scripts/python_libs/vtr/odin/odin.py @@ -25,6 +25,12 @@ def create_circuits_list(main_circuit, include_files): if include_files: # Verify that files are Paths or convert them to Paths + check that they exist for include in include_files: + file_extension = os.path.splitext(include)[-1] + # if the include file is not in the supported HDLs, we drop it + # NOTE: the include file is already copied to the temp folder + if file_extension not in FILE_TYPES: + continue + include_file = vtr.verify_file(include, "Circuit") circuit_list.append(include_file.name) @@ -109,6 +115,9 @@ def run( circuit_file : Circuit file to optimize + include_files : + list of header files + output_netlist : File name to output the resulting circuit to diff --git a/vtr_flow/scripts/python_libs/vtr/paths.py b/vtr_flow/scripts/python_libs/vtr/paths.py index b3212a951bd..61a4d3c8a48 100644 --- a/vtr_flow/scripts/python_libs/vtr/paths.py +++ b/vtr_flow/scripts/python_libs/vtr/paths.py @@ -17,9 +17,10 @@ odin_output_on_error_path = odin_path / "regression_test" / ".library" / "output_on_error.conf" # YOSYS paths -yosys_exe_path = root_path / "libs" / "EXTERNAL" / "libyosys" / "yosys" +yosys_path = root_path / "Yosys" +yosys_exe_path = yosys_path / "bin" / "yosys" yosys_lib_path = vtr_flow_path / "misc" / "yosyslib" -yosys_script_path = yosys_lib_path / "synthesis.ys" +yosys_script_path = yosys_lib_path / "synthesis.tcl" # ABC paths abc_path = root_path / "abc" diff --git a/vtr_flow/scripts/python_libs/vtr/yosys/yosys.py b/vtr_flow/scripts/python_libs/vtr/yosys/yosys.py index 0e2e29562b0..0cad32a963f 100644 --- a/vtr_flow/scripts/python_libs/vtr/yosys/yosys.py +++ b/vtr_flow/scripts/python_libs/vtr/yosys/yosys.py @@ -29,12 +29,18 @@ def create_circuits_list(main_circuit, include_files): - """Create a list of all (.v) and (.vh) files""" + """Create a list of supported HDL files""" circuit_list = [] # Check include files exist if include_files: # Verify that files are Paths or convert them to Paths + check that they exist for include in include_files: + file_extension = os.path.splitext(include)[-1] + # if the include file is not in the supported HDLs, we drop it + # NOTE: the include file is already copied to the temp folder + if file_extension not in FILE_TYPES: + continue + include_file = vtr.verify_file(include, "Circuit") circuit_list.append(include_file.name) @@ -69,12 +75,12 @@ def init_script_file( vtr.file_replace( yosys_script_full_path, { - "XXX": circuit_list[0], - "YYY": "./" + YOSYS_LIB_FILES["YSMDL"], - "SSS": "./" + YOSYS_LIB_FILES["SPRAM"], - "DDD": "./" + YOSYS_LIB_FILES["DPRAM"], - "SSR": "./" + YOSYS_LIB_FILES["SPRAMR"], - "DDR": "./" + YOSYS_LIB_FILES["DPRAMR"], + "XXX": "{}".format(" ".join(str(s) for s in circuit_list)), + "YYY": yosys_models_full_path, + "SSS": yosys_spram_full_path, + "DDD": yosys_dpram_full_path, + "SSR": yosys_spram_rename_full_path, + "DDR": yosys_dpram_rename_full_path, "TTT": str(vtr.paths.yosys_lib_path), "ZZZ": output_netlist, }, @@ -121,6 +127,9 @@ def run( circuit_file : Circuit file to optimize + include_files : + list of header files + output_netlist : File name to output the resulting circuit to @@ -165,14 +174,14 @@ def run( yosys_base_script = str(Path(yosys_script).resolve()) # Copy the script file - yosys_script = "synthesis.ys" + yosys_script = "synthesis.tcl" yosys_script_full_path = str(temp_dir / yosys_script) shutil.copyfile(yosys_base_script, yosys_script_full_path) # Copy the yosys models file yosys_models = YOSYS_LIB_FILES["YSMDL"] yosys_base_models = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["YSMDL"]) - yosys_models_full_path = str(temp_dir / yosys_models) + yosys_models_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_models) shutil.copyfile(yosys_base_models, yosys_models_full_path) # Copy the VTR memory blocks file @@ -184,10 +193,10 @@ def run( yosys_base_dpram = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["DPRAM"]) yosys_base_spram_rename = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["SPRAMR"]) yosys_base_dpram_rename = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["DPRAMR"]) - yosys_spram_full_path = str(temp_dir / yosys_spram) - yosys_dpram_full_path = str(temp_dir / yosys_dpram) - yosys_spram_rename_full_path = str(temp_dir / yosys_spram_rename) - yosys_dpram_rename_full_path = str(temp_dir / yosys_dpram_rename) + yosys_spram_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_spram) + yosys_dpram_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_dpram) + yosys_spram_rename_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_spram_rename) + yosys_dpram_rename_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_dpram_rename) shutil.copyfile(yosys_base_spram, yosys_spram_full_path) shutil.copyfile(yosys_base_dpram, yosys_dpram_full_path) shutil.copyfile(yosys_base_spram_rename, yosys_spram_rename_full_path) @@ -220,7 +229,7 @@ def run( else: pass - cmd += ["-s", yosys_script] + cmd += ["-c", yosys_script] command_runner.run_system_command( cmd, temp_dir=temp_dir, log_filename=log_filename, indent_depth=1 diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py index 7846d7b75da..eb5dc0ba0cd 100755 --- a/vtr_flow/scripts/run_vtr_flow.py +++ b/vtr_flow/scripts/run_vtr_flow.py @@ -146,6 +146,14 @@ def vtr_command_argparser(prog=None): dest="verbose", help="Verbosity of the script.", ) + parser.add_argument( + "-include", + nargs="*", + default=None, + dest="include_list_file", + help="List of include files to a benchmark circuit (pass to VTR" + + " frontends as a benchmark design set)", + ) # # Power arguments @@ -331,13 +339,6 @@ def vtr_command_argparser(prog=None): dest="elaborator", help="Specify the elaborator of the synthesis flow for Odin-II", ) - odin.add_argument( - "-include", - nargs="*", - default=None, - dest="include_list_file", - help="List of include files to a benchmark circuit(pass to Odin as a benchmark design set)", - ) odin.add_argument( "-top_module", default=None, diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt deleted file mode 100644 index d19496a28e1..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt +++ /dev/null @@ -1,40 +0,0 @@ -############################################################### -# Configuration file for running experiments -# This config file is testing the ability to specify include -# files that should pass to Odin with the top module of the -# benchmark (ch_intrinsic_top.v). This is done by specifying -# two Verilog header files that provide essential definitions, -# and memory_controller design that provides the design of an -# internal component for ch_intrinsic_top. If the include files -# are not properly included during compilation the benchmark is -# incomplete and the flow will error out. -############################################################### - -# Path to directory of circuits to use -circuits_dir=benchmarks/hdl_include - -# Path to directory of includes circuits to use -includes_dir=benchmarks/hdl_include/include - -# Path to directory of architectures to use -archs_dir=arch/no_timing/memory_sweep - -# Add circuits to list to sweep -circuit_list_add=ch_intrinsics_modified.v - -# Add circuits to includes list to sweep -include_list_add=generic_definitions1.vh -include_list_add=generic_definitions2.vh -include_list_add=memory_controller.v - -# Add architectures to list to sweep -arch_list_add=k4_N10_memSize16384_memData64.xml - -# Parse info and how to parse -parse_file=vpr_no_timing.txt - -# How to parse QoR info -qor_parse_file=qor_no_timing.txt - -# Script parameters -script_params_common=-track_memory_usage --timing_analysis off diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_odin/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_odin/config/config.txt new file mode 100644 index 00000000000..53e3aad1e21 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_odin/config/config.txt @@ -0,0 +1,41 @@ +################################################################# +# Configuration file for running experiments # +# # +# This config file is testing the ability to specify include # +# files that should pass to the VTR frontend with the top # +# module of the benchmark (ch_intrinsic_top.v). This is done # +# by specifying two Verilog header files that provide essential # +# definitions, and memory_controller design that provides the # +# design of an internal component for ch_intrinsic_top. If the # +# include files are not properly included during compilation # +# the benchmark is incomplete and the flow will error out. # +################################################################# + +# Path to directory of circuits to use +circuits_dir=benchmarks/hdl_include + +# Path to directory of includes circuits to use +includes_dir=benchmarks/hdl_include/include + +# Path to directory of architectures to use +archs_dir=arch/no_timing/memory_sweep + +# Add circuits to list to sweep +circuit_list_add=ch_intrinsics_modified.v + +# Add circuits to includes list to sweep +include_list_add=generic_definitions1.vh +include_list_add=generic_definitions2.vh +include_list_add=memory_controller.v + +# Add architectures to list to sweep +arch_list_add=k4_N10_memSize16384_memData64.xml + +# Parse info and how to parse +parse_file=vpr_no_timing.txt + +# How to parse QoR info +qor_parse_file=qor_no_timing.txt + +# Script parameters +script_params_common=-track_memory_usage --timing_analysis off diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/config.txt new file mode 100644 index 00000000000..b6d693eb831 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/config.txt @@ -0,0 +1,41 @@ +################################################################# +# Configuration file for running experiments # +# # +# This config file is testing the ability to specify include # +# files that should pass to the VTR frontend with the top # +# module of the benchmark (ch_intrinsic_top.v). This is done # +# by specifying two Verilog header files that provide essential # +# definitions, and memory_controller design that provides the # +# design of an internal component for ch_intrinsic_top. If the # +# include files are not properly included during compilation # +# the benchmark is incomplete and the flow will error out. # +################################################################# + +# Path to directory of circuits to use +circuits_dir=benchmarks/hdl_include + +# Path to directory of includes circuits to use +includes_dir=benchmarks/hdl_include/include + +# Path to directory of architectures to use +archs_dir=arch/no_timing/memory_sweep + +# Add circuits to list to sweep +circuit_list_add=ch_intrinsics_modified.v + +# Add circuits to includes list to sweep +include_list_add=generic_definitions1.vh +include_list_add=generic_definitions2.vh +include_list_add=memory_controller.v + +# Add architectures to list to sweep +arch_list_add=k4_N10_memSize16384_memData64.xml + +# Parse info and how to parse +parse_file=vpr_no_timing.txt + +# How to parse QoR info +qor_parse_file=qor_no_timing.txt + +# Script parameters +script_params_common=-track_memory_usage --timing_analysis off -start yosys diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys_odin/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys_odin/config/config.txt new file mode 100644 index 00000000000..b6c54d3f91e --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys_odin/config/config.txt @@ -0,0 +1,41 @@ +################################################################# +# Configuration file for running experiments # +# # +# This config file is testing the ability to specify include # +# files that should pass to the VTR frontend with the top # +# module of the benchmark (ch_intrinsic_top.v). This is done # +# by specifying two Verilog header files that provide essential # +# definitions, and memory_controller design that provides the # +# design of an internal component for ch_intrinsic_top. If the # +# include files are not properly included during compilation # +# the benchmark is incomplete and the flow will error out. # +################################################################# + +# Path to directory of circuits to use +circuits_dir=benchmarks/hdl_include + +# Path to directory of includes circuits to use +includes_dir=benchmarks/hdl_include/include + +# Path to directory of architectures to use +archs_dir=arch/no_timing/memory_sweep + +# Add circuits to list to sweep +circuit_list_add=ch_intrinsics_modified.v + +# Add circuits to includes list to sweep +include_list_add=generic_definitions1.vh +include_list_add=generic_definitions2.vh +include_list_add=memory_controller.v + +# Add architectures to list to sweep +arch_list_add=k4_N10_memSize16384_memData64.xml + +# Parse info and how to parse +parse_file=vpr_no_timing.txt + +# How to parse QoR info +qor_parse_file=qor_no_timing.txt + +# Script parameters +script_params_common=-track_memory_usage --timing_analysis off -elaborator yosys -fflegalize diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt index 8e10192c70b..c5b598387c4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt @@ -1,4 +1,6 @@ regression_tests/vtr_reg_basic/basic_no_timing regression_tests/vtr_reg_basic/basic_timing regression_tests/vtr_reg_basic/basic_timing_no_sdc -regression_tests/vtr_reg_basic/hdl_include +regression_tests/vtr_reg_basic/hdl_include_odin +regression_tests/vtr_reg_basic/hdl_include_yosys +regression_tests/vtr_reg_basic/hdl_include_yosys_odin