diff --git a/doc/src/arch/reference.rst b/doc/src/arch/reference.rst index 1227f88ff1a..5ae8e20b84b 100644 --- a/doc/src/arch/reference.rst +++ b/doc/src/arch/reference.rst @@ -2301,7 +2301,7 @@ The full format is documented below. Defined under the ```` XML node, one or more ```` entries is used to specify permutation functions that connect different sides of a switch block. -.. arch:tag:: +.. arch:tag:: :req_param num_conns: Specifies how many connections should be created between the from_type/from_switchpoint set and the to_type/to_switchpoint set. @@ -2401,6 +2401,14 @@ The full format is documented below. .. note:: See ``from_switchpoint_order`` for value descritpions. + :opt_param switch_override: + + Specifies the name of a switch to be used to override the wire_switch of the segments in the ``to`` set. + Can be used to create switch patterns where different switches are used for different types of connections. + By using a zero-delay and zero-resistance switch one can also create T and L shaped wire segments. + + **Default:** If no override is specified, the usual wire_switch that drives the ``to`` wire will be used. + .. arch:tag:: :req_param type: diff --git a/libs/libarchfpga/src/parse_switchblocks.cpp b/libs/libarchfpga/src/parse_switchblocks.cpp index 8587b1c561c..668c9120a65 100644 --- a/libs/libarchfpga/src/parse_switchblocks.cpp +++ b/libs/libarchfpga/src/parse_switchblocks.cpp @@ -41,16 +41,16 @@ using vtr::t_formula_data; /*---- Functions for Parsing Switchblocks from Architecture ----*/ //Load an XML wireconn specification into a t_wireconn_inf -t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data); +t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const t_arch_switch_inf* switches, int num_switches); //Process the desired order of a wireconn static void parse_switchpoint_order(const char* order, SwitchPointOrder& switchpoint_order); //Process a wireconn defined in the inline style (using attributes) -void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc); +void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches); //Process a wireconn defined in the multinode style (more advanced specification) -void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc); +void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches); //Process a or sub-node of a multinode wireconn t_wire_switchpoints parse_wireconn_from_to_node(pugi::xml_node node, const pugiutil::loc_data& loc_data); @@ -65,6 +65,9 @@ static void parse_comma_separated_wire_points(const char* ch, std::vectorwireconns.push_back(wc); SubElem = SubElem.next_sibling(SubElem.name()); } @@ -102,25 +105,25 @@ void read_sb_wireconns(const t_arch_switch_inf* /*switches*/, int /*num_switches return; } -t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data) { +t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const t_arch_switch_inf* switches, int num_switches) { t_wireconn_inf wc; size_t num_children = count_children(node, "from", loc_data, ReqOpt::OPTIONAL); num_children += count_children(node, "to", loc_data, ReqOpt::OPTIONAL); if (num_children == 0) { - parse_wireconn_inline(node, loc_data, wc); + parse_wireconn_inline(node, loc_data, wc, switches, num_switches); } else { VTR_ASSERT(num_children > 0); - parse_wireconn_multinode(node, loc_data, wc); + parse_wireconn_multinode(node, loc_data, wc, switches, num_switches); } return wc; } -void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc) { +void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches) { //Parse an inline wireconn definition, using attributes - expect_only_attributes(node, {"num_conns", "from_type", "to_type", "from_switchpoint", "to_switchpoint", "from_order", "to_order"}, loc_data); + expect_only_attributes(node, {"num_conns", "from_type", "to_type", "from_switchpoint", "to_switchpoint", "from_order", "to_order", "switch_override"}, loc_data); /* get the connection style */ const char* char_prop = get_attribute(node, "num_conns", loc_data).value(); @@ -147,9 +150,13 @@ void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_da char_prop = get_attribute(node, "to_order", loc_data, ReqOpt::OPTIONAL).value(); parse_switchpoint_order(char_prop, wc.to_switchpoint_order); + + // parse switch overrides if they exist: + char_prop = get_attribute(node, "switch_override", loc_data, ReqOpt::OPTIONAL).value(); + parse_switch_override(char_prop, wc, switches, num_switches); } -void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc) { +void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches) { expect_only_children(node, {"from", "to"}, loc_data); /* get the connection style */ @@ -162,6 +169,9 @@ void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc char_prop = get_attribute(node, "to_order", loc_data, ReqOpt::OPTIONAL).value(); parse_switchpoint_order(char_prop, wc.to_switchpoint_order); + char_prop = get_attribute(node, "switch_override", loc_data, ReqOpt::OPTIONAL).value(); + parse_switch_override(char_prop, wc, switches, num_switches); + size_t num_from_children = count_children(node, "from", loc_data); size_t num_to_children = count_children(node, "to", loc_data); @@ -331,6 +341,24 @@ void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiu return; } +static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const t_arch_switch_inf* switches, int num_switches) { + // sentinel value to use default driving switch for the receiving wire type + if (switch_override == std::string("")) { + wireconn.switch_override_indx = DEFAULT_SWITCH; //Default + return; + } + + // iterate through the valid switch names in the arch looking for the requested switch_override + for (int i = 0; i < num_switches; i++) { + if (0 == strcmp(switch_override, switches[i].name)) { + wireconn.switch_override_indx = i; + return; + } + } + // if we haven't found a switch that matched, then throw an error + archfpga_throw(__FILE__, __LINE__, "Unknown switch_override specified in wireconn of custom switch blocks: \"%s\"\n", switch_override); +} + /* checks for correctness of switch block read-in from the XML architecture file */ void check_switchblock(const t_switchblock_inf* sb, const t_arch* arch) { /* get directionality */ diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 4b326dd1f2a..8b7551398ce 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1688,6 +1688,8 @@ struct t_wireconn_inf { std::vector to_switchpoint_set; //The set of segment/wirepoints representing the 'to' set (union of all t_wire_switchpoints in vector) SwitchPointOrder from_switchpoint_order = SwitchPointOrder::FIXED; //The desired from_switchpoint_set ordering SwitchPointOrder to_switchpoint_order = SwitchPointOrder::FIXED; //The desired to_switchpoint_set ordering + int switch_override_indx = DEFAULT_SWITCH; // index in switch array of the switch used to override wire_switch of the 'to' set. + // DEFAULT_SWITCH is a sentinel value (i.e. the usual driving switch from a wire for the receiving wire will be used) std::string num_conns_formula; /* Specifies how many connections should be made for this wireconn. * diff --git a/vpr/src/route/build_switchblocks.cpp b/vpr/src/route/build_switchblocks.cpp index 18d83c3f403..f07cc7a820d 100644 --- a/vpr/src/route/build_switchblocks.cpp +++ b/vpr/src/route/build_switchblocks.cpp @@ -983,7 +983,13 @@ static void compute_wireconn_connections( t_switchblock_edge sb_edge; sb_edge.from_wire = from_wire; sb_edge.to_wire = to_wire; - sb_edge.switch_ind = to_chan_details[to_x][to_y][to_wire].arch_wire_switch(); + + // if the switch override has been set, use that. Otherwise use default + if (wireconn_ptr->switch_override_indx != DEFAULT_SWITCH) { + sb_edge.switch_ind = wireconn_ptr->switch_override_indx; + } else { + sb_edge.switch_ind = to_chan_details[to_x][to_y][to_wire].arch_wire_switch(); + } VTR_LOGV(verbose, " make_conn: %d -> %d switch=%d\n", sb_edge.from_wire, sb_edge.to_wire, sb_edge.switch_ind); /* and now, finally, add this switchblock connection to the switchblock connections map */ diff --git a/vtr_flow/arch/xilinx/simple-7series_diagonal.xml b/vtr_flow/arch/xilinx/simple-7series_diagonal.xml new file mode 100644 index 00000000000..fdc3c242eb0 --- /dev/null +++ b/vtr_flow/arch/xilinx/simple-7series_diagonal.xml @@ -0,0 +1,584 @@ + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + + 1 0 1 + 1 1 + + + + + + + 1 0 0 0 0 0 1 + 1 0 0 0 0 1 + + + + + + 1 1 0 0 0 0 1 + 1 0 0 0 0 1 + + + + + + 1 0 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 1 + + + + + 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 + + + + + + + + + + 1 1 + 1 + + + + + 1 1 + 1 + + + + + 1 1 + 1 + + + + + 1 1 + 1 + + + + + 1 1 + 1 + + + + + 1 1 + 1 + + + + + 1 1 + 1 + + + + + 1 1 + 1 + + + + + + + 1 0 0 1 + 1 0 1 + + + + + 1 0 0 1 + 1 0 1 + + + + + 1 0 0 1 + 1 0 1 + + + + + 1 0 0 1 + 1 0 1 + + + + + 1 0 0 1 + 1 0 1 + + + + + 1 0 0 1 + 1 0 1 + + + + + 1 0 0 1 + 1 0 1 + + + + + 1 0 0 1 + 1 0 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1.5200000000000002e-10 + 1.5200000000000002e-10 + 1.5e-10 + 1.5e-10 + 1.18e-10 + + + 4.4e-11 + 4.4e-11 + 4.2000000000000004e-11 + 4.6e-11 + 4.8e-11 + + + + + + + + + + + + + + + + + + + + + + + 1.6200000000000002e-10 + 1.6200000000000002e-10 + 1.6e-10 + 1.6e-10 + 1.6e-10 + 1.28e-10 + + + 4.4e-11 + 4.4e-11 + 4.2000000000000004e-11 + 4.6e-11 + 4.5e-11 + 4.8e-11 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/config.txt index d78e0e75d6e..4bba123d938 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/config.txt @@ -1,18 +1,3 @@ -# -############################################ -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/xilinx - -# Add circuits to list to sweep -circuit_list_add=stereovision3.v - -# Add architectures to list to sweep arch_list_add=simple-7series.xml @@ -25,4 +10,4 @@ qor_parse_file=qor_standard.txt # Pass requirements pass_requirements_file=pass_requirements.txt -script_params=-track_memory_usage \ No newline at end of file +script_params=-track_memory_usage diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/golden_results.txt index 05c5709f6b4..bcae3ef5503 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -simple-7series.xml stereovision3.v common 6.29 abc 35.90 MiB 0.02 9740 -1 -1 4 0.08 -1 -1 36688 -1 -1 22 11 -1 -1 success v8.0.0-5519-g63bece5be release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-110-generic x86_64 2022-06-07T15:36:15 goeders10 /home/chem3000/GitClones/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 25188 11 30 262 292 2 140 63 7 7 49 clb auto 1.30 -1 0.05 0.00 2.55798 -179.909 -2.55798 2.4065 0.09 0.000138229 0.00010071 0.0172101 0.0130552 134 4995 47 0 0 268641. 5482.48 3.97 0.0882994 0.0695876 3596 19 964 3842 2193586 1181146 4.44058 4.05352 -292.258 -4.44058 -3.396 -0.04 344576. 7032.17 0.11 0.23 0.0100284 0.00891518 +simple-7series.xml stereovision3.v common 6.29 abc 35.90 MiB 0.02 9740 -1 -1 4 0.08 -1 -1 36688 -1 -1 22 11 -1 -1 success v8.0.0-5519-g63bece5be release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-110-generic x86_64 2022-06-07T15:36:15 goeders10 /home/chem3000/GitClones/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 25188 11 30 262 292 2 140 63 7 7 49 clb auto 1.30 -1 0.05 0.00 2.55798 -179.909 -2.55798 2.4065 0.09 0.000138229 0.00010071 0.0172101 0.0130552 134 4995 47 0 0 268641. 5482.48 3.97 0.0882994 0.0695876 3596 19 964 3842 2193586 1181146 4.44058 4.05352 -292.258 -4.44058 -3.396 -0.04 344576. 7032.17 0.11 0.23 0.0100284 0.00891518