diff --git a/.github/kokoro/continuous/yosys_test.cfg b/.github/kokoro/continuous/yosys_test.cfg index e46c9873dbc..8573f1b7119 100644 --- a/.github/kokoro/continuous/yosys_test.cfg +++ b/.github/kokoro/continuous/yosys_test.cfg @@ -1,6 +1,6 @@ # Format: //devtools/kokoro/config/proto/build.proto -# vtr_reg_yosys_odin test runs the VTR benchmarks through -# the entire VTR with Yosys+Odin-II as the first CAD tool +# vtr_reg_yosys test runs the VTR benchmarks through +# the entire VTR with Yosys as the first CAD tool build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh" @@ -48,12 +48,12 @@ env_vars { #Use default build configuration env_vars { key: "VTR_CMAKE_PARAMS" - value: "" + value: "-DWITH_YOSYS=ON" } env_vars { key: "VTR_TEST" - value: "odin_reg_strong" + value: "vtr_reg_yosys" } #Options for run_reg_test.py @@ -65,5 +65,5 @@ env_vars { env_vars { key: "NUM_CORES" - value: "3" -} + value: "8" +} \ No newline at end of file diff --git a/.github/kokoro/presubmit/yosys_test.cfg b/.github/kokoro/presubmit/yosys_test.cfg index 075c05ca7e1..1f416bc4a6d 100644 --- a/.github/kokoro/presubmit/yosys_test.cfg +++ b/.github/kokoro/presubmit/yosys_test.cfg @@ -1,6 +1,6 @@ # Format: //devtools/kokoro/config/proto/build.proto -# vtr_reg_yosys_odin test runs the VTR benchmarks through -# the entire VTR with Yosys+Odin-II as the first CAD tool +# vtr_reg_yosys test runs the VTR benchmarks through +# the entire VTR with Yosys as the first CAD tool build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh" @@ -48,12 +48,12 @@ env_vars { #Use default build configuration env_vars { key: "VTR_CMAKE_PARAMS" - value: "" + value: "-DWITH_YOSYS=ON" } env_vars { key: "VTR_TEST" - value: "odin_reg_strong" + value: "vtr_reg_yosys" } #Options for run_reg_test.py diff --git a/CMakeLists.txt b/CMakeLists.txt index 75b1239f4fe..40179ed4552 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -52,6 +52,7 @@ option(ODIN_TIDY "Enable building odin with clang tidy" OFF) option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF) # Allow the user to enable building Yosys +option(WITH_YOSYS "Enable building Yosys" OFF) option(ODIN_USE_YOSYS "Enable building Yosys" OFF) set(VTR_VERSION_MAJOR 8) @@ -381,7 +382,10 @@ if(${WITH_ABC}) add_subdirectory(ace2) endif() add_subdirectory(utils) -if(${WITH_ODIN}) +# define cmake params to compile Yosys +if(${WITH_YOSYS}) + add_definitions("-D_YOSYS_") +elseif(${WITH_ODIN}) add_subdirectory(ODIN_II) # blifexplorer depends on odin if(${WITH_BLIFEXPLORER}) diff --git a/ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json index eba86d0ab45..984ebc4234a 100644 --- a/ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json +++ b/ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json @@ -58,15 +58,15 @@ "Latch Drivers": 1, "Pi": 273, "Po": 193, - "logic element": 4141, - "latch": 857, - "Adder": 136, + "logic element": 4204, + "latch": 871, + "Adder": 151, "Memory": 32, "generic logic size": 4, "Longest Path": 428, "Average Path": 4, - "Estimated LUTs": 4435, - "Total Node": 5167 + "Estimated LUTs": 4510, + "Total Node": 5259 }, "large/des_area/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "large/des_area/k6_frac_N10_frac_chain_mem32K_40nm", diff --git a/ODIN_II/regression_test/benchmark/task/yosys+odin/vtr/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/yosys+odin/vtr/synthesis_result.json index 2372effeb6e..5bec0b22b37 100644 --- a/ODIN_II/regression_test/benchmark/task/yosys+odin/vtr/synthesis_result.json +++ b/ODIN_II/regression_test/benchmark/task/yosys+odin/vtr/synthesis_result.json @@ -101,15 +101,15 @@ "Latch Drivers": 1, "Pi": 273, "Po": 193, - "logic element": 4141, - "latch": 857, - "Adder": 136, + "logic element": 4204, + "latch": 871, + "Adder": 151, "Memory": 32, "generic logic size": 4, "Longest Path": 428, "Average Path": 4, - "Estimated LUTs": 4435, - "Total Node": 5167 + "Estimated LUTs": 4510, + "Total Node": 5259 }, "vtr/ch_intrinsics/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "vtr/ch_intrinsics/k6_frac_N10_frac_chain_mem32K_40nm", diff --git a/ODIN_II/regression_test/benchmark/verilog/full/mcml.v b/ODIN_II/regression_test/benchmark/verilog/full/mcml.v index 5028f2d915f..3959f55bb04 100644 --- a/ODIN_II/regression_test/benchmark/verilog/full/mcml.v +++ b/ODIN_II/regression_test/benchmark/verilog/full/mcml.v @@ -1776,7 +1776,7 @@ wire [31:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; -assign dont_care_out = 32'b00000000000000000000000000000000; +// assign dont_care_out = 32'b00000000000000000000000000000000; defparam dpram1.ADDR_WIDTH = 13; defparam dpram1.DATA_WIDTH = 32; @@ -1813,7 +1813,7 @@ wire [31:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; -assign dont_care_out = 32'b00000000000000000000000000000000; +// assign dont_care_out = 32'b00000000000000000000000000000000; defparam dpram1.ADDR_WIDTH = 13; defparam dpram1.DATA_WIDTH = 32; @@ -1850,7 +1850,7 @@ wire [31:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; -assign dont_care_out = 32'b00000000000000000000000000000000; +// assign dont_care_out = 32'b00000000000000000000000000000000; defparam dpram1.ADDR_WIDTH = 13; defparam dpram1.DATA_WIDTH = 32; @@ -1887,7 +1887,7 @@ wire [31:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; -assign dont_care_out = 32'b00000000000000000000000000000000; +// assign dont_care_out = 32'b00000000000000000000000000000000; defparam dpram1.ADDR_WIDTH = 13; defparam dpram1.DATA_WIDTH = 32; @@ -1923,7 +1923,7 @@ wire [35:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 36'b000000000000000000000000000000000000; -assign dont_care_out = 36'b000000000000000000000000000000000000; +// assign dont_care_out = 36'b000000000000000000000000000000000000; defparam dpram1.ADDR_WIDTH = 16; defparam dpram1.DATA_WIDTH = 36; @@ -1959,7 +1959,7 @@ wire [17:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 18'b000000000000000000; -assign dont_care_out = 18'b000000000000000000; +// assign dont_care_out = 18'b000000000000000000; defparam dpram1.ADDR_WIDTH = 16; defparam dpram1.DATA_WIDTH = 18; @@ -1995,7 +1995,7 @@ wire [7:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 8'b00000000; -assign dont_care_out = 8'b00000000; +// assign dont_care_out = 8'b00000000; defparam dpram1.ADDR_WIDTH = 16; defparam dpram1.DATA_WIDTH = 8; diff --git a/ODIN_II/regression_test/benchmark/verilog/large/boundtop.v b/ODIN_II/regression_test/benchmark/verilog/large/boundtop.v index 3a6564cec86..3950128cf5d 100644 --- a/ODIN_II/regression_test/benchmark/verilog/large/boundtop.v +++ b/ODIN_II/regression_test/benchmark/verilog/large/boundtop.v @@ -222,7 +222,7 @@ wire[63:0] tldata; resultinterface ri (t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, resultid, newresult, resultready, resultdata, pglobalreset, tm3_clk_v0); rayinterface rayint (raygroupout, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, pglobalreset, tm3_clk_v0); boundcontroller boundcont01(raygroupout01, raygroupwe01, raygroupid01, enablenear01, raygroup01, raygroupvalid01, busy01, triIDvalid01, triID01, wanttriID, reset01, baseaddress01, newresult, BoundNodeID01, resultid, hitmask01, dataready01, empty01, level01, boundnodeIDout01, ack01, lhreset01, addrind01, addrindvalid01, ostdata, ostdatavalid, tladdr01, tladdrvalid01, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_01, t2_01, t3_01, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, id1_01, id2_01, id3_01, hit1_01, hit2_01, hit3_01, bcvalid01, done, cntreset01, passCTS01, passCTS10, pglobalreset, tm3_clk_v0, state01, debugsubcount01, debugcount01); - boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount01); + boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount10); resulttransmit restransinst (bcvalid01, bcvalid10, id1_01, id2_01, id3_01, id1_10, id2_10, id3_10, hit1_01, hit2_01, hit3_01, hit1_10, hit2_10, hit3_10, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, rgResultData, rgResultReady, rgResultSource, pglobalreset, tm3_clk_v0); assign raygroupout = raygroupout01 | raygroupout10 ; @@ -287,7 +287,7 @@ assign raygroupout = raygroupout01 | raygroupout10 ; resultcounter rc (resultid, newresult, done, cntreset, pglobalreset, tm3_clk_v0); - // global reset as an output is undriven! + // global reset as an output should be driven! assign globalreset = pglobalreset; endmodule @@ -2821,4 +2821,4 @@ endmodule end end end - endmodule \ No newline at end of file + endmodule diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index 341e7be2f9c..548cc45551f 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -14,9 +14,9 @@ if(VPR_USE_EZGL STREQUAL "on") add_subdirectory(libezgl) endif() -# The VTR root CMakeFile initializes the ODIN_USE_YOSYS +# The VTR root CMakeFile initializes the ODIN_USE_YOSYS or WITH_YOSYS # Yosys is compiled only if the user ask for it -if(${ODIN_USE_YOSYS}) +if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS}) add_subdirectory(libyosys) endif() diff --git a/libs/EXTERNAL/libyosys/CMakeLists.txt b/libs/EXTERNAL/libyosys/CMakeLists.txt index 33a568e8fa1..a6321247a68 100644 --- a/libs/EXTERNAL/libyosys/CMakeLists.txt +++ b/libs/EXTERNAL/libyosys/CMakeLists.txt @@ -1,13 +1,12 @@ cmake_minimum_required(VERSION 3.9) -# [KNOWN_ISSUE]: if ODIN_USE_YOSYS is active, abc will be compiled -# for the second time inside Yosys, since Yosys uses a different -# version of abc project("libyosys") # Create a target out of the library compilation result SET(LIB_FILE ${CMAKE_CURRENT_SOURCE_DIR}/libyosys.so) SET(BINARY_LIB_FILE ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/libyosys.so) +SET(YOSYS_EXEC ${CMAKE_CURRENT_SOURCE_DIR}/yosys) +SET(BINARY_EXEC_FILE ${CMAKE_CURRENT_BINARY_DIR}/bin/yosys) SET(YOSYS_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}) # handle make program with both ninja and unix style @@ -15,28 +14,28 @@ set(MAKE_PROGRAM "$(MAKE)") # handle cppflags to suppress yosys warning with both ninja and unix style set(CURRENT_CPPFLAGS "$(CPPFLAGS)-w") if(${CMAKE_GENERATOR} STREQUAL "Ninja") - set(MAKE_PROGRAM "make") - set(CURRENT_CPPFLAGS "-w") +set(MAKE_PROGRAM "make") +set(CURRENT_CPPFLAGS "-w") endif() # how to build the result of the library -add_custom_command(OUTPUT ${LIB_FILE} ${BINARY_LIB_FILE} - COMMAND ${MAKE_PROGRAM} -k "ENABLE_LIBYOSYS=1" - CPPFLAGS=${CURRENT_CPPFLAGS} - -j${CMAKE_BUILD_PARALLEL_LEVEL} - PREFIX=${CMAKE_CURRENT_BINARY_DIR} - > /dev/null - COMMAND ${MAKE_PROGRAM} install - PREFIX=${CMAKE_CURRENT_BINARY_DIR} - > /dev/null - COMMAND ${CMAKE_COMMAND} -E - make_directory ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/ - COMMAND ${CMAKE_COMMAND} -E - copy ${LIB_FILE} ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/ - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}) +add_custom_command(OUTPUT ${LIB_FILE} ${BINARY_LIB_FILE} ${YOSYS_EXEC} ${BINARY_EXEC_FILE} + COMMAND ${MAKE_PROGRAM} -k "ENABLE_LIBYOSYS=1" "ENABLE_ABC=0" + CPPFLAGS=${CURRENT_CPPFLAGS} + -j${CMAKE_BUILD_PARALLEL_LEVEL} + PREFIX=${CMAKE_CURRENT_BINARY_DIR} + > /dev/null + COMMAND ${MAKE_PROGRAM} install + PREFIX=${CMAKE_CURRENT_BINARY_DIR} + > /dev/null + COMMAND ${CMAKE_COMMAND} -E + make_directory ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/ + COMMAND ${CMAKE_COMMAND} -E + copy ${LIB_FILE} ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/ + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}) # create a target out of the library compilation result -add_custom_target(yosys DEPENDS ${LIB_FILE} ${BINARY_LIB_FILE}) +add_custom_target(yosys ALL DEPENDS ${LIB_FILE} ${BINARY_LIB_FILE}) # create an library target out of the library compilation result add_library(libyosys SHARED IMPORTED GLOBAL) @@ -47,3 +46,6 @@ set_target_properties(libyosys PROPERTIES PREFIX "" #Avoid extra 'lib' prefix IMPORTED_LOCATION ${LIB_FILE} INTERFACE_INCLUDE_DIRECTORIES ${YOSYS_INCLUDE_DIRS}) + + +install(FILES ${YOSYS_EXEC} DESTINATION ${CMAKE_CURRENT_BINARY_DIR}) \ No newline at end of file diff --git a/vtr_flow/benchmarks/verilog/arm_core.v b/vtr_flow/benchmarks/verilog/arm_core.v index 15f9ba5fbf3..907bc64202d 100644 --- a/vtr_flow/benchmarks/verilog/arm_core.v +++ b/vtr_flow/benchmarks/verilog/arm_core.v @@ -4048,7 +4048,7 @@ reg [31:0] r11 = 32'hdeadbeef; reg [31:0] r12 = 32'hdeadbeef; reg [31:0] r13 = 32'hdeadbeef; reg [31:0] r14 = 32'hdeadbeef; -reg [23:0] r15 = 24'hc0ffee; +reg [23:0] r15; // see line: 4272 wire [31:0] r0_out; wire [31:0] r1_out; @@ -4268,7 +4268,8 @@ assign r15_out_rm_nxt = { i_status_bits_flags, i_status_bits_firq_mask, i_pc, i_mode_exec}; - + +// if r15 is initialized => Yosys+ABC:A CI/CO pair share the name (u_execute.u_register_bank.r15[1]) but do not link directly assign r15_out_rn = {6'd0, r15, 2'd0}; diff --git a/vtr_flow/benchmarks/verilog/boundtop.v b/vtr_flow/benchmarks/verilog/boundtop.v index 5b3c21a3dab..3beb662c402 100644 --- a/vtr_flow/benchmarks/verilog/boundtop.v +++ b/vtr_flow/benchmarks/verilog/boundtop.v @@ -222,7 +222,7 @@ wire[63:0] tldata; resultinterface ri (t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, resultid, newresult, resultready, resultdata, pglobalreset, tm3_clk_v0); rayinterface rayint (raygroupout, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, pglobalreset, tm3_clk_v0); boundcontroller boundcont01(raygroupout01, raygroupwe01, raygroupid01, enablenear01, raygroup01, raygroupvalid01, busy01, triIDvalid01, triID01, wanttriID, reset01, baseaddress01, newresult, BoundNodeID01, resultid, hitmask01, dataready01, empty01, level01, boundnodeIDout01, ack01, lhreset01, addrind01, addrindvalid01, ostdata, ostdatavalid, tladdr01, tladdrvalid01, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_01, t2_01, t3_01, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, id1_01, id2_01, id3_01, hit1_01, hit2_01, hit3_01, bcvalid01, done, cntreset01, passCTS01, passCTS10, pglobalreset, tm3_clk_v0, state01, debugsubcount01, debugcount01); - boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount01); + boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount10); resulttransmit restransinst (bcvalid01, bcvalid10, id1_01, id2_01, id3_01, id1_10, id2_10, id3_10, hit1_01, hit2_01, hit3_01, hit1_10, hit2_10, hit3_10, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, rgResultData, rgResultReady, rgResultSource, pglobalreset, tm3_clk_v0); assign raygroupout = raygroupout01 | raygroupout10 ; diff --git a/vtr_flow/benchmarks/verilog/mcml.v b/vtr_flow/benchmarks/verilog/mcml.v index 5028f2d915f..3959f55bb04 100644 --- a/vtr_flow/benchmarks/verilog/mcml.v +++ b/vtr_flow/benchmarks/verilog/mcml.v @@ -1776,7 +1776,7 @@ wire [31:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; -assign dont_care_out = 32'b00000000000000000000000000000000; +// assign dont_care_out = 32'b00000000000000000000000000000000; defparam dpram1.ADDR_WIDTH = 13; defparam dpram1.DATA_WIDTH = 32; @@ -1813,7 +1813,7 @@ wire [31:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; -assign dont_care_out = 32'b00000000000000000000000000000000; +// assign dont_care_out = 32'b00000000000000000000000000000000; defparam dpram1.ADDR_WIDTH = 13; defparam dpram1.DATA_WIDTH = 32; @@ -1850,7 +1850,7 @@ wire [31:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; -assign dont_care_out = 32'b00000000000000000000000000000000; +// assign dont_care_out = 32'b00000000000000000000000000000000; defparam dpram1.ADDR_WIDTH = 13; defparam dpram1.DATA_WIDTH = 32; @@ -1887,7 +1887,7 @@ wire [31:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 32'b00000000000000000000000000000000; -assign dont_care_out = 32'b00000000000000000000000000000000; +// assign dont_care_out = 32'b00000000000000000000000000000000; defparam dpram1.ADDR_WIDTH = 13; defparam dpram1.DATA_WIDTH = 32; @@ -1923,7 +1923,7 @@ wire [35:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 36'b000000000000000000000000000000000000; -assign dont_care_out = 36'b000000000000000000000000000000000000; +// assign dont_care_out = 36'b000000000000000000000000000000000000; defparam dpram1.ADDR_WIDTH = 16; defparam dpram1.DATA_WIDTH = 36; @@ -1959,7 +1959,7 @@ wire [17:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 18'b000000000000000000; -assign dont_care_out = 18'b000000000000000000; +// assign dont_care_out = 18'b000000000000000000; defparam dpram1.ADDR_WIDTH = 16; defparam dpram1.DATA_WIDTH = 18; @@ -1995,7 +1995,7 @@ wire [7:0] dont_care_out; assign const_zero = 1'b0; assign const_zero_data = 8'b00000000; -assign dont_care_out = 8'b00000000; +// assign dont_care_out = 8'b00000000; defparam dpram1.ADDR_WIDTH = 16; defparam dpram1.DATA_WIDTH = 8; diff --git a/vtr_flow/misc/yosyslib/README.md b/vtr_flow/misc/yosyslib/README.md new file mode 100644 index 00000000000..feb63363383 --- /dev/null +++ b/vtr_flow/misc/yosyslib/README.md @@ -0,0 +1,34 @@ +# Yosys+VTR library files +This directory includes required Verilog models to run the VTR flow using Yosys as its front-end. +The approach of utilizing Yosys as the VTR synthesizer is mainly driven by what Eddie Hung proposed +for the [`VTR-to-Bitstream`](http://eddiehung.github.io/vtb.html) (VTB), based upon VTR 7. Although +some files, such as [`yosys_models.v`](./yosys_models.v) and [`multiply.v`](./multiply.v), are directly +copied from the VTB project, the other files have been subjected to a few changes due to significant +alterations from VTR 7 to the current version of VTR. Furthermore, Hung's approach was specifically +proposed for Xilinx Vertix-6 architecture. As a result, we have applied relevant changes to the remainder +of Yosys library files to make them compatible with the current VTR version and support routine architectures +used in the VTR regression tests. + +## What is new compared to the VTB files? +Changes applied to the VTB files are outlined as follows: + 1. Replacing Vertix-6 adder black-box (`xadder`) with the conventional adder used in the current version of VTR. + 2. If required, performing a recursive depth splitting for memory hard blocks, i.e., `single_port_ram` and `dual_port_ram`, to make them adaptable with the VTR flow configurations. + 3. Converting asynchronous DFFs with enable signals (ADFFE) to synchronous form using [`adffe2dffe.v`](./../../../ODIN_II/techlib/adffe2dff.v). + 4. Adding `dffunmap` to transform complex DFF sub-circuits, such as SDFFE (DFF with synchronous reset and enable), to their soft logic implementation, i.e., the combination of multiplexers and latches. + 5. Removing the ABC commands from the Yosys synthesis script and letting the VTR flow's ABC stage performs the technology mapping. (NOTE: the LUT size is considered the one defined in the architecture file as the same as the regular VTR flow) + +## How to add new changes? +The Yosys synthesis commands, including the generic synthesis and additional VTR specific configurations, are provided +in [`synthesis.ys`](./synthesis.ys). To make changes in the overall Yosys synthesis flow, the [`synthesis.ys`](./synthesis.ys) +script is perhaps the first file developers may require to change. + +Moreover, the [`yosys_models.v`](./yosys_models.v) file includes the required definitions for Yosys to how it should infer implicit +memories and instantiate arithmetic operations, such as addition, subtraction, and multiplication. Therefore, to alter these +behaviours or add more regulations such as how Yosys should behave when facing other arithmetic operations, for example modulo and division, +the [`yosys_models.v`](./yosys_models.v) Verilog file is required to be modified. + +Except for [`single_port_ram.v`](./single_port_ram.v) and [`dual_port_ram.v`](./dual_port_ram.v) Verilog files that perform the depth splitting +process, the other files are defined as black-box, i.e., their declarations are required while no definition is needed. To add new black-box +components, developers should first provide the corresponding Verilog files similar to the [`adder.v`](./adder.v). Then, a new `read_verilog -lib TTT/NEW_BB.v` +command should be added to the Yosys synthesis script. If there is an implicit inference of the new black-box component, the [`yosys_models.v`](./yosys_models.v) +Verilog file must also be modified, as mentioned earlier. diff --git a/vtr_flow/misc/yosyslib/adder.v b/vtr_flow/misc/yosyslib/adder.v new file mode 100644 index 00000000000..061b1d3df35 --- /dev/null +++ b/vtr_flow/misc/yosyslib/adder.v @@ -0,0 +1,13 @@ +/******************************************************** +# Description: definition of the hard adder black-box # +# # +# Author: Seyed Alireza Damghani (sdamghann@gmail.com) # +********************************************************/ + +(* blackbox *) +module adder(a, b, cin, cout, sumout); + input a, b, cin; + output cout, sumout; + + //assign {cout,sumout} = a + b + cin; +endmodule diff --git a/vtr_flow/misc/yosyslib/dpram_rename.v b/vtr_flow/misc/yosyslib/dpram_rename.v new file mode 100644 index 00000000000..fbcb5458a84 --- /dev/null +++ b/vtr_flow/misc/yosyslib/dpram_rename.v @@ -0,0 +1,70 @@ +/****************************************************************** +# Description: Renaming depth-split dualPortRam to dual_port_ram # +# to be recognized by VTR flow CAD tools. This file # +# is executed by the Yosys synthesis flow once the # +# dual_port_ram.v is executed. # +# # +# Author: Seyed Alireza Damghani (sdamghann@gmail.com) # +******************************************************************/ + + +`timescale 1ps/1ps + +`define MEM_MAXADDR PPP +`define MEM_MAXDATA 36 + +// depth and data may need to be splited +module dualPortRam(clk, we1, we2, addr1, addr2, data1, data2, out1, out2); + parameter ADDR_WIDTH = `MEM_MAXADDR; + parameter DATA_WIDTH = 1; + + input clk; + input we1, we2; + input [ADDR_WIDTH-1:0] addr1, addr2; + input [DATA_WIDTH-1:0] data1, data2; + + output reg [DATA_WIDTH-1:0] out1, out2; + + + dual_port_ram uut ( + .clk(clk), + .we1(we1), + .we2(we2), + .addr1(addr1), + .addr2(addr2), + .data1(data1), + .data2(data2), + .out1(out1), + .out2(out2) + ); + +endmodule + + + +(* blackbox *) +module dual_port_ram(clk, data2, data1, addr2, addr1, we2, we1, out2, out1); + localparam ADDR_WIDTH = `MEM_MAXADDR; + localparam DATA_WIDTH = 1; + + input clk; + input we1, we2; + input [ADDR_WIDTH-1:0] addr1, addr2; + input data1, data2; + + output reg out1, out2; + /* + reg [DATA_WIDTH-1:0] RAM [(1< `MEM_MAXADDR) + begin + + wire [ADDR_WIDTH-2:0] new_addr1 = addr1[ADDR_WIDTH-2:0]; + wire [ADDR_WIDTH-2:0] new_addr2 = addr2[ADDR_WIDTH-2:0]; + + wire [DATA_WIDTH-1:0] out1_h, out1_l; + wire [DATA_WIDTH-1:0] out2_h, out2_l; + + + defparam uut_h.ADDR_WIDTH = ADDR_WIDTH-1; + defparam uut_h.DATA_WIDTH = DATA_WIDTH; + dual_port_ram uut_h ( + .clk(clk), + .we1(we1), + .we2(we2), + .addr1(new_addr1), + .addr2(new_addr2), + .data1(data1), + .data2(data2), + .out1(out1_h), + .out2(out2_h) + ); + + defparam uut_l.ADDR_WIDTH = ADDR_WIDTH-1; + defparam uut_l.DATA_WIDTH = DATA_WIDTH; + dual_port_ram uut_l ( + .clk(clk), + .we1(we1), + .we2(we2), + .addr1(new_addr1), + .addr2(new_addr2), + .data1(data1), + .data2(data2), + .out1(out1_l), + .out2(out2_l) + ); + + reg additional_bit; + always @(posedge clk) additional_bit <= addr[ADDR_WIDTH-1]; + assign out1 = (additional_bit) ? out1_h : out1_l; + assign out2 = (additional_bit) ? out2_h : out2_l; + + end else begin + for (i = 0; i < DATA_WIDTH; i = i + 1) begin:single_bit_data + dualPortRam uut ( + .clk(clk), + .we1(we1), + .we2(we2), + .addr1({ {{`MEM_MAXADDR-ADDR_WIDTH}{1'bx}}, addr1[ADDR_WIDTH-1:0] }), + .addr2({ {{`MEM_MAXADDR-ADDR_WIDTH}{1'bx}}, addr2[ADDR_WIDTH-1:0] }), + .data1(data1[i]), + .data2(data2[i]), + .out1(out1[i]), + .out2(out2[i]) + ); + end + end + endgenerate + +endmodule + + + +(* blackbox *) +module dualPortRam(clk, data2, data1, addr2, addr1, we2, we1, out2, out1); + localparam ADDR_WIDTH = `MEM_MAXADDR; + localparam DATA_WIDTH = 1; + + input clk; + input we1, we2; + input [ADDR_WIDTH-1:0] addr1, addr2; + input data1, data2; + + output reg out1, out2; + /* + reg [DATA_WIDTH-1:0] RAM [(1< `MEM_MAXADDR) + begin + + wire [ADDR_WIDTH-2:0] new_addr = addr[ADDR_WIDTH-2:0]; + wire [DATA_WIDTH-1:0] out_h, out_l; + + + defparam uut_h.ADDR_WIDTH = ADDR_WIDTH-1; + defparam uut_h.DATA_WIDTH = DATA_WIDTH; + single_port_ram uut_h ( + .clk(clk), + .we(we), + .addr(new_addr), + .data(data), + .out(out_h) + ); + + defparam uut_l.ADDR_WIDTH = ADDR_WIDTH-1; + defparam uut_l.DATA_WIDTH = DATA_WIDTH; + single_port_ram uut_l ( + .clk(clk), + .we(we), + .addr(new_addr), + .data(data), + .out(out_l) + ); + + reg additional_bit; + always @(posedge clk) additional_bit <= addr[ADDR_WIDTH-1]; + assign out = (additional_bit) ? out_h : out_l; + + end else begin + for (i = 0; i < DATA_WIDTH; i = i + 1) begin:single_bit_data + singlePortRam uut ( + .clk(clk), + .we(we), + .addr({ {{`MEM_MAXADDR-ADDR_WIDTH}{1'bx}}, addr[ADDR_WIDTH-1:0] }), + .data(data[i]), + .out(out[i]) + ); + end + end + endgenerate + +endmodule + +(* blackbox *) +module singlePortRam(clk, data, addr, we, out); + + localparam ADDR_WIDTH = `MEM_MAXADDR; + localparam DATA_WIDTH = 1; + + input clk; + input we; + input [ADDR_WIDTH-1:0] addr; + input [DATA_WIDTH-1:0] data; + + output reg [DATA_WIDTH-1:0] out; + /* + reg [DATA_WIDTH-1:0] RAM [(1< b ? a : b) +`define MIN(a,b) (a < b ? a : b) + +module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); + parameter MEMID = ""; + parameter SIZE = 256; + parameter OFFSET = 0; + parameter ABITS = 8; + parameter WIDTH = 8; + parameter signed INIT = 1'bx; + + parameter RD_PORTS = 1; + parameter RD_CLK_ENABLE = 1'b1; + parameter RD_CLK_POLARITY = 1'b1; + parameter RD_TRANSPARENT = 1'b1; + + parameter WR_PORTS = 1; + parameter WR_CLK_ENABLE = 1'b1; + parameter WR_CLK_POLARITY = 1'b1; + + input [RD_PORTS-1:0] RD_CLK; + input [RD_PORTS-1:0] RD_EN; + input [RD_PORTS*ABITS-1:0] RD_ADDR; + output reg [RD_PORTS*WIDTH-1:0] RD_DATA; + + input [WR_PORTS-1:0] WR_CLK; + input [WR_PORTS*WIDTH-1:0] WR_EN; + input [WR_PORTS*ABITS-1:0] WR_ADDR; + input [WR_PORTS*WIDTH-1:0] WR_DATA; + + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + + parameter _TECHMAP_CONNMAP_RD_CLK_ = 0; + parameter _TECHMAP_CONNMAP_WR_CLK_ = 0; + + parameter _TECHMAP_CONNMAP_RD_ADDR_ = 0; + parameter _TECHMAP_CONNMAP_WR_ADDR_ = 0; + + parameter _TECHMAP_CONNMAP_WR_EN_ = 0; + parameter _TECHMAP_CONSTVAL_RD_EN_ = 0; + + parameter _TECHMAP_BITS_CONNMAP_ = 0; + //parameter _TECHMAP_CONNMAP_RD_PORTS_ = 0; + //parameter _TECHMAP_CONNMAP_WR_PORTS_ = 0; + + reg _TECHMAP_FAIL_; + initial begin + _TECHMAP_FAIL_ <= 0; + + // only map cells with only one read and one write port + if (RD_PORTS > 2 || WR_PORTS > 2) + _TECHMAP_FAIL_ <= 1; + + // read enable must not be constant low + if (_TECHMAP_CONSTVAL_RD_EN_[0] == 1'b0) + _TECHMAP_FAIL_ <= 1; + + // we expect positive read clock and non-transparent reads + if (RD_TRANSPARENT || !RD_CLK_ENABLE || !RD_CLK_POLARITY) + _TECHMAP_FAIL_ <= 1; + + // we expect positive write clock + if (!WR_CLK_ENABLE || !WR_CLK_POLARITY) + _TECHMAP_FAIL_ <= 1; + + // read and write must be in same clock domain + if (_TECHMAP_CONNMAP_RD_CLK_ != _TECHMAP_CONNMAP_WR_CLK_) + _TECHMAP_FAIL_ <= 1; + + // we don't do small memories or memories with offsets + if (OFFSET != 0 || ABITS < `MEM_MINWIDTH || SIZE < 2**`MEM_MINWIDTH) + _TECHMAP_FAIL_ <= 1; + + end + + genvar i; + for (i = 0; i < `MAX(RD_PORTS, WR_PORTS); i = i+1) begin + initial begin + // check each pair of read and write port are the same + if (RD_PORTS >= i && WR_PORTS >= i) begin + if (_TECHMAP_CONNMAP_RD_ADDR_[i*ABITS*_TECHMAP_BITS_CONNMAP_ +: ABITS*_TECHMAP_BITS_CONNMAP_] != + _TECHMAP_CONNMAP_WR_ADDR_[i*ABITS*_TECHMAP_BITS_CONNMAP_ +: ABITS*_TECHMAP_BITS_CONNMAP_]) + _TECHMAP_FAIL_ <= 1; + end + end + // check all bits of write enable are the same + if (i < WR_PORTS) begin + genvar j; + for (j = 1; j < WIDTH; j = j+1) begin + initial begin + if (_TECHMAP_CONNMAP_WR_EN_[0 +: _TECHMAP_BITS_CONNMAP_] != + _TECHMAP_CONNMAP_WR_EN_[j*_TECHMAP_BITS_CONNMAP_ +: _TECHMAP_BITS_CONNMAP_]) + _TECHMAP_FAIL_ <= 1; + end + end + end + end + + + \$__mem_gen #( + .MEMID(MEMID), .SIZE(SIZE), .OFFSET(OFFSET), .ABITS(ABITS), .WIDTH(WIDTH), + .RD_PORTS(RD_PORTS), .RD_CLK_ENABLE(RD_CLK_ENABLE), .RD_CLK_POLARITY(RD_CLK_POLARITY), .RD_TRANSPARENT(RD_TRANSPARENT), + .WR_PORTS(WR_PORTS), .WR_CLK_ENABLE(WR_CLK_ENABLE), .WR_CLK_POLARITY(WR_CLK_POLARITY) + ) _TECHMAP_REPLACE_ ( + .RD_CLK(RD_CLK), + .RD_EN(RD_EN), + .RD_ADDR(RD_ADDR), + .RD_DATA(RD_DATA), + .WR_CLK(WR_CLK), + .WR_EN(WR_EN), + .WR_ADDR(WR_ADDR), + .WR_DATA(WR_DATA) + ); +endmodule + +module \$__mem_gen (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); + parameter MEMID = ""; + parameter SIZE = 256; + parameter OFFSET = 0; + parameter ABITS = 8; + parameter WIDTH = 8; + parameter signed INIT = 1'bx; + + parameter RD_PORTS = 1; + parameter RD_CLK_ENABLE = 1'b1; + parameter RD_CLK_POLARITY = 1'b1; + parameter RD_TRANSPARENT = 1'b1; + + parameter WR_PORTS = 1; + parameter WR_CLK_ENABLE = 1'b1; + parameter WR_CLK_POLARITY = 1'b1; + + input [RD_PORTS-1:0] RD_CLK; + input [RD_PORTS-1:0] RD_EN; + input [RD_PORTS*ABITS-1:0] RD_ADDR; + output reg [RD_PORTS*WIDTH-1:0] RD_DATA; + + input [WR_PORTS-1:0] WR_CLK; + input [WR_PORTS*WIDTH-1:0] WR_EN; + input [WR_PORTS*ABITS-1:0] WR_ADDR; + input [WR_PORTS*WIDTH-1:0] WR_DATA; + + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + + genvar i; + generate + if (ABITS > `MEM_MAXADDR) begin + wire [WIDTH-1:0] rd_data_hi, rd_data_lo; + wire [(ABITS-1)*RD_PORTS-1:0] rd_addr_new; + for (i = 0; i < RD_PORTS; i = i+1) begin + assign rd_addr_new[(ABITS-1)*(i+1)-1:(ABITS-1)*i] = RD_ADDR[ABITS*(i+1)-2:ABITS*i]; + end + wire [(ABITS-1)*WR_PORTS-1:0] wr_addr_new; + wire [WR_PORTS-1:0] wr_en_new; + for (i = 0; i < WR_PORTS; i = i+1) begin + assign wr_addr_new[(ABITS-1)*(i+1)-1:(ABITS-1)*i] = WR_ADDR[ABITS*(i+1)-2:ABITS*i]; + assign wr_en_new[i] = WR_EN[i] & WR_ADDR[ABITS*(i+1)-1]; + end + + if (SIZE > 2**(ABITS-1)) begin + \$__mem_gen #( + .MEMID(MEMID), .SIZE(SIZE - 2**(ABITS-1)), .OFFSET(OFFSET), .ABITS(ABITS-1), .WIDTH(WIDTH), + .RD_PORTS(RD_PORTS), .RD_CLK_ENABLE(RD_CLK_ENABLE), .RD_CLK_POLARITY(RD_CLK_POLARITY), .RD_TRANSPARENT(RD_TRANSPARENT), + .WR_PORTS(WR_PORTS), .WR_CLK_ENABLE(WR_CLK_ENABLE), .WR_CLK_POLARITY(WR_CLK_POLARITY) + ) mem_hi ( + .RD_CLK(RD_CLK), + .RD_EN(RD_EN), + .RD_ADDR(rd_addr_new), + .RD_DATA(rd_data_hi), + .WR_CLK(WR_CLK), + .WR_EN(wr_en_new), + .WR_ADDR(wr_addr_new), + .WR_DATA(WR_DATA) + ); + end + else begin + assign rd_data_hi = {{WIDTH}{1'bx}}; + end + + \$__mem_gen #( + .MEMID(MEMID), .SIZE(SIZE > 2**(ABITS-1) ? 2**(ABITS-1) : SIZE), .OFFSET(OFFSET), .ABITS(ABITS-1), .WIDTH(WIDTH), + .RD_PORTS(RD_PORTS), .RD_CLK_ENABLE(RD_CLK_ENABLE), .RD_CLK_POLARITY(RD_CLK_POLARITY), .RD_TRANSPARENT(RD_TRANSPARENT), + .WR_PORTS(WR_PORTS), .WR_CLK_ENABLE(WR_CLK_ENABLE), .WR_CLK_POLARITY(WR_CLK_POLARITY) + ) mem_lo ( + .RD_CLK(RD_CLK), + .RD_EN(RD_EN), + .RD_ADDR(rd_addr_new), + .RD_DATA(rd_data_lo), + .WR_CLK(WR_CLK), + .WR_EN(wr_en_new), + .WR_ADDR(wr_addr_new), + .WR_DATA(WR_DATA) + ); + + reg [RD_PORTS-1:0] delayed_abit; + for (i = 0; i < RD_PORTS; i = i+1) begin + always @(posedge RD_CLK[i]) + delayed_abit[i] <= RD_ADDR[ABITS*(i+1)-1]; + assign RD_DATA[WIDTH*(i+1)-1:WIDTH*i] = delayed_abit[i] ? rd_data_hi : rd_data_lo; + end + end + else begin + for (i = 0; i < WIDTH; i=i+1) begin:slice + if (RD_PORTS <= 1 && WR_PORTS <= 1) + single_port_ram mem ( + .clk(RD_CLK[0]), + .addr({ {{`MEM_MAXADDR-ABITS}{1'bx}}, RD_ADDR[ABITS-1:0] }), + .data(WR_DATA[i]), + .out(RD_DATA[i]), + .we(WR_EN[0]) + ); + else if (RD_PORTS <= 2 && WR_PORTS <= 2) + dual_port_ram mem ( + .clk(RD_CLK[0]), + .addr1({ {{`MEM_MAXADDR-ABITS}{1'bx}}, RD_ADDR[ABITS-1:0] }), + .data1(WR_DATA[i]), + .out1(RD_DATA[i]), + .we1(WR_EN[0]), + .addr2({ {{`MEM_MAXADDR-ABITS}{1'bx}}, RD_ADDR[2*ABITS-1:ABITS] }), + .data2(WR_DATA[WIDTH+i]), + .out2(RD_DATA[WIDTH+i]), + .we2(WR_EN[WIDTH]) + ); + end + end + endgenerate +endmodule + +(* techmap_celltype = "$mul" *) +module mul_swap_ports (A, B, Y); +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 1; +parameter B_WIDTH = 1; +parameter Y_WIDTH = 1; + +input [A_WIDTH-1:0] A; +input [B_WIDTH-1:0] B; +output [Y_WIDTH-1:0] Y; + +wire _TECHMAP_FAIL_ = A_WIDTH <= B_WIDTH; + +\$mul #( + .A_SIGNED(B_SIGNED), + .B_SIGNED(A_SIGNED), + .A_WIDTH(B_WIDTH), + .B_WIDTH(A_WIDTH), + .Y_WIDTH(Y_WIDTH) +) _TECHMAP_REPLACE_ ( + .A(B), + .B(A), + .Y(Y) +); + +endmodule + +module \$mul (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + + reg _TECHMAP_FAIL_; + initial begin + _TECHMAP_FAIL_ <= 0; + + //if (A_SIGNED || B_SIGNED) + // _TECHMAP_FAIL_ <= 1; + + if (A_WIDTH < B_WIDTH) + _TECHMAP_FAIL_ <= 1; + if (A_WIDTH < `MULTIPLY_MINWIDTH || B_WIDTH < `MULTIPLY_MINWIDTH) + _TECHMAP_FAIL_ <= 1; + end + + generate + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) mul_slice ( + .A(A), + .B(B), + .Y(Y[Y_WIDTH-1:0]) + ); + endgenerate +endmodule + +module \$__mul_gen (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + + generate + if (A_WIDTH > `DSP_A_MAXWIDTH) begin + localparam n_floored = A_WIDTH/`DSP_A_MAXWIDTH; + localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0); + wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; + wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(`DSP_A_MAXWIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) mul_slice_first ( + .A(A[`DSP_A_MAXWIDTH-1:0]), + .B(B), + .Y(partial_sum[0]) + ); + + genvar i; + generate + for (i = 1; i < n-1; i=i+1) begin:slice + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(`DSP_A_MAXWIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) mul_slice ( + .A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]), + .B(B), + .Y(partial[i]) + ); + //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1]; + assign partial_sum[i] = { + partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:`DSP_A_MAXWIDTH], + partial[i][`DSP_A_MAXWIDTH-1:0] + partial_sum[i-1][B_WIDTH+(i*`DSP_A_MAXWIDTH)-1:B_WIDTH+((i-1)*`DSP_A_MAXWIDTH)], + partial_sum[i-1][B_WIDTH+((i-1)*`DSP_A_MAXWIDTH):0] + }; + end + endgenerate + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) mul_slice_last ( + .A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]), + .B(B), + .Y(partial[n-1]) + ); + //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2]; + assign Y = { + partial[n-1][B_WIDTH+`DSP_A_MAXWIDTH-1:`DSP_A_MAXWIDTH], + partial[n-1][`DSP_A_MAXWIDTH-1:0] + partial_sum[n-2][B_WIDTH+((n-1)*`DSP_A_MAXWIDTH)-1:B_WIDTH+((n-2)*`DSP_A_MAXWIDTH)], + partial_sum[n-2][B_WIDTH+((n-2)*`DSP_A_MAXWIDTH):0] + }; + end + else if (B_WIDTH > `DSP_B_MAXWIDTH) begin + localparam n_floored = B_WIDTH/`DSP_B_MAXWIDTH; + localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0); + wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1]; + wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH), + .Y_WIDTH(Y_WIDTH) + ) mul_first ( + .A(A), + .B(B[`DSP_B_MAXWIDTH-1:0]), + .Y(partial_sum[0]) + ); + + genvar i; + generate + for (i = 1; i < n-1; i=i+1) begin:slice + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH), + .Y_WIDTH(Y_WIDTH) + ) mul ( + .A(A), + .B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]), + .Y(partial[i]) + ); + //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; + assign partial_sum[i] = { + partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], + partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], + partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] + }; + end + endgenerate + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH), + .Y_WIDTH(Y_WIDTH) + ) mul_last ( + .A(A), + .B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]), + .Y(partial[n-1]) + ); + //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; + assign Y = { + partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], + partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], + partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] + }; + end + else begin + wire [A_WIDTH+B_WIDTH-1:0] out; + wire [(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)-(A_WIDTH+B_WIDTH)-1:0] dummy; + wire Asign, Bsign; + assign Asign = (A_SIGNED ? A[A_WIDTH-1] : 1'b0); + assign Bsign = (B_SIGNED ? B[B_WIDTH-1] : 1'b0); + multiply _TECHMAP_REPLACE_ ( + .a({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }), + .b({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }), + .out({dummy, out}) + ); + if (Y_WIDTH < A_WIDTH + B_WIDTH) + assign Y = out[Y_WIDTH-1:0]; + else begin + wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+BWIDTH-1] : 1'b0); + assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] }; + end + end + endgenerate +endmodule + +module \$add (A, B, Y); + parameter A_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_SIGNED = 0; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + + reg _TECHMAP_FAIL_; + initial begin + _TECHMAP_FAIL_ <= 0; + + //if (A_SIGNED || B_SIGNED) + // _TECHMAP_FAIL_ <= 1; + //if (A_WIDTH < 1 || B_WIDTH < 1) + // _TECHMAP_FAIL_ <= 1; + if (Y_WIDTH < `ADDER_MINWIDTH) + _TECHMAP_FAIL_ <= 1; + if (A_WIDTH < `ADDER_MINWIDTH && B_WIDTH < `ADDER_MINWIDTH) + _TECHMAP_FAIL_ <= 1; + end + + localparam maxab = `MAX(A_WIDTH, B_WIDTH); + localparam width = `MIN(Y_WIDTH, maxab+1); + + generate + wire [maxab-1:0] _a; + wire [maxab-1:0] _b; + wire [width-1:0] _y; + wire [width:0] _c; + wire [width:0] dummy; + wire Asign, Bsign; + + assign Asign = (A_SIGNED ? A[A_WIDTH-1] : 1'b0); + assign Bsign = (B_SIGNED ? B[B_WIDTH-1] : 1'b0); + assign _a = { {{maxab}{Asign}}, A }; + assign _b = { {{maxab}{Bsign}}, B }; + + adder add_first (.a(_a[0]), .b(_b[0]), .cin(1'bx), .cout(_c[1]), .sumout(_y[0])); + genvar i; + for (i = 1; i < width; i=i+1) begin : slice + if (i === maxab) + adder add_last (.a(1'b0), .b(1'b0), .cin(_c[i]), .cout(dummy[i+1]), .sumout(_y[i])); + else + adder add (.a(_a[i]), .b(_b[i]), .cin(_c[i]), .cout(_c[i+1]), .sumout(_y[i])); + end + + if (Y_WIDTH < maxab + 1) + assign Y = _y[Y_WIDTH-1:0]; + else begin + wire Ysign = (A_SIGNED || B_SIGNED ? _y[Y_WIDTH-1] : 1'b0); + assign Y = { {{Y_WIDTH-(maxab+1)}{_y[maxab+1-1]}}, _y[maxab+1-1:0] }; + end + endgenerate +endmodule + +module \$sub (A, B, Y); + parameter A_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_SIGNED = 0; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + + reg _TECHMAP_FAIL_; + initial begin + _TECHMAP_FAIL_ <= 0; + + //if (A_SIGNED || B_SIGNED) + // _TECHMAP_FAIL_ <= 1; + if (A_WIDTH < 1 || B_WIDTH < 1) + _TECHMAP_FAIL_ <= 1; + if (Y_WIDTH < `ADDER_MINWIDTH) + _TECHMAP_FAIL_ <= 1; + if (A_WIDTH < `ADDER_MINWIDTH && B_WIDTH < `ADDER_MINWIDTH) + _TECHMAP_FAIL_ <= 1; + end + + localparam maxab = `MAX(A_WIDTH, B_WIDTH); + localparam width = `MIN(Y_WIDTH, maxab+1); + + generate + wire [maxab-1:0] _a; + wire [maxab-1:0] _b; + wire [width-1:0] _y; + wire [width:0] _c; + wire [width:0] dummy; + wire Asign, Bsign; + + assign Asign = (A_SIGNED ? A[A_WIDTH-1] : 1'b0); + assign Bsign = (B_SIGNED ? B[B_WIDTH-1] : 1'b0); + assign _a = { {{maxab}{Asign}}, A }; + assign _b = { {{maxab}{Bsign}}, B }; + + // VPR requires that the first element of a carry chain have cin = 1'bx + // Therefore use sub_init to generate cout = 1'b1 for the + // actual first stage + adder sub_init (.a(1'b1), .b(~1'b0), .cin(1'bx), .cout(_c[0]), .sumout(dummy[0])); + adder sub_first (.a(_a[0]), .b(~_b[0]), .cin(_c[0]), .cout(_c[1]), .sumout(_y[0])); + genvar i; + for (i = 1; i < width; i=i+1) begin : slice + if (i === maxab) + adder sub_last (.a(1'b0), .b(~1'b0), .cin(_c[i]), .cout(dummy[i+1]), .sumout(_y[i])); + else + adder sub (.a(_a[i]), .b(~_b[i]), .cin(_c[i]), .cout(_c[i+1]), .sumout(_y[i])); + end + + if (Y_WIDTH < maxab+1) + assign Y = _y[Y_WIDTH-1:0]; + else begin + wire Ysign = (A_SIGNED || B_SIGNED ? _y[Y_WIDTH-1] : 1'b0); + assign Y = { {{Y_WIDTH-(maxab+1)}{_y[maxab+1-1]}}, _y[maxab+1-1:0] }; + end endgenerate +endmodule diff --git a/vtr_flow/parse/parse_config/adders.txt b/vtr_flow/parse/parse_config/adders.txt index 4badd22efe0..d3f685bbaaa 100644 --- a/vtr_flow/parse/parse_config/adders.txt +++ b/vtr_flow/parse/parse_config/adders.txt @@ -1,5 +1,6 @@ %include "common/vtr_flow.txt" %include "common/odin.txt" +%include "common/yosys.txt" %include "common/abc.txt" %include "common/ace.txt" diff --git a/vtr_flow/parse/parse_config/common/yosys.txt b/vtr_flow/parse/parse_config/common/yosys.txt new file mode 100644 index 00000000000..94aadbd14a0 --- /dev/null +++ b/vtr_flow/parse/parse_config/common/yosys.txt @@ -0,0 +1,4 @@ +#Yosys Run-time Metrics +yosys_synth_time;yosys.out;\s*User time \(seconds\): (.*) +max_yosys_mem;yosys.out;\s*Maximum resident set size \(kbytes\): (\d+) + diff --git a/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt b/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt index 13084291850..1771a729954 100644 --- a/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt +++ b/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt @@ -3,6 +3,7 @@ %include "common/vtr_flow.txt" %include "common/odin.txt" +%include "common/yosys.txt" %include "common/abc.txt" %include "common/ace.txt" diff --git a/vtr_flow/parse/parse_config/vpr_no_timing.txt b/vtr_flow/parse/parse_config/vpr_no_timing.txt index 068ecf1fe71..247ee97de50 100644 --- a/vtr_flow/parse/parse_config/vpr_no_timing.txt +++ b/vtr_flow/parse/parse_config/vpr_no_timing.txt @@ -1,5 +1,6 @@ %include "common/vtr_flow.txt" %include "common/odin.txt" +%include "common/yosys.txt" %include "common/abc.txt" %include "common/ace.txt" diff --git a/vtr_flow/parse/parse_config/vpr_standard.txt b/vtr_flow/parse/parse_config/vpr_standard.txt index f54a8ccef8c..df882085f33 100644 --- a/vtr_flow/parse/parse_config/vpr_standard.txt +++ b/vtr_flow/parse/parse_config/vpr_standard.txt @@ -3,6 +3,7 @@ %include "common/vtr_flow.txt" %include "common/odin.txt" +%include "common/yosys.txt" %include "common/abc.txt" %include "common/ace.txt" diff --git a/vtr_flow/scripts/python_libs/vtr/__init__.py b/vtr_flow/scripts/python_libs/vtr/__init__.py index 3f868ec8664..d4d5060a581 100644 --- a/vtr_flow/scripts/python_libs/vtr/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/__init__.py @@ -33,6 +33,7 @@ from .abc import run, run_lec from .vpr import run, run_relax_w, cmp_full_vs_incr_sta, run_second_time from .odin import run +from .yosys import run from .ace import run from .error import * from .flow import run, VtrStage diff --git a/vtr_flow/scripts/python_libs/vtr/flow.py b/vtr_flow/scripts/python_libs/vtr/flow.py index cf660548d4f..723fd8b06e4 100644 --- a/vtr_flow/scripts/python_libs/vtr/flow.py +++ b/vtr_flow/scripts/python_libs/vtr/flow.py @@ -14,9 +14,10 @@ class VtrStage(Enum): """ ODIN = 1 - ABC = 2 - ACE = 3 - VPR = 4 + YOSYS = 2 + ABC = 3 + ACE = 4 + VPR = 5 def __le__(self, other): if self.__class__ is other.__class__: @@ -40,11 +41,13 @@ def run( command_runner=vtr.CommandRunner(), temp_dir=Path("./temp"), odin_args=None, + yosys_args=None, abc_args=None, vpr_args=None, keep_intermediate_files=True, keep_result_files=True, odin_config=None, + yosys_script=None, min_hard_mult_size=3, min_hard_adder_size=1, check_equivalent=False, @@ -103,11 +106,11 @@ def run( Determines if the result files are kept or deleted min_hard_mult_size : - Tells ODIN II the minimum multiplier size that should + Tells ODIN II/YOSYS the minimum multiplier size that should be implemented using hard multiplier (if available) min_hard_adder_size : - Tells ODIN II the minimum adder size that should be implemented + Tells ODIN II/YOSYS the minimum adder size that should be implemented using hard adder (if available). check_equivalent : @@ -134,6 +137,7 @@ def run( # vpr_args = OrderedDict() if not vpr_args else vpr_args odin_args = OrderedDict() if not odin_args else odin_args + yosys_args = OrderedDict() if not yosys_args else yosys_args abc_args = OrderedDict() if not abc_args else abc_args # Verify that files are Paths or convert them to Paths and check that they exist architecture_file = vtr.util.verify_file(architecture_file, "Architecture") @@ -149,6 +153,7 @@ def run( # Define useful filenames post_odin_netlist = temp_dir / (circuit_file.stem + ".odin" + netlist_ext) + post_yosys_netlist = temp_dir / (circuit_file.stem + ".yosys" + netlist_ext) post_abc_netlist = temp_dir / (circuit_file.stem + ".abc" + netlist_ext) post_ace_netlist = temp_dir / (circuit_file.stem + ".ace" + netlist_ext) post_ace_activity_file = temp_dir / (circuit_file.stem + ".act") @@ -182,7 +187,7 @@ def run( next_stage_netlist = circuit_copy # - # RTL Elaboration & Synthesis + # RTL Elaboration & Synthesis (ODIN-II) # if should_run_stage(VtrStage.ODIN, start_stage, end_stage) and circuit_file.suffixes != ".blif": vtr.odin.run( @@ -201,6 +206,26 @@ def run( next_stage_netlist = post_odin_netlist lec_base_netlist = post_odin_netlist if not lec_base_netlist else lec_base_netlist + # + # RTL Elaboration & Synthesis (YOSYS) + # + elif should_run_stage(VtrStage.YOSYS, start_stage, end_stage): + vtr.yosys.run( + architecture_copy, + next_stage_netlist, + include_files, + output_netlist=post_yosys_netlist, + command_runner=command_runner, + temp_dir=temp_dir, + yosys_args=yosys_args, + yosys_script=yosys_script, + min_hard_mult_size=min_hard_mult_size, + min_hard_adder_size=min_hard_adder_size, + ) + + next_stage_netlist = post_yosys_netlist + + lec_base_netlist = post_yosys_netlist if not lec_base_netlist else lec_base_netlist # # Logic Optimization & Technology Mapping diff --git a/vtr_flow/scripts/python_libs/vtr/paths.py b/vtr_flow/scripts/python_libs/vtr/paths.py index 7556a2516f0..b3212a951bd 100644 --- a/vtr_flow/scripts/python_libs/vtr/paths.py +++ b/vtr_flow/scripts/python_libs/vtr/paths.py @@ -16,6 +16,11 @@ odin_benchmark_path = odin_path / "regression_test" / "benchmark" odin_output_on_error_path = odin_path / "regression_test" / ".library" / "output_on_error.conf" +# YOSYS paths +yosys_exe_path = root_path / "libs" / "EXTERNAL" / "libyosys" / "yosys" +yosys_lib_path = vtr_flow_path / "misc" / "yosyslib" +yosys_script_path = yosys_lib_path / "synthesis.ys" + # ABC paths abc_path = root_path / "abc" abc_exe_path = abc_path / "abc" diff --git a/vtr_flow/scripts/python_libs/vtr/yosys/__init__.py b/vtr_flow/scripts/python_libs/vtr/yosys/__init__.py new file mode 100644 index 00000000000..bfa4fe4e9ae --- /dev/null +++ b/vtr_flow/scripts/python_libs/vtr/yosys/__init__.py @@ -0,0 +1,4 @@ +""" + init for the YOSYS module +""" +from .yosys import run diff --git a/vtr_flow/scripts/python_libs/vtr/yosys/yosys.py b/vtr_flow/scripts/python_libs/vtr/yosys/yosys.py new file mode 100644 index 00000000000..0e2e29562b0 --- /dev/null +++ b/vtr_flow/scripts/python_libs/vtr/yosys/yosys.py @@ -0,0 +1,230 @@ +""" + Module to run YOSYS with its various arguments +""" +import os +import shutil +from collections import OrderedDict +from pathlib import Path +import vtr + +# supported input file type by Yosys +FILE_TYPES = { + ".v": "Verilog", + ".vh": "Verilog", + ".sv": "SystemVerilog", + ".blif": "BLIF", + ".aig": "aiger", + ".json": "JSON", + ".lib": "Liberty", + ".ys": "RTLIL", +} + +YOSYS_LIB_FILES = { + "YSMDL": "yosys_models.v", + "SPRAM": "single_port_ram.v", + "DPRAM": "dual_port_ram.v", + "SPRAMR": "spram_rename.v", + "DPRAMR": "dpram_rename.v", +} + + +def create_circuits_list(main_circuit, include_files): + """Create a list of all (.v) and (.vh) files""" + circuit_list = [] + # Check include files exist + if include_files: + # Verify that files are Paths or convert them to Paths + check that they exist + for include in include_files: + include_file = vtr.verify_file(include, "Circuit") + circuit_list.append(include_file.name) + + # Append the main circuit design as the last one + circuit_list.append(main_circuit.name) + + return circuit_list + + +# pylint: disable=too-many-arguments, too-many-locals +def init_script_file( + yosys_script_full_path, + yosys_models_full_path, + yosys_spram_full_path, + yosys_dpram_full_path, + yosys_spram_rename_full_path, + yosys_dpram_rename_full_path, + circuit_list, + output_netlist, + memory_addr_width, + min_hard_mult_size, + min_hard_adder_size, +): + """initializing the raw yosys script file""" + # specify the input files type + for circuit in circuit_list: + file_extension = os.path.splitext(circuit)[-1] + if file_extension not in FILE_TYPES: + raise vtr.VtrError("Inavlid input file type '{}'".format(file_extension)) + + # Update the config file + vtr.file_replace( + yosys_script_full_path, + { + "XXX": circuit_list[0], + "YYY": "./" + YOSYS_LIB_FILES["YSMDL"], + "SSS": "./" + YOSYS_LIB_FILES["SPRAM"], + "DDD": "./" + YOSYS_LIB_FILES["DPRAM"], + "SSR": "./" + YOSYS_LIB_FILES["SPRAMR"], + "DDR": "./" + YOSYS_LIB_FILES["DPRAMR"], + "TTT": str(vtr.paths.yosys_lib_path), + "ZZZ": output_netlist, + }, + ) + + # Update the config file + vtr.file_replace( + yosys_models_full_path, + {"PPP": memory_addr_width, "MMM": min_hard_mult_size, "AAA": min_hard_adder_size}, + ) + + # Update the config file files + vtr.file_replace(yosys_spram_full_path, {"PPP": memory_addr_width}) + vtr.file_replace(yosys_dpram_full_path, {"PPP": memory_addr_width}) + vtr.file_replace(yosys_spram_rename_full_path, {"PPP": memory_addr_width}) + vtr.file_replace(yosys_dpram_rename_full_path, {"PPP": memory_addr_width}) + + +# pylint: disable=too-many-arguments, too-many-locals +def run( + architecture_file, + circuit_file, + include_files, + output_netlist, + command_runner=vtr.CommandRunner(), + temp_dir=Path("."), + yosys_args="", + log_filename="yosys.out", + yosys_exec=None, + yosys_script=None, + min_hard_mult_size=3, + min_hard_adder_size=1, +): + """ + Runs YOSYS on the specified architecture file and circuit file + + .. note :: Usage: vtr.yosys.run(,,,[OPTIONS]) + + Arguments + ========= + architecture_file : + Architecture file to target + + circuit_file : + Circuit file to optimize + + output_netlist : + File name to output the resulting circuit to + + Other Parameters + ---------------- + command_runner : + A CommandRunner object used to run system commands + + temp_dir : + Directory to run in (created if non-existent) + + yosys_args: + A dictionary of keyword arguments to pass on to YOSYS + + log_filename : + File to log result to + + yosys_exec: + YOSYS executable to be run + + yosys_script: + The YOSYS script file + + """ + temp_dir = Path(temp_dir) if not isinstance(temp_dir, Path) else temp_dir + temp_dir.mkdir(parents=True, exist_ok=True) + + if yosys_args is None: + yosys_args = OrderedDict() + + # Verify that files are Paths or convert them to Paths and check that they exist + architecture_file = vtr.verify_file(architecture_file, "Architecture") + circuit_file = vtr.verify_file(circuit_file, "Circuit") + output_netlist = vtr.verify_file(output_netlist, "Output netlist", False) + + if yosys_exec is None: + yosys_exec = str(vtr.paths.yosys_exe_path) + + if yosys_script is None: + yosys_base_script = str(vtr.paths.yosys_script_path) + else: + yosys_base_script = str(Path(yosys_script).resolve()) + + # Copy the script file + yosys_script = "synthesis.ys" + yosys_script_full_path = str(temp_dir / yosys_script) + shutil.copyfile(yosys_base_script, yosys_script_full_path) + + # Copy the yosys models file + yosys_models = YOSYS_LIB_FILES["YSMDL"] + yosys_base_models = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["YSMDL"]) + yosys_models_full_path = str(temp_dir / yosys_models) + shutil.copyfile(yosys_base_models, yosys_models_full_path) + + # Copy the VTR memory blocks file + yosys_spram = YOSYS_LIB_FILES["SPRAM"] + yosys_dpram = YOSYS_LIB_FILES["DPRAM"] + yosys_spram_rename = YOSYS_LIB_FILES["SPRAMR"] + yosys_dpram_rename = YOSYS_LIB_FILES["DPRAMR"] + yosys_base_spram = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["SPRAM"]) + yosys_base_dpram = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["DPRAM"]) + yosys_base_spram_rename = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["SPRAMR"]) + yosys_base_dpram_rename = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["DPRAMR"]) + yosys_spram_full_path = str(temp_dir / yosys_spram) + yosys_dpram_full_path = str(temp_dir / yosys_dpram) + yosys_spram_rename_full_path = str(temp_dir / yosys_spram_rename) + yosys_dpram_rename_full_path = str(temp_dir / yosys_dpram_rename) + shutil.copyfile(yosys_base_spram, yosys_spram_full_path) + shutil.copyfile(yosys_base_dpram, yosys_dpram_full_path) + shutil.copyfile(yosys_base_spram_rename, yosys_spram_rename_full_path) + shutil.copyfile(yosys_base_dpram_rename, yosys_dpram_rename_full_path) + + # Create a list showing all (.v) and (.vh) files + circuit_list = create_circuits_list(circuit_file, include_files) + + init_script_file( + yosys_script_full_path, + yosys_models_full_path, + yosys_spram_full_path, + yosys_dpram_full_path, + yosys_spram_rename_full_path, + yosys_dpram_rename_full_path, + circuit_list, + output_netlist.name, + vtr.determine_memory_addr_width(str(architecture_file)), + min_hard_mult_size, + min_hard_adder_size, + ) + + cmd = [yosys_exec] + + for arg, value in yosys_args.items(): + if isinstance(value, bool) and value: + cmd += ["--" + arg] + elif isinstance(value, (str, int, float)): + cmd += ["--" + arg, str(value)] + else: + pass + + cmd += ["-s", yosys_script] + + command_runner.run_system_command( + cmd, temp_dir=temp_dir, log_filename=log_filename, indent_depth=1 + ) + + +# pylint: enable=too-many-arguments, too-many-locals diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py index 7b1cf4c3b7d..5930895397e 100755 --- a/vtr_flow/scripts/run_vtr_flow.py +++ b/vtr_flow/scripts/run_vtr_flow.py @@ -19,7 +19,7 @@ BASIC_VERBOSITY = 1 -VTR_STAGES = ["odin", "abc", "ace", "vpr"] +VTR_STAGES = ["odin", "yosys", "abc", "ace", "vpr"] # pylint: disable=too-few-public-methods class VtrStageArgparseAction(argparse.Action): @@ -30,6 +30,8 @@ class VtrStageArgparseAction(argparse.Action): def __call__(self, parser, namespace, value, option_string=None): if value == "odin": setattr(namespace, self.dest, vtr.VtrStage.ODIN) + elif value == "yosys": + setattr(namespace, self.dest, vtr.VtrStage.YOSYS) elif value == "abc": setattr(namespace, self.dest, vtr.VtrStage.ABC) elif value == "vpr": @@ -352,6 +354,17 @@ def vtr_command_argparser(prog=None): + "(Odin-II synthesis flow generates rising edge FFs by default)", ) # + # YOSYS arguments + # + yosys = parser.add_argument_group("Yosys", description="Arguments to be passed to Yosys") + yosys.add_argument( + "-yosys_script", + default=None, + dest="yosys_script", + help="Supplies Yosys with a .ys script file (similar to Tcl script)" + + ", including synthesis steps.", + ) + # # VPR arguments # vpr = parser.add_argument_group( @@ -483,11 +496,13 @@ def vtr_command_main(arg_list, prog=None): vpr_args=vpr_args, abc_args=process_abc_args(args), odin_args=process_odin_args(args), + yosys_args=process_yosys_args(), keep_intermediate_files=args.keep_intermediate_files, keep_result_files=args.keep_result_files, min_hard_mult_size=args.min_hard_mult_size, min_hard_adder_size=args.min_hard_adder_size, odin_config=args.odin_config, + yosys_script=args.yosys_script, check_equivalent=args.check_equivalent, check_incremental_sta_consistency=args.check_incremental_sta_consistency, use_old_abc_script=args.use_old_abc_script, @@ -632,6 +647,15 @@ def process_odin_args(args): return odin_args +def process_yosys_args(): + """ + Finds arguments needed in the YOSYS stage of the flow + """ + yosys_args = OrderedDict() + + return yosys_args + + def process_vpr_args(args, prog, temp_dir, vpr_args): """ Finds arguments needed in the VPR stage of the flow diff --git a/vtr_flow/tasks/regression_tests/regression_test.ods b/vtr_flow/tasks/regression_tests/regression_test.ods index f595ceb95d4..644a59a2c73 100644 Binary files a/vtr_flow/tasks/regression_tests/regression_test.ods and b/vtr_flow/tasks/regression_tests/regression_test.ods differ diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_yosys/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_yosys/task_list.txt new file mode 100644 index 00000000000..765ecfcf288 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_yosys/task_list.txt @@ -0,0 +1 @@ +regression_tests/vtr_reg_yosys/vtr_benchmarks/ diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_yosys/vtr_benchmarks/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_yosys/vtr_benchmarks/config/config.txt new file mode 100644 index 00000000000..db6f3e1ed4d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_yosys/vtr_benchmarks/config/config.txt @@ -0,0 +1,48 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=arm_core.v +circuit_list_add=bgm.v +circuit_list_add=blob_merge.v +circuit_list_add=boundtop.v +circuit_list_add=ch_intrinsics.v +circuit_list_add=diffeq1.v +circuit_list_add=diffeq2.v +circuit_list_add=mkDelayWorker32B.v +circuit_list_add=mkPktMerge.v +circuit_list_add=mkSMAdapter4B.v +circuit_list_add=or1200.v +circuit_list_add=raygentop.v +circuit_list_add=sha.v +circuit_list_add=spree.v +circuit_list_add=stereovision0.v +circuit_list_add=stereovision1.v +circuit_list_add=stereovision2.v +circuit_list_add=stereovision3.v +circuit_list_add=LU8PEEng.v +circuit_list_add=LU32PEEng.v +circuit_list_add=mcml.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 -start yosys diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_yosys/vtr_benchmarks/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_yosys/vtr_benchmarks/config/golden_results.txt new file mode 100644 index 00000000000..ed89416d897 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_yosys/vtr_benchmarks/config/golden_results.txt @@ -0,0 +1,22 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 451.37 -1 -1 31.59 563472 20 45.23 -1 -1 72252 -1 -1 857 133 24 0 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 238888 133 179 14304 14161 1 7135 1193 37 37 1369 clb auto 54.44 119420 19.12 0.13 17.513 -185047 -17.513 17.513 4.66 0.0423339 0.0378628 6.04365 5.22921 116 178346 46 7.54166e+07 5.93401e+07 9.94115e+06 7261.61 236.75 27.1516 23.96 166744 16 31277 120759 40909733 9445619 19.5757 19.5757 -206301 -19.5757 0 0 1.25212e+07 9146.25 3.55 12.03 2.383 2.18892 +k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 743.35 -1 -1 68.21 1381252 14 75.98 -1 -1 154492 -1 -1 2679 257 0 11 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 648540 257 32 35826 33457 1 19699 2979 62 62 3844 clb auto 100.58 253633 96.20 0.62 18.4299 -24150.1 -18.4299 18.4299 42.11 0.118325 0.107824 15.5229 13.5064 76 397723 43 2.30929e+08 1.4874e+08 1.99380e+07 5186.80 286.24 70.015 61.5257 375805 20 94355 420818 25154585 4015750 20.5174 20.5174 -27163.6 -20.5174 0 0 2.49292e+07 6485.22 7.84 11.69 6.37612 5.87229 +k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 113.63 -1 -1 16.99 270468 5 5.73 -1 -1 60700 -1 -1 485 36 0 0 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 133032 36 100 10163 7617 1 2777 621 28 28 784 clb auto 24.89 41373 7.24 0.05 13.4937 -2236.21 -13.4937 13.4937 2.41 0.0204639 0.0186331 2.88038 2.57653 70 71714 38 4.25198e+07 2.61386e+07 3.59791e+06 4589.17 41.50 10.2152 9.12951 61863 14 12947 66980 2728187 391107 15.348 15.348 -2593.38 -15.348 0 0 4.52633e+06 5773.37 1.38 1.68 1.08965 1.0106 +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 15.41 -1 -1 6.05 67564 3 1.04 -1 -1 41196 -1 -1 50 196 1 0 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 32808 196 193 1406 1499 1 667 440 15 15 225 io auto 1.06 2736 0.93 0.01 2.84726 -998.552 -2.84726 2.84726 0.54 0.00271389 0.00249257 0.408249 0.373468 38 5816 14 1.03862e+07 3.2427e+06 544116. 2418.30 3.24 1.2536 1.15877 5137 10 1652 2396 233368 62507 3.57832 3.57832 -1238.19 -3.57832 0 0 690508. 3068.92 0.19 0.15 0.106689 0.10188 +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 4.17 -1 -1 0.35 17400 3 0.07 -1 -1 38716 -1 -1 73 99 1 0 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 23712 99 130 347 477 1 226 303 13 13 169 clb auto 0.24 512 0.38 0.00 1.62126 -105.625 -1.62126 1.62126 0.37 0.000706905 0.000649234 0.118776 0.108374 40 1332 9 6.63067e+06 4.48226e+06 401688. 2376.85 1.58 0.375179 0.346046 1092 9 389 637 34086 11057 1.98279 1.98279 -131.906 -1.98279 0 0 505045. 2988.43 0.15 0.04 0.0234869 0.0223213 +k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 12.03 -1 -1 0.55 22964 8 0.21 -1 -1 38632 -1 -1 31 162 0 3 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 30832 162 96 1072 951 1 668 292 14 14 196 mult_36 auto 0.56 4461 0.87 0.01 14.4604 -1224.8 -14.4604 14.4604 0.46 0.00278096 0.00257389 0.404561 0.376825 62 8998 19 9.20055e+06 2.85871e+06 735792. 3754.04 7.19 1.41431 1.32778 8077 21 2786 5138 1315857 331563 15.69 15.69 -1422.46 -15.69 0 0 913676. 4661.61 0.24 0.42 0.153351 0.145845 +k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 11.09 -1 -1 0.44 21956 9 0.24 -1 -1 37472 -1 -1 31 66 0 3 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 32432 66 96 827 706 1 507 196 14 14 196 mult_36 auto 0.57 3401 0.66 0.01 11.2433 -716.376 -11.2433 11.2433 0.47 0.00228118 0.00210286 0.331232 0.307164 66 7200 21 9.20055e+06 2.85871e+06 787562. 4018.17 6.51 1.19593 1.1208 6829 19 2660 5598 1611125 379566 12.6399 12.6399 -844.816 -12.6399 0 0 978561. 4992.66 0.28 0.48 0.136963 0.130532 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 118.45 -1 -1 19.97 219708 5 3.25 -1 -1 71152 -1 -1 459 506 43 0 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 310924 506 553 3230 3728 1 2859 1561 50 50 2500 memory auto 6.48 15798 7.33 0.07 6.38341 -1860.59 -6.38341 6.38341 22.97 0.0184503 0.0165337 3.91281 3.57911 40 23797 18 1.47946e+08 4.83019e+07 7.18436e+06 2873.75 37.47 12.0367 11.2107 22891 14 3880 4837 4034782 1112984 7.16159 7.16159 -2356.11 -7.16159 0 0 8.97548e+06 3590.19 3.16 1.73 0.851706 0.808207 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 25.67 -1 -1 1.76 55340 2 0.23 -1 -1 42988 -1 -1 28 311 15 0 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 56992 311 156 1010 1153 1 961 510 28 28 784 memory auto 0.83 7851 1.34 0.01 3.71444 -4081.48 -3.71444 3.71444 2.29 0.00433835 0.00383464 0.646781 0.568604 36 14945 38 4.25198e+07 9.72903e+06 1.94918e+06 2486.20 13.20 2.38431 2.15075 13268 14 2990 3346 2497961 728017 4.12988 4.12988 -4838.99 -4.12988 -0.00135869 -0.00135869 2.40571e+06 3068.51 0.88 0.79 0.208865 0.195038 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 39.64 -1 -1 6.52 68048 5 2.01 -1 -1 43024 -1 -1 176 193 5 0 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 52632 193 205 2765 2699 1 1386 579 20 20 400 memory auto 3.65 11130 3.15 0.02 4.80348 -2579.64 -4.80348 4.80348 1.03 0.0061846 0.00552267 1.22091 1.08376 56 19498 20 2.07112e+07 1.22253e+07 1.41661e+06 3541.53 18.13 3.98006 3.60042 17261 14 5011 12851 936924 213837 5.47042 5.47042 -3018.54 -5.47042 0 0 1.80858e+06 4521.44 0.53 0.57 0.358495 0.336663 +k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 85.94 -1 -1 8.29 136976 8 4.21 -1 -1 45928 -1 -1 241 385 2 1 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 94548 385 394 4423 4318 1 2403 1023 27 27 729 io auto 9.04 30611 6.78 0.06 8.44173 -9493.04 -8.44173 8.44173 2.33 0.0134578 0.0122956 2.08093 1.91026 98 45291 21 3.93038e+07 1.44805e+07 4.48119e+06 6147.03 44.90 7.16021 6.63214 42535 19 9368 30356 2775139 511468 9.12094 9.12094 -10677.7 -9.12094 0 0 5.68448e+06 7797.64 1.75 1.44 0.810046 0.765091 +k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 40.21 -1 -1 4.69 47824 3 0.87 -1 -1 42252 -1 -1 125 236 1 18 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 71444 236 305 3269 3036 1 1594 685 26 26 676 mult_36 auto 2.80 15814 2.97 0.03 5.52245 -3183.75 -5.52245 5.52245 2.12 0.00814169 0.00755107 1.2804 1.18518 52 28465 34 3.69863e+07 1.44128e+07 2.31406e+06 3423.16 19.70 4.4928 4.18867 25887 14 6034 15536 4392508 960083 5.99634 5.99634 -3750.69 -5.99634 0 0 3.04613e+06 4506.11 0.87 1.27 0.401918 0.383601 +k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 21.93 -1 -1 2.96 57776 3 1.69 -1 -1 44720 -1 -1 133 38 0 0 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 53524 38 36 2812 2561 1 1042 207 16 16 256 clb auto 2.48 8956 1.78 0.02 8.98418 -2093.3 -8.98418 8.98418 0.65 0.00534575 0.00467226 0.780685 0.685826 82 12738 19 1.21132e+07 7.1679e+06 1.22682e+06 4792.28 8.44 3.11179 2.7825 12135 18 3462 8414 316070 52909 10.365 10.365 -2443.05 -10.365 0 0 1.54487e+06 6034.64 0.41 0.40 0.323191 0.300608 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 18.60 -1 -1 2.97 36344 16 0.61 -1 -1 39932 -1 -1 58 45 3 1 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 33472 45 32 1201 1160 1 778 139 14 14 196 memory auto 2.76 6534 0.77 0.01 9.67608 -6200.95 -9.67608 9.67608 0.47 0.00255497 0.00221813 0.364318 0.313788 64 12188 17 9.20055e+06 5.16585e+06 762053. 3888.03 7.83 1.46731 1.30334 11142 14 3459 9054 2057269 525434 11.2111 11.2111 -7457.1 -11.2111 0 0 953435. 4864.47 0.26 0.64 0.172724 0.161496 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 97.31 -1 -1 11.77 143816 5 7.58 -1 -1 70752 -1 -1 695 169 0 0 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 199656 169 197 23031 21171 1 6606 1061 33 33 1089 clb auto 13.27 40571 9.68 0.08 3.00022 -13014.8 -3.00022 3.00022 3.56 0.031264 0.0277024 4.45684 3.9099 56 62822 39 6.0475e+07 3.74565e+07 4.09277e+06 3758.28 32.14 17.5716 15.6613 58048 15 18075 28377 1225652 231591 3.79781 3.79781 -15451.1 -3.79781 0 0 5.21984e+06 4793.24 1.57 1.91 1.8601 1.7366 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 340.73 -1 -1 9.68 154492 3 13.63 -1 -1 87708 -1 -1 668 115 0 152 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 690924 115 145 22695 19132 1 9576 1080 72 72 5184 mult_36 auto 11.34 106140 15.52 0.10 7.00814 -28306.4 -7.00814 7.00814 52.99 0.0528456 0.0489492 8.24549 7.60836 40 156061 29 3.11004e+08 9.61944e+07 1.50616e+07 2905.41 188.79 27.7083 25.7819 147382 14 31463 49368 19846094 4255556 7.24267 7.24267 -32972.9 -7.24267 0 0 1.88063e+07 3627.77 7.41 6.38 2.44199 2.32489 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 1081.06 -1 -1 14.39 258176 5 7.48 -1 -1 185820 -1 -1 1630 149 0 480 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 2080372 149 182 58507 39500 1 30536 2441 128 128 16384 mult_36 auto 28.14 291985 58.36 0.42 13.3488 -59254.2 -13.3488 13.3488 194.04 0.170587 0.155933 25.1444 23.2969 98 389683 23 1.01881e+09 2.7792e+08 1.08455e+08 6619.54 595.39 101.891 94.48 376318 22 94455 109071 29217720 5934923 14.6559 14.6559 -67122.7 -14.6559 0 0 1.37504e+08 8392.55 50.52 15.52 9.32963 8.74473 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.82 -1 -1 0.68 21564 5 0.11 -1 -1 37852 -1 -1 16 11 0 0 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 18828 11 3 350 331 2 115 30 7 7 49 clb auto 0.45 429 0.11 0.00 2.37066 -156.974 -2.37066 2.087 0.06 0.000571381 0.000494118 0.069897 0.0597986 34 682 17 1.07788e+06 862304 84249.8 1719.38 0.45 0.223618 0.194642 634 15 338 678 14104 4589 2.92019 2.48918 -184.427 -2.92019 0 0 103542. 2113.11 0.02 0.04 0.0327379 0.0304065 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 810.72 -1 -1 91.16 2085580 92 81.45 -1 -1 155868 -1 -1 2173 114 45 8 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 579604 114 102 36345 32373 1 17170 2442 57 57 3249 clb auto 96.43 233241 75.73 0.51 62.7441 -52203.7 -62.7441 62.7441 32.06 0.102889 0.0930674 15.878 13.4729 100 332805 38 1.92089e+08 1.44942e+08 2.12617e+07 6544.09 356.04 65.6833 57.0597 314142 22 64108 254796 41257284 9859065 72.2772 72.2772 -66185.5 -72.2772 0 0 2.68217e+07 8255.37 8.75 17.19 6.71833 6.05797 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 3287.35 -1 -1 300.46 7822484 96 666.99 -1 -1 535948 -1 -1 7556 114 168 32 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 2330556 114 102 122282 109836 1 58346 7972 103 103 10609 clb auto 328.43 1072117 321.28 2.07 65.4744 -321729 -65.4744 65.4744 97.38 0.322717 0.28825 48.4594 41.3375 146 1379641 21 6.46441e+08 5.11919e+08 9.97823e+07 9405.44 1275.64 225.697 194.71 1342041 21 204638 885119 226525707 55032096 74.8745 74.8745 -445233 -74.8745 0 0 1.26370e+08 11911.6 38.37 75.21 22.6571 20.3106 +k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5775.04 -1 -1 358.71 4961208 25 3253.06 -1 -1 452248 -1 -1 6352 36 97 26 success v8.0.0-rc2-4624-g18c329690-dirty Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-305.12.1.el8_4.x86_64 x86_64 2021-09-27T22:13:40 node3 /root/mntssd/MD/sdamghan/vtr_flow/scripts 2285532 36 356 184483 159112 1 64074 6867 95 95 9025 clb auto 197.61 736588 401.42 2.38 41.5819 -276603 -41.5819 41.5819 80.35 0.339553 0.287768 56.3151 47.8084 142 954418 24 5.4965e+08 4.05758e+08 8.24996e+07 9141.23 1246.38 251.677 219.28 921403 22 217865 481818 67131311 15184502 45.2847 45.2847 -346057 -45.2847 0 0 1.04574e+08 11587.1 32.60 36.20 21.8607 19.8149