diff --git a/vpr/src/place/grid_tile_lookup.cpp b/vpr/src/place/grid_tile_lookup.cpp new file mode 100644 index 00000000000..231e997b272 --- /dev/null +++ b/vpr/src/place/grid_tile_lookup.cpp @@ -0,0 +1,143 @@ +#include "grid_tile_lookup.h" + +void GridTileLookup::initialize_grid_tile_matrices() { + auto& device_ctx = g_vpr_ctx.device(); + + //Will store the max number of tile locations for each logical block type + max_placement_locations.resize(device_ctx.logical_block_types.size()); + + for (const auto& type : device_ctx.logical_block_types) { + vtr::NdMatrix type_count({device_ctx.grid.width(), device_ctx.grid.height()}); + fill_type_matrix(&type, type_count); + block_type_matrices.push_back(type_count); + } +} + +void GridTileLookup::fill_type_matrix(t_logical_block_type_ptr block_type, vtr::NdMatrix& type_count) { + auto& device_ctx = g_vpr_ctx.device(); + + int num_rows = device_ctx.grid.height(); + int num_cols = device_ctx.grid.width(); + + /* + * Iterating through every location on the grid to store the number of subtiles of + * the correct type at each location. For each location, we store the cumulative + * number of tiles of the type up to that location - meaning we store the number of + * subtiles at the location, plus the number of subtiles at the locations above and to + * the right of it. + */ + for (int i_col = type_count.dim_size(0) - 1; i_col >= 0; i_col--) { + for (int j_row = type_count.dim_size(1) - 1; j_row >= 0; j_row--) { + auto& tile = device_ctx.grid[i_col][j_row].type; + type_count[i_col][j_row] = 0; + + if (is_tile_compatible(tile, block_type)) { + for (const auto& sub_tile : tile->sub_tiles) { + if (is_sub_tile_compatible(tile, block_type, sub_tile.capacity.low)) { + type_count[i_col][j_row] = sub_tile.capacity.total(); + } + } + } + + if (i_col < num_cols - 1) { + type_count[i_col][j_row] += type_count[i_col + 1][j_row]; + } + if (j_row < num_rows - 1) { + type_count[i_col][j_row] += type_count[i_col][j_row + 1]; + } + if (i_col < (num_cols - 1) && j_row < (num_rows - 1)) { + type_count[i_col][j_row] -= type_count[i_col + 1][j_row + 1]; + } + } + } + + //The total number of subtiles for the block type will be at [0][0] + max_placement_locations[block_type->index] = type_count[0][0]; +} + +vtr::NdMatrix& GridTileLookup::get_type_grid(t_logical_block_type_ptr block_type) { + return block_type_matrices[block_type->index]; +} + +int GridTileLookup::total_type_tiles(t_logical_block_type_ptr block_type) { + return max_placement_locations[block_type->index]; +} + +/* + * This routine uses pre-computed values from the grids for each block type to get the number of grid tiles + * covered by a region. + * For a region with no subtiles specified, the number of grid tiles can be calculated by adding + * and subtracting four values from within/at the edge of the region. + * The region with subtile case is taken care of by a helper routine, region_with_subtile_count(). + */ +int GridTileLookup::region_tile_count(const Region& reg, t_logical_block_type_ptr block_type) { + vtr::Rect reg_rect = reg.get_region_rect(); + int subtile = reg.get_sub_tile(); + + int xmin = reg_rect.xmin(); + int ymin = reg_rect.ymin(); + int xmax = reg_rect.xmax(); + int ymax = reg_rect.ymax(); + auto& type_grid = block_type_matrices[block_type->index]; + + int xdim = type_grid.dim_size(0); + int ydim = type_grid.dim_size(1); + + int num_tiles = 0; + + if (subtile == NO_SUBTILE) { + num_tiles = type_grid[xmin][ymin]; + + if ((ymax + 1) < ydim) { + num_tiles -= type_grid[xmin][ymax + 1]; + } + + if ((xmax + 1) < xdim) { + num_tiles -= type_grid[xmax + 1][ymin]; + } + + if ((xmax + 1) < xdim && (ymax + 1) < ydim) { + num_tiles += type_grid[xmax + 1][ymax + 1]; + } + } else { + num_tiles = region_with_subtile_count(reg, block_type); + } + + return num_tiles; +} + +/* + * This routine is for the subtile specified case; an O(region_size) scan needs to be done to check whether each grid + * location in the region is compatible for the block at the subtile specified. + */ +int GridTileLookup::region_with_subtile_count(const Region& reg, t_logical_block_type_ptr block_type) { + auto& device_ctx = g_vpr_ctx.device(); + int num_sub_tiles = 0; + vtr::Rect reg_rect = reg.get_region_rect(); + int subtile = reg.get_sub_tile(); + + int xmin = reg_rect.xmin(); + int ymin = reg_rect.ymin(); + int xmax = reg_rect.xmax(); + int ymax = reg_rect.ymax(); + + for (int i = xmax; i >= xmin; i--) { + for (int j = ymax; j >= ymin; j--) { + auto& tile = device_ctx.grid[i][j].type; + if (is_sub_tile_compatible(tile, block_type, subtile)) { + num_sub_tiles++; + } + } + } + + return num_sub_tiles; +} + +void GridTileLookup::print_type_matrix(vtr::NdMatrix& type_count) { + for (int i_col = type_count.dim_size(0) - 1; i_col >= 0; i_col--) { + for (int j_row = type_count.dim_size(1) - 1; j_row >= 0; j_row--) { + VTR_LOG("%d ", type_count[i_col][j_row]); + } + VTR_LOG("\n"); + } +} diff --git a/vpr/src/place/grid_tile_lookup.h b/vpr/src/place/grid_tile_lookup.h new file mode 100644 index 00000000000..edf4388f3ea --- /dev/null +++ b/vpr/src/place/grid_tile_lookup.h @@ -0,0 +1,49 @@ +/* + * This class is used to store a grid for each logical block type that stores the cumulative number of subtiles + * for that type available at each location in the grid. The cumulative number of subtiles is the subtiles at the + * location plus the subtiles available at the grid locations above and to the right of the locations. + * Having these grids allows for O(1) lookups about the number of subtiles available for a given type of block + * in a rectangular region. + * This lookup class is used during initial placement when sorting blocks by the size of their floorplan constraint + * regions. + */ +#ifndef VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ +#define VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ + +#include "place_util.h" +#include "globals.h" + +class GridTileLookup { + public: + vtr::NdMatrix& get_type_grid(t_logical_block_type_ptr block_type); + + void initialize_grid_tile_matrices(); + + void fill_type_matrix(t_logical_block_type_ptr block_type, vtr::NdMatrix& type_count); + + void print_type_matrix(vtr::NdMatrix& type_count); + + int region_tile_count(const Region& reg, t_logical_block_type_ptr block_type); + + int region_with_subtile_count(const Region& reg, t_logical_block_type_ptr block_type); + + int total_type_tiles(t_logical_block_type_ptr block_type); + + private: + /* + * Stores the cumulative total of subtiles available at each location in the grid for each block type. + * Therefore, the length of the vector will be the number of logical block types. To access the cumulative + * number of subtiles at a location, you would use block_type_matrices[iblock_type][x][y] - this would + * give the number of placement locations that are at, or above and to the right of the given [x,y] for + * the given block type. + */ + std::vector> block_type_matrices; + + /* + * Stores the total number of placement locations (i.e. compatible subtiles) for each block type. + * To access the max_placement locations for a particular block type, use max_placement_locations[block_type->index] + */ + std::vector max_placement_locations; +}; + +#endif /* VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ */ diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 23fd8683b18..07df5e2de69 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -15,9 +15,11 @@ struct t_block_score { int macro_size = 0; //how many members does the macro have, if the block is part of one, this value is zero if the block is not in a macro - int floorplan_constraints = 0; //how many floorplan constraints does it have, if any - - int num_equivalent_tiles = 1; //num of physical locations at which this block could be placed + /* + * The number of tiles NOT covered by the block's floorplan constraints. The higher this number, the more + * difficult the block is to place. + */ + int tiles_outside_of_floorplan_constraints = 0; }; /* The maximum number of tries when trying to place a carry chain at a * @@ -31,9 +33,9 @@ static int get_free_sub_tile(std::vector>& free_locations, int static int check_macro_can_be_placed(t_pl_macro pl_macro, int itype, t_pl_loc head_pos); static int try_place_macro(int itype, int ipos, int isub_tile, t_pl_macro pl_macro); -static void initial_placement_pl_macros(int macros_max_num_tries, std::vector>& free_locations); +static void initial_placement_pl_macros(int macros_max_num_tries, std::vector>& free_locations, const std::vector& sorted_macros); -static void initial_placement_blocks(std::vector>& free_locations, enum e_pad_loc_type pad_loc_type, std::vector sorted_blocks); +static void initial_placement_blocks(std::vector>& free_locations, enum e_pad_loc_type pad_loc_type, const std::vector& sorted_blocks); static t_physical_tile_type_ptr pick_placement_type(t_logical_block_type_ptr logical_block, int num_needed_types, @@ -44,10 +46,13 @@ static t_physical_tile_type_ptr pick_placement_type(t_logical_block_type_ptr log * Used for relative placement, so that the blocks that are more difficult to place can be placed first during initial placement. * A higher score indicates that the block is more difficult to place. */ -vtr::vector assign_block_scores(); +static vtr::vector assign_block_scores(); //Sort the blocks according to how difficult they are to place, prior to initial placement -std::vector sort_blocks(const vtr::vector& block_scores); +static std::vector sort_blocks(const vtr::vector& block_scores); + +//Sort the macros according to how difficult they are to place, prior to initial placement +static std::vector sort_macros(const vtr::vector& block_scores); void print_sorted_blocks(const std::vector& sorted_blocks, const vtr::vector& block_scores); @@ -161,33 +166,15 @@ static int try_place_macro(int itype, int ipos, int isub_tile, t_pl_macro pl_mac return (macro_placed); } -static void initial_placement_pl_macros(int macros_max_num_tries, std::vector>& free_locations) { +static void initial_placement_pl_macros(int macros_max_num_tries, std::vector>& free_locations, const std::vector& sorted_macros) { int macro_placed; int itype, itry, ipos, isub_tile; ClusterBlockId blk_id; auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_ctx = g_vpr_ctx.placement(); - - auto& pl_macros = place_ctx.pl_macros; - - // Sorting blocks to place to have most constricted ones to be placed first - std::vector sorted_pl_macros(pl_macros.begin(), pl_macros.end()); - - auto criteria = [&cluster_ctx](const t_pl_macro lhs, t_pl_macro rhs) { - auto lhs_logical_block = cluster_ctx.clb_nlist.block_type(lhs.members[0].blk_index); - auto rhs_logical_block = cluster_ctx.clb_nlist.block_type(rhs.members[0].blk_index); - - auto lhs_num_tiles = lhs_logical_block->equivalent_tiles.size(); - auto rhs_num_tiles = rhs_logical_block->equivalent_tiles.size(); - - return lhs_num_tiles < rhs_num_tiles; - }; - - std::stable_sort(sorted_pl_macros.begin(), sorted_pl_macros.end(), criteria); /* Macros are harder to place. Do them first */ - for (auto pl_macro : sorted_pl_macros) { + for (auto pl_macro : sorted_macros) { // Every macro are not placed in the beginnning macro_placed = false; @@ -255,7 +242,7 @@ static void initial_placement_pl_macros(int macros_max_num_tries, std::vector>& free_locations, enum e_pad_loc_type pad_loc_type, std::vector sorted_blocks) { +static void initial_placement_blocks(std::vector>& free_locations, enum e_pad_loc_type pad_loc_type, const std::vector& sorted_blocks) { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& place_ctx = g_vpr_ctx.mutable_placement(); @@ -346,18 +333,22 @@ static t_physical_tile_type_ptr pick_placement_type(t_logical_block_type_ptr log return nullptr; } -vtr::vector assign_block_scores() { +static vtr::vector assign_block_scores() { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& place_ctx = g_vpr_ctx.placement(); + auto& floorplan_ctx = g_vpr_ctx.floorplanning(); - auto blocks = cluster_ctx.clb_nlist.blocks(); - auto pl_macros = place_ctx.pl_macros; + auto& pl_macros = place_ctx.pl_macros; t_block_score score; vtr::vector block_scores; - block_scores.resize(blocks.size()); + block_scores.resize(cluster_ctx.clb_nlist.blocks().size()); + + //GridTileLookup class provides info needed for calculating number of tiles covered by a region + GridTileLookup grid_tiles; + grid_tiles.initialize_grid_tile_matrices(); /* * For the blocks with no floorplan constraints, and the blocks that are not part of macros, @@ -366,13 +357,13 @@ vtr::vector assign_block_scores() { */ //go through all blocks and store floorplan constraints and num equivalent tiles - for (auto blk_id : blocks) { + for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { if (is_cluster_constrained(blk_id)) { - block_scores[blk_id].floorplan_constraints = 1; + PartitionRegion pr = floorplan_ctx.cluster_constraints[blk_id]; + auto block_type = cluster_ctx.clb_nlist.block_type(blk_id); + int floorplan_score = get_floorplan_score(blk_id, pr, block_type, grid_tiles); + block_scores[blk_id].tiles_outside_of_floorplan_constraints = floorplan_score; } - auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); - auto num_tiles = logical_block->equivalent_tiles.size(); - block_scores[blk_id].num_equivalent_tiles = num_tiles; } //go through placement macros and store size of macro for each block @@ -386,16 +377,24 @@ vtr::vector assign_block_scores() { return block_scores; } -std::vector sort_blocks(const vtr::vector& block_scores) { +static std::vector sort_blocks(const vtr::vector& block_scores) { auto& cluster_ctx = g_vpr_ctx.clustering(); auto blocks = cluster_ctx.clb_nlist.blocks(); std::vector sorted_blocks(blocks.begin(), blocks.end()); + /* + * The criteria considers blocks that belong to a macro or to a floorplan region more difficult to place. + * The bigger the macro, and/or the tighter the floorplan constraint, the earlier the block will be in + * the list of sorted blocks. + * The tiles_outside_of_floorplan_constraints will dominate the criteria, since the number of tiles will + * likely be significantly bigger than the macro size. This is okay since the floorplan constraints give + * a more accurate picture of how difficult a block is to place. + */ auto criteria = [block_scores](ClusterBlockId lhs, ClusterBlockId rhs) { - int lhs_score = 100 * block_scores[lhs].macro_size + 10 * block_scores[lhs].floorplan_constraints + 10 / (block_scores[lhs].num_equivalent_tiles); - int rhs_score = 100 * block_scores[rhs].macro_size + 10 * block_scores[rhs].floorplan_constraints + 10 / (block_scores[rhs].num_equivalent_tiles); + int lhs_score = 10 * block_scores[lhs].macro_size + block_scores[lhs].tiles_outside_of_floorplan_constraints; + int rhs_score = 10 * block_scores[rhs].macro_size + block_scores[rhs].tiles_outside_of_floorplan_constraints; return lhs_score > rhs_score; }; @@ -406,10 +405,29 @@ std::vector sort_blocks(const vtr::vector sort_macros(const vtr::vector& block_scores) { + auto& place_ctx = g_vpr_ctx.placement(); + auto& pl_macros = place_ctx.pl_macros; + + // Sorting blocks to place to have most constricted ones to be placed first + std::vector sorted_pl_macros(pl_macros.begin(), pl_macros.end()); + + auto criteria = [block_scores](const t_pl_macro lhs, t_pl_macro rhs) { + int lhs_score = 10 * block_scores[lhs.members[0].blk_index].macro_size + block_scores[lhs.members[0].blk_index].tiles_outside_of_floorplan_constraints; + int rhs_score = 10 * block_scores[rhs.members[0].blk_index].macro_size + block_scores[rhs.members[0].blk_index].tiles_outside_of_floorplan_constraints; + + return lhs_score > rhs_score; + }; + + std::stable_sort(sorted_pl_macros.begin(), sorted_pl_macros.end(), criteria); + + return sorted_pl_macros; +} + void print_sorted_blocks(const std::vector& sorted_blocks, const vtr::vector& block_scores) { VTR_LOG("\nPrinting sorted blocks: \n"); for (unsigned int i = 0; i < sorted_blocks.size(); i++) { - VTR_LOG("Block_Id: %zu, Macro size: %d, Num floorplan constraints: %d, Num equivalent tiles %d \n", sorted_blocks[i], block_scores[sorted_blocks[i]].macro_size, block_scores[sorted_blocks[i]].floorplan_constraints, block_scores[sorted_blocks[i]].num_equivalent_tiles); + VTR_LOG("Block_Id: %zu, Macro size: %d, Num tiles outside floorplan constraints: %d\n", sorted_blocks[i], block_scores[sorted_blocks[i]].macro_size, block_scores[sorted_blocks[i]].tiles_outside_of_floorplan_constraints); } } @@ -421,15 +439,16 @@ void initial_placement(enum e_pad_loc_type pad_loc_type, const char* constraints * array that gives every legal value of (x,y,z) that can accommodate a block. */ - //Sort blocks - vtr::vector block_scores = assign_block_scores(); - std::vector sorted_blocks = sort_blocks(block_scores); - /* Go through cluster blocks to calculate the tightest placement * floorplan constraint for each constrained block */ propagate_place_constraints(); + //Sort blocks and placement macros according to how difficult they are to place + vtr::vector block_scores = assign_block_scores(); + std::vector sorted_blocks = sort_blocks(block_scores); + std::vector sorted_macros = sort_macros(block_scores); + // Loading legal placement locations zero_initialize_grid_blocks(); alloc_and_load_legal_placement_locations(legal_pos); @@ -483,7 +502,7 @@ void initial_placement(enum e_pad_loc_type pad_loc_type, const char* constraints * as fixed so they do not get moved during initial placement or during simulated annealing*/ mark_fixed_blocks(); - initial_placement_pl_macros(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, free_locations); + initial_placement_pl_macros(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, free_locations, sorted_macros); // All the macros are placed, update the legal_pos[][] array and free_locations[] array for (const auto& type : device_ctx.physical_tile_types) { diff --git a/vpr/src/place/place_constraints.cpp b/vpr/src/place/place_constraints.cpp index 43a8231fe3c..72765d04c26 100644 --- a/vpr/src/place/place_constraints.cpp +++ b/vpr/src/place/place_constraints.cpp @@ -413,3 +413,33 @@ bool is_pr_size_one(PartitionRegion& pr, t_logical_block_type_ptr block_type, t_ return pr_size_one; } + +int get_part_reg_size(PartitionRegion& pr, t_logical_block_type_ptr block_type, GridTileLookup& grid_tiles) { + std::vector part_reg = pr.get_partition_region(); + int num_tiles = 0; + + for (unsigned int i_reg = 0; i_reg < part_reg.size(); i_reg++) { + num_tiles += grid_tiles.region_tile_count(part_reg[i_reg], block_type); + } + + return num_tiles; +} + +int get_floorplan_score(ClusterBlockId blk_id, PartitionRegion& pr, t_logical_block_type_ptr block_type, GridTileLookup& grid_tiles) { + auto& cluster_ctx = g_vpr_ctx.clustering(); + + int num_pr_tiles = get_part_reg_size(pr, block_type, grid_tiles); + + if (num_pr_tiles == 0) { + VPR_FATAL_ERROR(VPR_ERROR_PLACE, + "Initial placement failed.\n" + "The specified floorplan region for block %s (# %d) has no available locations for its type. \n" + "Please specify a different floorplan region for the block. Note that if the region has a specified subtile, " + "an incompatible subtile location may be the cause of the floorplan region failure. \n", + cluster_ctx.clb_nlist.block_name(blk_id).c_str(), blk_id); + } + + int total_type_tiles = grid_tiles.total_type_tiles(block_type); + + return total_type_tiles - num_pr_tiles; +} diff --git a/vpr/src/place/place_constraints.h b/vpr/src/place/place_constraints.h index ccbe4c9f64e..c78167fdb0c 100644 --- a/vpr/src/place/place_constraints.h +++ b/vpr/src/place/place_constraints.h @@ -8,6 +8,9 @@ #include "move_transactions.h" #include "region.h" #include "clustered_netlist_utils.h" +#include "partition_region.h" +#include "place_macro.h" +#include "grid_tile_lookup.h" #ifndef VPR_SRC_PLACE_PLACE_CONSTRAINTS_H_ # define VPR_SRC_PLACE_PLACE_CONSTRAINTS_H_ @@ -113,4 +116,20 @@ int region_tile_cover(const Region& reg, t_logical_block_type_ptr block_type, t_ */ bool is_pr_size_one(PartitionRegion& pr, t_logical_block_type_ptr block_type, t_pl_loc& loc); +/* + * Returns the number of grid tiles that are covered by the partition region and + * compatible with the cluster's block type. + * Used prior to initial placement to help sort blocks based on how difficult they + * are to place. + */ +int get_part_reg_size(PartitionRegion& pr, t_logical_block_type_ptr block_type, GridTileLookup& grid_tiles); + +/* + * Return the floorplan score that will be used for sorting blocks during initial placement. This score is the + * total number of subtilesfor the block type in the grid, minus the number of subtiles in the block's floorplan PartitionRegion. + * The resulting number is the number of tiles outside the block's floorplan region, meaning the higher + * it is, the more difficult the block is to place. + */ +int get_floorplan_score(ClusterBlockId blk_id, PartitionRegion& pr, t_logical_block_type_ptr block_type, GridTileLookup& grid_tiles); + #endif /* VPR_SRC_PLACE_PLACE_CONSTRAINTS_H_ */ diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt index aa9fe3d89b2..991fa1fb600 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt @@ -1,22 +1,22 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 269.81 1.48 127116 18 68.27 -1 -1 66568 -1 -1 1008 133 24 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 351672 133 179 18339 18121 1 9040 1344 39 39 1521 clb auto 21.70 138925 15.16 0.10 17.3291 -132913 -17.3291 17.3291 3.70 0.030988 0.0256309 4.68525 3.40289 106 195650 27 8.65315e+07 6.74784e+07 1.02794e+07 6758.33 111.34 18.9185 14.7658 182348 15 34912 125847 27216363 6482638 19.2483 19.2483 -152788 -19.2483 0 0 1.30215e+07 8561.12 3.84 7.19 1.94061 1.68975 - k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 652.65 10.96 389048 15 231.59 -1 -1 147092 -1 -1 2712 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 758804 257 32 35908 33296 1 19534 3012 63 63 3969 clb auto 54.75 255913 69.34 0.47 18.1917 -23818.8 -18.1917 18.1917 30.31 0.082101 0.0725892 10.1014 7.361 80 392154 29 2.36641e+08 1.50518e+08 2.15027e+07 5417.67 196.92 48.53 37.628 366453 20 88192 390830 20471535 3157944 20.5117 20.5117 -26441.9 -20.5117 0 0 2.71248e+07 6834.16 9.06 9.76 5.1415 4.43401 - k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 141.23 0.44 55428 5 38.19 -1 -1 59600 -1 -1 619 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 188360 36 100 14037 11284 1 3230 755 31 31 961 clb auto 13.79 45897 5.68 0.04 13.3428 -2596.7 -13.3428 13.3428 2.40 0.0127153 0.0105197 2.12648 1.54036 60 76713 48 5.14688e+07 3.33604e+07 3.85800e+06 4014.56 69.22 7.38024 5.68246 66475 13 12384 59651 2545727 332961 15.3759 15.3759 -2979.2 -15.3759 0 0 4.86014e+06 5057.38 1.11 1.34 0.856679 0.744743 - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 6.29 0.51 44976 3 0.37 -1 -1 37684 -1 -1 93 142 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 73516 142 192 1069 1139 1 566 427 14 14 196 clb auto 0.63 1719 0.57 0.00 2.89823 -451.929 -2.89823 2.89823 0.28 0.00109467 0.000972948 0.195215 0.170313 38 3929 16 9.20055e+06 5.01214e+06 467348. 2384.43 1.64 0.54282 0.483482 3370 10 1156 1738 87127 23536 3.536 3.536 -547.719 -3.536 0 0 593372. 3027.41 0.10 0.06 0.0461998 0.0434643 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.22 0.05 9432 3 0.19 -1 -1 36200 -1 -1 65 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66664 99 130 363 493 1 251 295 12 12 144 clb auto 0.13 617 0.25 0.00 2.00545 -202.179 -2.00545 2.00545 0.18 0.000428766 0.000375707 0.0721075 0.0625634 46 1412 9 5.66058e+06 4.05111e+06 378966. 2631.71 0.42 0.132864 0.117642 1261 9 529 668 43396 14976 2.66687 2.66687 -234.696 -2.66687 0 0 486261. 3376.82 0.08 0.02 0.0148596 0.0138955 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 8.78 0.04 9016 6 0.17 -1 -1 34268 -1 -1 32 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 71732 162 96 1075 884 1 667 295 16 16 256 mult_36 auto 0.32 4733 0.50 0.01 15.5592 -1185.14 -15.5592 15.5592 0.37 0.00152817 0.00139693 0.217872 0.197068 62 10311 45 1.21132e+07 3.70461e+06 968026. 3781.35 5.42 0.963492 0.883003 8377 19 3224 5336 1782353 475161 17.1072 17.1072 -1423.44 -17.1072 0 0 1.20332e+06 4700.46 0.20 0.31 0.0853564 0.0797899 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 9.22 0.03 8168 6 0.09 -1 -1 33300 -1 -1 20 66 0 7 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 72192 66 96 866 607 1 547 189 18 18 324 mult_36 auto 0.35 4560 0.41 0.00 12.009 -735.792 -12.009 12.009 0.52 0.0014174 0.00132161 0.204848 0.188121 60 9415 21 1.57076e+07 3.84988e+06 1.22123e+06 3769.23 5.88 0.687682 0.638521 8603 17 2397 4657 1890034 439154 13.181 13.181 -845.871 -13.181 0 0 1.53789e+06 4746.57 0.26 0.30 0.0693529 0.0657309 - k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 479.27 7.49 218888 100 85.94 -1 -1 103964 -1 -1 2180 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 688176 114 102 38208 33849 1 17938 2448 57 57 3249 clb auto 67.56 239395 71.22 0.50 66.5755 -50925.9 -66.5755 66.5755 24.28 0.100265 0.0839475 14.2333 10.5167 92 361512 48 1.92089e+08 1.44771e+08 1.98119e+07 6097.84 167.92 39.0305 29.9848 328109 23 72468 273398 39855950 8187728 75.3499 75.3499 -63032 -75.3499 0 0 2.51903e+07 7753.25 6.70 13.57 5.43985 4.49789 - k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 3460.88 81.65 746632 102 807.97 -1 -1 358852 -1 -1 7495 114 167 32 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 2381312 114 102 124755 111050 1 59278 7910 102 102 10404 clb auto 217.77 1072406 485.23 2.74 67.6126 -342686 -67.6126 67.6126 92.31 0.258025 0.214171 43.9533 32.1826 128 1405319 39 6.36957e+08 5.08087e+08 8.68880e+07 8351.40 1524.24 198.521 153.641 1350075 21 217881 912992 253789873 63051185 76.337 76.337 -476260 -76.337 0 0 1.09718e+08 10545.7 33.11 91.44 18.9702 15.7474 - k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5064.63 57.54 928552 25 3403.75 -1 -1 373104 -1 -1 7078 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 2394848 36 33 190540 166259 1 61618 7333 99 99 9801 clb auto 219.72 718258 618.26 3.00 42.0812 -275832 -42.0812 42.0812 86.36 0.23051 0.192622 48.7536 36.0398 138 951582 21 6.00857e+08 4.79252e+08 8.73468e+07 8912.03 457.91 154.37 119.977 917221 22 225274 574203 91930691 20227411 45.1932 45.1932 -346416 -45.1932 0 0 1.11488e+08 11375.2 43.80 41.12 18.3494 15.6474 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 76.58 0.79 78332 5 5.90 -1 -1 53132 -1 -1 456 506 45 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 335340 506 553 3519 4017 1 3099 1560 50 50 2500 memory auto 4.49 15041 4.80 0.04 6.68635 -1894.57 -6.68635 6.68635 18.16 0.0114787 0.0103772 2.43774 2.17687 38 23149 16 1.47946e+08 4.92362e+07 6.86579e+06 2746.32 28.48 5.92539 5.40792 22207 14 4233 5386 3331744 828056 7.52959 7.52959 -2298.71 -7.52959 0 0 8.69102e+06 3476.41 2.30 1.00 0.522626 0.494679 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 11.81 0.11 17348 2 0.07 -1 -1 33996 -1 -1 29 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 94692 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.48 8138 0.84 0.01 3.74116 -4094.6 -3.74116 3.74116 1.58 0.00247621 0.00212405 0.376246 0.316773 36 14917 17 4.25198e+07 9.78293e+06 1.94918e+06 2486.20 4.51 1.03892 0.904886 13627 14 3139 3534 2595237 727498 4.23116 4.23116 -4785.8 -4.23116 0 0 2.40571e+06 3068.51 0.65 0.68 0.1696 0.155103 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 22.76 0.27 31996 4 1.67 -1 -1 37996 -1 -1 193 193 5 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 97460 193 205 2926 2852 1 1458 596 20 20 400 memory auto 2.70 11363 2.09 0.01 4.87719 -2477.32 -4.87719 4.87719 0.68 0.00375302 0.00313141 0.734772 0.593978 56 21377 42 2.07112e+07 1.31415e+07 1.41661e+06 3541.53 11.86 1.91815 1.61938 17625 14 4928 12826 996652 229620 5.25923 5.25923 -2945.62 -5.25923 0 0 1.80858e+06 4521.44 0.31 0.37 0.217726 0.200862 - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 185.04 0.46 40060 8 4.20 -1 -1 41872 -1 -1 253 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 118512 385 394 4649 4513 1 2409 1035 27 27 729 io auto 6.90 30379 4.46 0.04 8.13796 -9652.08 -8.13796 8.13796 1.52 0.00778595 0.0069791 1.38242 1.11181 88 45660 42 3.93038e+07 1.51272e+07 4.08947e+06 5609.70 160.25 6.5954 5.6945 42817 18 10128 34970 3224301 629152 8.72434 8.72434 -10837.7 -8.72434 0 0 5.12776e+06 7033.96 1.15 1.02 0.473228 0.433429 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 16.26 0.34 32004 3 0.90 -1 -1 40236 -1 -1 111 214 0 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 94072 214 305 2963 2869 1 1440 638 19 19 361 io auto 2.17 11058 1.30 0.01 4.28804 -2547.99 -4.28804 4.28804 0.59 0.00347113 0.00307978 0.466541 0.400197 58 23745 38 1.72706e+07 9.15023e+06 1.32779e+06 3678.09 7.20 1.56228 1.37605 19546 16 5825 13540 3597927 808321 4.87643 4.87643 -2976.1 -4.87643 0 0 1.69263e+06 4688.74 0.30 0.67 0.195534 0.18203 - k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 254.32 0.74 37996 3 235.25 -1 -1 95040 -1 -1 156 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 93376 38 36 2995 2744 1 1210 230 17 17 289 clb auto 2.15 11099 1.21 0.01 8.60024 -2289.89 -8.60024 8.60024 0.57 0.00286613 0.00243424 0.504352 0.391189 66 16854 22 1.34605e+07 8.40746e+06 1.18400e+06 4096.89 8.69 2.16811 1.76894 15692 22 4746 12707 469422 81010 9.99242 9.99242 -2671.82 -9.99242 0 0 1.47169e+06 5092.36 0.25 0.32 0.237773 0.213212 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 11.39 0.16 21036 15 0.66 -1 -1 35172 -1 -1 65 45 3 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 77936 45 32 1275 1232 1 827 146 14 14 196 memory auto 2.13 6673 0.55 0.00 10.0822 -6325.59 -10.0822 10.0822 0.28 0.00163847 0.00137079 0.247235 0.201216 72 12424 18 9.20055e+06 5.54311e+06 844708. 4309.73 5.35 0.904368 0.764839 10987 13 3155 8576 1581981 414115 11.6443 11.6443 -7336.6 -11.6443 0 0 1.05868e+06 5401.43 0.16 0.33 0.107953 0.0999341 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 92.23 1.43 118520 5 9.32 -1 -1 71236 -1 -1 704 157 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 271852 157 197 23846 21799 1 6676 1058 33 33 1089 clb auto 7.46 39618 6.23 0.05 2.9308 -13224.6 -2.9308 2.9308 2.55 0.0167976 0.0139089 2.72218 2.05998 50 62630 23 6.0475e+07 3.79415e+07 3.66263e+06 3363.29 50.73 11.3202 9.09089 55668 12 16379 25575 918337 183454 3.69492 3.69492 -15705.8 -3.69492 0 0 4.71657e+06 4331.10 1.02 1.12 1.08857 0.993885 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 168.50 1.33 104660 3 43.29 -1 -1 84672 -1 -1 675 115 0 40 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 321752 115 145 23133 19546 1 9716 975 40 40 1600 mult_36 auto 7.65 81193 8.04 0.06 4.85074 -22294.2 -4.85074 4.85074 3.91 0.0200686 0.0147713 3.09128 2.32254 82 134682 37 9.16046e+07 5.22191e+07 8.58295e+06 5364.35 81.91 12.8131 10.3486 119058 16 33969 51744 22437603 4613086 5.29409 5.29409 -25657.1 -5.29409 0 0 1.07702e+07 6731.38 2.47 4.83 1.29502 1.15861 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 500.44 1.66 148876 3 7.04 -1 -1 202128 -1 -1 1653 149 0 324 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1611520 149 182 65737 42630 1 35961 2308 104 104 10816 mult_36 auto 25.24 329951 42.93 0.27 14.5498 -61941.6 -14.5498 14.5498 91.37 0.0708359 0.0629052 11.9827 9.79984 80 453123 49 6.67561e+08 2.17385e+08 5.94869e+07 5499.90 235.52 45.2121 38.3272 431667 19 116030 135785 30345597 6109739 15.9454 15.9454 -72300.2 -15.9454 0 0 7.49726e+07 6931.63 24.72 9.60 4.52948 4.02549 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.77 0.05 9804 5 0.09 -1 -1 33052 -1 -1 14 11 0 0 success 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