diff --git a/ODIN_II/verify_odin.sh b/ODIN_II/verify_odin.sh index 58a96590ebb..1218717f82f 100755 --- a/ODIN_II/verify_odin.sh +++ b/ODIN_II/verify_odin.sh @@ -1256,6 +1256,9 @@ function run_vtr_reg() { pushd "${VTR_DIR}" &> /dev/null RELATIVE_PATH_TO_TEST=$(realapath_from "${FILTERED_VTR_TASK_PATH}" "${VTR_REG_DIR}") /usr/bin/env perl run_reg_test.py -j "${_NUMBER_OF_PROCESS}" $(dirname ${RELATIVE_PATH_TO_TEST}) + if [ _"$?" != "_0" ]; then + _exit_with_code "-1" + fi popd &> /dev/null } diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md new file mode 100644 index 00000000000..071fab6640f --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md @@ -0,0 +1,4 @@ +##ODIN-II Regression + +`task_list.txt` in this directory points to a set of tasks in the same directory. These tasks are referred to in +[`light_suite`](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf) which is part of a series of ODIN-II regression tests. `light_suite` is currently being run by CI under the name`odin_reg_basic`. First, Odin specific tests are run then the task_list is run by `run_vtr_task.py`. Thus, the entirety of the flow is tested for `vtr_reg_multiclock` tasks by CI. diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md new file mode 100644 index 00000000000..3f781146cca --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md @@ -0,0 +1 @@ +The tasks inside this directory tests that VTR can correctly handle multi-clock designs in different ways. The default way to handle multiple clocks is iterative. \ No newline at end of file diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt new file mode 100644 index 00000000000..2df5055ca24 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt @@ -0,0 +1,4 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.26 0.01 6744 1 0.02 -1 -1 35528 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 351120 6 1 13 14 2 8 9 4 4 16 clb auto 0 13 0 0 0.875884 -3.21829 -0.875884 0.545 0.01 9.152E-06 6.411E-06 0.00127579 0.000834052 20 13 2 107788 107788 10441.3 652.579 0.02 0.00190451 0.00132149 13 11 27 27 298 166 1.17974 0.545 -3.80732 -1.17974 0 0 13748.8 859.301 0 0 0.000371941 0.000300732 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.37 0.02 7180 1 0.02 -1 -1 35560 -1 -1 2 3 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 351456 3 1 25 26 2 8 6 4 4 16 clb auto 0.01 16 0 0 0.571 -8.56916 -0.571 0.557849 0.01 2.6811E-05 1.912E-05 0.000267223 0.000232957 20 21 4 107788 107788 10441.3 652.579 0.02 0.00146154 0.00126639 14 2 7 7 87 53 0.639606 0.557849 -8.83917 -0.639606 0 0 13748.8 859.301 0 0 0.000657086 0.000610546 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.24 0.01 6708 1 0 -1 -1 33668 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 352744 6 2 10 12 2 8 10 4 4 16 clb auto 0 12 0 0 0.543757 -1.83465 -0.543757 nan 0.01 7.375E-06 4.815E-06 0.000820477 0.000473849 20 15 6 107788 107788 10441.3 652.579 0.02 0.00127841 0.000806185 12 3 10 10 126 76 0.641597 nan -2.12623 -0.641597 0 0 13748.8 859.301 0 0 0.000145432 0.000113509 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt new file mode 100644 index 00000000000..498257579ef --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt @@ -0,0 +1,4 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.32 0.01 6736 1 0.02 -1 -1 35432 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 350784 6 1 13 14 2 8 9 4 4 16 clb auto 0 13 0 0 0.875884 -3.21829 -0.875884 0.545 0.01 9.133E-06 6.332E-06 0.00137103 0.000893379 20 13 2 107788 107788 10441.3 652.579 0.02 0.00202846 0.00140832 13 11 27 27 298 166 1.17974 0.545 -3.80732 -1.17974 0 0 13748.8 859.301 0 0 0.000363437 0.000297087 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.44 0.02 7156 1 0.02 -1 -1 35752 -1 -1 2 3 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 353248 3 1 23 24 2 8 6 4 4 16 clb auto 0.01 16 0 0 0.571 -8.02416 -0.571 0.557849 0.01 2.6392E-05 1.8474E-05 0.000392837 0.000356428 20 21 4 107788 107788 10441.3 652.579 0.02 0.00161969 0.00141089 14 2 7 7 87 53 0.639606 0.557849 -8.29417 -0.639606 0 0 13748.8 859.301 0 0 0.000617072 0.000570262 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.29 0.01 6724 1 0.01 -1 -1 33208 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 347368 6 2 10 12 2 8 10 4 4 16 clb auto 0 12 0 0 0.543757 -1.83465 -0.543757 nan 0.01 9.515E-06 6.506E-06 0.000866896 0.000551504 20 16 8 107788 107788 10441.3 652.579 0.02 0.00144256 0.000972468 21 4 13 13 358 237 0.81248 nan -2.64176 -0.81248 0 0 13748.8 859.301 0 0 0.000169618 0.000131886 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt new file mode 100644 index 00000000000..75a9fb1493b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt @@ -0,0 +1,4 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.26 0.01 6816 1 0.02 -1 -1 35772 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 349496 6 1 13 14 2 8 9 4 4 16 clb auto 0 13 0 0 0.875884 -3.21829 -0.875884 0.545 0.01 9.091E-06 6.295E-06 0.00129808 0.000845104 20 13 2 107788 107788 10441.3 652.579 0.02 0.00198582 0.00138501 13 11 27 27 298 166 1.17974 0.545 -3.80732 -1.17974 0 0 13748.8 859.301 0 0 0.000358376 0.000292334 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.38 0.02 7200 1 0.02 -1 -1 35364 -1 -1 2 3 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 349496 3 1 25 26 2 8 6 4 4 16 clb auto 0.01 16 0 0 0.571 -8.56916 -0.571 0.557849 0.01 2.6353E-05 1.8731E-05 0.000276021 0.00024129 20 21 4 107788 107788 10441.3 652.579 0.02 0.00149985 0.00130224 14 2 7 7 87 53 0.639606 0.557849 -8.83917 -0.639606 0 0 13748.8 859.301 0 0 0.000678691 0.000630364 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.28 0.01 6604 1 0.01 -1 -1 33600 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 352016 6 2 10 12 2 8 10 4 4 16 clb auto 0 12 0 0 0.543757 -1.83465 -0.543757 nan 0.01 1.3298E-05 9.555E-06 0.00112792 0.000716874 20 15 6 107788 107788 10441.3 652.579 0.02 0.00174703 0.00117687 12 3 10 10 126 76 0.641597 nan -2.12623 -0.641597 0 0 13748.8 859.301 0 0 0.00014824 0.000115483 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt new file mode 100644 index 00000000000..69e7acca37f --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt @@ -0,0 +1,4 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.31 0.01 6784 1 0.02 -1 -1 35732 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 350952 6 1 13 14 2 8 9 4 4 16 clb auto 0 13 0 0 0.875884 -3.21829 -0.875884 0.545 0.01 9.095E-06 6.307E-06 0.00129288 0.000842011 20 13 2 107788 107788 10441.3 652.579 0.02 0.00191938 0.00132537 13 11 27 27 298 166 1.17974 0.545 -3.80732 -1.17974 0 0 13748.8 859.301 0 0 0.000353606 0.000288916 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.44 0.02 7184 1 0.02 -1 -1 35612 -1 -1 2 3 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 350112 3 1 23 24 2 8 6 4 4 16 clb auto 0.01 16 0 0 0.571 -8.02416 -0.571 0.557849 0.01 2.6001E-05 1.8594E-05 0.000265426 0.000230778 20 21 4 107788 107788 10441.3 652.579 0.02 0.00142645 0.00123292 14 2 7 7 87 53 0.639606 0.557849 -8.29417 -0.639606 0 0 13748.8 859.301 0 0 0.000632038 0.000584601 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.28 0.01 6560 1 0.01 -1 -1 33160 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 351176 6 2 10 12 2 8 10 4 4 16 clb auto 0 12 0 0 0.543757 -1.83465 -0.543757 nan 0.01 7.409E-06 4.867E-06 0.000791344 0.000475707 20 16 8 107788 107788 10441.3 652.579 0.02 0.00133053 0.000866155 21 4 13 13 358 237 0.81248 nan -2.64176 -0.81248 0 0 13748.8 859.301 0 0 0.000176087 0.000137856 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt index 00ba1689b32..4703a730ff6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt @@ -1,4 +1,4 @@ -regression_tests/vtr_reg_nightly_basic/func_multiclock/blanket -regression_tests/vtr_reg_nightly_basic/func_multiclock/iterative -regression_tests/vtr_reg_nightly_basic/func_multiclock/once -regression_tests/vtr_reg_nightly_basic/func_multiclock/vanilla +regression_tests/vtr_reg_multiclock/func_multiclock/blanket +regression_tests/vtr_reg_multiclock/func_multiclock/iterative +regression_tests/vtr_reg_multiclock/func_multiclock/once +regression_tests/vtr_reg_multiclock/func_multiclock/vanilla diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt index 0074292af29..26619b3c436 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt @@ -1,6 +1,7 @@ #Refer to Issue #1770 for details. #regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees +regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/config.txt old mode 100755 new mode 100644 similarity index 87% rename from vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/config.txt index c1e990a3ef5..981a44d52b9 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/config.txt @@ -3,6 +3,9 @@ # Configuration file for running experiments ############################################## +#This task checks for logical equivalency of a netlist before and after VPR using ABC. It performs a formal equivalence check but tests the same +#benchmarks as vtr_reg_mcnc. + # Path to directory of circuits to use circuits_dir=benchmarks/blif/wiremap6 @@ -41,6 +44,8 @@ parse_file=vpr_standard.txt # Pass requirements pass_requirements_file=pass_requirements.txt -# +# How to parse QoR info +qor_parse_file=qor_standard.txt + script_params=-starting_stage vpr --gen_post_synthesis_netlist on -check_equivalent --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --absorb_buffer_luts off diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt deleted file mode 100644 index 4efcb0259c7..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt +++ /dev/null @@ -1,4 +0,0 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.26 0.01 6744 1 0.02 -1 -1 35528 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25080 6 1 13 14 2 8 9 4 4 16 clb auto 0.00 13 0.00 0.00 0.875884 -3.21829 -0.875884 0.545 0.01 9.152e-06 6.411e-06 0.00127579 0.000834052 20 13 2 107788 107788 10441.3 652.579 0.02 0.00190451 0.00132149 13 11 27 27 298 166 1.17974 0.545 -3.80732 -1.17974 0 0 13748.8 859.301 0.00 0.00 0.000371941 0.000300732 - k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.37 0.02 7180 1 0.02 -1 -1 35560 -1 -1 2 3 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25104 3 1 25 26 2 8 6 4 4 16 clb auto 0.01 16 0.00 0.00 0.571 -8.56916 -0.571 0.557849 0.01 2.6811e-05 1.912e-05 0.000267223 0.000232957 20 21 4 107788 107788 10441.3 652.579 0.02 0.00146154 0.00126639 14 2 7 7 87 53 0.639606 0.557849 -8.83917 -0.639606 0 0 13748.8 859.301 0.00 0.00 0.000657086 0.000610546 - k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.24 0.01 6708 1 0.00 -1 -1 33668 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25196 6 2 10 12 2 8 10 4 4 16 clb auto 0.00 12 0.00 0.00 0.543757 -1.83465 -0.543757 nan 0.01 7.375e-06 4.815e-06 0.000820477 0.000473849 20 15 6 107788 107788 10441.3 652.579 0.02 0.00127841 0.000806185 12 3 10 10 126 76 0.641597 nan -2.12623 -0.641597 0 0 13748.8 859.301 0.00 0.00 0.000145432 0.000113509 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt deleted file mode 100644 index 83505a3b7b2..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt +++ /dev/null @@ -1,4 +0,0 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.32 0.01 6736 1 0.02 -1 -1 35432 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25056 6 1 13 14 2 8 9 4 4 16 clb auto 0.00 13 0.00 0.00 0.875884 -3.21829 -0.875884 0.545 0.01 9.133e-06 6.332e-06 0.00137103 0.000893379 20 13 2 107788 107788 10441.3 652.579 0.02 0.00202846 0.00140832 13 11 27 27 298 166 1.17974 0.545 -3.80732 -1.17974 0 0 13748.8 859.301 0.00 0.00 0.000363437 0.000297087 - k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.44 0.02 7156 1 0.02 -1 -1 35752 -1 -1 2 3 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25232 3 1 23 24 2 8 6 4 4 16 clb auto 0.01 16 0.00 0.00 0.571 -8.02416 -0.571 0.557849 0.01 2.6392e-05 1.8474e-05 0.000392837 0.000356428 20 21 4 107788 107788 10441.3 652.579 0.02 0.00161969 0.00141089 14 2 7 7 87 53 0.639606 0.557849 -8.29417 -0.639606 0 0 13748.8 859.301 0.00 0.00 0.000617072 0.000570262 - k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.29 0.01 6724 1 0.01 -1 -1 33208 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 24812 6 2 10 12 2 8 10 4 4 16 clb auto 0.00 12 0.00 0.00 0.543757 -1.83465 -0.543757 nan 0.01 9.515e-06 6.506e-06 0.000866896 0.000551504 20 16 8 107788 107788 10441.3 652.579 0.02 0.00144256 0.000972468 21 4 13 13 358 237 0.81248 nan -2.64176 -0.81248 0 0 13748.8 859.301 0.00 0.00 0.000169618 0.000131886 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh deleted file mode 100755 index 454c7ccc7a1..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/bash - -RUN_SCRIPT='/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/scripts/run_vtr_task.py' -PARSE_SCRIPT='/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py' -check='0' -for top_dir in *;do - if [ -d "$top_dir" ]; then - echo "outer dir: $top_dir" - for inner_dir in $top_dir/*;do - if grep -q "config" <<< "$inner_dir";then - check=1 - break - fi - if grep -q "table_X" <<< "$inner_dir";then - check=1 - continue - fi - echo "$inner_dir" >>~/Desktop/timing_results1.txt - (time $RUN_SCRIPT $inner_dir) >>~/Desktop/run-results_test.txt 2>>~/Desktop/timing_results1_test.txt - - done - echo "$outer_dir" - if [[ "$check" == "1" ]]; then - echo "$top_dir" >>~/Desktop/timing_results1_test.txt - (time $RUN_SCRIPT $top_dir) >>~/Desktop/run-results_test.txt 2>>~/Desktop/timing_results1_test.txt - - fi - fi -done diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt deleted file mode 100644 index 74d14be1967..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt +++ /dev/null @@ -1,4 +0,0 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.26 0.01 6816 1 0.02 -1 -1 35772 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 24964 6 1 13 14 2 8 9 4 4 16 clb auto 0.00 13 0.00 0.00 0.875884 -3.21829 -0.875884 0.545 0.01 9.091e-06 6.295e-06 0.00129808 0.000845104 20 13 2 107788 107788 10441.3 652.579 0.02 0.00198582 0.00138501 13 11 27 27 298 166 1.17974 0.545 -3.80732 -1.17974 0 0 13748.8 859.301 0.00 0.00 0.000358376 0.000292334 - k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.38 0.02 7200 1 0.02 -1 -1 35364 -1 -1 2 3 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 24964 3 1 25 26 2 8 6 4 4 16 clb auto 0.01 16 0.00 0.00 0.571 -8.56916 -0.571 0.557849 0.01 2.6353e-05 1.8731e-05 0.000276021 0.00024129 20 21 4 107788 107788 10441.3 652.579 0.02 0.00149985 0.00130224 14 2 7 7 87 53 0.639606 0.557849 -8.83917 -0.639606 0 0 13748.8 859.301 0.00 0.00 0.000678691 0.000630364 - k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.28 0.01 6604 1 0.01 -1 -1 33600 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25144 6 2 10 12 2 8 10 4 4 16 clb auto 0.00 12 0.00 0.00 0.543757 -1.83465 -0.543757 nan 0.01 1.3298e-05 9.555e-06 0.00112792 0.000716874 20 15 6 107788 107788 10441.3 652.579 0.02 0.00174703 0.00117687 12 3 10 10 126 76 0.641597 nan -2.12623 -0.641597 0 0 13748.8 859.301 0.00 0.00 0.00014824 0.000115483 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt deleted file mode 100644 index 2d5b413c43a..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt +++ /dev/null @@ -1,4 +0,0 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.31 0.01 6784 1 0.02 -1 -1 35732 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25068 6 1 13 14 2 8 9 4 4 16 clb auto 0.00 13 0.00 0.00 0.875884 -3.21829 -0.875884 0.545 0.01 9.095e-06 6.307e-06 0.00129288 0.000842011 20 13 2 107788 107788 10441.3 652.579 0.02 0.00191938 0.00132537 13 11 27 27 298 166 1.17974 0.545 -3.80732 -1.17974 0 0 13748.8 859.301 0.00 0.00 0.000353606 0.000288916 - k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.44 0.02 7184 1 0.02 -1 -1 35612 -1 -1 2 3 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25008 3 1 23 24 2 8 6 4 4 16 clb auto 0.01 16 0.00 0.00 0.571 -8.02416 -0.571 0.557849 0.01 2.6001e-05 1.8594e-05 0.000265426 0.000230778 20 21 4 107788 107788 10441.3 652.579 0.02 0.00142645 0.00123292 14 2 7 7 87 53 0.639606 0.557849 -8.29417 -0.639606 0 0 13748.8 859.301 0.00 0.00 0.000632038 0.000584601 - k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.28 0.01 6560 1 0.01 -1 -1 33160 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25084 6 2 10 12 2 8 10 4 4 16 clb auto 0.00 12 0.00 0.00 0.543757 -1.83465 -0.543757 nan 0.01 7.409e-06 4.867e-06 0.000791344 0.000475707 20 16 8 107788 107788 10441.3 652.579 0.02 0.00133053 0.000866155 21 4 13 13 358 237 0.81248 nan -2.64176 -0.81248 0 0 13748.8 859.301 0.00 0.00 0.000176087 0.000137856 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt index 2a63a31ba2b..789b65077a5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt @@ -8,7 +8,8 @@ regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan -regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc +regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc regression_tests/vtr_reg_nightly_test2/titan_other regression_tests/vtr_reg_nightly_test2/titan_quick_qor + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/config.txt new file mode 100644 index 00000000000..69aed97be2a --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/config.txt @@ -0,0 +1,49 @@ +############################################## +# Configuration file for running experiments # +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +# Single-clock +circuit_list_add=bigkey.blif +circuit_list_add=clma.blif +circuit_list_add=diffeq.blif +circuit_list_add=dsip.blif +circuit_list_add=elliptic.blif +circuit_list_add=frisc.blif +circuit_list_add=s298.blif +circuit_list_add=s38417.blif +circuit_list_add=s38584.1.blif +circuit_list_add=tseng.blif + +# Combinational +#circuit_list_add=alu4.blif +#circuit_list_add=apex2.blif +#circuit_list_add=apex4.blif +#circuit_list_add=des.blif +#circuit_list_add=ex1010.blif +#circuit_list_add=ex5p.blif +#circuit_list_add=misex3.blif +#circuit_list_add=pdc.blif +#circuit_list_add=seq.blif +#circuit_list_add=spla.blif + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Script parameters +script_params=-starting_stage abc \ No newline at end of file diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt new file mode 100644 index 00000000000..dabe58c85d0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt @@ -0,0 +1,11 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml bigkey.blif common 5.28 -1 -1 3 0.34 -1 -1 35056 -1 -1 53 229 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 46028 229 197 1023 1220 1 510 479 16 16 256 io auto 0.21 3413 0.56 0.00 2.1735 -526.299 -2.1735 2.1735 0.39 0.00138821 0.00120378 0.19781 0.168309 40 6116 17 1.05632e+07 2.85638e+06 697968. 2726.44 2.40 0.722292 0.640772 5568 9 1309 2279 135603 31763 2.49868 2.49868 -621.799 -2.49868 0 0 870840. 3401.72 0.16 0.07 0.0510449 0.0478126 +k6_frac_N10_40nm.xml clma.blif common 5.08 -1 -1 7 2.05 -1 -1 39340 -1 -1 77 36 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 32676 36 82 542 624 1 390 195 11 11 121 clb auto 0.35 2039 0.33 0.00 4.11584 -147.948 -4.11584 4.11584 0.15 0.000539492 0.000452693 0.106625 0.0857617 40 4434 24 4.36541e+06 4.14984e+06 303235. 2506.08 1.15 0.303278 0.252285 3724 17 2001 6967 214647 45904 4.75061 4.75061 -182.205 -4.75061 0 0 379421. 3135.71 0.06 0.06 0.0359416 0.0326671 +k6_frac_N10_40nm.xml diffeq.blif common 3.20 -1 -1 8 0.40 -1 -1 34060 -1 -1 51 64 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 34940 64 39 941 980 1 450 154 10 10 100 clb auto 0.42 2664 0.24 0.00 4.29897 -783.884 -4.29897 4.29897 0.12 0.000839617 0.000669735 0.100486 0.0795009 46 5017 28 3.44922e+06 2.74859e+06 276332. 2763.32 1.05 0.326802 0.269909 4217 16 1848 5381 166684 35585 4.95374 4.95374 -932.485 -4.95374 0 0 354105. 3541.05 0.05 0.08 0.0542635 0.0494947 +k6_frac_N10_40nm.xml dsip.blif common 6.16 -1 -1 3 0.30 -1 -1 34940 -1 -1 68 229 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 47348 229 197 1135 1332 1 648 494 16 16 256 io auto 0.53 4829 0.66 0.01 2.11998 -540.899 -2.11998 2.11998 0.39 0.0015698 0.00130015 0.210921 0.176933 36 9346 20 1.05632e+07 3.66479e+06 638738. 2495.07 2.79 0.723593 0.631411 8188 14 2350 5770 322638 68924 2.64997 2.64997 -662.41 -2.64997 0 0 786978. 3074.13 0.15 0.12 0.076965 0.0713829 +k6_frac_N10_40nm.xml elliptic.blif common 10.48 -1 -1 10 1.16 -1 -1 37272 -1 -1 133 131 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 56752 131 114 2471 2585 1 967 378 14 14 196 clb auto 1.84 9009 0.83 0.01 6.26362 -3059.17 -6.26362 6.26362 0.28 0.00212795 0.00173305 0.286733 0.219064 64 15845 47 7.76074e+06 7.1679e+06 810706. 4136.26 4.27 1.22946 1.00099 14220 16 4723 20791 818717 140043 7.05815 7.05815 -3531.55 -7.05815 0 0 1.00880e+06 5146.95 0.16 0.27 0.154401 0.13779 +k6_frac_N10_40nm.xml frisc.blif common 13.84 -1 -1 12 1.91 -1 -1 37256 -1 -1 153 20 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62524 20 116 2477 2593 1 1097 289 15 15 225 clb auto 2.14 12755 0.94 0.01 6.79269 -3257.02 -6.79269 6.79269 0.34 0.00217438 0.00179657 0.327538 0.24583 76 21374 38 9.10809e+06 8.24578e+06 1.08042e+06 4801.85 6.09 1.27911 1.034 19100 16 5620 24310 1037891 171913 8.29693 8.29693 -3979.77 -8.29693 0 0 1.34805e+06 5991.31 0.22 0.35 0.179872 0.160752 +k6_frac_N10_40nm.xml s298.blif common 3.83 -1 -1 8 0.53 -1 -1 34316 -1 -1 62 4 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 34504 4 6 671 677 1 352 72 10 10 100 clb auto 0.56 3591 0.22 0.00 4.75477 -39.1418 -4.75477 4.75477 0.12 0.000769266 0.000586248 0.09084 0.0707559 52 5575 27 3.44922e+06 3.34143e+06 305142. 3051.42 1.47 0.36114 0.295188 5399 17 2374 11722 416659 74881 5.56322 5.56322 -46.7971 -5.56322 0 0 401807. 4018.07 0.06 0.11 0.0543908 0.049368 +k6_frac_N10_40nm.xml s38417.blif common 12.03 -1 -1 6 2.75 -1 -1 42360 -1 -1 177 29 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63792 29 106 3450 3556 1 1202 312 16 16 256 clb auto 1.56 8615 1.15 0.01 3.98518 -2557.22 -3.98518 3.98518 0.39 0.00302166 0.00218012 0.456703 0.332458 46 14847 24 1.05632e+07 9.53924e+06 786978. 3074.13 3.52 1.37805 1.08296 13205 15 5027 16599 520957 107073 4.83175 4.83175 -2954.7 -4.83175 0 0 1.01084e+06 3948.58 0.17 0.30 0.238471 0.215337 +k6_frac_N10_40nm.xml s38584.1.blif common 12.46 -1 -1 6 2.08 -1 -1 40804 -1 -1 194 38 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66920 38 304 3256 3560 1 1587 536 16 16 256 clb auto 1.98 10122 1.65 0.01 3.64177 -2138.5 -3.64177 3.64177 0.40 0.00317473 0.00262755 0.578661 0.434442 58 18006 25 1.05632e+07 1.04554e+07 977637. 3818.90 3.81 1.57474 1.25106 15785 16 5100 13564 505628 106920 4.7203 4.7203 -2481.9 -4.7203 0 0 1.24374e+06 4858.37 0.21 0.26 0.211794 0.191547 +k6_frac_N10_40nm.xml tseng.blif common 2.48 -1 -1 7 0.23 -1 -1 34700 -1 -1 34 52 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 31260 52 122 664 786 1 355 208 8 8 64 io clb auto 0.41 1686 0.21 0.00 3.70214 -536.987 -3.70214 3.70214 0.07 0.000641877 0.000544632 0.0739312 0.060713 58 3324 47 1.94018e+06 1.8324e+06 203254. 3175.84 0.73 0.26935 0.22784 2902 11 1075 2671 103928 28289 4.55633 4.55633 -641.099 -4.55633 0 0 258247. 4035.11 0.04 0.07 0.046514 0.0424413