From d873c64bf5de545aec9ad593718a48e3d74350e9 Mon Sep 17 00:00:00 2001 From: Seyed Alireza Damghani Date: Fri, 11 Jun 2021 12:08:55 -0300 Subject: [PATCH 1/3] [Infra]: Adding include_list_add and include_dir (both optional) to task config file Signed-off-by: Seyed Alireza Damghani --- vtr_flow/scripts/python_libs/vtr/flow.py | 12 ++- vtr_flow/scripts/python_libs/vtr/odin/odin.py | 81 ++++++++++++++++--- vtr_flow/scripts/python_libs/vtr/task.py | 45 +++++++++++ vtr_flow/scripts/run_vtr_flow.py | 13 ++- 4 files changed, 138 insertions(+), 13 deletions(-) diff --git a/vtr_flow/scripts/python_libs/vtr/flow.py b/vtr_flow/scripts/python_libs/vtr/flow.py index 9a62e1334cd..cf660548d4f 100644 --- a/vtr_flow/scripts/python_libs/vtr/flow.py +++ b/vtr_flow/scripts/python_libs/vtr/flow.py @@ -34,6 +34,7 @@ def run( architecture_file, circuit_file, power_tech_file=None, + include_files=None, start_stage=VtrStage.ODIN, end_stage=VtrStage.VPR, command_runner=vtr.CommandRunner(), @@ -134,7 +135,6 @@ def run( vpr_args = OrderedDict() if not vpr_args else vpr_args odin_args = OrderedDict() if not odin_args else odin_args abc_args = OrderedDict() if not abc_args else abc_args - # Verify that files are Paths or convert them to Paths and check that they exist architecture_file = vtr.util.verify_file(architecture_file, "Architecture") circuit_file = vtr.util.verify_file(circuit_file, "Circuit") @@ -167,6 +167,15 @@ def run( shutil.copy(str(circuit_file), str(circuit_copy)) shutil.copy(str(architecture_file), str(architecture_copy)) + # Check whether any inclulde is specified + if include_files: + # Verify include files are Paths or convert them to Path + check that they exist + # Copy include files to the run directory + for include in include_files: + include_file = vtr.util.verify_file(include, "Circuit") + include_copy = temp_dir / include_file.name + shutil.copy(str(include), str(include_copy)) + # There are multiple potential paths for the netlist to reach a tool # We initialize it here to the user specified circuit and let downstream # stages update it @@ -179,6 +188,7 @@ def run( vtr.odin.run( architecture_copy, next_stage_netlist, + include_files, output_netlist=post_odin_netlist, command_runner=command_runner, temp_dir=temp_dir, diff --git a/vtr_flow/scripts/python_libs/vtr/odin/odin.py b/vtr_flow/scripts/python_libs/vtr/odin/odin.py index 68677497bf4..91e2f5fe1c8 100644 --- a/vtr_flow/scripts/python_libs/vtr/odin/odin.py +++ b/vtr_flow/scripts/python_libs/vtr/odin/odin.py @@ -4,13 +4,72 @@ import shutil from collections import OrderedDict from pathlib import Path +import xml.etree.ElementTree as ET from vtr import file_replace, determine_memory_addr_width, verify_file, CommandRunner, paths +def create_circuits_list(main_circuit, include_files): + """Create a list of all (.v) and (.vh) files""" + circuit_list = [] + # Check include files exist + if include_files: + # Verify that files are Paths or convert them to Paths + check that they exist + for include in include_files: + include_file = verify_file(include, "Circuit") + circuit_list.append(include_file.name) + + # Append the main circuit design as the last one + circuit_list.append(main_circuit.name) + + return circuit_list + + +# pylint: disable=too-many-arguments, too-many-locals +def init_config_file( + odin_config_full_path, + circuit_list, + architecture_file, + output_netlist, + memory_addr_width, + min_hard_mult_size, + min_hard_adder_size, +): + + """initializing the raw odin config file""" + # Update the config file + file_replace( + odin_config_full_path, + { + "YYY": architecture_file, + "ZZZ": output_netlist, + "PPP": memory_addr_width, + "MMM": min_hard_mult_size, + "AAA": min_hard_adder_size, + }, + ) + + # loading the given config file + config_file = ET.parse(odin_config_full_path) + root = config_file.getroot() + + # based on the base condfig file + verilog_files_tag = root.find("verilog_files") + # remove the template line XXX, verilog_files_tag [0] is a comment + verilog_files_tag.remove(verilog_files_tag[0]) + for circuit in circuit_list: + verilog_file = ET.SubElement(verilog_files_tag, "verilog_file") + verilog_file.tail = "\n\n\t" if (circuit == circuit_list[-1]) else "\n\n\t\t" + verilog_file.text = circuit + + # update the config file with new values + config_file.write(odin_config_full_path) + + # pylint: disable=too-many-arguments, too-many-locals def run( architecture_file, circuit_file, + include_files, output_netlist, command_runner=CommandRunner(), temp_dir=Path("."), @@ -90,17 +149,17 @@ def run( odin_config_full_path = str(temp_dir / odin_config) shutil.copyfile(odin_base_config, odin_config_full_path) - # Update the config file - file_replace( + # Create a list showing all (.v) and (.vh) files + circuit_list = create_circuits_list(circuit_file, include_files) + + init_config_file( odin_config_full_path, - { - "XXX": circuit_file.name, - "YYY": architecture_file.name, - "ZZZ": output_netlist.name, - "PPP": determine_memory_addr_width(str(architecture_file)), - "MMM": min_hard_mult_size, - "AAA": min_hard_adder_size, - }, + circuit_list, + architecture_file.name, + output_netlist.name, + determine_memory_addr_width(str(architecture_file)), + min_hard_mult_size, + min_hard_adder_size, ) cmd = [odin_exec] @@ -126,7 +185,7 @@ def run( "-a", architecture_file.name, "-V", - circuit_file.name, + circuit_list, "-o", output_netlist.name, ] diff --git a/vtr_flow/scripts/python_libs/vtr/task.py b/vtr_flow/scripts/python_libs/vtr/task.py index 33c9d4ab41a..0927f886f98 100644 --- a/vtr_flow/scripts/python_libs/vtr/task.py +++ b/vtr_flow/scripts/python_libs/vtr/task.py @@ -33,6 +33,8 @@ def __init__( circuit_list_add, arch_list_add, parse_file, + includes_dir=None, + include_list_add=None, second_parse_file=None, script_path=None, script_params=None, @@ -53,6 +55,8 @@ def __init__( self.arch_dir = archs_dir self.circuits = circuit_list_add self.archs = arch_list_add + self.include_dir = includes_dir + self.includes = include_list_add self.parse_file = parse_file self.second_parse_file = second_parse_file self.script_path = script_path @@ -82,6 +86,7 @@ def __init__( task_name, arch, circuit, + include, script_params, work_dir, run_command, @@ -92,6 +97,7 @@ def __init__( self._task_name = task_name self._arch = arch self._circuit = circuit + self._include = include self._script_params = script_params self._run_command = run_command self._parse_command = parse_command @@ -117,6 +123,12 @@ def circuit(self): """ return self._circuit + def include(self): + """ + return the list of include files (.v/.vh) of the job. + """ + return self._include + def script_params(self): """ return the script parameter of the job @@ -174,6 +186,7 @@ def load_task_config(config_file): unique_keys = set( [ "circuits_dir", + "includes_dir", "archs_dir", "additional_files", "parse_file", @@ -238,6 +251,7 @@ def load_task_config(config_file): key_values["script_params_common"] = split(key_values["script_params_common"]) check_required_fields(config_file, required_keys, key_values) + check_include_fields(config_file, key_values) # Useful meta-data about the config config_dir = str(Path(config_file).parent) @@ -261,6 +275,20 @@ def check_required_fields(config_file, required_keys, key_values): ) +def check_include_fields(config_file, key_values): + """ + Check that includes_dir was specified if some files to include + in the designs (include_list_add) was specified. + """ + if "include_list_add" in key_values: + if "includes_dir" not in key_values: + raise VtrError( + "Missing required key '{key}' in config file {file}".format( + key="includes_dir", file=config_file + ) + ) + + def shorten_task_names(configs, common_task_prefix): """ Shorten the task names of the configs by remove the common task prefix. @@ -316,6 +344,19 @@ def create_jobs(args, configs, after_run=False): # Collect any extra script params from the config file cmd = [abs_circuit_filepath, abs_arch_filepath] + # Resolve and collect all include paths in the config file + # as -include ["include1", "include2", ..] + includes = [] + if config.includes: + cmd += ["-include"] + for include in config.includes: + abs_include_filepath = resolve_vtr_source_file( + config, include, config.include_dir + ) + includes.append(abs_include_filepath) + + cmd += includes + # Check if additional architectural data files are present if config.additional_files_list_add: for additional_file in config.additional_files_list_add: @@ -401,6 +442,7 @@ def create_jobs(args, configs, after_run=False): args, config, circuit, + includes, arch, value, cmd, @@ -418,6 +460,7 @@ def create_jobs(args, configs, after_run=False): args, config, circuit, + includes, arch, None, cmd, @@ -437,6 +480,7 @@ def create_job( args, config, circuit, + include, arch, param, cmd, @@ -501,6 +545,7 @@ def create_job( config.task_name, arch, circuit, + include, param_string, work_dir + "/" + param_string, current_cmd, diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py index 13b1346caed..34588f86c94 100755 --- a/vtr_flow/scripts/run_vtr_flow.py +++ b/vtr_flow/scripts/run_vtr_flow.py @@ -42,7 +42,7 @@ def __call__(self, parser, namespace, value, option_string=None): # pylint: enable=too-few-public-methods - +# pylint: disable=too-many-statements def vtr_command_argparser(prog=None): """ The VTR command arg parser @@ -322,6 +322,13 @@ def vtr_command_argparser(prog=None): dest="odin_config", help="Supplies Odin with a custom config file for optimizations.", ) + odin.add_argument( + "-include", + nargs="*", + default=None, + dest="include_list_file", + help="List of include files to a benchmark circuit(pass to Odin as a benchmark design set)", + ) # # VPR arguments # @@ -382,6 +389,9 @@ def vtr_command_argparser(prog=None): return parser +# pylint: enable=too-many-statements + + def vtr_command_main(arg_list, prog=None): """ Running VTR with the specified arguemnts. @@ -423,6 +433,7 @@ def vtr_command_main(arg_list, prog=None): Path(args.architecture_file), Path(args.circuit_file), power_tech_file=args.power_tech, + include_files=args.include_list_file, temp_dir=temp_dir, start_stage=args.start, end_stage=args.end, From 77acc8dc0b88f859b1de0080dc49e9a7a5a54723 Mon Sep 17 00:00:00 2001 From: Seyed Alireza Damghani Date: Fri, 11 Jun 2021 12:09:29 -0300 Subject: [PATCH 2/3] [Infra]: - Adding a new benchmark, hdl_include, splitting the ch_intrinsic into multiple files - Adding hdl_include to vtr_reg_basic, to validate the include capability for tasks config file Signed-off-by: Seyed Alireza Damghani --- .../hdl_include/ch_intrinsics_modified.v | 231 ++++++++++++++++++ .../benchmarks/hdl_include/include/README.md | 44 ++++ .../include/generic_definitions1.vh | 7 + .../include/generic_definitions2.vh | 8 + .../hdl_include/include/memory_controller.v | 64 +++++ .../hdl_include/config/config.txt | 40 +++ .../vtr_reg_basic/task_list.txt | 1 + 7 files changed, 395 insertions(+) create mode 100755 vtr_flow/benchmarks/hdl_include/ch_intrinsics_modified.v create mode 100755 vtr_flow/benchmarks/hdl_include/include/README.md create mode 100755 vtr_flow/benchmarks/hdl_include/include/generic_definitions1.vh create mode 100755 vtr_flow/benchmarks/hdl_include/include/generic_definitions2.vh create mode 100755 vtr_flow/benchmarks/hdl_include/include/memory_controller.v create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt diff --git a/vtr_flow/benchmarks/hdl_include/ch_intrinsics_modified.v b/vtr_flow/benchmarks/hdl_include/ch_intrinsics_modified.v new file mode 100755 index 00000000000..39b0ff93554 --- /dev/null +++ b/vtr_flow/benchmarks/hdl_include/ch_intrinsics_modified.v @@ -0,0 +1,231 @@ +/* + * Modified ch_intrinsic.v relies on definitons provided in header + * files and a sub module, memeory_controller located at: + * vtr_flow/benchmark/hdl_include/include/generic_definitions1.vh + * vtr_flow/benchmark/hdl_include/include/generic_definitions2.vh + * vtr_flow/benchmark/hdl_include/include/memory_controller.v + * + * This test is modified to allow testing of run_vtr_task capability to + * include additional files in a benchmark +*/ + +module memset + ( + clk, + reset, + start, + finish, + return_val, + m, + c, + n, + memory_controller_write_enable, + memory_controller_address, + memory_controller_in, + memory_controller_out + ); + +output[`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val; +input clk; +input reset; +input start; + +output finish; +reg finish; + +input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] m; +input [31:0] c; +input [31:0] n; + +output [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; + +output memory_controller_write_enable; +reg memory_controller_write_enable; + +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; +reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; + +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; + +reg [3:0] cur_state; + +/* +parameter Wait = 4'd0; +parameter entry = 4'd1; +parameter entry_1 = 4'd2; +parameter entry_2 = 4'd3; +parameter bb = 4'd4; +parameter bb_1 = 4'd5; +parameter bb1 = 4'd6; +parameter bb1_1 = 4'd7; +parameter bb_nph = 4'd8; +parameter bb2 = 4'd9; +parameter bb2_1 = 4'd10; +parameter bb2_2 = 4'd11; +parameter bb2_3 = 4'd12; +parameter bb2_4 = 4'd13; +parameter bb4 = 4'd14; +*/ + +memory_controller memtroll (clk,memory_controller_address, memory_controller_write_enable, memory_controller_in, memory_controller_out); + + +reg [31:0] indvar; +reg var1; +reg [31:0] tmp; +reg [31:0] tmp8; +reg var2; +reg [31:0] var0; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07; +reg [31:0] indvar_next; +reg exitcond; + +always @(posedge clk) +if (reset) + cur_state <= 4'b0000; +else +case(cur_state) + 4'b0000: + begin + finish <= 1'b0; + if (start == 1'b1) + cur_state <= 4'b0001; + else + cur_state <= 4'b0000; + end + 4'b0001: + begin + + + + var0 <= n & 32'b00000000000000000000000000000011; + + cur_state <= 4'b0010; + end + 4'b0010: + begin + + var1 <= 1'b0; + var0 <= 32'b00000000000000000000000000000000; + + cur_state <= 4'b0011; + end + 4'b0011: + begin + + + if (|var1) begin + cur_state <= 4'b0110; + end + else + begin + + cur_state <= 4'b0100; + end + end + 4'b0100: + begin + + cur_state <= 4'b0101; + end + 4'b0101: + begin + cur_state <= 4'b0110; + end + 4'b0110: + begin + + var2 <= | (n [31:4]); + + cur_state <= 4'b0111; + end + 4'b0111: + begin + + if (|var2) + begin + cur_state <= 4'b1110; + end + else + begin + cur_state <= 4'b1000; + end + end + 4'b1000: + begin + + tmp <= n ; + + indvar <= 32'b00000000000000000000000000000000; + cur_state <= 4'b1001; + end + 4'b1001: + begin + + cur_state <= 4'b1010; + end + 4'b1010: + begin + tmp8 <= indvar; + indvar_next <= indvar; + cur_state <= 4'b1011; + end + 4'b1011: + begin + + scevgep <= (m & tmp8); + + exitcond <= (indvar_next == tmp); + + cur_state <= 4'b1100; + end + 4'b1100: + begin + + s_07 <= scevgep; + + cur_state <= 4'b1101; + end + 4'b1101: + + begin + + + if (exitcond) + begin + cur_state <= 4'b1110; + end + else + begin + indvar <= indvar_next; + cur_state <= 4'b1001; + end + end + + + 4'b1110: + begin + + return_val <= m; + finish <= 1'b1; + cur_state <= 4'b0000; + end +endcase + +always @(cur_state) +begin + + case(cur_state) + 4'b1101: + begin + memory_controller_address = s_07; + memory_controller_write_enable = 1'b1; + memory_controller_in = c; + end + endcase +end + +endmodule diff --git a/vtr_flow/benchmarks/hdl_include/include/README.md b/vtr_flow/benchmarks/hdl_include/include/README.md new file mode 100755 index 00000000000..4685e5effea --- /dev/null +++ b/vtr_flow/benchmarks/hdl_include/include/README.md @@ -0,0 +1,44 @@ +# include files + +This folder contains _include_ files for running the modified version of ch_intrisinc. + +_include_ files can be either a Verilog file or a Verilog header file. The main point worth mentioning is that the union of include files and the circuit design includes the top module should not result in any conflict like having multiple top modules or declaring different variables with the same name. + +To create a task config file, the syntax for _include_ files is pretty much like the circuits or architectures. +In the beginning, _includes_dir_, a path to _include_ files should be specified. In the following, specifiers include_add_list adds specific _include_ files, using a relative path that will be pre-pended by the _includes_dir_ path. +If config.txt file lists multiple benchmark circuits and multiple include files, all include files will be considered (unioned into) each circuit design. In other words, _include_ files are shared among given benchmark circuits. + +___________________________hdl_include task config file____________________________ +############################################## +\# Configuration file for running experiments +############################################## + +\# Path to directory of circuits to use +circuits_dir=benchmarks/hdl_include + +\# Path to directory of includes circuits to use +includes_dir=benchmarks/hdl_include/include + +\# Path to directory of architectures to use +archs_dir=arch/no_timing/memory_sweep + +\# Add circuits to list to sweep +circuit_list_add=ch_intrinsics_top.v + +\# Add circuits to includes list to sweep +include_list_add=generic_definitions1.vh +include_list_add=generic_definitions2.vh +include_list_add=memory_controller.vh + +\# Add architectures to list to sweep +arch_list_add=k4_N10_memSize16384_memData64.xml + +\# Parse info and how to parse +parse_file=vpr_no_timing.txt + +\# How to parse QoR info +qor_parse_file=qor_no_timing.txt + +\# Script parameters +script_params_common=-track_memory_usage --timing_analysis off +___________________________________________________________________________________ diff --git a/vtr_flow/benchmarks/hdl_include/include/generic_definitions1.vh b/vtr_flow/benchmarks/hdl_include/include/generic_definitions1.vh new file mode 100755 index 00000000000..aa9d5b7a9b4 --- /dev/null +++ b/vtr_flow/benchmarks/hdl_include/include/generic_definitions1.vh @@ -0,0 +1,7 @@ +/* + * This header file provides definitions for ch_intrinsic_modified.v + * located at: + * vtr_flow/benchmarks/hdl_include/ch_intrinsic_modified.v +*/ +`define MEMORY_CONTROLLER_ADDR_SIZE 32 +`define MEMORY_CONTROLLER_DATA_SIZE 32 \ No newline at end of file diff --git a/vtr_flow/benchmarks/hdl_include/include/generic_definitions2.vh b/vtr_flow/benchmarks/hdl_include/include/generic_definitions2.vh new file mode 100755 index 00000000000..6c5a993cf5e --- /dev/null +++ b/vtr_flow/benchmarks/hdl_include/include/generic_definitions2.vh @@ -0,0 +1,8 @@ +/* + * This header file provides definitions for ch_intrinsic_modified.v + * located at: + * vtr_flow/benchmarks/hdl_include/ch_intrinsic_modified.v +*/ +`define MEMORY_CONTROLLER_TAGS 1 +`define MEMORY_CONTROLLER_TAG_SIZE 1 +`define TAG__str 1'b0 \ No newline at end of file diff --git a/vtr_flow/benchmarks/hdl_include/include/memory_controller.v b/vtr_flow/benchmarks/hdl_include/include/memory_controller.v new file mode 100755 index 00000000000..81988fe8e10 --- /dev/null +++ b/vtr_flow/benchmarks/hdl_include/include/memory_controller.v @@ -0,0 +1,64 @@ +/* + * This Verilog file provides the memory_controller description + * for ch_intrinsic_modified.v located at: + * vtr_flow/benchmarks/hdl_include/ch_intrinsic_modified.v +*/ +module memory_controller +( + clk, + memory_controller_address, + memory_controller_write_enable, + memory_controller_in, + memory_controller_out +); +input clk; +input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; +input memory_controller_write_enable; +input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; +reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; + + +reg [4:0] str_address; +reg str_write_enable; +reg [7:0] str_in; +wire [7:0] str_out; + +single_port_ram _str ( + .clk( clk ), + .addr( str_address ), + .we( str_write_enable ), + .data( str_in ), + .out( str_out ) +); + + +wire tag; + +//must use all wires inside module..... +assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in; +reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag; +always @(posedge clk) + prevTag <= tag; +always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in) +begin + +case(tag) + + 1'b0: + begin + str_address = memory_controller_address[5-1+0:0]; + str_write_enable = memory_controller_write_enable; + str_in[8-1:0] = memory_controller_in[8-1:0]; + end +endcase + +case(prevTag) + + 1'b0: + memory_controller_out = str_out; +endcase +end + +endmodule + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt new file mode 100644 index 00000000000..d19496a28e1 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt @@ -0,0 +1,40 @@ +############################################################### +# Configuration file for running experiments +# This config file is testing the ability to specify include +# files that should pass to Odin with the top module of the +# benchmark (ch_intrinsic_top.v). This is done by specifying +# two Verilog header files that provide essential definitions, +# and memory_controller design that provides the design of an +# internal component for ch_intrinsic_top. If the include files +# are not properly included during compilation the benchmark is +# incomplete and the flow will error out. +############################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/hdl_include + +# Path to directory of includes circuits to use +includes_dir=benchmarks/hdl_include/include + +# Path to directory of architectures to use +archs_dir=arch/no_timing/memory_sweep + +# Add circuits to list to sweep +circuit_list_add=ch_intrinsics_modified.v + +# Add circuits to includes list to sweep +include_list_add=generic_definitions1.vh +include_list_add=generic_definitions2.vh +include_list_add=memory_controller.v + +# Add architectures to list to sweep +arch_list_add=k4_N10_memSize16384_memData64.xml + +# Parse info and how to parse +parse_file=vpr_no_timing.txt + +# How to parse QoR info +qor_parse_file=qor_no_timing.txt + +# Script parameters +script_params_common=-track_memory_usage --timing_analysis off diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt index 5aefdaf1f2c..8e10192c70b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt @@ -1,3 +1,4 @@ regression_tests/vtr_reg_basic/basic_no_timing regression_tests/vtr_reg_basic/basic_timing regression_tests/vtr_reg_basic/basic_timing_no_sdc +regression_tests/vtr_reg_basic/hdl_include From bb87df4dfcac60d861ceb92bb00f4b45a054d245 Mon Sep 17 00:00:00 2001 From: Seyed Alireza Damghani Date: Fri, 11 Jun 2021 12:09:45 -0300 Subject: [PATCH 3/3] [Doc]: updating the documentation corresponding to include feature Signed-off-by: Seyed Alireza Damghani --- doc/src/vtr/tasks.rst | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/doc/src/vtr/tasks.rst b/doc/src/vtr/tasks.rst index f09c87c0e57..f1c501f4e80 100644 --- a/doc/src/vtr/tasks.rst +++ b/doc/src/vtr/tasks.rst @@ -140,6 +140,20 @@ Optional Fields For instance with ``circuit_list_add=my_circuit.v`` or ``circuit_list_add=my_circuit.blif``, the flow would look for an SDC file named ``my_circuit.sdc`` within the specified ``sdc_dir``. +* **includes_dir**: Directory path to benchmark _include_ files + + Absolute path or relative to ``$VTR_ROOT/vtr_flow/``. + + Note: Multiple _includes_dir_ are NOT allowed in a task config file. + +* **include_list_add**: A path to an _include_ file, which is relative to _includes_dir_ + + Multiple _include_list_add_ can be provided. + + _include_ files could act as the top module complementary, like definitions, macros or sub-modules. + + Note: _include_ files will be shared among all benchmark circuits in the task config file. + * **pass_requirements_file**: :ref:`vtr_pass_requirements` file. Absolute path or relative to ``$VTR_ROOT/vtr_flow/parse/pass_requirements/`` or ``$VTR_ROOT/vtr_flow/tasks//config/``