diff --git a/.github/kokoro/presubmit/nightly.cfg b/.github/kokoro/presubmit/nightly_test1.cfg similarity index 96% rename from .github/kokoro/presubmit/nightly.cfg rename to .github/kokoro/presubmit/nightly_test1.cfg index abf16949cb2..a88b7b8561c 100644 --- a/.github/kokoro/presubmit/nightly.cfg +++ b/.github/kokoro/presubmit/nightly_test1.cfg @@ -51,7 +51,7 @@ env_vars { env_vars { key: "VTR_TEST" - value: "vtr_reg_nightly" + value: "vtr_reg_nightly_test1" } #Options for run_reg_test.py @@ -63,5 +63,5 @@ env_vars { env_vars { key: "NUM_CORES" - value: "3" + value: "8" } diff --git a/.github/kokoro/presubmit/nightly_test2.cfg b/.github/kokoro/presubmit/nightly_test2.cfg new file mode 100644 index 00000000000..7754ca0ff81 --- /dev/null +++ b/.github/kokoro/presubmit/nightly_test2.cfg @@ -0,0 +1,67 @@ +# Format: //devtools/kokoro/config/proto/build.proto + +build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh" + +# 72 hours +timeout_mins: 4320 + +action { + define_artifacts { + # File types + regex: "**/*.out" + regex: "**/vpr_stdout.log" + regex: "**/parse_results.txt" + regex: "**/qor_results.txt" + regex: "**/pack.log" + regex: "**/place.log" + regex: "**/route.log" + regex: "**/*_qor.csv" + regex: "**/*.out.gz" + regex: "**/vpr_stdout.log.gz" + regex: "**/parse_results.txt.gz" + regex: "**/qor_results.txt.gz" + regex: "**/pack.log.gz" + regex: "**/place.log.gz" + regex: "**/route.log.gz" + regex: "**/*_qor.csv.gz" + strip_prefix: "github/vtr-verilog-to-routing/" + } +} + +env_vars { + key: "KOKORO_TYPE" + value: "presubmit" +} + +env_vars { + key: "KOKORO_DIR" + value: "vtr-verilog-to-routing" +} + +env_vars { + key: "VTR_DIR" + value: "vtr-verilog-to-routing" +} + +#Use default build configuration +env_vars { + key: "VTR_CMAKE_PARAMS" + value: "" +} + +env_vars { + key: "VTR_TEST" + value: "vtr_reg_nightly_test2" +} + +#Options for run_reg_test.py +# -show_failures: show tool failures in main log output +env_vars { + key: "VTR_TEST_OPTIONS" + value: "-show_failures" +} + +env_vars { + key: "NUM_CORES" + value: "8" +} diff --git a/.github/kokoro/presubmit/nightly_test3.cfg b/.github/kokoro/presubmit/nightly_test3.cfg new file mode 100644 index 00000000000..82fd5719bbb --- /dev/null +++ b/.github/kokoro/presubmit/nightly_test3.cfg @@ -0,0 +1,67 @@ +# Format: //devtools/kokoro/config/proto/build.proto + +build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh" + +# 72 hours +timeout_mins: 4320 + +action { + define_artifacts { + # File types + regex: "**/*.out" + regex: "**/vpr_stdout.log" + regex: "**/parse_results.txt" + regex: "**/qor_results.txt" + regex: "**/pack.log" + regex: "**/place.log" + regex: "**/route.log" + regex: "**/*_qor.csv" + regex: "**/*.out.gz" + regex: "**/vpr_stdout.log.gz" + regex: "**/parse_results.txt.gz" + regex: "**/qor_results.txt.gz" + regex: "**/pack.log.gz" + regex: "**/place.log.gz" + regex: "**/route.log.gz" + regex: "**/*_qor.csv.gz" + strip_prefix: "github/vtr-verilog-to-routing/" + } +} + +env_vars { + key: "KOKORO_TYPE" + value: "presubmit" +} + +env_vars { + key: "KOKORO_DIR" + value: "vtr-verilog-to-routing" +} + +env_vars { + key: "VTR_DIR" + value: "vtr-verilog-to-routing" +} + +#Use default build configuration +env_vars { + key: "VTR_CMAKE_PARAMS" + value: "" +} + +env_vars { + key: "VTR_TEST" + value: "vtr_reg_nightly_test3" +} + +#Options for run_reg_test.py +# -show_failures: show tool failures in main log output +env_vars { + key: "VTR_TEST_OPTIONS" + value: "-show_failures" +} + +env_vars { + key: "NUM_CORES" + value: "8" +} diff --git a/.github/kokoro/steps/vtr-test.sh b/.github/kokoro/steps/vtr-test.sh index 91b60b6b54e..067ed0c857f 100644 --- a/.github/kokoro/steps/vtr-test.sh +++ b/.github/kokoro/steps/vtr-test.sh @@ -69,7 +69,10 @@ find vtr_flow/benchmarks/titan_blif/ -type f -not -name 'README.*' -delete find . -type f -regex ".*\.tar\.\(gz\|xz\)" -delete #Gzip output files from vtr_reg_nightly tests to lower working directory disk space -find vtr_flow/tasks/regression_tests/vtr_reg_nightly/ -type f -print0 | xargs -0 -P $(nproc) gzip +find vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/ -type f -print0 | xargs -0 -P $(nproc) gzip +find vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/ -type f -print0 | xargs -0 -P $(nproc) gzip +find vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/ -type f -print0 | xargs -0 -P $(nproc) gzip + # Make sure working directory doesn't exceed disk space limit! echo "Working directory size: $(du -sh)" diff --git a/README.developers.md b/README.developers.md index 638803bc406..f8f7797386f 100644 --- a/README.developers.md +++ b/README.developers.md @@ -754,12 +754,12 @@ There may be times when a regression test fails its QoR test because its golden_ 2. Next, generate new golden reference results using `parse_vtr_task.py` and the `-create_golden` option. ```shell - $ ../scripts/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -create_golden + $ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -create_golden ``` 3. Lastly, check that the results match with the `-check_golden` option ```shell - $ ../scripts/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -check_golden + $ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -check_golden ``` Once the `-check_golden` command passes, the changes to the golden result can be committed so that the reg test will pass in future runs of vtr_reg_nightly. diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml index 5e4ce7bd1eb..df0d18d57f2 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml @@ -132,7 +132,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - + @@ -144,7 +144,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml index cd7eb1a867a..4e0134b086f 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml @@ -156,7 +156,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + @@ -168,7 +168,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml index bb0e36420b5..ea4f169c28e 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml @@ -159,7 +159,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + @@ -171,7 +171,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml index d8835fba6f2..a5e70613c90 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml @@ -156,7 +156,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + @@ -168,7 +168,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml index 191304bbf91..ff4d57cfac1 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml @@ -158,7 +158,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + @@ -170,7 +170,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml index 54b08daf89b..ac7f539ec68 100644 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml @@ -117,7 +117,8 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin @@ -153,7 +154,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + @@ -165,7 +166,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml index c8d6426c267..b9e761548ce 100644 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml @@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin @@ -148,7 +149,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - + @@ -160,7 +161,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml index fb6ced886a4..ab8bc930c77 100644 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml @@ -132,7 +132,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - + @@ -144,7 +144,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml index c5ba6c1bcae..4ae3a253147 100644 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml @@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin @@ -148,7 +149,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - + @@ -160,7 +161,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml index 86cc65a5fd3..a6c900ffc49 100644 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml @@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin @@ -148,7 +149,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - + @@ -160,7 +161,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml index 7fabe02d1bc..922dd391322 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml @@ -154,7 +154,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + @@ -166,7 +166,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml index 769a4486681..32afaa9469c 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml @@ -157,7 +157,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + @@ -169,7 +169,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml index 0299a404e11..89aa7e4ac62 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml @@ -154,7 +154,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + @@ -166,7 +166,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml index 75f434e5276..ab0a5d6dad2 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml @@ -156,7 +156,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + @@ -168,7 +168,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - + diff --git a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2ripple_N8_22nm.xml b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2ripple_N8_22nm.xml index cd1251dc842..fa4fd7c6a5f 100644 --- a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2ripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2ripple_N8_22nm.xml @@ -117,7 +117,8 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin diff --git a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2uripple_N8_22nm.xml b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2uripple_N8_22nm.xml index c095d0b7e87..65da8c37608 100644 --- a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2uripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2uripple_N8_22nm.xml @@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin diff --git a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_ripple_N8_22nm.xml b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_ripple_N8_22nm.xml index e38a7f3df64..b98f9a9e564 100644 --- a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_ripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_ripple_N8_22nm.xml @@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin diff --git a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_uripple_N8_22nm.xml b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_uripple_N8_22nm.xml index de6e13aca41..7ea63ae64fe 100644 --- a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_uripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_uripple_N8_22nm.xml @@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin diff --git a/vtr_flow/benchmarks/arithmetic/FIR_filters/verilog/generate_fir.c++ b/vtr_flow/benchmarks/arithmetic/FIR_filters/verilog/generate_fir.c++ index da149951f8b..dda509121af 100644 --- a/vtr_flow/benchmarks/arithmetic/FIR_filters/verilog/generate_fir.c++ +++ b/vtr_flow/benchmarks/arithmetic/FIR_filters/verilog/generate_fir.c++ @@ -325,13 +325,13 @@ int main(int argc, char const *argv[]) { string level_output_wires = make_output_wire_name(level); string level_input_wires = make_output_wire_name(level-1); - cout << " // ************************* LEVEL "< 0) { - cout << " // ********* Byes ******** \\\\\n"; + cout << " // ********* Byes ******** \\\n"; size_t offset = -1; if (level == 0) { offset = LEVEL_WIDTH_WO_EXTRAS; // in L0 the bye is the center one diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_10.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_10.v index 81ced68b2b2..249658bc8af 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_10.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_10.v @@ -123,7 +123,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -162,8 +162,8 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -202,7 +202,7 @@ module fir ( // (5 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -221,7 +221,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_4( .dataa (L1_mult_wires_4), .result(L1_output_wires_2) @@ -229,7 +229,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -241,7 +241,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_2( .dataa (L1_output_wires_2), .result(L2_output_wires_1) @@ -249,7 +249,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_11.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_11.v index 5bb6e2fbeba..cb239aa48e5 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_11.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_11.v @@ -127,7 +127,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -167,7 +167,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_5( .dataa (INPUT_PIPELINE_REG_5), .result(L0_output_wires_5) @@ -175,8 +175,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -222,7 +222,7 @@ module fir ( // (6 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -247,7 +247,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -259,7 +259,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_2( .dataa (L1_output_wires_2), .result(L2_output_wires_1) @@ -267,7 +267,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_12.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_12.v index d2e1640b9cd..86216ea79a2 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_12.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_12.v @@ -129,7 +129,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -175,8 +175,8 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -222,7 +222,7 @@ module fir ( // (6 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -247,7 +247,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -259,7 +259,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_2( .dataa (L1_output_wires_2), .result(L2_output_wires_1) @@ -267,7 +267,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_13.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_13.v index 4b287504c29..0e9c3a91c78 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_13.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_13.v @@ -133,7 +133,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -180,7 +180,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_6( .dataa (INPUT_PIPELINE_REG_6), .result(L0_output_wires_6) @@ -188,8 +188,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -242,7 +242,7 @@ module fir ( // (7 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -268,7 +268,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_6( .dataa (L1_mult_wires_6), .result(L1_output_wires_3) @@ -276,7 +276,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -294,7 +294,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_14.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_14.v index 86208c4d19e..c915f65fcde 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_14.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_14.v @@ -135,7 +135,8 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* + wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -188,8 +189,9 @@ module fir ( // (7 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** + wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -242,7 +244,8 @@ module fir ( // (7 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** + wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -268,7 +271,8 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** + one_register L1_byereg_for_6( .dataa (L1_mult_wires_6), .result(L1_output_wires_3) @@ -276,31 +280,33 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* + wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; adder_with_1_reg L2_adder_0and1( - .dataa (L1_output_wires_0), - .datab (L1_output_wires_1), - .result(L2_output_wires_0) + .dataa (L1_output_wires_0), + .datab (L1_output_wires_1), + .result (L2_output_wires_0) ); adder_with_1_reg L2_adder_2and3( .dataa (L1_output_wires_2), .datab (L1_output_wires_3), - .result(L2_output_wires_1) + .result (L2_output_wires_1) ); // (2 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* + wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( - .dataa (L2_output_wires_0), - .datab (L2_output_wires_1), - .result(L3_output_wires_0) + .dataa (L2_output_wires_0), + .datab (L2_output_wires_1), + .result (L3_output_wires_0) ); // (1 main tree Adders) @@ -435,9 +441,9 @@ module adder_with_1_reg ( dataa, datab, result); + input clk; + input clk_ena; - input clk; - input clk_ena; input [17:0] dataa; input [17:0] datab; output [17:0] result; @@ -451,9 +457,9 @@ module multiplier_with_reg ( dataa, datab, result); + input clk; + input clk_ena; - input clk; - input clk_ena; input [17:0] dataa; input [17:0] datab; output [17:0] result; @@ -466,9 +472,8 @@ endmodule module one_register ( dataa, result); - - input clk; - input clk_ena; + input clk; + input clk_ena; input [17:0] dataa; output [17:0] result; diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_15.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_15.v index 9ab1f4116b1..85a725d535a 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_15.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_15.v @@ -139,7 +139,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -193,7 +193,7 @@ module fir ( // (7 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_7( .dataa (INPUT_PIPELINE_REG_7), .result(L0_output_wires_7) @@ -201,8 +201,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -262,7 +262,7 @@ module fir ( // (8 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -294,7 +294,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -312,7 +312,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_16.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_16.v index e38d485e6cf..15fdb30a1cc 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_16.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_16.v @@ -141,7 +141,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -201,8 +201,8 @@ module fir ( // (8 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -262,7 +262,7 @@ module fir ( // (8 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -294,7 +294,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -312,7 +312,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_17.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_17.v index d4b8589239e..c70adc9b302 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_17.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_17.v @@ -145,7 +145,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -206,7 +206,7 @@ module fir ( // (8 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_8( .dataa (INPUT_PIPELINE_REG_8), .result(L0_output_wires_8) @@ -214,8 +214,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -282,7 +282,7 @@ module fir ( // (9 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -315,7 +315,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_8( .dataa (L1_mult_wires_8), .result(L1_output_wires_4) @@ -323,7 +323,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -342,7 +342,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_4( .dataa (L1_output_wires_4), .result(L2_output_wires_2) @@ -350,7 +350,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -362,7 +362,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .dataa (L2_output_wires_2), .result(L3_output_wires_1) @@ -370,7 +370,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_18.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_18.v index 6a60ec99aec..21f55813a0f 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_18.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_18.v @@ -147,7 +147,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -214,8 +214,8 @@ module fir ( // (9 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -282,7 +282,7 @@ module fir ( // (9 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -315,7 +315,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_8( .dataa (L1_mult_wires_8), .result(L1_output_wires_4) @@ -323,7 +323,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -342,7 +342,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_4( .dataa (L1_output_wires_4), .result(L2_output_wires_2) @@ -350,7 +350,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -362,7 +362,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .dataa (L2_output_wires_2), .result(L3_output_wires_1) @@ -370,7 +370,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_19.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_19.v index d1f42b80798..746bbeff84f 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_19.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_19.v @@ -151,7 +151,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -219,7 +219,7 @@ module fir ( // (9 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_9( .dataa (INPUT_PIPELINE_REG_9), .result(L0_output_wires_9) @@ -227,8 +227,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -302,7 +302,7 @@ module fir ( // (10 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -341,7 +341,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -360,7 +360,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_4( .dataa (L1_output_wires_4), .result(L2_output_wires_2) @@ -368,7 +368,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -380,7 +380,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .dataa (L2_output_wires_2), .result(L3_output_wires_1) @@ -388,7 +388,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_20.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_20.v index e362dd9c148..4c3d9b486ae 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_20.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_20.v @@ -153,7 +153,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -227,8 +227,8 @@ module fir ( // (10 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -302,7 +302,7 @@ module fir ( // (10 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -341,7 +341,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -360,7 +360,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_4( .dataa (L1_output_wires_4), .result(L2_output_wires_2) @@ -368,7 +368,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -380,7 +380,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .dataa (L2_output_wires_2), .result(L3_output_wires_1) @@ -388,7 +388,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_21.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_21.v index a0cc79bb8f0..25893eab9d8 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_21.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_21.v @@ -157,7 +157,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -232,7 +232,7 @@ module fir ( // (10 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_10( .dataa (INPUT_PIPELINE_REG_10), .result(L0_output_wires_10) @@ -240,8 +240,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -322,7 +322,7 @@ module fir ( // (11 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -362,7 +362,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_10( .dataa (L1_mult_wires_10), .result(L1_output_wires_5) @@ -370,7 +370,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -395,7 +395,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -407,7 +407,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .dataa (L2_output_wires_2), .result(L3_output_wires_1) @@ -415,7 +415,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_22.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_22.v index 59740eacbea..e54f86adf6c 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_22.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_22.v @@ -159,7 +159,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -240,8 +240,8 @@ module fir ( // (11 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -322,7 +322,7 @@ module fir ( // (11 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -362,7 +362,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_10( .dataa (L1_mult_wires_10), .result(L1_output_wires_5) @@ -370,7 +370,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -395,7 +395,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -407,7 +407,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .dataa (L2_output_wires_2), .result(L3_output_wires_1) @@ -415,7 +415,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_23.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_23.v index ab60e2b5447..f203802662d 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_23.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_23.v @@ -163,7 +163,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -245,7 +245,7 @@ module fir ( // (11 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_11( .dataa (INPUT_PIPELINE_REG_11), .result(L0_output_wires_11) @@ -253,8 +253,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -342,7 +342,7 @@ module fir ( // (12 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -388,7 +388,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -413,7 +413,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -425,7 +425,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .dataa (L2_output_wires_2), .result(L3_output_wires_1) @@ -433,7 +433,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_24.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_24.v index f7ef8144d70..f7a734d71f5 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_24.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_24.v @@ -165,7 +165,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -253,8 +253,8 @@ module fir ( // (12 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -342,7 +342,7 @@ module fir ( // (12 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -388,7 +388,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -413,7 +413,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -425,7 +425,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .dataa (L2_output_wires_2), .result(L3_output_wires_1) @@ -433,7 +433,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_25.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_25.v index 394b6ca7242..867be953169 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_25.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_25.v @@ -169,7 +169,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -258,7 +258,7 @@ module fir ( // (12 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_12( .dataa (INPUT_PIPELINE_REG_12), .result(L0_output_wires_12) @@ -266,8 +266,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -362,7 +362,7 @@ module fir ( // (13 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -409,7 +409,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_12( .dataa (L1_mult_wires_12), .result(L1_output_wires_6) @@ -417,7 +417,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -443,7 +443,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_6( .dataa (L1_output_wires_6), .result(L2_output_wires_3) @@ -451,7 +451,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -469,7 +469,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_26.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_26.v index f49186eea03..64757c5345a 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_26.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_26.v @@ -171,7 +171,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -266,8 +266,8 @@ module fir ( // (13 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -362,7 +362,7 @@ module fir ( // (13 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -409,7 +409,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_12( .dataa (L1_mult_wires_12), .result(L1_output_wires_6) @@ -417,7 +417,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -443,7 +443,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_6( .dataa (L1_output_wires_6), .result(L2_output_wires_3) @@ -451,7 +451,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -469,7 +469,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_27.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_27.v index e7c90e76d44..694d6a161ae 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_27.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_27.v @@ -175,7 +175,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -271,7 +271,7 @@ module fir ( // (13 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_13( .dataa (INPUT_PIPELINE_REG_13), .result(L0_output_wires_13) @@ -279,8 +279,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -382,7 +382,7 @@ module fir ( // (14 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -435,7 +435,7 @@ module fir ( // (7 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -461,7 +461,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_6( .dataa (L1_output_wires_6), .result(L2_output_wires_3) @@ -469,7 +469,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -487,7 +487,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_28.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_28.v index 4ae331f3a09..007aca9e1b1 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_28.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_28.v @@ -177,7 +177,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -279,8 +279,8 @@ module fir ( // (14 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -382,7 +382,7 @@ module fir ( // (14 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -435,7 +435,7 @@ module fir ( // (7 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -461,7 +461,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_6( .dataa (L1_output_wires_6), .result(L2_output_wires_3) @@ -469,7 +469,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -487,7 +487,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_29.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_29.v index 8036a54714e..b17c4ccde22 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_29.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_29.v @@ -181,7 +181,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -284,7 +284,7 @@ module fir ( // (14 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_14( .dataa (INPUT_PIPELINE_REG_14), .result(L0_output_wires_14) @@ -292,8 +292,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -402,7 +402,7 @@ module fir ( // (15 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -456,7 +456,7 @@ module fir ( // (7 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_14( .dataa (L1_mult_wires_14), .result(L1_output_wires_7) @@ -464,7 +464,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -496,7 +496,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -514,7 +514,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_30.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_30.v index b66dc9acd06..c9ac3210c0b 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_30.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_30.v @@ -183,7 +183,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -292,8 +292,8 @@ module fir ( // (15 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -402,7 +402,7 @@ module fir ( // (15 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -456,7 +456,7 @@ module fir ( // (7 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_14( .dataa (L1_mult_wires_14), .result(L1_output_wires_7) @@ -464,7 +464,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -496,7 +496,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -514,7 +514,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_31.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_31.v index 7771c6b5334..3247d1be08a 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_31.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_31.v @@ -187,7 +187,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -297,7 +297,7 @@ module fir ( // (15 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_15( .dataa (INPUT_PIPELINE_REG_15), .result(L0_output_wires_15) @@ -305,8 +305,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -422,7 +422,7 @@ module fir ( // (16 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -482,7 +482,7 @@ module fir ( // (8 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -514,7 +514,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -532,7 +532,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_32.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_32.v index 22be1cbe9b0..2e0ac33a6e1 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_32.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_32.v @@ -189,7 +189,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -305,8 +305,8 @@ module fir ( // (16 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -422,7 +422,7 @@ module fir ( // (16 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -482,7 +482,7 @@ module fir ( // (8 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -514,7 +514,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -532,7 +532,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_33.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_33.v index 9f49d788150..a212b0bd271 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_33.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_33.v @@ -193,7 +193,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -310,7 +310,7 @@ module fir ( // (16 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_16( .dataa (INPUT_PIPELINE_REG_16), .result(L0_output_wires_16) @@ -318,8 +318,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -442,7 +442,7 @@ module fir ( // (17 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -503,7 +503,7 @@ module fir ( // (8 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_16( .dataa (L1_mult_wires_16), .result(L1_output_wires_8) @@ -511,7 +511,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -544,7 +544,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_8( .dataa (L1_output_wires_8), .result(L2_output_wires_4) @@ -552,7 +552,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -571,7 +571,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .dataa (L2_output_wires_4), .result(L3_output_wires_2) @@ -579,7 +579,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -591,7 +591,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -599,7 +599,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_34.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_34.v index e0ed2da69e8..9e26fa4c407 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_34.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_34.v @@ -195,7 +195,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -318,8 +318,8 @@ module fir ( // (17 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -442,7 +442,7 @@ module fir ( // (17 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -503,7 +503,7 @@ module fir ( // (8 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_16( .dataa (L1_mult_wires_16), .result(L1_output_wires_8) @@ -511,7 +511,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -544,7 +544,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_8( .dataa (L1_output_wires_8), .result(L2_output_wires_4) @@ -552,7 +552,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -571,7 +571,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .dataa (L2_output_wires_4), .result(L3_output_wires_2) @@ -579,7 +579,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -591,7 +591,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -599,7 +599,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_35.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_35.v index c4b6bde2e9f..30806a44b8c 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_35.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_35.v @@ -199,7 +199,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -323,7 +323,7 @@ module fir ( // (17 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_17( .dataa (INPUT_PIPELINE_REG_17), .result(L0_output_wires_17) @@ -331,8 +331,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -462,7 +462,7 @@ module fir ( // (18 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -529,7 +529,7 @@ module fir ( // (9 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -562,7 +562,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_8( .dataa (L1_output_wires_8), .result(L2_output_wires_4) @@ -570,7 +570,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -589,7 +589,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .dataa (L2_output_wires_4), .result(L3_output_wires_2) @@ -597,7 +597,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -609,7 +609,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -617,7 +617,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_36.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_36.v index f4b85854561..7899842f8ad 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_36.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_36.v @@ -201,7 +201,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -331,8 +331,8 @@ module fir ( // (18 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -462,7 +462,7 @@ module fir ( // (18 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -529,7 +529,7 @@ module fir ( // (9 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -562,7 +562,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_8( .dataa (L1_output_wires_8), .result(L2_output_wires_4) @@ -570,7 +570,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -589,7 +589,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .dataa (L2_output_wires_4), .result(L3_output_wires_2) @@ -597,7 +597,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -609,7 +609,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -617,7 +617,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_37.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_37.v index da0b7bde514..d2407271901 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_37.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_37.v @@ -205,7 +205,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -336,7 +336,7 @@ module fir ( // (18 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_18( .dataa (INPUT_PIPELINE_REG_18), .result(L0_output_wires_18) @@ -344,8 +344,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -482,7 +482,7 @@ module fir ( // (19 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -550,7 +550,7 @@ module fir ( // (9 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_18( .dataa (L1_mult_wires_18), .result(L1_output_wires_9) @@ -558,7 +558,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -597,7 +597,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -616,7 +616,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .dataa (L2_output_wires_4), .result(L3_output_wires_2) @@ -624,7 +624,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -636,7 +636,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -644,7 +644,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_38.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_38.v index 61d27ff0140..e34d623cd69 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_38.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_38.v @@ -207,7 +207,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -344,8 +344,8 @@ module fir ( // (19 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -482,7 +482,7 @@ module fir ( // (19 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -550,7 +550,7 @@ module fir ( // (9 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_18( .dataa (L1_mult_wires_18), .result(L1_output_wires_9) @@ -558,7 +558,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -597,7 +597,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -616,7 +616,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .dataa (L2_output_wires_4), .result(L3_output_wires_2) @@ -624,7 +624,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -636,7 +636,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -644,7 +644,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_39.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_39.v index 1d6af80e320..54bb5fb630a 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_39.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_39.v @@ -211,7 +211,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -349,7 +349,7 @@ module fir ( // (19 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_19( .dataa (INPUT_PIPELINE_REG_19), .result(L0_output_wires_19) @@ -357,8 +357,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -502,7 +502,7 @@ module fir ( // (20 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -576,7 +576,7 @@ module fir ( // (10 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -615,7 +615,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -634,7 +634,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .dataa (L2_output_wires_4), .result(L3_output_wires_2) @@ -642,7 +642,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -654,7 +654,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -662,7 +662,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_40.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_40.v index e93c21c1566..d497bfe1488 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_40.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_40.v @@ -213,7 +213,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -357,8 +357,8 @@ module fir ( // (20 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -502,7 +502,7 @@ module fir ( // (20 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -576,7 +576,7 @@ module fir ( // (10 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -615,7 +615,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -634,7 +634,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .dataa (L2_output_wires_4), .result(L3_output_wires_2) @@ -642,7 +642,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -654,7 +654,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -662,7 +662,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_41.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_41.v index 02498b25981..c7f44211906 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_41.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_41.v @@ -217,7 +217,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -362,7 +362,7 @@ module fir ( // (20 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_20( .dataa (INPUT_PIPELINE_REG_20), .result(L0_output_wires_20) @@ -370,8 +370,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -522,7 +522,7 @@ module fir ( // (21 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -597,7 +597,7 @@ module fir ( // (10 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_20( .dataa (L1_mult_wires_20), .result(L1_output_wires_10) @@ -605,7 +605,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -645,7 +645,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_10( .dataa (L1_output_wires_10), .result(L2_output_wires_5) @@ -653,7 +653,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -678,7 +678,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -690,7 +690,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -698,7 +698,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_42.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_42.v index 2482ac0ff74..a43fc5523ea 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_42.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_42.v @@ -219,7 +219,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -370,8 +370,8 @@ module fir ( // (21 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -522,7 +522,7 @@ module fir ( // (21 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -597,7 +597,7 @@ module fir ( // (10 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_20( .dataa (L1_mult_wires_20), .result(L1_output_wires_10) @@ -605,7 +605,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -645,7 +645,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_10( .dataa (L1_output_wires_10), .result(L2_output_wires_5) @@ -653,7 +653,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -678,7 +678,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -690,7 +690,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -698,7 +698,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_43.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_43.v index 4cd88b878e2..2a3cd95a148 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_43.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_43.v @@ -223,7 +223,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -375,7 +375,7 @@ module fir ( // (21 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_21( .dataa (INPUT_PIPELINE_REG_21), .result(L0_output_wires_21) @@ -383,8 +383,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -542,7 +542,7 @@ module fir ( // (22 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -623,7 +623,7 @@ module fir ( // (11 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -663,7 +663,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_10( .dataa (L1_output_wires_10), .result(L2_output_wires_5) @@ -671,7 +671,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -696,7 +696,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -708,7 +708,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -716,7 +716,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_44.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_44.v index 8c4949de0f2..453ff3d5531 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_44.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_44.v @@ -225,7 +225,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -383,8 +383,8 @@ module fir ( // (22 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -542,7 +542,7 @@ module fir ( // (22 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -623,7 +623,7 @@ module fir ( // (11 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -663,7 +663,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_10( .dataa (L1_output_wires_10), .result(L2_output_wires_5) @@ -671,7 +671,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -696,7 +696,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -708,7 +708,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -716,7 +716,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_45.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_45.v index a82f8815128..47d4041c822 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_45.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_45.v @@ -229,7 +229,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -388,7 +388,7 @@ module fir ( // (22 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_22( .dataa (INPUT_PIPELINE_REG_22), .result(L0_output_wires_22) @@ -396,8 +396,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -562,7 +562,7 @@ module fir ( // (23 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -644,7 +644,7 @@ module fir ( // (11 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_22( .dataa (L1_mult_wires_22), .result(L1_output_wires_11) @@ -652,7 +652,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -698,7 +698,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -723,7 +723,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -735,7 +735,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -743,7 +743,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_46.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_46.v index 066eb4acb85..f0cf11cdfd7 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_46.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_46.v @@ -231,7 +231,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -396,8 +396,8 @@ module fir ( // (23 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -562,7 +562,7 @@ module fir ( // (23 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -644,7 +644,7 @@ module fir ( // (11 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_22( .dataa (L1_mult_wires_22), .result(L1_output_wires_11) @@ -652,7 +652,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -698,7 +698,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -723,7 +723,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -735,7 +735,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -743,7 +743,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_47.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_47.v index f0bffe6b29c..951c3fa6e74 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_47.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_47.v @@ -235,7 +235,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -401,7 +401,7 @@ module fir ( // (23 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_23( .dataa (INPUT_PIPELINE_REG_23), .result(L0_output_wires_23) @@ -409,8 +409,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -582,7 +582,7 @@ module fir ( // (24 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -670,7 +670,7 @@ module fir ( // (12 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -716,7 +716,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -741,7 +741,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -753,7 +753,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -761,7 +761,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_48.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_48.v index 129db59cc43..57a6ac11bb4 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_48.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_48.v @@ -237,7 +237,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -409,8 +409,8 @@ module fir ( // (24 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -582,7 +582,7 @@ module fir ( // (24 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -670,7 +670,7 @@ module fir ( // (12 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -716,7 +716,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -741,7 +741,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -753,7 +753,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .dataa (L3_output_wires_2), .result(L4_output_wires_1) @@ -761,7 +761,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_49.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_49.v index b79bbe17fd7..e80d606efdc 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_49.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_49.v @@ -241,7 +241,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -414,7 +414,7 @@ module fir ( // (24 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_24( .dataa (INPUT_PIPELINE_REG_24), .result(L0_output_wires_24) @@ -422,8 +422,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -602,7 +602,7 @@ module fir ( // (25 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -691,7 +691,7 @@ module fir ( // (12 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_24( .dataa (L1_mult_wires_24), .result(L1_output_wires_12) @@ -699,7 +699,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -746,7 +746,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_12( .dataa (L1_output_wires_12), .result(L2_output_wires_6) @@ -754,7 +754,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -780,7 +780,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_6( .dataa (L2_output_wires_6), .result(L3_output_wires_3) @@ -788,7 +788,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -806,7 +806,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_50.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_50.v index 1c32f9e6409..1bbf26cc68f 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_50.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_50.v @@ -243,7 +243,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -422,8 +422,8 @@ module fir ( // (25 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -602,7 +602,7 @@ module fir ( // (25 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -691,7 +691,7 @@ module fir ( // (12 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_24( .dataa (L1_mult_wires_24), .result(L1_output_wires_12) @@ -699,7 +699,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -746,7 +746,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_12( .dataa (L1_output_wires_12), .result(L2_output_wires_6) @@ -754,7 +754,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -780,7 +780,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_6( .dataa (L2_output_wires_6), .result(L3_output_wires_3) @@ -788,7 +788,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -806,7 +806,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_51.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_51.v index efa0d27442f..eaa694d3759 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_51.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_51.v @@ -246,7 +246,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -426,7 +426,7 @@ module fir ( // (25 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_25( .dataa (INPUT_PIPELINE_REG_25), .result(L0_output_wires_25) @@ -434,8 +434,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -621,7 +621,7 @@ module fir ( // (26 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -716,7 +716,7 @@ module fir ( // (13 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -763,7 +763,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_12( .dataa (L1_output_wires_12), .result(L2_output_wires_6) @@ -771,7 +771,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -797,7 +797,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_6( .dataa (L2_output_wires_6), .result(L3_output_wires_3) @@ -805,7 +805,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -823,7 +823,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_52.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_52.v index 09b4a1f3776..19a7feb97d5 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_52.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_52.v @@ -248,7 +248,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -434,8 +434,8 @@ module fir ( // (26 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -621,7 +621,7 @@ module fir ( // (26 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -716,7 +716,7 @@ module fir ( // (13 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -763,7 +763,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_12( .dataa (L1_output_wires_12), .result(L2_output_wires_6) @@ -771,7 +771,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -797,7 +797,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_6( .dataa (L2_output_wires_6), .result(L3_output_wires_3) @@ -805,7 +805,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -823,7 +823,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_10.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_10.v index 4ae27e69daa..4ab846c4554 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_10.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_10.v @@ -123,7 +123,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -167,8 +167,8 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -212,7 +212,7 @@ module fir ( // (5 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -233,7 +233,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_4), @@ -242,7 +242,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -255,7 +255,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_2), @@ -264,7 +264,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_11.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_11.v index 31f268e6b40..d9ca46976dc 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_11.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_11.v @@ -127,7 +127,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -172,7 +172,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_5( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_5), @@ -181,8 +181,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -234,7 +234,7 @@ module fir ( // (6 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -262,7 +262,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -275,7 +275,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_2), @@ -284,7 +284,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_12.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_12.v index d948682d83e..756d04ad181 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_12.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_12.v @@ -129,7 +129,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -181,8 +181,8 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -234,7 +234,7 @@ module fir ( // (6 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -262,7 +262,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -275,7 +275,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_2), @@ -284,7 +284,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_13.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_13.v index 26f277fe49c..3ec2cf35437 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_13.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_13.v @@ -133,7 +133,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -186,7 +186,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_6( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_6), @@ -195,8 +195,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -256,7 +256,7 @@ module fir ( // (7 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -285,7 +285,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_6( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_6), @@ -294,7 +294,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -314,7 +314,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_14.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_14.v index 7ec65967aff..d6b4fe345b5 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_14.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_14.v @@ -135,7 +135,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -195,8 +195,8 @@ module fir ( // (7 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -256,7 +256,7 @@ module fir ( // (7 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -285,7 +285,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_6( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_6), @@ -294,7 +294,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -314,7 +314,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_15.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_15.v index 52a1300be82..dd593d5c89b 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_15.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_15.v @@ -139,7 +139,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -200,7 +200,7 @@ module fir ( // (7 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_7( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_7), @@ -209,8 +209,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -278,7 +278,7 @@ module fir ( // (8 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -314,7 +314,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -334,7 +334,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_16.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_16.v index afc50f590eb..aa45ad44a8d 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_16.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_16.v @@ -141,7 +141,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -209,8 +209,8 @@ module fir ( // (8 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -278,7 +278,7 @@ module fir ( // (8 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -314,7 +314,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; @@ -334,7 +334,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; adder_with_1_reg L3_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_17.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_17.v index f5f83d27cd6..44bbe03baf1 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_17.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_17.v @@ -145,7 +145,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -214,7 +214,7 @@ module fir ( // (8 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_8( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_8), @@ -223,8 +223,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -300,7 +300,7 @@ module fir ( // (9 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -337,7 +337,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_8( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_8), @@ -346,7 +346,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -367,7 +367,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_4), @@ -376,7 +376,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -389,7 +389,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_2), @@ -398,7 +398,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_18.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_18.v index cb783e64aa3..48d5e9937b6 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_18.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_18.v @@ -147,7 +147,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -223,8 +223,8 @@ module fir ( // (9 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -300,7 +300,7 @@ module fir ( // (9 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -337,7 +337,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_8( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_8), @@ -346,7 +346,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -367,7 +367,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_4), @@ -376,7 +376,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -389,7 +389,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_2), @@ -398,7 +398,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_19.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_19.v index 83e11f8eaeb..c21dd08371a 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_19.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_19.v @@ -151,7 +151,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -228,7 +228,7 @@ module fir ( // (9 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_9( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_9), @@ -237,8 +237,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -322,7 +322,7 @@ module fir ( // (10 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -366,7 +366,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -387,7 +387,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_4), @@ -396,7 +396,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -409,7 +409,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_2), @@ -418,7 +418,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_20.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_20.v index 9e47c8d69f3..cedef43ec09 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_20.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_20.v @@ -153,7 +153,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -237,8 +237,8 @@ module fir ( // (10 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -322,7 +322,7 @@ module fir ( // (10 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -366,7 +366,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -387,7 +387,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_4), @@ -396,7 +396,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -409,7 +409,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_2), @@ -418,7 +418,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_21.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_21.v index dc3fd51c605..00aa5670f54 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_21.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_21.v @@ -157,7 +157,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -242,7 +242,7 @@ module fir ( // (10 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_10( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_10), @@ -251,8 +251,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -344,7 +344,7 @@ module fir ( // (11 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -389,7 +389,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_10( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_10), @@ -398,7 +398,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -426,7 +426,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -439,7 +439,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_2), @@ -448,7 +448,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_22.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_22.v index 97924a4e3e8..fb23dc8046c 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_22.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_22.v @@ -159,7 +159,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -251,8 +251,8 @@ module fir ( // (11 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -344,7 +344,7 @@ module fir ( // (11 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -389,7 +389,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_10( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_10), @@ -398,7 +398,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -426,7 +426,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -439,7 +439,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_2), @@ -448,7 +448,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_23.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_23.v index 73afecc08ee..f78ab10be56 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_23.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_23.v @@ -163,7 +163,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -256,7 +256,7 @@ module fir ( // (11 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_11( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_11), @@ -265,8 +265,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -366,7 +366,7 @@ module fir ( // (12 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -418,7 +418,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -446,7 +446,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -459,7 +459,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_2), @@ -468,7 +468,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_24.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_24.v index 6603fbf97f8..1c700b3fcc5 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_24.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_24.v @@ -165,7 +165,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -265,8 +265,8 @@ module fir ( // (12 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -366,7 +366,7 @@ module fir ( // (12 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -418,7 +418,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -446,7 +446,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -459,7 +459,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_2), @@ -468,7 +468,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_25.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_25.v index 218bea0b3e4..4a7785cc0a2 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_25.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_25.v @@ -169,7 +169,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -270,7 +270,7 @@ module fir ( // (12 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_12( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_12), @@ -279,8 +279,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -388,7 +388,7 @@ module fir ( // (13 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -441,7 +441,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_12( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_12), @@ -450,7 +450,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -479,7 +479,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_6( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_6), @@ -488,7 +488,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -508,7 +508,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_26.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_26.v index 37881e4c277..e3856d4e3a9 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_26.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_26.v @@ -171,7 +171,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -279,8 +279,8 @@ module fir ( // (13 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -388,7 +388,7 @@ module fir ( // (13 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -441,7 +441,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_12( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_12), @@ -450,7 +450,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -479,7 +479,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_6( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_6), @@ -488,7 +488,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -508,7 +508,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_27.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_27.v index 7713ecc462c..71a101b0d01 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_27.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_27.v @@ -175,7 +175,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -284,7 +284,7 @@ module fir ( // (13 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_13( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_13), @@ -293,8 +293,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -410,7 +410,7 @@ module fir ( // (14 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -470,7 +470,7 @@ module fir ( // (7 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -499,7 +499,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_6( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_6), @@ -508,7 +508,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -528,7 +528,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_28.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_28.v index e08ea68d97f..a1cb3492f32 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_28.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_28.v @@ -177,7 +177,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -293,8 +293,8 @@ module fir ( // (14 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -410,7 +410,7 @@ module fir ( // (14 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -470,7 +470,7 @@ module fir ( // (7 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -499,7 +499,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_6( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_6), @@ -508,7 +508,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -528,7 +528,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_29.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_29.v index d16cf64a722..fb5109f088e 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_29.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_29.v @@ -181,7 +181,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -298,7 +298,7 @@ module fir ( // (14 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_14( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_14), @@ -307,8 +307,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -432,7 +432,7 @@ module fir ( // (15 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -493,7 +493,7 @@ module fir ( // (7 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_14( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_14), @@ -502,7 +502,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -538,7 +538,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -558,7 +558,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_30.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_30.v index 8402a9057a7..1fbca32d524 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_30.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_30.v @@ -183,7 +183,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -307,8 +307,8 @@ module fir ( // (15 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -432,7 +432,7 @@ module fir ( // (15 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -493,7 +493,7 @@ module fir ( // (7 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_14( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_14), @@ -502,7 +502,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -538,7 +538,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -558,7 +558,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_31.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_31.v index 5bae04085f3..0818dcc4f6d 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_31.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_31.v @@ -187,7 +187,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -312,7 +312,7 @@ module fir ( // (15 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_15( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_15), @@ -321,8 +321,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -454,7 +454,7 @@ module fir ( // (16 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -522,7 +522,7 @@ module fir ( // (8 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -558,7 +558,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -578,7 +578,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_32.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_32.v index 8e5043eb5ce..735e086e627 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_32.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_32.v @@ -189,7 +189,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -321,8 +321,8 @@ module fir ( // (16 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -454,7 +454,7 @@ module fir ( // (16 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -522,7 +522,7 @@ module fir ( // (8 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -558,7 +558,7 @@ module fir ( // (4 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; @@ -578,7 +578,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; adder_with_1_reg L4_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_33.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_33.v index 00aee5fa8d4..93946275d35 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_33.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_33.v @@ -193,7 +193,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -326,7 +326,7 @@ module fir ( // (16 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_16( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_16), @@ -335,8 +335,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -476,7 +476,7 @@ module fir ( // (17 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -545,7 +545,7 @@ module fir ( // (8 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_16( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_16), @@ -554,7 +554,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -591,7 +591,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_8( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_8), @@ -600,7 +600,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -621,7 +621,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_4), @@ -630,7 +630,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -643,7 +643,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -652,7 +652,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_34.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_34.v index 6daf1cce871..ad11b3efa95 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_34.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_34.v @@ -195,7 +195,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -335,8 +335,8 @@ module fir ( // (17 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -476,7 +476,7 @@ module fir ( // (17 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -545,7 +545,7 @@ module fir ( // (8 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_16( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_16), @@ -554,7 +554,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -591,7 +591,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_8( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_8), @@ -600,7 +600,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -621,7 +621,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_4), @@ -630,7 +630,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -643,7 +643,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -652,7 +652,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_35.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_35.v index 6c579a6f408..0270e808bd1 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_35.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_35.v @@ -199,7 +199,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -340,7 +340,7 @@ module fir ( // (17 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_17( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_17), @@ -349,8 +349,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -498,7 +498,7 @@ module fir ( // (18 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -574,7 +574,7 @@ module fir ( // (9 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -611,7 +611,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_8( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_8), @@ -620,7 +620,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -641,7 +641,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_4), @@ -650,7 +650,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -663,7 +663,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -672,7 +672,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_36.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_36.v index bdcea8c1145..c86620837ea 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_36.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_36.v @@ -201,7 +201,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -349,8 +349,8 @@ module fir ( // (18 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -498,7 +498,7 @@ module fir ( // (18 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -574,7 +574,7 @@ module fir ( // (9 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -611,7 +611,7 @@ module fir ( // (4 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_8( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_8), @@ -620,7 +620,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -641,7 +641,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_4), @@ -650,7 +650,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -663,7 +663,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -672,7 +672,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_37.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_37.v index ee34318498f..6993a0c4ae1 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_37.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_37.v @@ -205,7 +205,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -354,7 +354,7 @@ module fir ( // (18 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_18( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_18), @@ -363,8 +363,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -520,7 +520,7 @@ module fir ( // (19 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -597,7 +597,7 @@ module fir ( // (9 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_18( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_18), @@ -606,7 +606,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -650,7 +650,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -671,7 +671,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_4), @@ -680,7 +680,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -693,7 +693,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -702,7 +702,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_38.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_38.v index 78f668a8b7a..b34ca421a5c 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_38.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_38.v @@ -207,7 +207,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -363,8 +363,8 @@ module fir ( // (19 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -520,7 +520,7 @@ module fir ( // (19 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -597,7 +597,7 @@ module fir ( // (9 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_18( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_18), @@ -606,7 +606,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -650,7 +650,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -671,7 +671,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_4), @@ -680,7 +680,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -693,7 +693,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -702,7 +702,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_39.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_39.v index daeb3ea15b9..1fe09e330d1 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_39.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_39.v @@ -211,7 +211,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -368,7 +368,7 @@ module fir ( // (19 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_19( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_19), @@ -377,8 +377,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -542,7 +542,7 @@ module fir ( // (20 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -626,7 +626,7 @@ module fir ( // (10 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -670,7 +670,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -691,7 +691,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_4), @@ -700,7 +700,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -713,7 +713,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -722,7 +722,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_40.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_40.v index b52beedf49d..d3d5acec761 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_40.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_40.v @@ -213,7 +213,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -377,8 +377,8 @@ module fir ( // (20 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -542,7 +542,7 @@ module fir ( // (20 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -626,7 +626,7 @@ module fir ( // (10 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -670,7 +670,7 @@ module fir ( // (5 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -691,7 +691,7 @@ module fir ( // (2 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_4( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_4), @@ -700,7 +700,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -713,7 +713,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -722,7 +722,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_41.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_41.v index d2b88794bf8..04513c40372 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_41.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_41.v @@ -217,7 +217,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -382,7 +382,7 @@ module fir ( // (20 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_20( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_20), @@ -391,8 +391,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -564,7 +564,7 @@ module fir ( // (21 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -649,7 +649,7 @@ module fir ( // (10 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_20( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_20), @@ -658,7 +658,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -703,7 +703,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_10( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_10), @@ -712,7 +712,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -740,7 +740,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -753,7 +753,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -762,7 +762,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_42.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_42.v index f339b51e37f..64c54373cd7 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_42.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_42.v @@ -219,7 +219,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -391,8 +391,8 @@ module fir ( // (21 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -564,7 +564,7 @@ module fir ( // (21 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -649,7 +649,7 @@ module fir ( // (10 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_20( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_20), @@ -658,7 +658,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -703,7 +703,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_10( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_10), @@ -712,7 +712,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -740,7 +740,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -753,7 +753,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -762,7 +762,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_43.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_43.v index 7ebbf18d416..a1f7c7f3999 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_43.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_43.v @@ -223,7 +223,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -396,7 +396,7 @@ module fir ( // (21 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_21( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_21), @@ -405,8 +405,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -586,7 +586,7 @@ module fir ( // (22 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -678,7 +678,7 @@ module fir ( // (11 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -723,7 +723,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_10( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_10), @@ -732,7 +732,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -760,7 +760,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -773,7 +773,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -782,7 +782,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_44.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_44.v index 0c00e6285cc..e4bc78e3e5a 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_44.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_44.v @@ -225,7 +225,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -405,8 +405,8 @@ module fir ( // (22 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -586,7 +586,7 @@ module fir ( // (22 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -678,7 +678,7 @@ module fir ( // (11 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -723,7 +723,7 @@ module fir ( // (5 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_10( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_10), @@ -732,7 +732,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -760,7 +760,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -773,7 +773,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -782,7 +782,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_45.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_45.v index efcf455f944..c59f0ffe767 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_45.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_45.v @@ -229,7 +229,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -410,7 +410,7 @@ module fir ( // (22 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_22( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_22), @@ -419,8 +419,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -608,7 +608,7 @@ module fir ( // (23 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -701,7 +701,7 @@ module fir ( // (11 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_22( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_22), @@ -710,7 +710,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -762,7 +762,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -790,7 +790,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -803,7 +803,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -812,7 +812,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_46.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_46.v index b2a90867ee9..fdeb91aab6e 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_46.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_46.v @@ -231,7 +231,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -419,8 +419,8 @@ module fir ( // (23 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -608,7 +608,7 @@ module fir ( // (23 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -701,7 +701,7 @@ module fir ( // (11 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_22( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_22), @@ -710,7 +710,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -762,7 +762,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -790,7 +790,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -803,7 +803,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -812,7 +812,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_47.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_47.v index faf2e812639..7824c1e8373 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_47.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_47.v @@ -235,7 +235,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -424,7 +424,7 @@ module fir ( // (23 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_23( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_23), @@ -433,8 +433,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -630,7 +630,7 @@ module fir ( // (24 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -730,7 +730,7 @@ module fir ( // (12 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -782,7 +782,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -810,7 +810,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -823,7 +823,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -832,7 +832,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_48.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_48.v index a9df9cd771d..079175af35e 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_48.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_48.v @@ -237,7 +237,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -433,8 +433,8 @@ module fir ( // (24 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -630,7 +630,7 @@ module fir ( // (24 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -730,7 +730,7 @@ module fir ( // (12 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -782,7 +782,7 @@ module fir ( // (6 main tree Adders) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -810,7 +810,7 @@ module fir ( // (3 main tree Adders) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -823,7 +823,7 @@ module fir ( // (1 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L4_byereg_for_2( .clk(clk), .clk_ena(clk_ena), .dataa (L3_output_wires_2), @@ -832,7 +832,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_49.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_49.v index 9b0b12ec730..a8b925e8675 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_49.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_49.v @@ -241,7 +241,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -438,7 +438,7 @@ module fir ( // (24 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_24( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_24), @@ -447,8 +447,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -652,7 +652,7 @@ module fir ( // (25 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -753,7 +753,7 @@ module fir ( // (12 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_24( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_24), @@ -762,7 +762,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -815,7 +815,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_12( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_12), @@ -824,7 +824,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -853,7 +853,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_6( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_6), @@ -862,7 +862,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -882,7 +882,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_50.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_50.v index 5d5f4aad9c4..84e6390fc63 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_50.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_50.v @@ -243,7 +243,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -447,8 +447,8 @@ module fir ( // (25 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -652,7 +652,7 @@ module fir ( // (25 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -753,7 +753,7 @@ module fir ( // (12 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L1_byereg_for_24( .clk(clk), .clk_ena(clk_ena), .dataa (L1_mult_wires_24), @@ -762,7 +762,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -815,7 +815,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_12( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_12), @@ -824,7 +824,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -853,7 +853,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_6( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_6), @@ -862,7 +862,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -882,7 +882,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_51.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_51.v index 02fe9f4b51b..cfba8826671 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_51.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_51.v @@ -246,7 +246,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -451,7 +451,7 @@ module fir ( // (25 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L0_byereg_for_25( .clk(clk), .clk_ena(clk_ena), .dataa (INPUT_PIPELINE_REG_25), @@ -460,8 +460,8 @@ module fir ( // (1 byes) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -673,7 +673,7 @@ module fir ( // (26 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -781,7 +781,7 @@ module fir ( // (13 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -834,7 +834,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_12( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_12), @@ -843,7 +843,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -872,7 +872,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_6( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_6), @@ -881,7 +881,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -901,7 +901,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_52.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_52.v index 1d25a4528f9..b0c5f71c5d5 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_52.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_52.v @@ -248,7 +248,7 @@ module fir ( // * // ***************************************************** - // ************************* LEVEL 0 ************************* \\ + // ************************* LEVEL 0 ************************* wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; @@ -460,8 +460,8 @@ module fir ( // (26 main tree Adders) - // ************************* LEVEL 1 ************************* \\ - // **************** Multipliers **************** \\ + // ************************* LEVEL 1 ************************* + // **************** Multipliers **************** wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; @@ -673,7 +673,7 @@ module fir ( // (26 Multipliers) - // **************** Adders **************** \\ + // **************** Adders **************** wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; @@ -781,7 +781,7 @@ module fir ( // (13 main tree Adders) - // ************************* LEVEL 2 ************************* \\ + // ************************* LEVEL 2 ************************* wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; @@ -834,7 +834,7 @@ module fir ( // (6 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L2_byereg_for_12( .clk(clk), .clk_ena(clk_ena), .dataa (L1_output_wires_12), @@ -843,7 +843,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 3 ************************* \\ + // ************************* LEVEL 3 ************************* wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; @@ -872,7 +872,7 @@ module fir ( // (3 main tree Adders) - // ********* Byes ******** \\ + // ********* Byes ******** one_register L3_byereg_for_6( .clk(clk), .clk_ena(clk_ena), .dataa (L2_output_wires_6), @@ -881,7 +881,7 @@ module fir ( // (1 byes) - // ************************* LEVEL 4 ************************* \\ + // ************************* LEVEL 4 ************************* wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; @@ -901,7 +901,7 @@ module fir ( // (2 main tree Adders) - // ************************* LEVEL 5 ************************* \\ + // ************************* LEVEL 5 ************************* wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( diff --git a/vtr_flow/benchmarks/arithmetic/generated_circuits/cmu_DFT/verilog/64-16bit-fixed-JACM.v b/vtr_flow/benchmarks/arithmetic/generated_circuits/cmu_DFT/verilog/64-16bit-fixed-JACM.v index e9ff98ec4a9..8b25c26a876 100644 --- a/vtr_flow/benchmarks/arithmetic/generated_circuits/cmu_DFT/verilog/64-16bit-fixed-JACM.v +++ b/vtr_flow/benchmarks/arithmetic/generated_circuits/cmu_DFT/verilog/64-16bit-fixed-JACM.v @@ -992,7 +992,7 @@ endmodule -module memMod(in, out, inAddr, outAddr, writeSel, clk); +/*module memMod(in, out, inAddr, outAddr, writeSel, clk); parameter depth=1024, width=16, logDepth=10; @@ -1012,7 +1012,7 @@ module memMod(in, out, inAddr, outAddr, writeSel, clk); if (writeSel) mem[inAddr] <= in; end -endmodule +endmodule */ diff --git a/vtr_flow/benchmarks/verilog/raygentop.v b/vtr_flow/benchmarks/verilog/raygentop.v index 2aaeec7a6f4..e55b8bff8a7 100755 --- a/vtr_flow/benchmarks/verilog/raygentop.v +++ b/vtr_flow/benchmarks/verilog/raygentop.v @@ -1,4 +1,4 @@ - module paj_raygentop_hierarchy_no_mem (rgwant_addr, rgwant_data, rgread_ready, rgaddr_ready, rgdata_ready, rgwant_read, rgdatain, rgdataout, rgaddrin, rgCont, rgStat, rgCfgData, rgwant_CfgData, rgCfgData_ready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, tm3_clk_v0, fbdata, fbdatavalid, fbnextscanline, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, rgData, rgAddr, rgWE, rgAddrValid, rgDone, rgResultData, rgResultReady, rgResultSource); + module paj_raygentop_hierarchy_no_mem (rgwant_addr, rgwant_data, rgread_ready, rgaddr_ready, rgdata_ready, rgwant_read, rgdatain, rgdataout, rgaddrin, rgCont, rgStat, rgCfgData, rgwant_CfgData, rgCfgData_ready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, clk, fbdata, fbdatavalid, fbnextscanline, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, rgData, rgAddr, rgWE, rgAddrValid, rgDone, rgResultData, rgResultReady, rgResultSource); output rgwant_addr; wire rgwant_addr; @@ -35,7 +35,7 @@ wire[1:0] tm3_sram_oe; output tm3_sram_adsp; wire tm3_sram_adsp; - input tm3_clk_v0; + input clk; output[63:0] fbdata; wire[63:0] fbdata; @@ -158,9 +158,9 @@ assign rgwant_CfgData = wantcfg ; - onlyonecycle onlyeonecycleinst (rgCont[0], go, globalreset, tm3_clk_v0); + onlyonecycle onlyeonecycleinst (rgCont[0], go, globalreset, clk); - always @(posedge tm3_clk_v0) + always @(posedge clk) begin if (globalreset == 1'b1) begin @@ -174,18 +174,18 @@ end assign fbpage = ~page ; - matmult matmultinst(sramdatal[47:32], sramdatal[31:16], sramdatal[15:0], m11, m12, m13, m21, m22, m23, m31, m32, m33, dir[47:32], dir[31:16], dir[15:0], tm3_clk_v0); + matmult matmultinst(sramdatal[47:32], sramdatal[31:16], sramdatal[15:0], m11, m12, m13, m21, m22, m23, m31, m32, m33, dir[47:32], dir[31:16], dir[15:0], clk); - delay1x3 dir01delay(dirReady, dirReadyl, tm3_clk_v0); - rgconfigmemory ConfigMemoryInst (rgCfgData[31:28], rgCfgData[27:0], rgCfgData_ready, wantcfg, origx, origy, origz, m11, m12, m13, m21, m22, m23, m31, m32, m33, bkcolour, texinfo, globalreset, tm3_clk_v0); + delay1x3 dir01delay(dirReady, dirReadyl, clk); + rgconfigmemory ConfigMemoryInst (rgCfgData[31:28], rgCfgData[27:0], rgCfgData_ready, wantcfg, origx, origy, origz, m11, m12, m13, m21, m22, m23, m31, m32, m33, bkcolour, texinfo, globalreset, clk); - rgsramcontroller sramcont (rgwant_addr, rgaddr_ready, rgaddrin, rgwant_data, rgdata_ready, rgdatain, rgwant_read, rgread_ready, rgdataout, dirReady, wantDir, sramdatal, address, wantwriteback, writebackack, writebackdata, writebackaddr, fbdata, fbnextscanline, fbdatavalid, fbpage, shadedata, triID, wantshadedata, shadedataready, texeladdr, texel, wanttexel, texelready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, tm3_clk_v0); - raysend raysendinst (as01, ack01, addr01, dir01, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, tm3_clk_v0, statepeek2); + rgsramcontroller sramcont (rgwant_addr, rgaddr_ready, rgaddrin, rgwant_data, rgdata_ready, rgdatain, rgwant_read, rgread_ready, rgdataout, dirReady, wantDir, sramdatal, address, wantwriteback, writebackack, writebackdata, writebackaddr, fbdata, fbnextscanline, fbdatavalid, fbpage, shadedata, triID, wantshadedata, shadedataready, texeladdr, texel, wanttexel, texelready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, clk); + raysend raysendinst (as01, ack01, addr01, dir01, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, clk, statepeek2); - raygencont raygencontinst(go, rgCont[15:1], rgStat[31], cyclecounter, nextaddr01, nas01, nas10, page, dirReadyl, wantDir, dir, address, as01, addr01, ack01, dir01, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, tm3_clk_v0, statepeekct); - resultrecieve resultrecieveinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, tm3_clk_v0); + raygencont raygencontinst(go, rgCont[15:1], rgStat[31], cyclecounter, nextaddr01, nas01, nas10, page, dirReadyl, wantDir, dir, address, as01, addr01, ack01, dir01, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, clk, statepeekct); + resultrecieve resultrecieveinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); assign debugglobalreset = globalreset | go ; - resultwriter resultwriteinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, nextaddr01, nas01, nas10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, writebackdata, writebackaddr, wantwriteback, writebackack, debugglobalreset, tm3_clk_v0); + resultwriter resultwriteinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, nextaddr01, nas01, nas10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, writebackdata, writebackaddr, wantwriteback, writebackack, debugglobalreset, clk); assign rgStat[30:0] = cyclecounter ; endmodule diff --git a/vtr_flow/tasks/arithmetic_tasks/table_X/config/config.txt b/vtr_flow/tasks/arithmetic_tasks/table_X/config/config.txt deleted file mode 100644 index ae4c154c4a9..00000000000 --- a/vtr_flow/tasks/arithmetic_tasks/table_X/config/config.txt +++ /dev/null @@ -1,41 +0,0 @@ -# -############################################ -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/arithmetic/generated_circuits/table_X/verilog - -# Path to directory of architectures to use -archs_dir=arch/COFFE_22nm - -# Add circuits to list to sweep -circuit_list_add=arm_core.v -circuit_list_add=LU8PEEng.v -circuit_list_add=mcml.v -circuit_list_add=or1200.v -circuit_list_add=sha.v -circuit_list_add=stereovision2.v -circuit_list_add=LU32PEEng.v -circuit_list_add=bgm.v -circuit_list_add=boundtop.v -circuit_list_add=blob_merge.v -circuit_list_add=mkSMAdapter4B.v -circuit_list_add=raygentop.v -circuit_list_add=stereovision0.v -circuit_list_add=stereovision1.v - -# Add architectures to list to sweep -arch_list_add=k6_N8_gate_boost_0.2V_22nm.xml -arch_list_add=k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml -arch_list_add=k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml -arch_list_add=k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml -arch_list_add=k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml - -# Parse info and how to parse -parse_file=vpr_chain.txt - -# Pass requirements -pass_requirements_file=pass_requirements_chain.txt - -script_params=-lut_size 6 -routing_failure_predictor off diff --git a/vtr_flow/tasks/basic_flow/config/config.txt b/vtr_flow/tasks/basic_flow/config/config.txt deleted file mode 100644 index 0d743635636..00000000000 --- a/vtr_flow/tasks/basic_flow/config/config.txt +++ /dev/null @@ -1,21 +0,0 @@ -############################################## -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/timing - -# Add circuits to list to sweep -circuit_list_add=ch_intrinsics.v - -# Add architectures to list to sweep -arch_list_add=k6_frac_N10_mem32K_40nm.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements.txt diff --git a/vtr_flow/tasks/basic_flow/config/golden_results.txt b/vtr_flow/tasks/basic_flow/config/golden_results.txt deleted file mode 100644 index edde206c70f..00000000000 --- a/vtr_flow/tasks/basic_flow/config/golden_results.txt +++ /dev/null @@ -1,2 +0,0 @@ -arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v 30d086154 success 419 549 298 249 10 10 19 99 130 1 0 2262 2.74023 -250.655 -2.74023 42 2555 15 2250 12 3.5255 -318.677 -3.5255 0 0 3.92691e+06 1.57199e+06 236681. 2366.81 297605. 2976.05 0.03 0.00 -1 -1 -1 0.15 0.27 0.64 0.06 1.70 -1 -1 -1 diff --git a/vtr_flow/tasks/checkin_reg/config/config.txt b/vtr_flow/tasks/checkin_reg/config/config.txt deleted file mode 100644 index f8a64437c45..00000000000 --- a/vtr_flow/tasks/checkin_reg/config/config.txt +++ /dev/null @@ -1,25 +0,0 @@ -############################################## -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/timing - -# Add circuits to list to sweep -circuit_list_add=ch_intrinsics.v -circuit_list_add=diffeq1.v - -# Add architectures to list to sweep -arch_list_add=k6_N10_mem32K_40nm.xml - -# Parse info and how to parse -#parse_file=vpr_memory.txt # for tracking memory usage -parse_file=vpr_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements.txt - -script_params=-track_memory_usage diff --git a/vtr_flow/tasks/checkin_reg/config/golden_results.txt b/vtr_flow/tasks/checkin_reg/config/golden_results.txt deleted file mode 100644 index 301b0f590d0..00000000000 --- a/vtr_flow/tasks/checkin_reg/config/golden_results.txt +++ /dev/null @@ -1,3 +0,0 @@ -arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem -k6_N10_mem32K_40nm.xml ch_intrinsics.v 30d086154 success 419 549 297 254 10 10 24 99 130 1 0 2221 2.62528 -243.1 -2.62528 44 1941 18 1755 17 3.02966 -286.064 -3.02966 0 0 3.92691e+06 1.84146e+06 235874. 2358.74 307351. 3073.51 0.03 0.01 -1 -1 -1 0.11 0.27 0.63 0.07 1.67 25272 9284 36400 -k6_N10_mem32K_40nm.xml diffeq1.v 30d086154 success 1001 938 713 312 16 16 49 162 96 0 5 10746 19.7499 -1523.89 -19.7499 50 10835 24 9313 26 21.7518 -1689.63 -21.7518 0 0 1.21132e+07 4.62081e+06 746321. 2915.31 990901. 3870.71 0.02 0.01 -1 -1 -1 0.30 0.82 2.63 0.61 5.09 38284 8328 37216 diff --git a/vtr_flow/tasks/arithmetic_tasks/cmu_DFT/config/config.txt b/vtr_flow/tasks/cmu_DFT/config/config.txt similarity index 95% rename from vtr_flow/tasks/arithmetic_tasks/cmu_DFT/config/config.txt rename to vtr_flow/tasks/cmu_DFT/config/config.txt index e8dcb7103f3..17a579dc39d 100644 --- a/vtr_flow/tasks/arithmetic_tasks/cmu_DFT/config/config.txt +++ b/vtr_flow/tasks/cmu_DFT/config/config.txt @@ -10,7 +10,7 @@ circuits_dir=benchmarks/arithmetic/generated_circuits/cmu_DFT/verilog archs_dir=arch/COFFE_22nm # Add circuits to list to sweep - +#Issue 1369 (circuit does not go through odin) circuit_list_add=64-16bit-fixed-JACM.v # Add architectures to list to sweep diff --git a/vtr_flow/tasks/cmu_DFT/config/golden_results.txt b/vtr_flow/tasks/cmu_DFT/config/golden_results.txt new file mode 100644 index 00000000000..097a8396445 --- /dev/null +++ b/vtr_flow/tasks/cmu_DFT/config/golden_results.txt @@ -0,0 +1,6 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_N8_gate_boost_0.2V_22nm.xml 64-16bit-fixed-JACM.v common 0.02 -1 1060 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 127 unknown unknown unknown unknown betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml 64-16bit-fixed-JACM.v common 0.02 -1 1124 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 127 unknown unknown unknown unknown betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml 64-16bit-fixed-JACM.v common 0.02 -1 996 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 127 unknown unknown unknown unknown betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml 64-16bit-fixed-JACM.v common 0.02 -1 996 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 127 unknown unknown unknown unknown betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml 64-16bit-fixed-JACM.v common 0.05 -1 1000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 127 unknown unknown unknown unknown betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/arithmetic_tasks/cmu_DFT_frac/config/config.txt b/vtr_flow/tasks/cmu_DFT_frac/config/config.txt similarity index 94% rename from vtr_flow/tasks/arithmetic_tasks/cmu_DFT_frac/config/config.txt rename to vtr_flow/tasks/cmu_DFT_frac/config/config.txt index e6508bb3223..162a87f85e7 100644 --- a/vtr_flow/tasks/arithmetic_tasks/cmu_DFT_frac/config/config.txt +++ b/vtr_flow/tasks/cmu_DFT_frac/config/config.txt @@ -10,7 +10,7 @@ circuits_dir=benchmarks/arithmetic/generated_circuits/cmu_DFT/verilog archs_dir=arch/timing/fraclut_carrychain # Add circuits to list to sweep - +#Issue 1369 (circuit does not go through odin) circuit_list_add=64-16bit-fixed-JACM.v # Add architectures to list to sweep diff --git a/vtr_flow/tasks/cmu_DFT_frac/config/golden_results.txt b/vtr_flow/tasks/cmu_DFT_frac/config/golden_results.txt new file mode 100644 index 00000000000..2c1a23cd5d7 --- /dev/null +++ b/vtr_flow/tasks/cmu_DFT_frac/config/golden_results.txt @@ -0,0 +1,6 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_2ripple_N8_22nm.xml 64-16bit-fixed-JACM.v common 0.01 -1 1056 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 127 unknown unknown unknown unknown betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_2uripple_N8_22nm.xml 64-16bit-fixed-JACM.v common 0.01 -1 1064 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 127 unknown unknown unknown unknown betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N8_22nm.xml 64-16bit-fixed-JACM.v common 0.03 -1 928 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 127 unknown unknown unknown unknown betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_ripple_N8_22nm.xml 64-16bit-fixed-JACM.v common 0.01 -1 1060 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 127 unknown unknown unknown unknown betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_uripple_N8_22nm.xml 64-16bit-fixed-JACM.v common 0.02 -1 1064 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 127 unknown unknown unknown unknown betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/power/power_frac_sweep/config/config.txt b/vtr_flow/tasks/power/power_frac_sweep/config/config.txt index fd2cc834e7b..906f38f0c34 100644 --- a/vtr_flow/tasks/power/power_frac_sweep/config/config.txt +++ b/vtr_flow/tasks/power/power_frac_sweep/config/config.txt @@ -29,9 +29,12 @@ circuit_list_add=mkSMAdapter4B.v circuit_list_add=or1200.v circuit_list_add=raygentop.v circuit_list_add=sha.v -circuit_list_add=stereovision0.v -circuit_list_add=stereovision1.v -circuit_list_add=stereovision2.v +#These circuits do not go through ACE2. It falsely thinks there are multiple clocks in the circuit. There is a bug with using module instantiation by port when two modules have different names for their clocks, in this case instantiation by name must be used. Tried altering the instantiation method & clock names but did not work. This fixed the error for raygentop.v + +#circuit_list_add=stereovision0.v +#circuit_list_add=stereovision1.v +#circuit_list_add=stereovision2.v + #circuit_list_add=stereovision3.v # Add architectures to list to sweep @@ -51,7 +54,9 @@ arch_list_add=k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml arch_list_add=k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml # Parse info and how to parse -parse_file=vpr_power_detailed.txt +#vpr_power_detailed.txt produces incompelete QoR results. (Issue #1749) +#parse_file=vpr_power_detailed.txt +parse_file=vpr_power.txt # Pass requirements -pass_requirements_file=pass_requirements.txt +pass_requirements_file=pass_requirements_power.txt diff --git a/vtr_flow/tasks/power/power_frac_sweep/config/golden_results.txt b/vtr_flow/tasks/power/power_frac_sweep/config/golden_results.txt new file mode 100644 index 00000000000..b2092d679f2 --- /dev/null +++ b/vtr_flow/tasks/power/power_frac_sweep/config/golden_results.txt @@ -0,0 +1,151 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 1002.76 22.54 392628 22 484.87 -1 -1 152564 -1 -1 2577 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 694504 257 32 32168 31683 1 18846 2877 61 61 3721 clb auto 26.22 248262 66.64 0.46 16.1566 -22531.6 -16.1566 16.1566 32.83 0.0782438 0.0564755 9.8695 7.26509 78 389797 32 2.18169e+08 1.43244e+08 1.95891e+07 5264.48 241.23 42.8957 33.3179 366085 22 98144 432924 25406325 4095083 18.6941 18.6941 -25477 -18.6941 0 0 2.48035e+07 6665.81 7.58 11.18 5.0928 4.31523 0.1661 0.4522 0.02583 0.522 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 176.37 0.63 59296 18 83.90 -1 -1 67772 -1 -1 550 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 155232 36 100 6600 6700 1 2867 686 30 30 900 clb auto 5.34 44762 9.99 0.03 8.63778 -2522.46 -8.63778 8.63778 2.18 0.0107005 0.00911638 4.08545 3.08985 68 74187 37 4.8774e+07 2.96417e+07 4.08678e+06 4540.87 48.69 10.2662 8.17288 63873 14 12588 62114 2688244 348253 9.86001 9.86001 -2850.16 -9.86001 0 0 5.07014e+06 5633.48 1.25 2.01 1.28752 1.09941 0.0241 0.394 0.04131 0.5647 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 5.37 0.73 46996 2 0.43 -1 -1 37096 -1 -1 84 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 66180 114 192 455 647 1 309 390 13 13 169 clb auto 0.07 749 0.36 0.00 1.5681 -199.971 -1.5681 1.5681 0.22 0.000601647 0.000526337 0.101817 0.0892152 38 1909 18 6.63067e+06 4.5271e+06 384612. 2275.81 1.04 0.279876 0.251151 1613 8 646 807 49022 15408 2.13287 2.13287 -254.934 -2.13287 0 0 489150. 2894.38 0.08 0.03 0.0159116 0.0147728 0.006178 0.4297 0.1195 0.4508 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.38 0.04 9280 3 0.28 -1 -1 36156 -1 -1 68 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 64924 99 130 363 493 1 256 298 12 12 144 clb auto 0.09 706 0.28 0.00 1.86328 -198.021 -1.86328 1.86328 0.26 0.000421259 0.000369279 0.0776921 0.067166 46 1510 15 5.66058e+06 4.21279e+06 378970. 2631.74 0.92 0.230073 0.203412 1419 13 512 678 54408 17907 2.4649 2.4649 -230.915 -2.4649 0 0 486261. 3376.82 0.08 0.03 0.0158575 0.014549 0.00814 0.2379 0.08094 0.6811 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 9.29 0.04 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4.47648 -2445.68 -4.47648 4.47648 0.98 0.00328965 0.00290216 0.520609 0.446436 48 28763 44 2.50602e+07 1.07858e+07 1.59437e+06 3294.16 12.39 1.74353 1.53118 22364 15 6216 13503 3819992 817185 5.30831 5.30831 -3092.16 -5.30831 0 0 2.04427e+06 4223.70 0.40 0.88 0.232959 0.215715 0.02167 0.4611 0.0416 0.4973 +k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml sha.v common 631.70 1.07 38008 20 597.99 -1 -1 95324 -1 -1 213 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 95568 38 36 3404 3440 1 1383 287 19 19 361 clb auto 1.69 14277 1.41 0.01 11.6767 -4084.53 -11.6767 11.6767 0.65 0.00475767 0.00396084 0.580303 0.426071 58 23260 33 1.72706e+07 1.14794e+07 1.39531e+06 3865.12 13.19 3.54284 2.94459 19956 15 4801 18065 573853 101241 14.3234 14.3234 -4727.14 -14.3234 0 0 1.77306e+06 4911.54 0.51 0.68 0.500405 0.445919 0.01059 0.3583 0.02666 0.6151 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/home/ahmadi55/vtr-verilog-to-routing 155524 36 100 6600 6700 1 2936 635 29 29 841 clb auto 3.30 46229 6.16 0.03 8.40852 -2603.38 -8.40852 8.40852 2.73 0.0105882 0.00907557 2.27992 1.72051 76 68701 28 4.4999e+07 2.68931e+07 4.31509e+06 5130.91 45.96 7.18288 5.75326 64084 15 12481 61473 2744401 364670 9.93273 9.93273 -2924.03 -9.93273 0 0 5.38156e+06 6399.00 1.82 1.40 0.79591 0.696069 0.02723 0.3594 0.03588 0.6047 +k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml boundtop.v common 6.84 0.76 47068 2 0.45 -1 -1 37040 -1 -1 84 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 66292 114 192 455 647 1 308 390 13 13 169 clb auto 0.18 729 0.57 0.00 1.8593 -228.354 -1.8593 1.8593 0.34 0.00097119 0.000851272 0.16511 0.143083 32 2259 24 6.63067e+06 4.5271e+06 356714. 2110.73 1.69 0.424623 0.377137 2013 12 749 944 89367 27197 2.46866 2.46866 -282.119 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 70088 162 96 999 932 1 692 302 16 16 256 mult_36 auto 0.29 5373 0.54 0.01 19.7363 -1627.54 -19.7363 19.7363 0.40 0.0015933 0.00145946 0.22656 0.203345 48 12242 28 1.21132e+07 4.08187e+06 791884. 3093.30 6.54 0.884932 0.804179 9857 17 3022 6181 1681171 422674 22.2387 22.2387 -1852.74 -22.2387 0 0 1.01413e+06 3961.44 0.29 0.51 0.159736 0.148902 0.008288 0.3389 0.01598 0.6451 +k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml diffeq2.v common 14.97 0.03 8168 14 0.33 -1 -1 33484 -1 -1 25 66 0 7 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 70540 66 96 719 590 1 524 194 18 18 324 mult_36 auto 0.25 4925 0.67 0.01 15.6681 -903.528 -15.6681 15.6681 0.87 0.00265058 0.00245439 0.371409 0.338242 38 13260 43 1.57076e+07 4.11935e+06 845836. 2610.61 9.10 1.04649 0.958821 10497 22 3161 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success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 2140328 114 102 102506 101104 1 54017 6664 94 94 8836 clb auto 1206.71 1064569 429.60 2.45 67.0299 -313148 -67.0299 67.0299 77.33 0.317171 0.225623 43.0633 32.2968 144 1379618 27 5.40921e+08 4.40939e+08 8.54134e+07 9666.52 3392.49 167.84 132.268 1310115 20 187972 803324 216756823 50873205 79.8846 79.8846 -444059 -79.8846 -26.1439 -0.17036 1.08076e+08 12231.4 34.19 78.11 16.402 13.7655 0.4375 0.4598 0.008792 0.5315 +k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml mcml.v common 11453.62 64.01 954232 75 8679.08 -1 -1 447760 -1 -1 7022 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 1989484 36 33 134466 132924 1 42685 7277 99 99 9801 clb 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2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 84688 193 205 2232 2437 1 1246 564 20 20 400 memory auto 2.20 9258 1.64 0.01 4.81139 -2626.5 -4.81139 4.81139 0.74 0.00317824 0.00250505 0.599371 0.481259 48 17624 38 2.07112e+07 1.14169e+07 1.28923e+06 3223.08 10.30 2.03337 1.72605 14975 15 4347 10898 1069816 252269 5.41651 5.41651 -3112.77 -5.41651 -7.45564 -0.360359 1.65199e+06 4129.98 0.33 0.33 0.159081 0.145467 0.03063 0.1998 0.02435 0.7759 +k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml or1200.v common 71.29 0.58 40828 27 4.90 -1 -1 43880 -1 -1 220 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 121604 385 394 3979 4310 1 2359 1002 27 27 729 io auto 2.00 30963 3.67 0.03 12.7491 -11216.3 -12.7491 12.7491 1.79 0.00728249 0.00647447 1.20087 0.995382 88 48009 21 3.93038e+07 1.33487e+07 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2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 87304 214 305 2625 2741 1 1516 659 22 22 484 mult_36 auto 14.04 12379 1.52 0.02 4.47648 -2408.37 -4.47648 4.47648 1.02 0.00445537 0.00397044 0.525065 0.45193 48 28218 44 2.50602e+07 1.06241e+07 1.65992e+06 3429.59 15.03 1.94138 1.70365 21808 16 6246 13552 4472971 963087 5.11979 5.11979 -3084.59 -5.11979 0 0 2.12755e+06 4395.76 0.46 0.83 0.1752 0.162222 0.02209 0.4489 0.04261 0.5085 +k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml sha.v common 691.11 0.85 38060 20 658.19 -1 -1 95332 -1 -1 208 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 95452 38 36 3404 3440 1 1363 282 19 19 361 clb auto 3.23 14310 1.42 0.01 11.4448 -4167.06 -11.4448 11.4448 1.03 0.00375423 0.00317596 0.600228 0.433893 62 22568 35 1.72706e+07 1.121e+07 1.55602e+06 4310.31 13.33 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2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 84880 193 205 2232 2437 1 1245 560 20 20 400 memory auto 2.91 9409 2.81 0.01 4.51843 -2563.66 -4.51843 4.51843 1.13 0.00308431 0.00260283 1.24575 1.02119 58 16810 27 2.07112e+07 1.12014e+07 1.47096e+06 3677.41 11.41 3.07986 2.63519 14781 15 4544 11156 910084 208759 5.21689 5.21689 -3041.22 -5.21689 -7.97206 -0.342703 1.87544e+06 4688.60 0.54 0.60 0.364422 0.330135 0.03036 0.2234 0.02796 0.7486 +k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml or1200.v common 68.62 0.62 40800 27 7.68 -1 -1 43856 -1 -1 224 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 125172 385 394 3979 4310 1 2344 1006 27 27 729 io auto 1.87 31017 3.71 0.03 12.7758 -11318.1 -12.7758 12.7758 2.65 0.00751072 0.00667678 1.27483 1.04848 84 52290 47 3.93038e+07 1.35643e+07 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success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 96152 38 36 3404 3440 1 1353 283 19 19 361 clb auto 2.31 13585 1.69 0.01 11.3536 -4012.03 -11.3536 11.3536 0.98 0.00373774 0.00314843 0.748625 0.564202 62 21104 18 1.72706e+07 1.12638e+07 1.42202e+06 3939.11 9.65 2.05676 1.65636 19366 16 5216 19604 638674 108002 13.8896 13.8896 -4503.3 -13.8896 0 0 1.76637e+06 4892.99 0.32 0.38 0.253914 0.224973 0.01055 0.368 0.0272 0.6048 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml bgm.v common 1207.73 22.88 392688 22 467.66 -1 -1 152696 -1 -1 2482 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 653024 257 32 32168 31683 1 18642 2782 60 60 3600 clb auto 199.91 246916 77.04 0.41 16.0631 -22271.7 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0.0855782 0.00818 0.3412 0.01568 0.6432 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml diffeq2.v common 12.85 0.05 8352 14 0.28 -1 -1 33504 -1 -1 26 66 0 7 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 69816 66 96 719 590 1 522 195 18 18 324 mult_36 auto 0.24 4698 0.57 0.00 15.3166 -899.181 -15.3166 15.3166 0.72 0.00146677 0.00135197 0.310634 0.282634 50 11023 27 1.57076e+07 4.17324e+06 1.01953e+06 3146.70 7.66 0.941489 0.865458 9164 17 2835 6624 2911113 732283 17.4293 17.4293 -1057.83 -17.4293 0 0 1.31112e+06 4046.65 0.24 0.52 0.0814129 0.0766058 0.01032 0.3102 0.01927 0.6706 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 991.70 20.82 227552 129 272.40 -1 -1 100728 -1 -1 1844 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 575992 114 102 29578 29304 1 15488 2112 52 52 2704 clb auto 204.12 218897 46.23 0.26 70.1192 -51431.5 -70.1192 70.1192 25.82 0.0557967 0.0471795 9.9385 7.31465 102 319152 33 1.58905e+08 1.26664e+08 1.78867e+07 6614.90 285.48 38.0077 29.3571 293704 19 59621 235362 44721484 9984605 79.8495 79.8495 -65611.6 -79.8495 -12.7907 -0.295467 2.24325e+07 8296.04 6.78 14.66 4.19921 3.52002 0.1049 0.3984 0.01026 0.5913 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml LU32PEEng.v common 8335.23 170.81 770436 128 1442.63 -1 -1 298516 -1 -1 6516 114 167 32 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 2051868 114 102 102506 101104 1 54494 6931 96 96 9216 clb auto 808.62 1044778 450.89 2.20 68.8178 -305537 -68.8178 68.8178 90.43 0.246295 0.207807 45.7569 34.6771 134 1416605 43 5.62531e+08 4.55327e+08 7.95217e+07 8628.65 4820.23 191.196 149.235 1320145 19 205747 867559 280552175 73459018 79.4826 79.4826 -431452 -79.4826 -18.9655 -0.29436 1.01618e+08 11026.2 33.54 118.98 18.3662 15.5502 0.4221 0.456 0.009206 0.5348 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml mcml.v common 12058.87 65.57 954184 75 9100.81 -1 -1 447760 -1 -1 6994 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 1892932 36 33 134466 132924 1 42567 7249 99 99 9801 clb auto 231.53 503257 276.18 1.59 58 -286364 -58 58 92.88 0.183093 0.154545 36.0139 27.4517 84 720728 49 6.00857e+08 4.74722e+08 5.61951e+07 5733.61 1714.33 145.148 116.225 661785 19 160918 494750 89979470 20715328 63.9293 63.9293 -350198 -63.9293 0 0 7.13851e+07 7283.45 25.25 34.77 12.471 10.6618 0.311 0.3482 0.01347 0.6383 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml mkDelayWorker32B.v common 83.49 1.09 78788 5 9.84 -1 -1 52504 -1 -1 456 506 47 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 319444 506 553 3285 3838 1 3022 1562 50 50 2500 memory auto 3.54 14298 5.13 0.03 6.71903 -1709.56 -6.71903 6.71903 18.85 0.0116391 0.0105543 2.60085 2.328 38 21968 15 1.47946e+08 5.03323e+07 6.86584e+06 2746.33 25.57 6.56725 6.00387 21087 16 4239 5383 4422419 1140648 7.15342 7.15342 -2239.08 -7.15342 -1.97725 -0.217081 8.69095e+06 3476.38 2.44 1.18 0.529048 0.497642 0.1823 0.1299 0.03963 0.8305 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml mkPktMerge.v common 23.40 0.10 16980 2 0.11 -1 -1 33700 -1 -1 26 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 90800 311 156 972 1128 1 953 508 28 28 784 memory auto 0.54 8291 1.40 0.01 4.09443 -4075.92 -4.09443 4.09443 2.57 0.00251173 0.00214987 0.698141 0.592902 36 14945 22 4.25198e+07 9.62124e+06 1.94918e+06 2486.20 12.22 2.02292 1.77741 13861 16 2949 3439 2774694 801507 4.54352 4.54352 -4989.89 -4.54352 -15.4115 -0.339827 2.40571e+06 3068.51 0.56 0.58 0.118153 0.107078 0.08554 0.1456 0.01648 0.8379 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml mkSMAdapter4B.v common 22.23 0.32 32020 7 2.63 -1 -1 37908 -1 -1 162 193 5 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 85048 193 205 2232 2437 1 1246 565 20 20 400 memory auto 2.17 9201 1.64 0.01 4.61852 -2566.21 -4.61852 4.61852 0.73 0.00312794 0.00247119 0.593516 0.479019 52 17036 22 2.07112e+07 1.14708e+07 1.31074e+06 3276.84 8.73 1.75981 1.48859 15454 16 4604 11241 1090818 249095 5.90007 5.90007 -3053.05 -5.90007 -10.2359 -0.339827 1.72518e+06 4312.96 0.41 0.46 0.2407 0.217865 0.02878 0.2101 0.02483 0.765 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml or1200.v common 94.07 0.53 40836 27 6.16 -1 -1 43596 -1 -1 225 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 117008 385 394 3979 4310 1 2344 1007 27 27 729 io auto 2.33 30480 3.65 0.03 12.8271 -11470.3 -12.8271 12.8271 1.64 0.00731674 0.00651191 1.20104 0.993064 78 52764 50 3.93038e+07 1.36182e+07 3.65949e+06 5019.88 66.55 5.62229 4.89842 44918 15 10820 38559 2823326 504017 14.8802 14.8802 -12878.2 -14.8802 0 0 4.63207e+06 6354.00 1.06 0.90 0.419152 0.38172 0.02472 0.4233 0.02389 0.5529 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml raygentop.v common 53.77 0.44 32980 8 1.81 -1 -1 40540 -1 -1 112 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 87596 214 305 2625 2741 1 1480 640 22 22 484 mult_36 auto 26.11 12249 1.31 0.01 4.3155 -2361.4 -4.3155 4.3155 1.00 0.00334942 0.00290708 0.45395 0.389067 52 27409 32 2.50602e+07 9.60013e+06 1.61880e+06 3344.62 15.18 1.84791 1.62495 22603 23 7808 17648 5084943 1131570 5.03078 5.03078 -2997.26 -5.03078 0 0 2.13063e+06 4402.12 0.43 1.03 0.236297 0.214374 0.0252 0.4216 0.03923 0.5391 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml sha.v common 623.50 0.77 38148 20 593.27 -1 -1 95472 -1 -1 205 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 97036 38 36 3404 3440 1 1360 279 19 19 361 clb auto 2.12 13579 1.31 0.01 11.476 -4014.58 -11.476 11.476 0.61 0.00362419 0.00303952 0.555544 0.408923 62 22039 46 1.72706e+07 1.10483e+07 1.42202e+06 3939.11 11.81 1.89391 1.51108 19536 17 5440 19490 633132 108489 13.5704 13.5704 -4723.34 -13.5704 0 0 1.76637e+06 4892.99 0.57 0.77 0.559275 0.495515 0.01144 0.3451 0.02564 0.6293 diff --git a/vtr_flow/tasks/power/power_nofrac/config/config.txt b/vtr_flow/tasks/power/power_nofrac/config/config.txt index 9f4424a60d0..ccb26327370 100644 --- a/vtr_flow/tasks/power/power_nofrac/config/config.txt +++ b/vtr_flow/tasks/power/power_nofrac/config/config.txt @@ -29,16 +29,20 @@ circuit_list_add=mkSMAdapter4B.v circuit_list_add=or1200.v circuit_list_add=raygentop.v circuit_list_add=sha.v -circuit_list_add=stereovision0.v -circuit_list_add=stereovision1.v -circuit_list_add=stereovision2.v +#These circuits do not go through ACE2. It falsely thinks there are multiple clocks in the circuit. There is a bug with using module instantiation by port when two modules have different names for their clocks, in this case instantiation by name must be used. Tried altering the instantiation method & clock names but did not work. This fixed the error for raygentop.v +#circuit_list_add=stereovision0.v +#circuit_list_add=stereovision1.v +#circuit_list_add=stereovision2.v + #circuit_list_add=stereovision3.v # Add architectures to list to sweep arch_list_add=k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml # Parse info and how to parse -parse_file=vpr_power_detailed.txt +#vpr_power_detailed.txt produces incompelete QoR results. (Issue #1749) +#parse_file=vpr_power_detailed.txt +parse_file=vpr_power.txt # Pass requirements -pass_requirements_file=pass_requirements.txt +pass_requirements_file=pass_requirements_power.txt diff --git a/vtr_flow/tasks/power/power_nofrac/config/golden_results.txt b/vtr_flow/tasks/power/power_nofrac/config/golden_results.txt new file mode 100644 index 00000000000..effb934e1dc --- /dev/null +++ b/vtr_flow/tasks/power/power_nofrac/config/golden_results.txt @@ -0,0 +1,16 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml bgm.v common 996.18 24.11 392624 22 457.33 -1 -1 152636 -1 -1 3241 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 697664 257 32 32168 31683 1 18834 3541 69 69 4761 clb auto 12.54 272663 104.20 0.61 16.0544 -23810.1 -16.0544 16.0544 39.75 0.0686501 0.0581941 11.2309 8.30308 72 421149 26 2.85477e+08 1.79025e+08 2.26653e+07 4760.63 217.54 43.9413 34.5636 396386 19 86912 410164 24647680 4045668 18.3051 18.3051 -26433.6 -18.3051 0 0 2.84096e+07 5967.16 9.56 12.95 6.60088 5.56121 0.176 0.485 0.0303 0.4847 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml blob_merge.v common 160.77 0.45 59324 18 81.60 -1 -1 67688 -1 -1 685 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 157052 36 100 6600 6700 1 2841 821 33 33 1089 clb auto 1.90 49880 5.37 0.04 9.11388 -2669.3 -9.11388 9.11388 2.50 0.0106408 0.00902749 1.68607 1.2263 58 78148 39 6.0475e+07 3.69175e+07 4.04653e+06 3715.82 49.10 7.17606 5.76709 69473 14 12378 69462 3117547 388750 10.1476 10.1476 -2988.64 -10.1476 0 0 5.16078e+06 4739.01 1.23 1.29 0.677391 0.599031 0.02438 0.3962 0.04361 0.5602 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml boundtop.v common 6.28 0.71 46972 2 0.57 -1 -1 37096 -1 -1 89 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 66172 114 192 455 647 1 308 395 14 14 196 clb auto 0.09 736 0.36 0.00 1.76159 -209.498 -1.76159 1.76159 0.28 0.000584678 0.000515708 0.0983276 0.0862735 36 2153 23 9.20055e+06 4.79657e+06 427814. 2182.73 1.52 0.295519 0.263969 1732 10 542 787 55965 15257 2.29042 2.29042 -260.053 -2.29042 0 0 528560. 2696.73 0.15 0.05 0.0302233 0.0277977 0.006247 0.4018 0.129 0.4692 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml ch_intrinsics.v common 3.72 0.05 9228 3 0.28 -1 -1 36108 -1 -1 70 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 64036 99 130 363 493 1 254 300 12 12 144 clb auto 0.07 624 0.27 0.00 1.9342 -205.561 -1.9342 1.9342 0.26 0.000420454 0.000368236 0.0728933 0.0630404 36 1776 21 5.66058e+06 4.32058e+06 292866. 2033.79 1.15 0.219287 0.192795 1461 12 598 830 76776 25694 2.6407 2.6407 -248.082 -2.6407 0 0 363034. 2521.07 0.09 0.05 0.0254275 0.0233243 0.00729 0.2201 0.07406 0.7058 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml diffeq1.v common 13.22 0.04 9144 15 0.48 -1 -1 34588 -1 -1 52 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 78820 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.25 5402 0.91 0.01 20.0113 -1727.78 -20.0113 20.0113 0.61 0.00338847 0.00310892 0.403941 0.359303 52 11718 35 1.21132e+07 4.78249e+06 771607. 3014.09 7.25 1.04816 0.945674 9869 20 3159 6858 2186883 579440 22.1421 22.1421 -1952.73 -22.1421 0 0 1.01513e+06 3965.34 0.18 0.39 0.0892249 0.0832632 0.007598 0.3771 0.01802 0.6049 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml diffeq2.v common 14.19 0.02 8228 14 0.32 -1 -1 33492 -1 -1 37 66 0 7 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 69732 66 96 719 590 1 552 206 18 18 324 mult_36 auto 0.20 4964 0.80 0.01 15.2103 -911.934 -15.2103 15.2103 0.86 0.00316724 0.00291963 0.432401 0.393932 38 12603 25 1.57076e+07 4.76608e+06 768853. 2373.00 7.71 1.04453 0.959193 10465 19 2941 6917 2782951 674398 17.613 17.613 -1073 -17.613 0 0 971792. 2999.36 0.32 0.78 0.157262 0.148259 0.008925 0.3264 0.01978 0.6538 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml LU8PEEng.v common 1078.19 21.20 227532 129 258.81 -1 -1 100820 -1 -1 2654 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 602232 114 102 29578 29304 1 15480 2922 62 62 3844 clb auto 12.14 231440 68.57 0.36 74.447 -57558.1 -74.447 74.447 28.18 0.0683549 0.0484705 11.7172 8.54631 74 345516 35 2.30929e+08 1.70314e+08 1.86412e+07 4849.42 572.48 39.4707 30.3522 322242 21 58780 244354 38044494 7494189 86.8479 86.8479 -74857.6 -86.8479 -13.2074 -0.293253 2.32921e+07 6059.34 6.83 12.38 4.21141 3.46641 0.1006 0.4297 0.01197 0.5584 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml LU32PEEng.v common 4802.37 169.65 770560 128 1480.56 -1 -1 298640 -1 -1 9168 114 167 32 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 2182068 114 102 102506 101104 1 54645 9583 113 113 12769 clb auto 57.57 1112759 598.94 2.87 75.4885 -376364 -75.4885 75.4885 80.55 0.25457 0.211431 43.5632 32.7369 106 1477755 46 7.84268e+08 5.98238e+08 8.53330e+07 6682.83 1879.38 172.359 135.102 1390670 18 192854 861898 244824100 63341117 85.4957 85.4957 -505886 -85.4957 -25.031 -0.172573 1.08019e+08 8459.43 37.33 92.77 16.9632 14.5404 0.4082 0.4932 0.0107 0.4961 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml mcml.v common 12558.62 67.96 954112 75 9020.24 -1 -1 447752 -1 -1 8821 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 1959676 36 33 134466 132924 1 42854 9076 111 111 12321 clb auto 45.18 575706 333.87 2.01 60.7822 -295117 -60.7822 60.7822 77.75 0.185888 0.154855 36.2428 27.7376 72 778217 49 7.58755e+08 5.73176e+08 5.96025e+07 4837.47 2414.79 132.258 106.03 727476 19 143272 491382 85992415 20238847 67.3582 67.3582 -447037 -67.3582 -0.103902 -0.0259755 7.48566e+07 6075.53 29.25 33.44 12.979 10.9948 0.302 0.3843 0.01466 0.6011 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml mkDelayWorker32B.v common 84.85 0.92 78736 5 11.67 -1 -1 52380 -1 -1 503 506 47 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 267320 506 553 3285 3838 1 3016 1609 50 50 2500 memory auto 3.48 14770 5.49 0.04 6.53689 -1745.91 -6.53689 6.53689 18.68 0.011478 0.0104038 2.76336 2.47792 38 22734 16 1.47946e+08 5.28654e+07 6.57953e+06 2631.81 25.67 7.52918 6.89426 21776 15 4094 5229 3971502 1020635 7.2002 7.2002 -2141.68 -7.2002 -1.75953 -0.218188 8.28755e+06 3315.02 2.59 1.12 0.51092 0.480739 0.1667 0.1414 0.03866 0.8199 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml mkPktMerge.v common 22.93 0.14 16972 2 0.13 -1 -1 33700 -1 -1 32 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 91656 311 156 972 1128 1 953 514 28 28 784 memory auto 0.40 7734 1.21 0.01 4.26529 -4145.29 -4.26529 4.26529 2.09 0.00386849 0.00326477 0.556787 0.470656 36 14427 19 4.25198e+07 9.94461e+06 1.86960e+06 2384.70 13.34 2.09046 1.84932 13092 12 2490 2836 2393772 710314 4.393 4.393 -4974.69 -4.393 -24.4362 -0.341744 2.30301e+06 2937.52 0.57 0.51 0.0981844 0.089379 0.08209 0.1482 0.01757 0.8342 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml mkSMAdapter4B.v common 25.51 0.37 31972 7 3.61 -1 -1 37864 -1 -1 194 193 5 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 84592 193 205 2232 2437 1 1205 597 20 20 400 memory auto 0.76 9393 3.18 0.02 4.79416 -2611.33 -4.79416 4.79416 1.16 0.00690124 0.00610717 1.40618 1.16172 50 15931 20 2.07112e+07 1.31954e+07 1.21314e+06 3032.86 9.42 3.00901 2.5651 14860 19 3910 10326 905742 215407 5.57131 5.57131 -3057.06 -5.57131 -9.74406 -0.360359 1.55522e+06 3888.04 0.48 0.61 0.373151 0.339258 0.02725 0.2123 0.02608 0.7616 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml or1200.v common 62.80 0.46 40892 27 5.17 -1 -1 43888 -1 -1 310 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 112984 385 394 3979 4310 1 2327 1092 27 27 729 io auto 1.09 32208 6.58 0.06 13.8008 -12292.5 -13.8008 13.8008 1.60 0.0154967 0.0137496 2.29112 1.90555 66 52753 38 3.93038e+07 1.81991e+07 3.07043e+06 4211.84 36.07 5.20268 4.47628 46527 14 9945 38363 3256607 624611 15.244 15.244 -14381.7 -15.244 0 0 3.80131e+06 5214.42 0.94 0.97 0.378691 0.347548 0.02043 0.4542 0.02588 0.5199 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml raygentop.v common 27.10 0.42 32912 8 1.48 -1 -1 40568 -1 -1 164 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 85992 214 305 2625 2741 1 1484 692 22 22 484 mult_36 auto 0.94 12254 2.98 0.03 4.33375 -2436.25 -4.33375 4.33375 1.51 0.0074118 0.00667342 1.29634 1.07964 46 27339 29 2.50602e+07 1.24026e+07 1.39451e+06 2881.21 10.01 2.37762 2.03755 22113 20 7094 17358 4643777 1014001 5.16832 5.16832 -3054.89 -5.16832 0 0 1.79209e+06 3702.67 0.36 0.88 0.211034 0.192565 0.02097 0.4776 0.04283 0.4796 +k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml sha.v common 710.00 0.87 38160 20 674.57 -1 -1 95308 -1 -1 260 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 95880 38 36 3404 3440 1 1302 334 21 21 441 clb auto 1.25 15053 1.42 0.01 12.1417 -4462.98 -12.1417 12.1417 1.06 0.00406402 0.00338654 0.540501 0.397001 50 24207 39 2.24358e+07 1.40124e+07 1.34532e+06 3050.61 16.10 2.33213 1.87284 21652 18 5200 21310 701520 120083 14.6896 14.6896 -4988.15 -14.6896 0 0 1.72482e+06 3911.16 0.56 0.77 0.556845 0.493347 0.01015 0.385 0.02894 0.586 diff --git a/vtr_flow/tasks/power/power_nofrac_130nm/config/config.txt b/vtr_flow/tasks/power/power_nofrac_130nm/config/config.txt index ec5594c6f94..77ec9bcb4d8 100644 --- a/vtr_flow/tasks/power/power_nofrac_130nm/config/config.txt +++ b/vtr_flow/tasks/power/power_nofrac_130nm/config/config.txt @@ -29,16 +29,19 @@ circuit_list_add=mkSMAdapter4B.v circuit_list_add=or1200.v circuit_list_add=raygentop.v circuit_list_add=sha.v -circuit_list_add=stereovision0.v -circuit_list_add=stereovision1.v -circuit_list_add=stereovision2.v +#These circuits do not go through ACE2. It falsely thinks there are multiple clocks in the circuit. There is a bug with using module instantiation by port when two modules have different names for their clocks, in this case instantiation by name must be used. Tried altering the instantiation method & clock names but did not work. This fixed the error for raygentop.v +#circuit_list_add=stereovision0.v +#circuit_list_add=stereovision1.v +#circuit_list_add=stereovision2.v + #circuit_list_add=stereovision3.v # Add architectures to list to sweep arch_list_add=k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml # Parse info and how to parse -parse_file=vpr_power_detailed.txt - +#vpr_power_detailed.txt produces incompelete QoR results. (Issue #1749) +#parse_file=vpr_power_detailed.txt +parse_file=vpr_power.txt # Pass requirements -pass_requirements_file=pass_requirements.txt +pass_requirements_file=pass_requirements_power.txt diff --git a/vtr_flow/tasks/power/power_nofrac_130nm/config/golden_results.txt b/vtr_flow/tasks/power/power_nofrac_130nm/config/golden_results.txt new file mode 100644 index 00000000000..b02990caeb2 --- /dev/null +++ b/vtr_flow/tasks/power/power_nofrac_130nm/config/golden_results.txt @@ -0,0 +1,16 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml bgm.v common 1001.49 21.76 392604 22 498.71 -1 -1 152660 -1 -1 3226 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 688364 257 32 32168 31683 1 18850 3526 68 68 4624 clb auto 17.47 261060 87.67 0.59 17.8318 -23770.9 -17.8318 17.8318 30.56 0.0778818 0.056732 9.6271 7.0857 66 405813 23 2.2854e+08 1.73861e+08 2.05906e+07 4452.98 205.86 40.3086 31.5187 386195 20 91510 436169 24669839 3969839 20.1129 20.1129 -26723.2 -20.1129 0 0 2.54527e+07 5504.48 7.31 12.16 5.8409 4.90804 1.317 0.3307 0.02443 0.6449 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml blob_merge.v common 167.26 0.64 59272 18 85.67 -1 -1 67556 -1 -1 688 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 157224 36 100 6600 6700 1 2823 824 33 33 1089 clb auto 1.83 51124 5.45 0.04 9.1879 -2675.84 -9.1879 9.1879 3.03 0.0107914 0.0091292 1.70375 1.25499 62 75698 38 4.93869e+07 3.70792e+07 4.34183e+06 3986.99 47.69 8.15251 6.57611 69942 13 11685 66360 2995952 372422 10.9318 10.9318 -3032.11 -10.9318 0 0 5.36507e+06 4926.60 1.67 1.73 0.959089 0.833779 0.2263 0.2852 0.02962 0.6852 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml boundtop.v common 7.91 0.79 46916 2 0.44 -1 -1 37068 -1 -1 89 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 66072 114 192 455 647 1 308 395 14 14 196 clb auto 0.09 761 0.57 0.00 1.6729 -216.114 -1.6729 1.6729 0.43 0.000980915 0.000860283 0.162867 0.140903 30 2386 29 8.01255e+06 4.79657e+06 375824. 1917.47 2.35 0.543892 0.483657 1961 9 621 864 67469 18554 2.32295 2.32295 -279.266 -2.32295 0 0 464326. 2369.01 0.13 0.05 0.0282556 0.0259956 0.04863 0.2532 0.09951 0.6473 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml ch_intrinsics.v common 3.32 0.05 9360 3 0.31 -1 -1 36188 -1 -1 70 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 64648 99 130 363 493 1 254 300 12 12 144 clb auto 0.05 637 0.31 0.00 1.99999 -206.507 -1.99999 1.99999 0.20 0.000432724 0.000379633 0.0837723 0.0723465 40 1648 20 4.86858e+06 4.32058e+06 318116. 2209.14 0.91 0.237158 0.209278 1482 12 555 807 64512 21941 2.70645 2.70645 -249.933 -2.70645 0 0 401429. 2787.70 0.10 0.03 0.0147293 0.0134884 0.04238 0.2004 0.0875 0.7121 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml diffeq1.v common 15.26 0.04 8992 15 0.43 -1 -1 34612 -1 -1 52 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 75208 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.25 5509 1.04 0.01 19.9589 -1764.56 -19.9589 19.9589 0.54 0.00345671 0.00315515 0.49119 0.441855 50 11983 29 9.73716e+06 2.80249e+06 746321. 2915.31 8.84 1.675 1.52572 9956 21 3230 6801 2149843 531129 23.0252 23.0252 -2035.7 -23.0252 0 0 955817. 3733.66 0.24 0.67 0.196275 0.182185 0.04763 0.329 0.01818 0.6528 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml diffeq2.v common 14.16 0.03 8204 14 0.33 -1 -1 33608 -1 -1 37 66 0 7 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 69676 66 96 719 590 1 552 206 18 18 324 mult_36 auto 0.13 4864 0.41 0.00 15.2361 -903.939 -15.2361 15.2361 0.52 0.00143401 0.00133028 0.201586 0.183051 38 12103 29 1.25396e+07 1.99408e+06 768853. 2373.00 8.97 1.06094 0.979285 9845 18 2999 6779 2560467 614308 17.5608 17.5608 -1085.85 -17.5608 0 0 971792. 2999.36 0.29 0.67 0.146814 0.137805 0.05563 0.2886 0.0218 0.6896 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml LU8PEEng.v common 1051.23 21.64 227552 129 257.48 -1 -1 100900 -1 -1 2650 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 601952 114 102 29578 29304 1 15467 2918 62 62 3844 clb auto 13.40 241228 52.94 0.32 74.4372 -62189.2 -74.4372 74.4372 23.52 0.0565953 0.0470431 9.63737 6.94589 78 351833 27 1.89352e+08 1.66931e+08 1.93958e+07 5045.73 553.88 31.7783 24.1038 323930 18 56919 237907 40655830 8858260 88.4711 88.4711 -81623.7 -88.4711 -9.96178 -0.204056 2.45017e+07 6374.02 7.72 14.00 4.00906 3.29306 0.8797 0.3519 0.009987 0.6381 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml LU32PEEng.v common 6447.09 169.67 770432 128 1492.76 -1 -1 298656 -1 -1 9181 114 167 32 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 2176996 114 102 102506 101104 1 54589 9596 113 113 12769 clb auto 55.87 1137762 572.17 3.06 75.71 -396743 -75.71 75.71 77.98 0.321324 0.215019 45.3253 32.6934 110 1496997 37 6.3458e+08 5.86268e+08 8.84209e+07 6924.65 3538.90 180.068 139.344 1409291 19 192509 859898 237614431 59510906 87.2402 87.2402 -561033 -87.2402 -32.0581 -0.163771 1.12508e+08 8811.03 47.89 89.00 15.769 13.0847 3.485 0.4169 0.0091 0.574 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml mcml.v common 12334.21 70.92 954100 75 8916.05 -1 -1 447688 -1 -1 8827 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 1957772 36 33 134466 132924 1 42877 9082 111 111 12321 clb auto 36.66 575500 314.82 1.83 62.6821 -323144 -62.6821 62.6821 76.41 0.186016 0.15549 32.2593 24.8172 76 743108 23 6.19761e+08 5.62809e+08 6.20212e+07 5033.78 2292.00 121.971 97.9344 721017 18 143488 487489 76331225 16939092 68.3856 68.3856 -394964 -68.3856 -0.182629 -0.0183325 7.73530e+07 6278.14 25.01 32.86 13.9467 11.9616 2.594 0.3157 0.0122 0.6721 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml mkDelayWorker32B.v common 76.49 0.83 78784 5 9.16 -1 -1 52484 -1 -1 503 506 47 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 267120 506 553 3285 3838 1 3016 1609 50 50 2500 memory auto 3.02 13920 5.12 0.04 6.28873 -1883.39 -6.28873 6.28873 14.85 0.0115589 0.0104695 2.53168 2.2625 38 21473 15 1.19435e+08 5.28654e+07 6.57953e+06 2631.81 25.11 7.18953 6.58087 20533 14 3920 4882 2935787 757946 7.26179 7.26179 -2448.47 -7.26179 -6.93636 -0.336313 8.28755e+06 3315.02 2.40 1.31 0.880661 0.81762 0.81 0.1562 0.05268 0.7912 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml mkPktMerge.v common 21.84 0.14 17016 2 0.12 -1 -1 33664 -1 -1 32 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 91676 311 156 972 1128 1 953 514 28 28 784 memory auto 0.47 8378 0.91 0.01 4.54593 -4260.94 -4.54593 4.54593 2.24 0.00273473 0.00231106 0.40801 0.339559 34 15368 24 3.53916e+07 9.94461e+06 1.78976e+06 2282.86 11.11 1.3651 1.18373 14436 11 2754 3098 2475725 741589 5.29017 5.29017 -5136.96 -5.29017 -11.9117 -0.287771 2.20520e+06 2812.76 0.77 0.78 0.147992 0.134549 0.3181 0.1761 0.02486 0.799 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml mkSMAdapter4B.v common 20.88 0.28 31960 7 3.40 -1 -1 37832 -1 -1 194 193 5 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 84480 193 205 2232 2437 1 1205 597 20 20 400 memory auto 0.75 9284 1.65 0.01 4.72106 -2630.81 -4.72106 4.72106 0.96 0.00308397 0.00262651 0.56208 0.453113 40 19411 34 1.75432e+07 1.31954e+07 997078. 2492.70 7.10 1.42987 1.19645 15360 16 4361 11140 1028207 247300 5.24416 5.24416 -3096.36 -5.24416 -3.23175 -0.336313 1.25462e+06 3136.55 0.40 0.61 0.335972 0.301138 0.1469 0.1981 0.03187 0.7701 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml or1200.v common 55.00 0.43 40860 27 4.88 -1 -1 43696 -1 -1 309 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 106532 385 394 3979 4310 1 2333 1091 27 27 729 io auto 1.70 32531 4.09 0.03 14.1081 -12584.6 -14.1081 14.1081 1.95 0.00740925 0.0065677 1.23839 1.01124 68 54523 49 3.21756e+07 1.77492e+07 3.14616e+06 4315.72 28.13 4.75921 4.14104 46739 15 9844 37757 3046413 577311 16.5388 16.5388 -14240.5 -16.5388 0 0 3.87891e+06 5320.86 0.92 0.94 0.398485 0.361806 0.1582 0.3526 0.02101 0.6264 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml raygentop.v common 24.67 0.31 32960 8 1.64 -1 -1 40480 -1 -1 164 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 86144 214 305 2625 2741 1 1484 692 22 22 484 mult_36 auto 0.75 12265 1.48 0.02 4.39099 -2475.96 -4.39099 4.39099 0.97 0.00333309 0.00291795 0.468538 0.399987 46 27273 31 2.11002e+07 8.83862e+06 1.39451e+06 2881.21 11.34 1.47185 1.28893 21854 20 7330 17866 5375653 1185020 5.02034 5.02034 -3160.56 -5.02034 0 0 1.79209e+06 3702.67 0.37 0.93 0.198049 0.18148 0.1435 0.3317 0.0431 0.6252 +k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml sha.v common 682.24 0.86 38196 20 656.07 -1 -1 95308 -1 -1 260 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 95664 38 36 3404 3440 1 1302 334 21 21 441 clb auto 0.86 14925 1.51 0.01 12.0697 -4701.41 -12.0697 12.0697 0.77 0.00441407 0.00311217 0.589359 0.421925 48 24188 35 1.92678e+07 1.40124e+07 1.30072e+06 2949.48 9.11 2.17633 1.73131 21808 16 5267 21888 729350 123404 14.892 14.892 -5301.84 -14.892 0 0 1.67072e+06 3788.48 0.33 0.39 0.242653 0.21569 0.09058 0.2567 0.02193 0.7214 diff --git a/vtr_flow/tasks/power/power_nofrac_22nm/config/config.txt b/vtr_flow/tasks/power/power_nofrac_22nm/config/config.txt index a1e8d766235..cf276bfda1a 100644 --- a/vtr_flow/tasks/power/power_nofrac_22nm/config/config.txt +++ b/vtr_flow/tasks/power/power_nofrac_22nm/config/config.txt @@ -29,16 +29,20 @@ circuit_list_add=mkSMAdapter4B.v circuit_list_add=or1200.v circuit_list_add=raygentop.v circuit_list_add=sha.v -circuit_list_add=stereovision0.v -circuit_list_add=stereovision1.v -circuit_list_add=stereovision2.v +#These circuits do not go through ACE2. It falsely thinks there are multiple clocks in the circuit. There is a bug with using module instantiation by port when two modules have different names for their clocks, in this case instantiation by name must be used. Tried altering the instantiation method & clock names but did not work. This fixed the error for raygentop.v +#circuit_list_add=stereovision0.v +#circuit_list_add=stereovision1.v +#circuit_list_add=stereovision2.v + #circuit_list_add=stereovision3.v # Add architectures to list to sweep arch_list_add=k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml # Parse info and how to parse -parse_file=vpr_power_detailed.txt +#vpr_power_detailed.txt produces incompelete QoR results. (Issue #1749) +#parse_file=vpr_power_detailed.txt +parse_file=vpr_power.txt # Pass requirements -pass_requirements_file=pass_requirements.txt +pass_requirements_file=pass_requirements_power.txt diff --git a/vtr_flow/tasks/power/power_nofrac_22nm/config/golden_results.txt b/vtr_flow/tasks/power/power_nofrac_22nm/config/golden_results.txt new file mode 100644 index 00000000000..5bb0326e557 --- /dev/null +++ b/vtr_flow/tasks/power/power_nofrac_22nm/config/golden_results.txt @@ -0,0 +1,16 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml bgm.v common 996.00 22.76 392552 22 484.66 -1 -1 152608 -1 -1 3236 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 696420 257 32 32168 31683 1 18840 3536 69 69 4761 clb auto 12.75 268683 88.75 0.77 16.6755 -23588.6 -16.6755 16.6755 35.99 0.0685939 0.0581003 9.92569 7.33289 66 415301 39 2.85477e+08 1.78756e+08 2.12066e+07 4454.23 208.60 40.8397 32.0344 392814 19 94025 445220 23579087 3649236 18.8456 18.8456 -26085.3 -18.8456 0 0 2.62127e+07 5505.72 9.41 12.87 6.10538 5.12512 0.4132 0.5778 0.009963 0.4123 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml blob_merge.v common 163.11 0.51 59312 18 85.26 -1 -1 67664 -1 -1 693 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 156548 36 100 6600 6700 1 2812 829 33 33 1089 clb auto 2.76 49117 5.91 0.05 9.00635 -2550.31 -9.00635 9.00635 4.65 0.021806 0.0161817 1.90562 1.41555 58 75913 46 6.0475e+07 3.73487e+07 4.04653e+06 3715.82 41.19 8.6833 7.02027 68205 13 12026 67946 2984964 374164 10.0384 10.0384 -2844.79 -10.0384 0 0 5.16078e+06 4739.01 1.25 1.25 0.665477 0.58228 0.0724 0.5442 0.009035 0.4468 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml boundtop.v common 5.35 0.65 47004 2 0.37 -1 -1 37032 -1 -1 89 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 66368 114 192 455 647 1 308 395 14 14 196 clb auto 0.09 759 0.31 0.00 1.6727 -215.299 -1.6727 1.6727 0.28 0.000601197 0.000524328 0.0837469 0.0730603 30 2171 17 9.20055e+06 4.79657e+06 375824. 1917.47 1.29 0.262802 0.234885 1889 9 584 863 65781 17855 2.22723 2.22723 -273.702 -2.22723 0 0 464326. 2369.01 0.09 0.03 0.0161 0.0149204 0.008546 0.539 0.03692 0.4241 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml ch_intrinsics.v common 3.22 0.05 9352 3 0.19 -1 -1 36108 -1 -1 70 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 64504 99 130 363 493 1 254 300 12 12 144 clb auto 0.07 650 0.26 0.00 1.98229 -203.664 -1.98229 1.98229 0.18 0.000422446 0.000371088 0.0726229 0.0626495 38 1539 19 5.66058e+06 4.32058e+06 306247. 2126.71 0.95 0.229358 0.202873 1364 11 498 718 49506 17330 2.41077 2.41077 -237.454 -2.41077 0 0 388532. 2698.14 0.09 0.04 0.0237922 0.0218133 0.008025 0.4683 0.03177 0.4999 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml diffeq1.v common 8.45 0.04 9056 15 0.30 -1 -1 34548 -1 -1 52 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 78956 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.25 5449 0.57 0.01 19.6298 -1714.57 -19.6298 19.6298 0.38 0.00162281 0.00148249 0.232576 0.208213 46 12294 42 1.21132e+07 4.78249e+06 696785. 2721.82 3.66 0.703549 0.638643 10169 20 3095 6756 2162390 571562 22.2543 22.2543 -1981.03 -22.2543 0 0 894618. 3494.60 0.16 0.39 0.09022 0.0840685 0.01466 0.5784 0.007708 0.4139 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml diffeq2.v common 11.01 0.02 8264 14 0.34 -1 -1 33480 -1 -1 37 66 0 7 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 69840 66 96 719 590 1 552 206 18 18 324 mult_36 auto 0.19 4999 0.43 0.00 15.1924 -898.447 -15.1924 15.1924 0.53 0.00141419 0.00130537 0.205988 0.187271 46 12114 41 1.57076e+07 4.76608e+06 907093. 2799.67 6.09 0.748677 0.68775 9933 21 2835 6543 3130704 735040 17.4114 17.4114 -1054.2 -17.4114 0 0 1.16496e+06 3595.55 0.21 0.48 0.0818561 0.0763921 0.01788 0.5725 0.008565 0.4189 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml LU8PEEng.v common 1113.60 20.34 227632 129 275.28 -1 -1 100716 -1 -1 2649 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 601916 114 102 29578 29304 1 15497 2917 62 62 3844 clb auto 13.06 237129 62.44 0.36 72.5287 -56507.2 -72.5287 72.5287 25.66 0.056505 0.0484137 9.82269 7.10417 78 347366 30 2.30929e+08 1.70045e+08 1.93958e+07 5045.73 598.26 33.802 26.018 319188 17 56175 236677 33775645 7134565 85.2757 85.2757 -68022.2 -85.2757 -39.3096 -0.304527 2.45017e+07 6374.02 7.66 12.30 4.21977 3.51433 0.3441 0.6076 0.006901 0.3855 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml LU32PEEng.v common 15356.79 172.49 770484 128 1432.68 -1 -1 298492 -1 -1 9172 114 167 32 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 2054164 114 102 102506 101104 1 54560 9587 113 113 12769 clb auto 49.87 1125296 595.51 3.44 73.7538 -356623 -73.7538 73.7538 92.43 0.567144 0.424096 47.588 34.9825 104 1482043 41 7.84268e+08 5.98453e+08 8.40019e+07 6578.58 12454.20 151.121 117.377 1403946 17 192077 858205 263181417 67543863 84.0599 84.0599 -490488 -84.0599 -15.2404 -0.180527 1.06512e+08 8341.49 36.57 95.65 14.8559 12.251 1.403 0.6605 0.006032 0.3334 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml mcml.v common 11462.80 70.82 954224 75 9095.38 -1 -1 447776 -1 -1 8823 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 1956568 36 33 134466 132924 1 42817 9078 111 111 12321 clb auto 36.55 558325 301.46 1.94 59.2298 -306548 -59.2298 59.2298 78.00 0.185798 0.155767 30.5864 23.4743 68 763856 45 7.58755e+08 5.73284e+08 5.71375e+07 4637.40 1319.29 124.824 100.048 705876 19 148843 504532 75600543 16974510 65.3806 65.3806 -383798 -65.3806 -0.194093 -0.0485233 7.04391e+07 5717.00 22.66 28.95 11.6583 10.0265 0.9287 0.5608 0.007892 0.4313 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml mkDelayWorker32B.v common 81.67 1.14 78756 5 9.78 -1 -1 52568 -1 -1 504 506 47 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 267552 506 553 3285 3838 1 3022 1610 50 50 2500 memory auto 4.17 14409 5.16 0.04 6.47354 -1700.16 -6.47354 6.47354 16.12 0.0116911 0.0106314 2.56244 2.29056 38 22080 17 1.47946e+08 5.29193e+07 6.57953e+06 2631.81 25.06 7.2849 6.66912 21046 14 3647 4659 3366712 828652 7.40517 7.40517 -2143.07 -7.40517 -7.58418 -0.229289 8.28755e+06 3315.02 2.44 0.96 0.476925 0.449357 0.165 0.3903 0.02078 0.5889 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml mkPktMerge.v common 21.34 0.15 17044 2 0.13 -1 -1 33644 -1 -1 32 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 91816 311 156 972 1128 1 953 514 28 28 784 memory auto 0.46 8001 1.45 0.02 3.70978 -3981.66 -3.70978 3.70978 2.52 0.00964772 0.00848806 0.696781 0.595823 38 14152 13 4.25198e+07 9.94461e+06 1.95643e+06 2495.44 10.53 1.74935 1.52648 12908 12 2387 2684 2258138 638401 4.13117 4.13117 -4657.46 -4.13117 -28.4004 -0.328977 2.46901e+06 3149.24 0.62 0.45 0.0963053 0.0880007 0.0681 0.3582 0.01069 0.6311 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml mkSMAdapter4B.v common 23.84 0.37 31964 7 3.79 -1 -1 37944 -1 -1 192 193 5 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 84352 193 205 2232 2437 1 1200 595 20 20 400 memory auto 0.55 9400 1.60 0.01 4.48327 -2633.22 -4.48327 4.48327 0.69 0.00284841 0.00243428 0.547671 0.442183 46 17302 26 2.07112e+07 1.30876e+07 1.13224e+06 2830.60 9.58 2.17408 1.8639 15204 15 4316 11205 988592 237733 5.40424 5.40424 -3031.51 -5.40424 -6.91684 -0.344875 1.45490e+06 3637.26 0.41 0.56 0.321683 0.293747 0.03032 0.4566 0.01191 0.5315 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml or1200.v common 56.74 0.60 40792 27 6.05 -1 -1 43664 -1 -1 305 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 111260 385 394 3979 4310 1 2325 1087 27 27 729 io auto 1.09 32178 6.38 0.07 13.569 -11878.3 -13.569 13.569 1.59 0.0225141 0.0201672 2.4187 2.01787 70 52633 43 3.93038e+07 1.79297e+07 3.21761e+06 4413.73 27.32 6.23023 5.40292 46310 13 9634 37512 2966762 564542 15.0206 15.0206 -13271.1 -15.0206 0 0 4.03559e+06 5535.79 1.42 1.56 0.721129 0.650534 0.05521 0.6228 0.007223 0.37 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml raygentop.v common 22.93 0.38 32936 8 1.39 -1 -1 40440 -1 -1 164 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 85908 214 305 2625 2741 1 1484 692 22 22 484 mult_36 auto 0.71 12198 1.39 0.02 4.40807 -2352.47 -4.40807 4.40807 0.91 0.00325733 0.00284932 0.4473 0.382488 46 26824 35 2.50602e+07 1.24026e+07 1.39451e+06 2881.21 10.23 1.76302 1.5453 21725 17 6484 15419 4582616 1017667 4.82511 4.82511 -2928.15 -4.82511 0 0 1.79209e+06 3702.67 0.49 1.02 0.245602 0.225696 0.03159 0.5833 0.01469 0.402 +k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml sha.v common 682.91 0.82 38152 20 651.39 -1 -1 95488 -1 -1 260 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 95608 38 36 3404 3440 1 1302 334 21 21 441 clb auto 1.24 15283 1.47 0.01 11.9452 -4468.63 -11.9452 11.9452 0.84 0.00498693 0.00354808 0.577831 0.409821 50 24872 32 2.24358e+07 1.40124e+07 1.34532e+06 3050.61 13.14 2.28158 1.81238 21995 16 5111 20558 675574 115537 14.0924 14.0924 -4962.06 -14.0924 0 0 1.72482e+06 3911.16 0.46 0.44 0.286126 0.245556 0.02763 0.5125 0.007754 0.4797 diff --git a/vtr_flow/tasks/power/power_quick/config/config.txt b/vtr_flow/tasks/power/power_quick/config/config.txt index b89ebd2adb8..b61b38dbc8d 100644 --- a/vtr_flow/tasks/power/power_quick/config/config.txt +++ b/vtr_flow/tasks/power/power_quick/config/config.txt @@ -41,4 +41,4 @@ arch_list_add=k6_frac_N10_mem32K_40nm.xml parse_file=vpr_power.txt # Pass requirements -pass_requirements_file=pass_requirements.txt +pass_requirements_file=pass_requirements_power.txt diff --git a/vtr_flow/tasks/power/power_quick/config/golden_results.txt b/vtr_flow/tasks/power/power_quick/config/golden_results.txt new file mode 100644 index 00000000000..b7986e36fa6 --- /dev/null +++ b/vtr_flow/tasks/power/power_quick/config/golden_results.txt @@ -0,0 +1,11 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml blob_merge.v common 149.42 0.67 59296 18 87.49 -1 -1 67848 -1 -1 567 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 162376 36 100 6600 6700 1 2796 703 30 30 900 clb auto 4.86 45280 5.29 0.04 9.00388 -2553.91 -9.00388 9.00388 2.16 0.0111997 0.0095747 1.81163 1.36443 64 69768 27 4.8774e+07 3.05579e+07 3.87092e+06 4301.02 27.07 6.73295 5.4421 65164 13 12410 63616 2886592 377212 10.3791 10.3791 -2909.67 -10.3791 0 0 4.83441e+06 5371.56 1.17 1.23 0.694718 0.616406 0.025 0.3666 0.03807 0.5953 +k6_frac_N10_mem32K_40nm.xml boundtop.v common 7.22 0.81 46920 2 0.57 -1 -1 37012 -1 -1 82 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 69704 114 192 455 647 1 312 388 13 13 169 clb auto 0.16 758 0.56 0.00 1.70835 -203.113 -1.70835 1.70835 0.34 0.000976047 0.000854198 0.161957 0.13986 36 2211 20 6.63067e+06 4.41931e+06 367804. 2176.36 1.64 0.460495 0.409135 1762 13 705 924 61330 17686 2.27648 2.27648 -247.759 -2.27648 0 0 456028. 2698.39 0.11 0.06 0.0383482 0.0355571 0.00733 0.3528 0.09256 0.5546 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.29 0.05 9292 3 0.30 -1 -1 36152 -1 -1 65 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 70896 99 130 363 493 1 251 295 12 12 144 clb auto 0.12 615 0.39 0.00 1.97933 -202.994 -1.97933 1.97933 0.29 0.000637589 0.000549661 0.107568 0.0916289 46 1389 13 5.66058e+06 4.05111e+06 378970. 2631.74 1.33 0.336025 0.295263 1274 8 580 750 63298 22590 2.47625 2.47625 -241.499 -2.47625 0 0 486261. 3376.82 0.12 0.05 0.0233275 0.0215625 0.009076 0.2039 0.07227 0.7239 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 10.76 0.04 9160 15 0.46 -1 -1 34596 -1 -1 36 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 70556 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.38 5304 0.90 0.01 19.7038 -1798.95 -19.7038 19.7038 0.61 0.00289557 0.00265919 0.431869 0.386185 50 11378 23 1.21132e+07 3.92018e+06 780512. 3048.87 4.63 0.961355 0.870492 9589 21 3086 6045 1539878 392193 22.8395 22.8395 -2030.13 -22.8395 0 0 1.00276e+06 3917.05 0.21 0.37 0.11341 0.106043 0.007811 0.3508 0.0162 0.633 +k6_frac_N10_mem32K_40nm.xml diffeq2.v common 12.30 0.03 8308 14 0.34 -1 -1 33544 -1 -1 29 66 0 7 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 70008 66 96 719 590 1 525 198 18 18 324 mult_36 auto 0.30 4790 0.42 0.00 15.3213 -871.24 -15.3213 15.3213 0.84 0.00141308 0.00131027 0.217961 0.199231 38 11506 50 1.57076e+07 4.33493e+06 803540. 2480.06 6.24 0.860594 0.793647 10051 18 2900 6407 2371930 564906 18.2473 18.2473 -1032.11 -18.2473 0 0 1.01953e+06 3146.70 0.29 0.65 0.158463 0.148985 0.009421 0.3037 0.01834 0.678 +k6_frac_N10_mem32K_40nm.xml mkPktMerge.v common 17.82 0.16 16964 2 0.11 -1 -1 33736 -1 -1 27 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 90796 311 156 972 1128 1 953 509 28 28 784 memory auto 0.53 7827 0.86 0.01 3.90797 -4026.08 -3.90797 3.90797 1.71 0.00249662 0.00213566 0.378096 0.317729 36 14479 14 4.25198e+07 9.67514e+06 1.94918e+06 2486.20 8.42 1.27326 1.11249 13472 13 2891 3230 2215365 647096 4.52093 4.52093 -4789.05 -4.52093 -25.8456 -0.339827 2.40571e+06 3068.51 0.83 0.47 0.107209 0.0976762 0.08502 0.1435 0.01666 0.8399 +k6_frac_N10_mem32K_40nm.xml mkSMAdapter4B.v common 25.22 0.36 31976 7 2.69 -1 -1 37956 -1 -1 165 193 5 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 86772 193 205 2232 2437 1 1190 568 20 20 400 memory auto 1.29 8936 1.62 0.01 4.44855 -2528.04 -4.44855 4.44855 0.75 0.00282609 0.00241744 0.586948 0.474437 48 17495 46 2.07112e+07 1.16325e+07 1.23055e+06 3076.38 11.51 1.93275 1.63513 14708 14 4521 11092 1106779 263595 5.53986 5.53986 -2984.41 -5.53986 -4.85712 -0.29436 1.57502e+06 3937.55 0.36 0.34 0.169369 0.155213 0.0293 0.2036 0.02481 0.7716 +k6_frac_N10_mem32K_40nm.xml or1200.v common 70.22 0.55 40832 27 5.31 -1 -1 43828 -1 -1 259 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 115772 385 394 3979 4310 1 2379 1041 27 27 729 io auto 3.47 31242 3.72 0.03 13.271 -13061.1 -13.271 13.271 1.72 0.00762478 0.00673748 1.16799 0.97424 76 51110 29 3.93038e+07 1.54505e+07 3.58343e+06 4915.54 41.99 4.90125 4.28119 46131 14 10355 37426 3388428 639602 15.072 15.072 -14934.3 -15.072 0 0 4.48127e+06 6147.14 1.07 1.00 0.404446 0.371647 0.02317 0.4367 0.02471 0.5386 +k6_frac_N10_mem32K_40nm.xml raygentop.v common 30.58 0.40 32972 8 1.99 -1 -1 40616 -1 -1 107 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 88680 214 305 2625 2741 1 1449 635 22 22 484 mult_36 auto 2.38 11585 1.53 0.01 4.30664 -2400.31 -4.30664 4.30664 1.48 0.00351355 0.00308259 0.591307 0.506205 50 26386 46 2.50602e+07 9.33066e+06 1.56759e+06 3238.82 12.63 1.97252 1.73499 21391 21 7225 15930 4958964 1086872 5.40231 5.40231 -3027.78 -5.40231 0 0 2.01671e+06 4166.75 0.49 1.08 0.293596 0.265513 0.02275 0.432 0.03813 0.5299 +k6_frac_N10_mem32K_40nm.xml sha.v common 615.49 1.15 38192 20 587.49 -1 -1 95400 -1 -1 208 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 98348 38 36 3404 3440 1 1281 282 19 19 361 clb auto 1.85 13341 1.68 0.01 11.5537 -3886.76 -11.5537 11.5537 0.65 0.00374746 0.00310762 0.71887 0.544538 56 21996 28 1.72706e+07 1.121e+07 1.27879e+06 3542.35 9.80 2.90409 2.37175 19799 15 5276 20061 681706 118206 14.2741 14.2741 -4632.48 -14.2741 0 0 1.63234e+06 4521.70 0.48 0.74 0.503724 0.445712 0.01026 0.3549 0.02594 0.6191 diff --git a/vtr_flow/tasks/power/power_sparse_crossbar_sweep/config/config.txt b/vtr_flow/tasks/power/power_sparse_crossbar_sweep/config/config.txt index 9483cd8120b..56ca723a6d2 100644 --- a/vtr_flow/tasks/power/power_sparse_crossbar_sweep/config/config.txt +++ b/vtr_flow/tasks/power/power_sparse_crossbar_sweep/config/config.txt @@ -29,9 +29,12 @@ circuit_list_add=mkSMAdapter4B.v circuit_list_add=or1200.v circuit_list_add=raygentop.v circuit_list_add=sha.v -circuit_list_add=stereovision0.v -circuit_list_add=stereovision1.v -circuit_list_add=stereovision2.v +#These circuits do not go through ACE2. It falsely thinks there are multiple clocks in the circuit. There is a bug with using module instantiation by port when two modules have different names for their clocks, in this case instantiation by name must be used. Tried altering the instantiation method & clock names but did not work. This fixed the error for raygentop.v + +#circuit_list_add=stereovision0.v +#circuit_list_add=stereovision1.v +#circuit_list_add=stereovision2.v + #circuit_list_add=stereovision3.v # Add architectures to list to sweep @@ -60,7 +63,9 @@ arch_list_add=k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml arch_list_add=k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml # Parse info and how to parse -parse_file=vpr_power_detailed.txt +#vpr_power_detailed.txt produces incompelete QoR results. (Issue #1749) +#parse_file=vpr_power_detailed.txt +parse_file=vpr_power.txt # Pass requirements -pass_requirements_file=pass_requirements.txt +pass_requirements_file=pass_requirements_power.txt diff --git a/vtr_flow/tasks/power/power_sparse_crossbar_sweep/config/golden_results.txt b/vtr_flow/tasks/power/power_sparse_crossbar_sweep/config/golden_results.txt new file mode 100644 index 00000000000..e5f15020e79 --- /dev/null +++ b/vtr_flow/tasks/power/power_sparse_crossbar_sweep/config/golden_results.txt @@ -0,0 +1,331 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_N10_I40_Fi6_L4_frac1_ff2_C5_45nm.xml bgm.v common 2573.82 22.75 392640 22 502.96 -1 -1 152568 -1 -1 2858 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 868484 257 32 32168 31683 1 24285 3158 65 65 4225 clb auto 515.38 282444 92.44 0.61 19.7912 -26517.5 -19.7912 19.7912 37.71 0.0666864 0.0573557 9.87265 7.38586 172 1029056 36 2.50934e+08 1.58386e+08 4.54631e+07 10760.5 1194.64 48.3091 38.0615 908674 15 95565 455534 256022540 51023360 23.6901 23.6901 -32127.2 -23.6901 0 0 5.76082e+07 13635.1 21.89 50.99 4.49249 3.7812 0.2129 0.7823 0.02247 0.1952 +k6_N10_I40_Fi6_L4_frac1_ff2_C5_45nm.xml blob_merge.v common 444.41 0.46 59416 18 78.76 -1 -1 67520 -1 -1 611 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 218680 36 100 6600 6700 1 4471 747 31 31 961 clb auto 74.28 53377 6.66 0.05 11.8407 -3349.19 -11.8407 11.8407 2.83 0.0109847 0.00933497 1.76476 1.34499 166 206947 21 5.14688e+07 3.29292e+07 9.55054e+06 9938.12 250.68 7.07731 5.69042 179520 11 13384 73496 40471721 8111907 15.7863 15.7863 -3999.38 -15.7863 0 0 1.21559e+07 12649.3 3.13 7.40 0.664959 0.584195 0.03277 0.7134 0.0398 0.2468 +k6_N10_I40_Fi6_L4_frac1_ff2_C5_45nm.xml boundtop.v common 10.91 0.80 47084 2 0.56 -1 -1 37044 -1 -1 84 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 66520 114 192 455 647 1 328 390 13 13 169 clb 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/home/ahmadi55/vtr-verilog-to-routing 97704 38 36 3404 3440 1 1277 303 20 20 400 clb auto 2.13 13877 1.40 0.01 13.7761 -4732.37 -13.7761 13.7761 0.83 0.00447009 0.00323393 0.580649 0.41538 112 57890 47 2.07112e+07 1.23417e+07 2.64871e+06 6621.77 71.65 3.3727 2.78766 46666 11 4727 21033 10060608 2250760 17.2865 17.2865 -5850.3 -17.2865 0 0 3.36057e+06 8401.42 0.71 1.70 0.216286 0.190174 0.01556 0.5144 0.02689 0.4588 +k6_N10_I40_Fi6_L4_frac1_ff2_C55_45nm.xml bgm.v common 1958.69 24.54 393428 22 456.66 -1 -1 152548 -1 -1 2534 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 763248 257 32 32168 31683 1 18723 2834 61 61 3721 clb auto 43.11 239755 65.51 0.48 16.4175 -23807.7 -16.4175 16.4175 31.07 0.076182 0.0544202 9.53742 6.9849 152 787984 32 2.18169e+08 1.40926e+08 3.55240e+07 9546.88 1161.04 42.8654 33.3509 710020 14 70459 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Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 69944 114 192 455 647 1 308 390 13 13 169 clb auto 0.11 732 0.48 0.00 2.02143 -236.158 -2.02143 2.02143 0.37 0.0011349 0.000981705 0.148042 0.128819 38 3291 34 6.63067e+06 4.5271e+06 384612. 2275.81 2.79 0.525306 0.469014 2793 12 757 1028 265851 86690 2.41145 2.41145 -294.624 -2.41145 0 0 489150. 2894.38 0.12 0.10 0.0365271 0.0336783 0.009067 0.4484 0.07213 0.4795 +k6_N10_I40_Fi6_L4_frac1_ff2_C55_45nm.xml ch_intrinsics.v common 4.50 0.06 10048 3 0.21 -1 -1 36132 -1 -1 68 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 71132 99 130 363 493 1 256 298 12 12 144 clb auto 0.10 734 0.40 0.00 2.09818 -221.105 -2.09818 2.09818 0.32 0.000702193 0.000600952 0.112103 0.0950978 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3.97 0.03 15.0792 -13433.6 -15.0792 15.0792 2.00 0.00739364 0.00658233 1.19567 0.991181 112 96398 30 3.93038e+07 1.81452e+07 4.78672e+06 6566.14 175.81 4.81703 4.18122 81544 12 8534 34622 21105727 4193472 17.8315 17.8315 -16194.5 -17.8315 0 0 6.07132e+06 8328.29 2.32 4.24 0.382957 0.347116 0.02656 0.5644 0.02537 0.4103 +k6_N10_I40_Fi6_L4_frac0_ff1_C40_45nm.xml raygentop.v common 51.98 0.48 33664 8 1.64 -1 -1 40488 -1 -1 164 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 86188 214 305 2625 2741 1 1484 692 22 22 484 mult_36 auto 0.59 12181 1.51 0.01 4.74402 -2690.97 -4.74402 4.74402 1.26 0.00330878 0.00289416 0.487977 0.41554 70 40611 24 2.50602e+07 1.24026e+07 2.07987e+06 4297.25 37.04 1.84034 1.62346 33989 11 5410 13450 8285227 1798926 6.04885 6.04885 -3488.97 -6.04885 0 0 2.60933e+06 5391.18 0.77 1.36 0.148465 0.137664 0.02534 0.566 0.03708 0.397 +k6_N10_I40_Fi6_L4_frac0_ff1_C40_45nm.xml sha.v common 822.70 1.18 38744 20 723.11 -1 -1 95340 -1 -1 260 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 99448 38 36 3404 3440 1 1302 334 21 21 441 clb auto 0.89 14912 1.43 0.01 14.4925 -4894.48 -14.4925 14.4925 0.97 0.00498898 0.00439777 0.56064 0.404385 102 57673 30 2.24358e+07 1.40124e+07 2.56171e+06 5808.86 78.03 2.46471 1.95423 48615 12 4676 21932 10132662 2270398 18.0821 18.0821 -5931.91 -18.0821 0 0 3.21213e+06 7283.74 1.06 1.78 0.225746 0.201192 0.01451 0.539 0.02612 0.4349 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml bgm.v common 1867.91 24.66 393248 22 470.49 -1 -1 152668 -1 -1 3241 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 810512 257 32 32168 31683 1 18834 3541 69 69 4761 clb auto 13.89 265071 107.75 0.59 18.3261 -25450 -18.3261 18.3261 36.45 0.0779382 0.0560956 12.0059 8.97188 132 877645 21 2.85477e+08 1.79025e+08 3.80409e+07 7990.10 1028.36 44.3649 34.7329 791096 16 73299 355498 216134643 43403759 21.6859 21.6859 -29935.1 -21.6859 0 0 4.86949e+07 10227.9 21.35 42.93 4.37649 3.73821 0.2553 0.5841 0.02179 0.3941 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml blob_merge.v common 449.75 0.67 60068 18 86.46 -1 -1 67492 -1 -1 685 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 196292 36 100 6600 6700 1 2841 821 33 33 1089 clb auto 2.08 48358 6.95 0.04 9.82017 -2794.46 -9.82017 9.82017 3.83 0.0152251 0.0101434 2.27703 1.6455 116 176547 24 6.0475e+07 3.69175e+07 7.47568e+06 6864.72 314.86 7.64512 5.98956 152554 11 10761 68115 42446653 8102787 12.6025 12.6025 -3337.37 -12.6025 0 0 9.39776e+06 8629.72 2.57 8.52 0.763523 0.669265 0.03656 0.5164 0.03801 0.4456 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml boundtop.v common 9.94 0.74 47708 2 0.56 -1 -1 37028 -1 -1 89 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 66520 114 192 455 647 1 308 395 14 14 196 clb auto 0.06 814 0.38 0.00 1.66682 -227.557 -1.66682 1.66682 0.37 0.000588647 0.000517582 0.104695 0.0910545 38 3658 22 9.20055e+06 4.79657e+06 447211. 2281.69 4.65 0.413109 0.367927 2833 10 575 871 232602 70865 2.34668 2.34668 -291.437 -2.34668 0 0 565754. 2886.50 0.16 0.09 0.0316647 0.0292566 0.008466 0.5066 0.09476 0.3987 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml ch_intrinsics.v common 6.07 0.06 9952 3 0.28 -1 -1 36072 -1 -1 70 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 71644 99 130 363 493 1 254 300 12 12 144 clb auto 0.07 657 0.39 0.00 2.31626 -233.028 -2.31626 2.31626 0.32 0.00067349 0.000579824 0.109123 0.0927105 40 3084 20 5.66058e+06 4.32058e+06 318116. 2209.14 3.13 0.356086 0.312811 2455 10 564 821 254447 84245 2.8143 2.8143 -275.799 -2.8143 0 0 401429. 2787.70 0.10 0.09 0.0256342 0.0235287 0.008554 0.3289 0.06249 0.6086 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml diffeq1.v common 26.76 0.04 9732 15 0.31 -1 -1 34576 -1 -1 52 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 76272 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.26 5563 0.57 0.01 21.1276 -1911.14 -21.1276 21.1276 0.59 0.00162586 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LU8PEEng.v common 1616.34 21.37 228180 129 264.49 -1 -1 100884 -1 -1 2654 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 673292 114 102 29578 29304 1 15480 2922 62 62 3844 clb auto 14.87 236321 58.24 0.39 80.7008 -61858.5 -80.7008 80.7008 27.79 0.0665593 0.0466575 8.82052 6.57842 132 680940 28 2.30929e+08 1.70314e+08 3.06624e+07 7976.69 1068.00 39.3675 30.307 594909 16 48561 207829 142036607 30088126 102.745 102.745 -79399.2 -102.745 -31.6286 -0.292146 3.92624e+07 10213.9 14.33 30.52 3.57386 2.95153 0.1383 0.5356 0.009425 0.4549 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml LU32PEEng.v common 15629.35 175.54 771144 128 1503.71 -1 -1 298376 -1 -1 9168 114 167 32 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 2253648 114 102 102506 101104 1 54645 9583 113 113 12769 clb auto 54.18 1131537 545.49 2.99 83.9332 -407110 -83.9332 83.9332 86.77 0.267652 0.22827 41.516 31.0253 168 2645891 31 7.84268e+08 5.98238e+08 1.29354e+08 10130.3 12554.58 149.524 115.761 2422059 14 158737 726763 750602129 180822827 98.0936 98.0936 -557170 -98.0936 -15.9129 -0.172573 1.63768e+08 12825.4 77.21 222.38 14.5029 12.0077 0.5459 0.573 0.008628 0.4184 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml mcml.v common 15934.67 65.71 954652 75 9233.62 -1 -1 447700 -1 -1 8821 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 2173188 36 33 134466 132924 1 42854 9076 111 111 12321 clb auto 42.13 570815 331.87 1.83 65.341 -317154 -65.341 65.341 93.91 0.194442 0.165701 34.5497 26.3928 124 1464747 39 7.58755e+08 5.73176e+08 9.52606e+07 7731.56 5491.07 136.939 109.074 1324789 15 126942 450681 330213561 69873653 77.6632 77.6632 -489206 -77.6632 -1.1874 -0.169253 1.20267e+08 9761.15 40.30 82.44 11.4742 9.85683 0.4042 0.4971 0.01188 0.491 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml mkDelayWorker32B.v common 88.49 1.17 79476 5 10.07 -1 -1 52356 -1 -1 503 506 47 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 276308 506 553 3285 3838 1 3016 1609 50 50 2500 memory auto 3.76 15118 5.18 0.04 6.2866 -1900.81 -6.2866 6.2866 17.08 0.0120865 0.0109964 2.56724 2.2944 38 26943 23 1.47946e+08 5.28654e+07 6.57953e+06 2631.81 30.23 7.41575 6.78549 25696 11 2782 3574 4484685 1191162 7.41397 7.41397 -2312.53 -7.41397 -4.68704 -0.295467 8.28755e+06 3315.02 2.91 1.18 0.451757 0.424844 0.1683 0.1514 0.03769 0.8109 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml mkPktMerge.v common 26.05 0.18 17700 2 0.14 -1 -1 33668 -1 -1 32 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 91176 311 156 972 1128 1 953 514 28 28 784 memory auto 0.47 8023 1.53 0.01 3.88478 -4298.57 -3.88478 3.88478 2.68 0.00255561 0.00216856 0.71981 0.614472 38 16522 27 4.25198e+07 9.94461e+06 1.95643e+06 2495.44 14.50 1.99291 1.74337 14932 10 2157 2461 3207853 906171 4.55911 4.55911 -4962.22 -4.55911 -19.5833 -0.360359 2.46901e+06 3149.24 0.82 0.68 0.10516 0.0963671 0.08229 0.167 0.01724 0.8158 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml mkSMAdapter4B.v common 55.31 0.31 32660 7 3.18 -1 -1 37868 -1 -1 194 193 5 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 84532 193 205 2232 2437 1 1205 597 20 20 400 memory auto 0.54 9634 1.73 0.01 5.37484 -2949.86 -5.37484 5.37484 1.05 0.00311249 0.00246185 0.601522 0.479818 76 32760 33 2.07112e+07 1.31954e+07 1.79151e+06 4478.77 39.71 1.97322 1.65933 28493 12 4280 11381 7711003 1656345 6.79893 6.79893 -3690.49 -6.79893 -8.76981 -0.360359 2.23557e+06 5588.92 0.84 2.12 0.235742 0.213957 0.02756 0.3063 0.02677 0.6669 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml or1200.v common 301.06 0.66 41636 27 5.46 -1 -1 43592 -1 -1 310 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 136324 385 394 3979 4310 1 2327 1092 27 27 729 io auto 1.50 31882 5.52 0.03 15.152 -13317.8 -15.152 15.152 2.55 0.00758503 0.00674949 1.89997 1.56643 112 101575 35 3.93038e+07 1.81991e+07 4.78672e+06 6566.14 265.77 5.46399 4.70547 82212 12 8890 35902 23638003 4768496 18.062 18.062 -15292.8 -18.062 0 0 6.07132e+06 8328.29 2.42 4.86 0.429555 0.386659 0.0272 0.5483 0.02448 0.4272 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml raygentop.v common 63.98 0.46 33612 8 1.98 -1 -1 40576 -1 -1 164 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 86908 214 305 2625 2741 1 1484 692 22 22 484 mult_36 auto 0.84 12354 1.47 0.01 4.66666 -2670.13 -4.66666 4.66666 1.12 0.00330474 0.00286817 0.475919 0.404142 70 40998 38 2.50602e+07 1.24026e+07 2.07987e+06 4297.25 47.91 2.20505 1.93834 33995 12 5454 13701 8406764 1823110 6.13744 6.13744 -3483.19 -6.13744 0 0 2.60933e+06 5391.18 0.74 1.39 0.14929 0.138429 0.02546 0.5507 0.03638 0.4129 +k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml sha.v common 740.85 0.87 38672 20 617.59 -1 -1 95312 -1 -1 260 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 99160 38 36 3404 3440 1 1302 334 21 21 441 clb auto 1.42 15093 1.78 0.01 13.9957 -4867 -13.9957 13.9957 1.77 0.00622013 0.00395888 0.76739 0.529325 102 57017 27 2.24358e+07 1.40124e+07 2.56171e+06 5808.86 98.67 3.29948 2.62369 48771 14 4711 21376 10025068 2236900 18.4009 18.4009 -5883.63 -18.4009 0 0 3.21213e+06 7283.74 0.88 1.81 0.253156 0.222136 0.01491 0.5186 0.02501 0.4564 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml bgm.v common 2085.15 22.47 393300 22 539.25 -1 -1 152568 -1 -1 3241 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 810168 257 32 32168 31683 1 18834 3541 69 69 4761 clb auto 13.14 274616 83.72 0.61 17.7364 -26019.8 -17.7364 17.7364 35.00 0.0681491 0.0580647 9.50696 7.05097 136 900120 27 2.85477e+08 1.79025e+08 3.90929e+07 8211.07 1186.20 45.6611 35.7686 793004 14 81089 393358 230719437 45977126 20.8848 20.8848 -30219.3 -20.8848 0 0 4.97065e+07 10440.4 19.88 47.51 4.1748 3.54014 0.2685 0.5709 0.02195 0.4071 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml blob_merge.v common 431.77 0.51 60132 18 86.05 -1 -1 67824 -1 -1 685 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 197072 36 100 6600 6700 1 2841 821 33 33 1089 clb auto 1.87 49746 6.00 0.09 9.97265 -2880.19 -9.97265 9.97265 3.36 0.0343134 0.0258511 2.04216 1.43713 120 173023 21 6.0475e+07 3.69175e+07 7.71890e+06 7088.06 301.83 10.0426 7.98208 149278 11 10058 63528 37052621 7212829 12.7616 12.7616 -3338.93 -12.7616 0 0 9.69442e+06 8902.13 2.56 6.71 0.607841 0.537145 0.0378 0.5066 0.03715 0.4563 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml boundtop.v common 9.25 0.85 47776 2 0.37 -1 -1 37000 -1 -1 89 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 67276 114 192 455 647 1 308 395 14 14 196 clb auto 0.10 814 0.35 0.00 1.66682 -227.557 -1.66682 1.66682 0.32 0.000583631 0.000514412 0.0966101 0.0846321 38 3676 45 9.20055e+06 4.79657e+06 447211. 2281.69 4.34 0.380709 0.339296 2858 9 564 856 216619 66961 2.34668 2.34668 -288.669 -2.34668 0 0 565754. 2886.50 0.10 0.05 0.01697 0.0156507 0.008553 0.502 0.09379 0.4042 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml ch_intrinsics.v common 4.87 0.06 9976 3 0.19 -1 -1 36104 -1 -1 70 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 71696 99 130 363 493 1 254 300 12 12 144 clb auto 0.05 657 0.26 0.00 2.31626 -233.028 -2.31626 2.31626 0.21 0.00047983 0.000414056 0.0726684 0.062402 40 3060 26 5.66058e+06 4.32058e+06 318116. 2209.14 2.53 0.277989 0.243421 2489 11 587 836 252558 83096 2.8143 2.8143 -280.417 -2.8143 0 0 401429. 2787.70 0.07 0.05 0.0150245 0.0137073 0.008723 0.3317 0.06128 0.607 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml diffeq1.v common 20.26 0.05 9844 15 0.30 -1 -1 34508 -1 -1 52 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 76136 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.17 5507 0.56 0.01 21.537 -1892.48 -21.537 21.537 0.47 0.0016454 0.00148075 0.232521 0.207066 72 18220 21 1.21132e+07 4.78249e+06 1.05993e+06 4140.35 15.14 0.847426 0.767879 15784 13 2793 6039 4154292 946454 24.84 24.84 -2312.33 -24.84 0 0 1.33020e+06 5196.10 0.24 0.64 0.0792216 0.0741311 0.008951 0.4489 0.01633 0.5348 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml diffeq2.v common 27.81 0.04 8928 14 0.23 -1 -1 33492 -1 -1 37 66 0 7 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 70184 66 96 719 590 1 552 206 18 18 324 mult_36 auto 0.22 4964 0.73 0.01 16.4065 -983.682 -16.4065 16.4065 0.61 0.00299973 0.00279931 0.391793 0.357869 52 17193 45 1.57076e+07 4.76608e+06 1.00459e+06 3100.59 21.33 0.942689 0.8669 14193 14 2792 6385 4085362 957025 20.4351 20.4351 -1217.92 -20.4351 0 0 1.32187e+06 4079.86 0.43 1.04 0.118382 0.111824 0.009525 0.3734 0.01898 0.6076 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml LU8PEEng.v common 2039.98 21.05 228328 129 295.57 -1 -1 100860 -1 -1 2654 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 675532 114 102 29578 29304 1 15480 2922 62 62 3844 clb auto 14.28 240417 85.03 0.77 81.932 -62111.7 -81.932 81.932 31.98 0.148674 0.112922 12.5899 9.47622 136 694346 27 2.30929e+08 1.70314e+08 3.15099e+07 8197.17 1432.35 44.8605 34.4272 592010 16 48384 206250 147738030 31630031 101.558 101.558 -78103.4 -101.558 -21.5483 -0.29436 4.00754e+07 10425.4 12.96 33.40 3.60158 2.98811 0.1436 0.524 0.009362 0.4666 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml LU32PEEng.v common 18536.01 171.79 771164 128 1574.86 -1 -1 298564 -1 -1 9168 114 167 32 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 2254792 114 102 102506 101104 1 54645 9583 113 113 12769 clb auto 57.22 1140377 621.50 2.99 82.5548 -401072 -82.5548 82.5548 99.19 0.255533 0.212396 46.9133 35.1076 168 2650545 49 7.84268e+08 5.98238e+08 1.29354e+08 10130.3 15244.69 176.319 137.575 2419840 16 157631 707783 799129713 196621807 99.2105 99.2105 -551955 -99.2105 -24.4489 -0.174787 1.63768e+08 12825.4 78.06 246.54 14.0694 11.5903 0.5595 0.5581 0.00841 0.4335 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml mcml.v common 15970.04 69.72 954644 75 9242.01 -1 -1 447788 -1 -1 8821 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 2177828 36 33 134466 132924 1 42854 9076 111 111 12321 clb auto 35.86 573231 326.66 1.87 66.7581 -323714 -66.7581 66.7581 93.96 0.182667 0.153564 34.0224 26.2992 128 1364710 28 7.58755e+08 5.73176e+08 9.77457e+07 7933.26 5607.21 137 109.379 1277672 14 121045 425849 273752260 60018501 77.2353 77.2353 -483299 -77.2353 -0.278334 -0.0359377 1.23461e+08 10020.4 41.46 65.72 10.3642 8.98335 0.4153 0.4901 0.01174 0.4981 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml mkDelayWorker32B.v common 88.98 1.22 79468 5 9.43 -1 -1 52416 -1 -1 503 506 47 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 275900 506 553 3285 3838 1 3016 1609 50 50 2500 memory auto 2.90 14311 6.96 0.06 6.38219 -1757.77 -6.38219 6.38219 17.95 0.0174293 0.0157669 3.43556 3.06356 38 25985 11 1.47946e+08 5.28654e+07 6.57953e+06 2631.81 29.78 7.96675 7.26188 25121 9 2666 3624 4420548 1130214 7.67786 7.67786 -2100.54 -7.67786 -2.47499 -0.295467 8.28755e+06 3315.02 2.75 1.00 0.370458 0.350057 0.1642 0.1493 0.03791 0.8128 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml mkPktMerge.v common 25.18 0.13 17676 2 0.12 -1 -1 33676 -1 -1 32 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 91484 311 156 972 1128 1 953 514 28 28 784 memory auto 0.52 8023 0.96 0.01 3.88478 -4298.57 -3.88478 3.88478 2.22 0.00266285 0.00219368 0.422808 0.355243 38 16382 24 4.25198e+07 9.94461e+06 1.95643e+06 2495.44 14.31 1.60946 1.40321 14942 13 2264 2573 3388978 953144 4.55911 4.55911 -4999.52 -4.55911 -20.2607 -0.360359 2.46901e+06 3149.24 0.94 0.70 0.104467 0.0954877 0.08267 0.1662 0.01716 0.8167 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml mkSMAdapter4B.v common 67.29 0.37 32716 7 3.13 -1 -1 37788 -1 -1 194 193 5 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 85148 193 205 2232 2437 1 1205 597 20 20 400 memory auto 0.62 9210 1.66 0.01 5.26404 -2858.15 -5.26404 5.26404 1.19 0.00295206 0.00251001 0.579448 0.465892 70 35409 42 2.07112e+07 1.31954e+07 1.68865e+06 4221.63 51.39 2.85458 2.44907 27566 13 4434 11662 6993194 1535696 6.50429 6.50429 -3495.8 -6.50429 -9.43179 -0.360359 2.11985e+06 5299.64 0.69 1.24 0.171743 0.156408 0.02837 0.292 0.02605 0.682 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml or1200.v common 212.73 0.51 41620 27 6.45 -1 -1 43848 -1 -1 310 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 137004 385 394 3979 4310 1 2327 1092 27 27 729 io auto 1.86 32211 3.81 0.03 15.0264 -13246.9 -15.0264 15.0264 2.01 0.00713456 0.00639319 1.15787 0.96535 114 96682 36 3.93038e+07 1.81991e+07 4.86480e+06 6673.25 175.35 5.22171 4.50321 83153 11 8948 35465 23133387 4532281 18.9007 18.9007 -16220 -18.9007 0 0 6.14143e+06 8424.45 2.75 7.09 0.5408 0.478472 0.02753 0.5383 0.02381 0.4379 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml raygentop.v common 63.55 0.40 33668 8 1.63 -1 -1 40540 -1 -1 164 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 87116 214 305 2625 2741 1 1484 692 22 22 484 mult_36 auto 0.65 12071 1.46 0.02 4.62805 -2632.35 -4.62805 4.62805 1.19 0.00360003 0.00317107 0.470832 0.401337 70 40205 19 2.50602e+07 1.24026e+07 2.07987e+06 4297.25 46.76 2.36446 2.10262 33588 11 5028 12606 7917289 1709081 6.56949 6.56949 -3486.24 -6.56949 0 0 2.60933e+06 5391.18 0.91 1.87 0.201998 0.186297 0.02455 0.5369 0.03533 0.4278 +k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml sha.v common 860.19 1.32 38868 20 763.59 -1 -1 95372 -1 -1 260 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 98308 38 36 3404 3440 1 1302 334 21 21 441 clb auto 1.32 14960 1.47 0.01 14.3385 -4779.46 -14.3385 14.3385 1.04 0.00443092 0.00313353 0.571567 0.408247 102 55246 21 2.24358e+07 1.40124e+07 2.56171e+06 5808.86 72.68 2.72138 2.17406 47959 12 4715 21208 9952834 2213170 18.2505 18.2505 -5823.33 -18.2505 0 0 3.21213e+06 7283.74 1.21 2.56 0.35048 0.309577 0.01544 0.5055 0.02434 0.4701 diff --git a/vtr_flow/tasks/power/power_std/config/config.txt b/vtr_flow/tasks/power/power_std/config/config.txt index d9a10998928..d6d0293e271 100644 --- a/vtr_flow/tasks/power/power_std/config/config.txt +++ b/vtr_flow/tasks/power/power_std/config/config.txt @@ -29,16 +29,20 @@ circuit_list_add=mkSMAdapter4B.v circuit_list_add=or1200.v circuit_list_add=raygentop.v circuit_list_add=sha.v -circuit_list_add=stereovision0.v -circuit_list_add=stereovision1.v -circuit_list_add=stereovision2.v +#These circuits do not go through ACE2. It falsely thinks there are multiple clocks in the circuit. There is a bug with using module instantiation by port when two modules have different names for their clocks, in this case instantiation by name must be used. Tried altering the instantiation method & clock names but did not work. This fixed the error for raygentop.v +#circuit_list_add=stereovision0.v +#circuit_list_add=stereovision1.v +#circuit_list_add=stereovision2.v + #circuit_list_add=stereovision3.v # Add architectures to list to sweep arch_list_add=k6_frac_N10_mem32K_40nm.xml # Parse info and how to parse -parse_file=vpr_power_detailed.txt +#vpr_power_detailed.txt produces incompelete QoR results. (Issue #1749) +#parse_file=vpr_power_detailed.txt +parse_file=vpr_power.txt # Pass requirements -pass_requirements_file=pass_requirements.txt +pass_requirements_file=pass_requirements_power.txt diff --git a/vtr_flow/tasks/power/power_std/config/golden_results.txt b/vtr_flow/tasks/power/power_std/config/golden_results.txt new file mode 100644 index 00000000000..9fc5461395a --- /dev/null +++ b/vtr_flow/tasks/power/power_std/config/golden_results.txt @@ -0,0 +1,16 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml bgm.v common 993.16 23.30 392652 22 468.27 -1 -1 152632 -1 -1 2635 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 700260 257 32 32168 31683 1 18570 2935 62 62 3844 clb auto 33.81 251381 68.53 0.50 15.8414 -22071.7 -15.8414 15.8414 30.38 0.0762625 0.0556687 9.46634 6.97832 80 385161 34 2.30929e+08 1.46369e+08 2.08145e+07 5414.81 217.48 43.0199 34.032 362853 19 90380 408929 23298092 3778029 18.4127 18.4127 -25123.9 -18.4127 0 0 2.62565e+07 6830.53 8.54 10.36 5.01216 4.30582 0.1735 0.4466 0.02668 0.5267 +k6_frac_N10_mem32K_40nm.xml blob_merge.v common 147.36 0.58 59328 18 81.92 -1 -1 67544 -1 -1 567 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 162172 36 100 6600 6700 1 2796 703 30 30 900 clb auto 4.86 45280 5.70 0.04 9.00388 -2553.91 -9.00388 9.00388 2.23 0.0119654 0.0103369 2.00698 1.52489 64 69768 27 4.8774e+07 3.05579e+07 3.87092e+06 4301.02 28.28 7.19469 5.76621 65164 13 12410 63616 2886592 377212 10.3791 10.3791 -2909.67 -10.3791 0 0 4.83441e+06 5371.56 1.88 2.10 1.14247 0.975394 0.025 0.3666 0.03807 0.5953 +k6_frac_N10_mem32K_40nm.xml boundtop.v common 5.74 0.75 47016 2 0.40 -1 -1 36996 -1 -1 82 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 69520 114 192 455 647 1 312 388 13 13 169 clb auto 0.14 758 0.38 0.00 1.70835 -203.113 -1.70835 1.70835 0.26 0.000589842 0.000523076 0.107992 0.0947967 36 2211 20 6.63067e+06 4.41931e+06 367804. 2176.36 1.09 0.29774 0.266955 1762 13 705 924 61330 17686 2.27648 2.27648 -247.759 -2.27648 0 0 456028. 2698.39 0.08 0.04 0.0238337 0.0221336 0.00733 0.3528 0.09256 0.5546 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.97 0.04 9292 3 0.23 -1 -1 36192 -1 -1 65 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 71000 99 130 363 493 1 251 295 12 12 144 clb auto 0.11 615 0.43 0.00 1.97933 -202.994 -1.97933 1.97933 0.19 0.000686016 0.000598315 0.11644 0.100167 46 1389 13 5.66058e+06 4.05111e+06 378970. 2631.74 1.13 0.303061 0.26742 1274 8 580 750 63298 22590 2.47625 2.47625 -241.499 -2.47625 0 0 486261. 3376.82 0.08 0.03 0.0135836 0.0125971 0.009076 0.2039 0.07227 0.7239 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 10.94 0.06 9048 15 0.36 -1 -1 34488 -1 -1 36 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 70356 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.25 5304 0.59 0.01 19.7038 -1798.95 -19.7038 19.7038 0.51 0.0029583 0.00269035 0.254881 0.228332 50 11378 23 1.21132e+07 3.92018e+06 780512. 3048.87 4.97 0.855992 0.780232 9589 21 3086 6045 1539878 392193 22.8395 22.8395 -2030.13 -22.8395 0 0 1.00276e+06 3917.05 0.29 0.55 0.185621 0.173456 0.007811 0.3508 0.0162 0.633 +k6_frac_N10_mem32K_40nm.xml diffeq2.v common 11.49 0.08 8312 14 0.27 -1 -1 33504 -1 -1 29 66 0 7 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 70252 66 96 719 590 1 525 198 18 18 324 mult_36 auto 0.26 4790 0.68 0.00 15.3213 -871.24 -15.3213 15.3213 0.59 0.00146855 0.00135568 0.370686 0.335826 38 11506 50 1.57076e+07 4.33493e+06 803540. 2480.06 6.03 0.98577 0.904424 10051 18 2900 6407 2371930 564906 18.2473 18.2473 -1032.11 -18.2473 0 0 1.01953e+06 3146.70 0.20 0.38 0.0775576 0.0729958 0.009421 0.3037 0.01834 0.678 +k6_frac_N10_mem32K_40nm.xml LU8PEEng.v common 1260.94 18.96 227648 129 265.44 -1 -1 100704 -1 -1 2014 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 610880 114 102 29578 29304 1 15300 2282 54 54 2916 clb auto 29.45 221607 50.06 0.32 71.2325 -55284.1 -71.2325 71.2325 22.37 0.0566456 0.0486916 9.55069 6.87794 94 337754 46 1.70873e+08 1.35826e+08 1.81141e+07 6211.98 750.60 42.8504 33.1133 303103 19 58820 237189 45913981 9240264 81.9617 81.9617 -68418.6 -81.9617 -17.9647 -0.295467 2.28201e+07 7825.81 7.26 14.48 4.67341 4.00067 0.1024 0.4121 0.01053 0.5774 +k6_frac_N10_mem32K_40nm.xml LU32PEEng.v common 8292.37 165.31 770524 128 1478.06 -1 -1 298496 -1 -1 7158 114 167 32 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 2183728 114 102 102506 101104 1 53881 7573 101 101 10201 clb auto 122.57 1091478 485.43 2.65 71.3486 -321265 -71.3486 71.3486 99.44 0.316499 0.22677 45.7049 33.1572 132 1443144 45 6.22828e+08 4.89923e+08 8.69606e+07 8524.71 5352.13 198.325 154.127 1362969 20 201471 870642 300733375 77624623 81.4008 81.4008 -459455 -81.4008 -25.9109 -0.17368 1.11338e+08 10914.4 45.81 117.21 17.3219 14.4488 0.4271 0.4811 0.009337 0.5095 +k6_frac_N10_mem32K_40nm.xml mcml.v common 11490.00 64.83 954212 75 8913.96 -1 -1 447636 -1 -1 5472 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 1916236 36 33 134466 132924 1 39653 5727 92 92 8464 memory auto 61.97 461165 222.95 1.31 58.0342 -281589 -58.0342 58.0342 78.37 0.199968 0.169035 33.8438 25.6696 84 676396 47 5.19428e+08 3.92705e+08 4.83041e+07 5707.00 1580.00 148.649 119.357 624063 21 149746 460070 93047904 23777435 65.3427 65.3427 -353766 -65.3427 -0.0861913 -0.0215478 6.13894e+07 7253.00 18.13 38.33 13.696 11.7956 0.2664 0.3611 0.01299 0.6259 +k6_frac_N10_mem32K_40nm.xml mkDelayWorker32B.v common 90.52 1.14 78816 5 8.08 -1 -1 52432 -1 -1 456 506 47 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 320252 506 553 3285 3838 1 3022 1562 50 50 2500 memory auto 3.44 13844 6.15 0.03 5.95267 -1737.1 -5.95267 5.95267 20.64 0.012365 0.010885 3.07062 2.74121 38 21834 15 1.47946e+08 5.03323e+07 6.86584e+06 2746.33 31.44 7.52573 6.8807 20620 16 4027 5047 3622996 886535 6.85724 6.85724 -2206.18 -6.85724 -7.78106 -0.293253 8.69095e+06 3476.38 2.53 1.21 0.586494 0.552676 0.1861 0.1281 0.03834 0.8336 +k6_frac_N10_mem32K_40nm.xml mkPktMerge.v common 21.18 0.18 16980 2 0.13 -1 -1 33668 -1 -1 27 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 90764 311 156 972 1128 1 953 509 28 28 784 memory auto 0.40 7827 1.40 0.01 3.90797 -4026.08 -3.90797 3.90797 2.49 0.00479418 0.0042137 0.633651 0.537307 36 14479 14 4.25198e+07 9.67514e+06 1.94918e+06 2486.20 11.03 1.87312 1.65376 13472 13 2891 3230 2215365 647096 4.52093 4.52093 -4789.05 -4.52093 -25.8456 -0.339827 2.40571e+06 3068.51 0.56 0.47 0.105075 0.0960577 0.08502 0.1435 0.01666 0.8399 +k6_frac_N10_mem32K_40nm.xml mkSMAdapter4B.v common 25.32 0.35 31892 7 3.04 -1 -1 37864 -1 -1 165 193 5 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 86940 193 205 2232 2437 1 1190 568 20 20 400 memory auto 1.30 8936 2.03 0.01 4.44855 -2528.04 -4.44855 4.44855 0.86 0.00314212 0.00272543 0.780105 0.626009 48 17495 46 2.07112e+07 1.16325e+07 1.23055e+06 3076.38 11.56 2.18786 1.84391 14708 14 4521 11092 1106779 263595 5.53986 5.53986 -2984.41 -5.53986 -4.85712 -0.29436 1.57502e+06 3937.55 0.30 0.38 0.183247 0.168496 0.0293 0.2036 0.02481 0.7716 +k6_frac_N10_mem32K_40nm.xml or1200.v common 72.49 0.59 40832 27 5.55 -1 -1 43848 -1 -1 259 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 116052 385 394 3979 4310 1 2379 1041 27 27 729 io auto 3.51 31242 3.76 0.03 13.271 -13061.1 -13.271 13.271 1.75 0.00736652 0.00662886 1.18375 0.987094 76 51110 29 3.93038e+07 1.54505e+07 3.58343e+06 4915.54 42.42 4.82241 4.19008 46131 14 10355 37426 3388428 639602 15.072 15.072 -14934.3 -15.072 0 0 4.48127e+06 6147.14 1.87 1.14 0.46423 0.424524 0.02317 0.4367 0.02471 0.5386 +k6_frac_N10_mem32K_40nm.xml raygentop.v common 27.80 0.39 32896 8 1.89 -1 -1 40484 -1 -1 107 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 88700 214 305 2625 2741 1 1449 635 22 22 484 mult_36 auto 1.82 11585 1.31 0.01 4.30664 -2400.31 -4.30664 4.30664 0.98 0.00341223 0.00302836 0.47218 0.408523 50 26386 46 2.50602e+07 9.33066e+06 1.56759e+06 3238.82 12.71 1.84859 1.63625 21391 21 7225 15930 4958964 1086872 5.40231 5.40231 -3027.78 -5.40231 0 0 2.01671e+06 4166.75 0.42 0.98 0.237377 0.217771 0.02275 0.432 0.03813 0.5299 +k6_frac_N10_mem32K_40nm.xml sha.v common 784.92 1.17 38104 20 756.44 -1 -1 95404 -1 -1 208 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing 98508 38 36 3404 3440 1 1281 282 19 19 361 clb auto 1.69 13341 1.43 0.01 11.5537 -3886.76 -11.5537 11.5537 0.65 0.00395868 0.00333349 0.590888 0.437396 56 21996 28 1.72706e+07 1.121e+07 1.27879e+06 3542.35 10.04 3.00182 2.48345 19799 15 5276 20061 681706 118206 14.2741 14.2741 -4632.48 -14.2741 0 0 1.63234e+06 4521.70 0.36 0.40 0.272269 0.243728 0.01026 0.3549 0.02594 0.6191 diff --git a/vtr_flow/tasks/regression_bidir/config/config.txt b/vtr_flow/tasks/regression_bidir/config/config.txt deleted file mode 100644 index b9ecc1eb300..00000000000 --- a/vtr_flow/tasks/regression_bidir/config/config.txt +++ /dev/null @@ -1,21 +0,0 @@ -############################################## -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/bidir - -# Add circuits to list to sweep -circuit_list_add=ch_intrinsics.v - -# Add architectures to list to sweep -arch_list_add=k4_n4_v7_bidir.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements.txt diff --git a/vtr_flow/tasks/regression_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_bidir/config/golden_results.txt deleted file mode 100644 index 0798a9b1254..00000000000 --- a/vtr_flow/tasks/regression_bidir/config/golden_results.txt +++ /dev/null @@ -1,2 +0,0 @@ -arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem -k4_n4_v7_bidir.xml ch_intrinsics.v 30d086154 success 477 607 323 302 17 17 73 99 130 -1 -1 4323 7.15427 -644.01 -7.15427 13 2820 17 2655 18 9.92513 -904.128 -9.92513 0 0 6.75e+06 2.19e+06 -1 -1 -1 -1 0.03 0.01 -1 -1 -1 0.07 0.34 1.68 0.08 2.79 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_fpu_hard_block_arch/config/config.txt b/vtr_flow/tasks/regression_fpu_hard_block_arch/config/config.txt deleted file mode 100755 index 7e888b370a4..00000000000 --- a/vtr_flow/tasks/regression_fpu_hard_block_arch/config/config.txt +++ /dev/null @@ -1,32 +0,0 @@ -# -############################################ -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/fpu/hardlogic - -# Path to directory of architectures to use -archs_dir=arch/timing - -# Add circuits to list to sweep -circuit_list_add=bfly.v -circuit_list_add=bgm.v -circuit_list_add=dscg.v -circuit_list_add=fir.v -circuit_list_add=mm3.v -circuit_list_add=ode.v -circuit_list_add=syn2.v -circuit_list_add=syn7.v - -# Add architectures to list to sweep -arch_list_add=hard_fpu_arch_timing.xml - -# Parse info and how to parse -parse_file=vpr_hard_fpu.txt - -# Pass requirements -pass_requirements_file=pass_requirements_fixed_chan_width.txt - -# Parameters for vtr flow -script_params=-no_mem -vpr_route_chan_width 72 -vpr_cluster_seed_type max_inputs diff --git a/vtr_flow/tasks/regression_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_fpu_hard_block_arch/config/golden_results.txt deleted file mode 100644 index 8f6ce817df8..00000000000 --- a/vtr_flow/tasks/regression_fpu_hard_block_arch/config/golden_results.txt +++ /dev/null @@ -1,9 +0,0 @@ -arch circuit min_chan_width_route_time crit_path_route_time vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult num_fpu placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile pack_time place_time crit_path_route_time max_vpr_mem max_odin_mem max_abc_mem -hard_fpu_arch_timing.xml bfly.v 1.15 1.15 30d086154 success 833 649 353 260 24 24 0 193 64 -1 -1 3 7751 2.985 -1309.88 -2.985 7158 5 2.985 -1353.41 -2.985 -1 -1 1.06129e+06 103149 1.28794e+06 2236.02 1.90 0.67 1.15 -1 -1 -1 -hard_fpu_arch_timing.xml bgm.v 8.35 8.35 30d086154 success 1281 693 1021 299 38 38 0 257 32 -1 -1 10 25456 2.985 -3103.91 -2.985 24104 19 2.985 -3437.93 -2.985 -1 -1 2.90196e+06 343832 3.35777e+06 2325.33 5.71 1.72 8.35 -1 -1 -1 -hard_fpu_arch_timing.xml dscg.v 5.30 5.30 30d086154 success 769 585 513 198 32 32 0 129 64 -1 -1 5 11247 2.985 -1352.85 -2.985 11193 18 2.985 -1507.79 -2.985 -1 -1 2.063e+06 171916 2.37490e+06 2319.23 4.39 0.85 5.30 -1 -1 -1 -hard_fpu_arch_timing.xml fir.v 1.83 1.83 30d086154 success 993 808 543 232 30 30 35 161 32 -1 -1 4 10396 2.985 -1321.5 -2.985 9078 16 2.985 -1439.96 -2.985 -1 -1 1.6779e+06 217760 2.03108e+06 2256.75 37.10 0.81 1.83 -1 -1 -1 -hard_fpu_arch_timing.xml mm3.v 0.51 0.51 30d086154 success 545 422 289 227 21 21 0 193 32 -1 -1 2 4808 2.985 -796.832 -2.985 4357 12 2.985 -808.072 -2.985 -1 -1 809148 68766.3 979092. 2220.16 1.02 0.43 0.51 -1 -1 -1 -hard_fpu_arch_timing.xml ode.v 0.82 0.82 30d086154 success 1194 1103 573 329 19 19 125 130 72 -1 -1 2 7946 2.985 -1338.84 -2.985 6856 9 2.985 -1405.11 -2.985 -1 -1 653279 355293 795482. 2203.55 34.32 0.65 0.82 -1 -1 -1 -hard_fpu_arch_timing.xml syn2.v 2.38 2.38 30d086154 success 641 490 479 293 30 30 0 161 128 -1 -1 4 11817 2.985 -1451.94 -2.985 10444 19 2.985 -1567.97 -2.985 -1 -1 1.6779e+06 137533 2.03108e+06 2256.75 1.21 0.89 2.38 -1 -1 -1 -hard_fpu_arch_timing.xml syn7.v 35.22 35.22 30d086154 success 1921 499 1703 310 54 54 0 161 128 -1 -1 21 76097 2.985 -7796.95 -2.985 59989 9 2.985 -8544.41 -2.985 -1 -1 6.08571e+06 722046 6.89978e+06 2366.18 1.66 4.28 35.22 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_fpu_soft_logic_arch/config/config.txt b/vtr_flow/tasks/regression_fpu_soft_logic_arch/config/config.txt deleted file mode 100755 index c3a90e46526..00000000000 --- a/vtr_flow/tasks/regression_fpu_soft_logic_arch/config/config.txt +++ /dev/null @@ -1,32 +0,0 @@ -# -############################################ -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/fpu/softlogic - -# Path to directory of architectures to use -archs_dir=arch/timing - -# Add circuits to list to sweep -circuit_list_add=bfly.v -circuit_list_add=bgm.v -circuit_list_add=dscg.v -circuit_list_add=fir.v -circuit_list_add=mm3.v -circuit_list_add=ode.v -circuit_list_add=syn2.v -# circuit_list_add=syn7.v # Cannot run this at channel width 72 because does not route - -# Add architectures to list to sweep -arch_list_add=soft_fpu_arch_timing.xml - -# Parse info and how to parse -parse_file=vpr_fixed_chan_width.txt - -# Pass requirements -pass_requirements_file=pass_requirements_fixed_chan_width.txt - -# Parameters for vtr flow -script_params=-no_mem -vpr_route_chan_width 72 diff --git a/vtr_flow/tasks/regression_fpu_soft_logic_arch/config/golden_results.txt b/vtr_flow/tasks/regression_fpu_soft_logic_arch/config/golden_results.txt deleted file mode 100755 index e72523fa858..00000000000 --- a/vtr_flow/tasks/regression_fpu_soft_logic_arch/config/golden_results.txt +++ /dev/null @@ -1,8 +0,0 @@ -arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength crit_path_route_success_iteration logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem -soft_fpu_arch_timing.xml bfly.v 30d086154 success 21428 21492 15809 5570 75 75 5313 193 64 -1 -1 1195432 37.5527 -10727.6 -37.5527 413177 26 1.22145e+07 1.21778e+07 1.34390e+07 2389.15 40.0815 -11382.8 -40.0815 -30.9576 -0.0851 3.05 0.30 -1 -1 -1 10.11 65.91 22.28 120.62 -1 -1 -1 -soft_fpu_arch_timing.xml bgm.v 30d086154 success 47249 47281 34602 12072 111 111 11783 257 32 -1 -1 3884086 40.195 -27340.8 -40.195 980899 26 2.72317e+07 2.70071e+07 2.96941e+07 2410.04 41.297 -28960.7 -41.297 -36.9193 -0.0851 12.70 0.78 -1 -1 -1 48.74 520.54 75.83 710.94 -1 -1 -1 -soft_fpu_arch_timing.xml dscg.v 30d086154 success 17701 17765 12924 4601 69 69 4408 129 64 -1 -1 894971 37.7555 -9413.39 -37.7555 332340 21 1.02892e+07 1.01036e+07 1.13481e+07 2383.55 38.2171 -9918.27 -38.2171 -29.785 -0.0851 3.36 0.32 -1 -1 -1 10.01 79.47 21.65 135.12 -1 -1 -1 -soft_fpu_arch_timing.xml fir.v 30d086154 success 20956 20988 15449 5391 75 75 5198 161 32 -1 -1 1172460 34.8219 -10424 -34.8219 374058 26 1.22145e+07 1.19143e+07 1.34390e+07 2389.15 36.3823 -11094.2 -36.3823 -30.6185 -0.0851 2.76 0.30 -1 -1 -1 12.15 99.80 29.81 165.52 -1 -1 -1 -soft_fpu_arch_timing.xml mm3.v 30d086154 success 15471 15503 11397 4053 64 64 3828 193 32 -1 -1 736956 34.5712 -7456.47 -34.5712 275738 25 8.81088e+06 8.77421e+06 9.74059e+06 2378.07 35.6735 -7853.8 -35.6735 -17.1051 -0.0851 1.57 0.21 -1 -1 -1 6.51 52.03 22.42 97.36 -1 -1 -1 -soft_fpu_arch_timing.xml ode.v 30d086154 success 10164 10236 7293 2690 52 52 2488 130 72 -1 -1 379123 33.3651 -5001.53 -33.3651 175069 26 5.73043e+06 5.70293e+06 6.38377e+06 2360.86 35.8313 -5285.77 -35.8313 -31.1862 -0.0851 1.66 0.21 -1 -1 -1 4.50 30.70 11.84 59.98 -1 -1 -1 -soft_fpu_arch_timing.xml syn2.v 30d086154 success 19489 19617 14367 5129 72 72 4840 161 128 -1 -1 1037592 35.1526 -9915.73 -35.1526 382798 26 1.12312e+07 1.10937e+07 1.23715e+07 2386.47 36.3648 -10499.4 -36.3648 -18.6928 -0.0851 3.90 0.36 -1 -1 -1 11.08 89.35 30.23 155.94 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_mcnc/config/golden_results.txt deleted file mode 100755 index 2799d40de28..00000000000 --- a/vtr_flow/tasks/regression_mcnc/config/golden_results.txt +++ /dev/null @@ -1,21 +0,0 @@ -arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem -k6_N10_40nm.xml alu4.pre-vpr.blif 30d086154 success 926 934 477 115 12 12 93 14 8 -1 -1 6282 4.40554 -31.5582 -4.40554 40 6544 16 6297 18 4.71972 -33.8691 -4.71972 0 0 5.3894e+06 5.01214e+06 346969. 2409.51 435722. 3025.85 -1 -1 -1 -1 -1 1.42 0.63 3.08 0.29 5.86 -1 -1 -1 -k6_N10_40nm.xml apex2.pre-vpr.blif 30d086154 success 1113 1116 641 149 13 13 108 38 3 -1 -1 10542 4.87555 -14.4261 -4.87555 58 13034 24 12011 20 5.13724 -15.1863 -5.13724 0 0 6.52117e+06 5.82055e+06 584019. 3455.73 741857. 4389.69 -1 -1 -1 -1 -1 0.98 0.97 5.68 0.55 8.65 -1 -1 -1 -k6_N10_40nm.xml apex4.pre-vpr.blif 30d086154 success 897 916 537 117 12 12 89 9 19 -1 -1 7861 4.67666 -73.0804 -4.67666 60 10715 42 9343 17 4.90275 -78.4088 -4.90275 0 0 5.3894e+06 4.79657e+06 505417. 3509.84 632511. 4392.44 -1 -1 -1 -1 -1 0.86 0.71 3.67 0.43 6.08 -1 -1 -1 -k6_N10_40nm.xml bigkey.pre-vpr.blif 30d086154 success 1364 1561 503 518 16 16 92 229 197 -1 -1 8461 2.49859 -624.203 -2.49859 38 7698 18 7213 19 2.76978 -723.548 -2.76978 0 0 1.05632e+07 4.95825e+06 632420. 2470.39 795593. 3107.78 -1 -1 -1 -1 -1 0.84 1.09 3.28 0.36 6.00 -1 -1 -1 -k6_N10_40nm.xml clma.pre-vpr.blif 30d086154 success 3672 3754 2299 502 21 21 358 62 82 -1 -1 56897 7.51433 -364.35 -7.51433 74 46078 27 44201 22 7.74002 -401.439 -7.74002 0 0 1.94557e+07 1.92941e+07 2.06377e+06 4679.75 2.56926e+06 5825.98 -1 -1 -1 -1 -1 3.88 5.73 21.65 2.45 35.10 -1 -1 -1 -k6_N10_40nm.xml des.pre-vpr.blif 30d086154 success 954 1199 596 571 18 18 70 256 245 -1 -1 10930 3.64649 -677.099 -3.64649 34 9426 31 8257 20 4.3436 -782.519 -4.3436 0 0 1.37969e+07 3.77258e+06 748928. 2311.50 917842. 2832.85 -1 -1 -1 -1 -1 0.34 1.05 2.36 0.29 4.41 -1 -1 -1 -k6_N10_40nm.xml diffeq.pre-vpr.blif 30d086154 success 1371 1410 588 197 12 12 94 64 39 -1 -1 6629 4.29949 -998.109 -4.29949 34 5938 25 5438 20 4.68767 -1073.21 -4.68767 0 0 5.3894e+06 5.06604e+06 307290. 2133.96 376278. 2613.04 -1 -1 -1 -1 -1 0.48 0.64 2.09 0.25 3.88 -1 -1 -1 -k6_N10_40nm.xml dsip.pre-vpr.blif 30d086154 success 1362 1559 527 517 16 16 91 229 197 -1 -1 9720 2.49628 -623.571 -2.49628 36 8661 24 8231 21 2.85657 -745.54 -2.85657 0 0 1.05632e+07 4.90435e+06 605313. 2364.50 744064. 2906.50 -1 -1 -1 -1 -1 0.93 1.17 3.60 0.39 6.53 -1 -1 -1 -k6_N10_40nm.xml elliptic.pre-vpr.blif 30d086154 success 3421 3535 1250 462 17 17 217 131 114 -1 -1 21010 6.86415 -3945.87 -6.86415 50 18908 42 16434 19 7.23344 -4315.99 -7.23344 0 0 1.21262e+07 1.1695e+07 907546. 3140.30 1.20603e+06 4173.11 -1 -1 -1 -1 -1 1.49 2.27 9.60 0.80 15.04 -1 -1 -1 -k6_N10_40nm.xml ex1010.pre-vpr.blif 30d086154 success 2659 2669 1396 285 19 19 265 10 10 -1 -1 31712 5.95872 -57.354 -5.95872 88 43202 29 40118 20 6.21184 -59.9851 -6.21184 0 0 1.55754e+07 1.42819e+07 1.92623e+06 5335.82 2.40765e+06 6669.39 -1 -1 -1 -1 -1 3.21 3.14 24.04 2.19 33.64 -1 -1 -1 -k6_N10_40nm.xml ex5p.pre-vpr.blif 30d086154 success 761 824 427 148 11 11 77 8 63 -1 -1 5498 3.65588 -160.336 -3.65588 50 6788 35 6024 18 4.10669 -184.16 -4.10669 0 0 4.36541e+06 4.14984e+06 346807. 2866.17 460672. 3807.21 -1 -1 -1 -1 -1 0.82 0.59 2.05 0.29 4.13 -1 -1 -1 -k6_N10_40nm.xml frisc.pre-vpr.blif 30d086154 success 3175 3291 1259 364 18 18 228 20 116 -1 -1 24921 7.57606 -4118.34 -7.57606 62 26350 22 22700 16 8.04046 -4445.13 -8.04046 0 0 1.37969e+07 1.22878e+07 1.27511e+06 3935.53 1.56830e+06 4840.43 -1 -1 -1 -1 -1 1.57 2.80 12.02 0.97 18.27 -1 -1 -1 -k6_N10_40nm.xml misex3.pre-vpr.blif 30d086154 success 828 842 451 111 12 12 83 14 14 -1 -1 6310 4.18059 -54.4041 -4.18059 40 7240 38 6680 19 4.50783 -59.6217 -4.50783 0 0 5.3894e+06 4.4732e+06 346969. 2409.51 435722. 3025.85 -1 -1 -1 -1 -1 0.98 0.63 2.40 0.40 4.78 -1 -1 -1 -k6_N10_40nm.xml pdc.pre-vpr.blif 30d086154 success 2839 2879 1457 339 19 19 283 16 40 -1 -1 32609 6.12486 -222.536 -6.12486 76 38722 29 35970 20 6.48833 -238.077 -6.48833 0 0 1.55754e+07 1.5252e+07 1.69786e+06 4703.20 2.10944e+06 5843.31 -1 -1 -1 -1 -1 4.17 3.46 14.88 1.94 25.69 -1 -1 -1 -k6_N10_40nm.xml s298.pre-vpr.blif 30d086154 success 726 732 374 82 11 11 72 4 6 -1 -1 4632 5.57792 -45.6578 -5.57792 40 5876 24 5450 20 6.04619 -52.6309 -6.04619 0 0 4.36541e+06 3.88037e+06 284999. 2355.36 358204. 2960.36 -1 -1 -1 -1 -1 0.92 0.45 2.36 0.30 4.36 -1 -1 -1 -k6_N10_40nm.xml s38417.pre-vpr.blif 30d086154 success 4782 4888 2172 492 21 21 357 29 106 -1 -1 42993 4.58603 -3433.21 -4.58603 40 23114 28 21518 22 5.11358 -3734.12 -5.11358 0 0 1.94557e+07 1.92402e+07 1.17842e+06 2672.15 1.47671e+06 3348.55 -1 -1 -1 -1 -1 2.03 4.01 6.05 1.09 14.39 -1 -1 -1 -k6_N10_40nm.xml s38584.1.pre-vpr.blif 30d086154 success 4457 4761 2139 674 21 21 332 38 304 -1 -1 44053 4.04847 -2927.82 -4.04847 44 24999 28 22006 20 4.63096 -3210.71 -4.63096 0 0 1.94557e+07 1.78928e+07 1.27749e+06 2896.80 1.65404e+06 3750.67 -1 -1 -1 -1 -1 1.47 4.07 5.46 1.02 13.21 -1 -1 -1 -k6_N10_40nm.xml seq.pre-vpr.blif 30d086154 success 1006 1041 581 174 12 12 98 41 35 -1 -1 8559 4.35251 -122.979 -4.35251 58 10680 22 10003 19 4.56915 -134.621 -4.56915 0 0 5.3894e+06 5.28161e+06 488429. 3391.87 620391. 4308.27 -1 -1 -1 -1 -1 1.03 0.92 4.07 0.46 6.93 -1 -1 -1 -k6_N10_40nm.xml spla.pre-vpr.blif 30d086154 success 2232 2278 1146 284 17 17 222 16 46 -1 -1 22691 5.63391 -190.594 -5.63391 64 26019 25 25946 23 6.12471 -211.056 -6.12471 0 0 1.21262e+07 1.19645e+07 1.16329e+06 4025.22 1.44914e+06 5014.31 -1 -1 -1 -1 -1 3.37 2.19 8.08 1.24 15.69 -1 -1 -1 -k6_N10_40nm.xml tseng.pre-vpr.blif 30d086154 success 1461 1583 508 277 13 13 103 52 122 -1 -1 6291 4.48051 -1117.23 -4.48051 32 5407 13 4887 15 4.79129 -1242.35 -4.79129 0 0 6.52117e+06 5.55108e+06 352895. 2088.14 431135. 2551.09 -1 -1 -1 -1 -1 0.40 0.60 1.91 0.16 3.46 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/README.md b/vtr_flow/tasks/regression_tests/README.md index 7b29e764f3b..70a224f77f8 100644 --- a/vtr_flow/tasks/regression_tests/README.md +++ b/vtr_flow/tasks/regression_tests/README.md @@ -73,40 +73,41 @@ Create golden results with: /parse_vtr_task.py -create_golden -l /regression_tests/vtr_reg_strong/task_list.txt ``` -## LEVEL THREE - Nightly VTR Regression - `vtr_reg_nightly` +## LEVEL THREE - Nightly VTR Regression - `vtr_reg_nightly_test#` - * To be run by automated build system every night. + * To be run by automated build system every night and on every pull request. + * To keep the wall-clock time of this suite under ~4 hours using -j8, it is divided into multiple sub-suites, and each of them are submitted as different jobs to different kokoro machines. * Estimated Runtime: ~15-20 hours DO-IT-ALL COMMAND - This command will execute, parse, and check results. ``` -./run_reg_test.py vtr_reg_nightly +./run_reg_test.py vtr_reg_nightly_test# ./run_reg_test.py vtr_reg_valgrind ``` To create golden results, use: ``` -./run_reg_test.py -create_golden vtr_reg_nightly +./run_reg_test.py -create_golden vtr_reg_nightly_test# ``` Execute with: ``` -/run_vtr_task.py -l /regression_tests/vtr_reg_nightly/task_list.txt +/run_vtr_task.py -l /regression_tests/vtr_reg_nightly_test#/task_list.txt ``` Parse results with: ``` -/parse_vtr_task.py -l /regression_tests/vtr_reg_nightly/task_list.txt +/parse_vtr_task.py -l /regression_tests/vtr_reg_nightly_test#/task_list.txt ``` Check results with: ``` -/parse_vtr_task.py -check_golden -l /regression_tests/vtr_reg_nightly/task_list.txt +/parse_vtr_task.py -check_golden -l /regression_tests/vtr_reg_nightly_test#/task_list.txt ``` Create golden results with: ``` -/parse_vtr_task.py -create_golden -l /regression_tests/vtr_reg_nightly/task_list.txt +/parse_vtr_task.py -create_golden -l /regression_tests/vtr_reg_nightly_test#/task_list.txt ``` diff --git a/vtr_flow/tasks/regression_tests/README_nightly_regression_parallelism.md b/vtr_flow/tasks/regression_tests/README_nightly_regression_parallelism.md new file mode 100644 index 00000000000..2734491bf9c --- /dev/null +++ b/vtr_flow/tasks/regression_tests/README_nightly_regression_parallelism.md @@ -0,0 +1,18 @@ +# Parallesim Startegy for vtr_reg_nightly: +## Current Sub-suites: + + * The nightly regression suite is broken up into multiple sub-suites to minimize the wall-clock when ran by CI using Kokoro machines. + * The lower bound for the run-time of the nightly regression tests is the longest vtr_flow run in all suites (currently this flow is in vtr_reg_nightly_test2/vtr_reg_qor) + * To minimize wall-clock time, tasks which have the three longest flow runs are put in seperate directories and other tasks are added to keep the + run-time for the sub-suite under ~4 hours using -j8. + * The longest tasks are put at the bottom of task_list.txt to get started first (the files are read in backwards in `run_reg_test.py` + * If tasks that do not have long flow runs are to be added, it is best that they are added under vtr_reg_nightly_test1 as this suite has the smallest run-time + of all suites (~2 hours using -j8). + * If tasks with long flows that exceed ~1.5-2 hours are to be added, it is best to seperate them from the other suites and put it in a seperate test + at the bottom of the task list. + +## Adding Sub-suites: + * To add additional suites, a config file (.cfg) has to be added to [the config list for Kokoro machines](https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/.github/kokoro/presubmit). The new config should be indentical to the other config file for nightly tests, with the only difference being the value for VTR_TEST (i.e. the value should be changed to the directory name for the new suite). + + + diff --git a/vtr_flow/tasks/regression_mcnc/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt similarity index 70% rename from vtr_flow/tasks/regression_mcnc/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt index 2e3fbb1a1eb..c1e990a3ef5 100755 --- a/vtr_flow/tasks/regression_mcnc/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt @@ -25,7 +25,8 @@ circuit_list_add=frisc.pre-vpr.blif circuit_list_add=misex3.pre-vpr.blif circuit_list_add=pdc.pre-vpr.blif circuit_list_add=s298.pre-vpr.blif -circuit_list_add=s38417.pre-vpr.blif +#The test appears to reach a time-limit and exits. Logical equivalence is UNDECIDED (not false). Tried running combinational verification instead of sequential verification manually on ABC. Since VPR changes the names of elements, this is not an appropriate verification method. +#circuit_list_add=s38417.pre-vpr.blif circuit_list_add=s38584.1.pre-vpr.blif circuit_list_add=seq.pre-vpr.blif circuit_list_add=spla.pre-vpr.blif @@ -40,5 +41,6 @@ parse_file=vpr_standard.txt # Pass requirements pass_requirements_file=pass_requirements.txt -script_params=-no_mem -starting_stage vpr -check_equivalent +# +script_params=-starting_stage vpr --gen_post_synthesis_netlist on -check_equivalent --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --absorb_buffer_luts off diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt new file mode 100644 index 00000000000..12b0d594c61 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt @@ -0,0 +1,20 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_40nm.xml alu4.pre-vpr.blif common 3.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 96 14 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 39200 14 8 926 934 0 478 118 12 12 144 clb auto 0.26 4814 0.32 0.00 4.30446 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-1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 40120 9 19 897 916 0 536 123 12 12 144 clb auto 0.30 6374 0.35 0.00 4.61877 -75.0193 -4.61877 nan 0.19 0.00100258 0.000740471 0.119521 0.0911157 70 10066 28 5.3894e+06 5.11993e+06 586610. 4073.68 1.48 0.394256 0.315564 9147 25 5449 27385 1182325 172059 4.91405 nan -80.9103 -4.91405 0 0 732627. 5087.69 0.12 0.25 0.0887408 0.0776228 +k6_N10_40nm.xml bigkey.pre-vpr.blif common 5.28 -1 -1 -1 -1 -1 -1 -1 -1 -1 94 229 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 47976 263 197 1372 1603 1 490 554 17 17 289 io auto 0.21 4524 0.67 0.01 2.60008 -650.597 -2.60008 2.60008 0.44 0.0015296 0.00127211 0.196951 0.164542 34 8009 45 1.21262e+07 5.06604e+06 661981. 2290.59 2.28 0.650584 0.563315 7362 18 2388 12207 687931 134699 2.98622 2.98622 -761.04 -2.98622 0 0 811075. 2806.49 0.16 0.18 0.0793216 0.0714196 +k6_N10_40nm.xml clma.pre-vpr.blif common 27.11 -1 -1 -1 -1 -1 -1 -1 -1 -1 380 62 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 100484 383 82 3674 4077 1 2327 845 22 22 484 clb auto 1.22 30799 4.22 0.03 7.81815 -317.417 -7.81815 7.81815 0.90 0.0059914 0.00372653 1.01679 0.666279 86 48554 35 2.15576e+07 2.04797e+07 2.58188e+06 5334.46 11.26 3.23066 2.36536 44729 26 20973 95393 4959730 642131 8.00909 8.00909 -350.887 -8.00909 0 0 3.23937e+06 6692.90 0.67 1.34 0.475046 0.39322 +k6_N10_40nm.xml des.pre-vpr.blif common 5.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 99 256 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 42744 256 245 954 1199 0 610 600 18 18 324 io auto 0.16 4894 0.58 0.01 3.59246 -679.876 -3.59246 nan 0.52 0.00156703 0.00138989 0.171411 0.151208 34 7704 36 1.37969e+07 5.33551e+06 748928. 2311.50 2.03 0.599611 0.542463 7041 19 2784 6772 372605 79648 3.963 nan -754.212 -3.963 0 0 917842. 2832.85 0.19 0.13 0.0758948 0.070432 +k6_N10_40nm.xml diffeq.pre-vpr.blif common 3.58 -1 -1 -1 -1 -1 -1 -1 -1 -1 97 64 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 39132 64 39 1371 1410 1 553 200 12 12 144 clb auto 0.23 3692 0.32 0.00 4.72655 -954.904 -4.72655 4.72655 0.19 0.00100861 0.00082038 0.120004 0.0922416 36 5140 29 5.3894e+06 5.22772e+06 320399. 2224.99 0.91 0.403539 0.327736 4761 27 3087 10851 419353 73563 5.50221 5.50221 -1088.02 -5.50221 0 0 394751. 2741.33 0.07 0.14 0.0817274 0.0709849 +k6_N10_40nm.xml dsip.pre-vpr.blif common 4.74 -1 -1 -1 -1 -1 -1 -1 -1 -1 95 229 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 44888 229 197 1370 1567 1 535 521 16 16 256 io auto 0.22 4506 0.66 0.01 2.49408 -629.437 -2.49408 2.49408 0.38 0.00154264 0.00127544 0.190288 0.157275 34 8719 42 1.05632e+07 5.11993e+06 580208. 2266.44 1.84 0.577019 0.495515 7623 24 2986 11751 735573 151858 3.03309 3.03309 -756.901 -3.03309 0 0 710900. 2776.95 0.14 0.21 0.100002 0.090087 +k6_N10_40nm.xml elliptic.pre-vpr.blif common 16.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 230 131 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68792 131 114 3421 3535 1 1217 475 18 18 324 clb auto 0.69 11509 1.15 0.01 6.7484 -4002.56 -6.7484 6.7484 0.53 0.00331781 0.00228781 0.395444 0.281229 48 19779 41 1.37969e+07 1.23956e+07 993200. 3065.43 4.82 1.41361 1.09099 17206 27 8575 39180 1893706 281944 7.28092 7.28092 -4693.1 -7.28092 0 0 1.27511e+06 3935.53 0.25 0.53 0.249735 0.209131 +k6_N10_40nm.xml ex1010.pre-vpr.blif common 23.56 -1 -1 -1 -1 -1 -1 -1 -1 -1 302 10 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 81084 10 10 2659 2669 0 1417 322 20 20 400 clb auto 1.05 26554 1.63 0.01 6.16799 -60.2696 -6.16799 nan 0.66 0.00368526 0.0025354 0.472463 0.333483 88 48623 40 1.74617e+07 1.6276e+07 2.14967e+06 5374.18 15.21 2.15767 1.60935 42086 26 13627 85296 5269084 608977 6.66736 nan -64.4644 -6.66736 0 0 2.68685e+06 6717.13 0.51 1.18 0.326258 0.266174 +k6_N10_40nm.xml ex5p.pre-vpr.blif common 3.67 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 8 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 37004 8 63 761 824 0 443 149 11 11 121 clb auto 0.22 4417 0.29 0.00 3.78797 -168.76 -3.78797 nan 0.15 0.000842121 0.000625779 0.0951432 0.0725943 56 7756 40 4.36541e+06 4.20373e+06 384634. 3178.79 1.84 0.429632 0.34709 6720 27 5012 21593 1018121 163519 4.35912 nan -191.647 -4.35912 0 0 491412. 4061.26 0.08 0.21 0.0711569 0.061656 +k6_N10_40nm.xml frisc.pre-vpr.blif common 14.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 240 20 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68700 20 116 3175 3291 1 1254 376 18 18 324 clb auto 0.69 15344 1.14 0.01 8.10932 -4228.26 -8.10932 8.10932 0.51 0.00275 0.00198929 0.360382 0.268421 64 24921 47 1.37969e+07 1.29346e+07 1.31637e+06 4062.87 4.62 1.35464 1.0511 21994 33 9165 39291 2143763 310219 9.04024 9.04024 -4776.93 -9.04024 0 0 1.63962e+06 5060.55 0.34 0.75 0.345746 0.283362 +k6_N10_40nm.xml misex3.pre-vpr.blif common 3.70 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 14 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 36872 14 14 828 842 0 488 115 12 12 144 clb auto 0.25 4803 0.29 0.00 4.09122 -53.5889 -4.09122 nan 0.19 0.000876854 0.000684055 0.104159 0.0794147 48 8135 43 5.3894e+06 4.68878e+06 408411. 2836.19 1.36 0.388988 0.311789 7235 33 5301 23317 977390 159676 4.95088 nan -62.7442 -4.95088 0 0 523024. 3632.11 0.09 0.23 0.086753 0.0748506 +k6_N10_40nm.xml pdc.pre-vpr.blif common 24.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 307 16 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 83344 16 40 2839 2879 0 1501 363 20 20 400 clb auto 0.89 24957 1.71 0.01 6.14413 -225.571 -6.14413 nan 0.71 0.00410999 0.00288584 0.52749 0.350613 78 42446 48 1.74617e+07 1.65455e+07 1.93229e+06 4830.73 13.58 2.30066 1.69075 37766 24 13244 77776 3921239 502795 6.83041 nan -244.653 -6.83041 0 0 2.43175e+06 6079.38 0.55 1.33 0.470489 0.400283 +k6_N10_40nm.xml s298.pre-vpr.blif common 3.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 77 4 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 35212 4 6 726 732 1 378 87 11 11 121 clb auto 0.21 3716 0.23 0.00 5.71121 -46.2336 -5.71121 5.71121 0.15 0.000846857 0.000638317 0.0950246 0.0735267 44 6280 41 4.36541e+06 4.14984e+06 309216. 2555.51 1.10 0.333571 0.271218 5365 29 4054 22082 941035 143823 5.8999 5.8999 -49.9378 -5.8999 0 0 401578. 3318.83 0.07 0.20 0.0727852 0.0637362 +k6_N10_40nm.xml s38584.1.pre-vpr.blif common 24.04 -1 -1 -1 -1 -1 -1 -1 -1 -1 368 38 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 88992 39 304 4677 4982 1 2229 711 22 22 484 clb auto 0.83 15536 1.93 0.02 4.41692 -2935.09 -4.41692 4.41692 0.91 0.00455311 0.00312826 0.566365 0.398763 46 23136 35 2.15576e+07 1.9833e+07 1.47372e+06 3044.87 4.09 1.88886 1.46252 21484 26 12644 35500 1633261 291191 5.11746 5.11746 -3317.26 -5.11746 0 0 1.89173e+06 3908.53 0.37 0.59 0.334044 0.277708 +k6_N10_40nm.xml seq.pre-vpr.blif common 4.44 -1 -1 -1 -1 -1 -1 -1 -1 -1 103 41 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 41704 41 35 1006 1041 0 588 179 13 13 169 clb auto 0.34 6825 0.44 0.00 4.2488 -124.521 -4.2488 nan 0.23 0.00110795 0.000810473 0.135138 0.102529 62 11140 29 6.52117e+06 5.55108e+06 625464. 3700.97 1.71 0.446736 0.354571 10150 27 6502 31106 1376375 204918 4.67375 nan -137.385 -4.67375 0 0 769731. 4554.62 0.13 0.29 0.0947632 0.0818525 +k6_N10_40nm.xml spla.pre-vpr.blif common 13.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 245 16 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68928 16 46 2232 2278 0 1154 307 18 18 324 clb auto 0.70 16481 1.27 0.01 5.54429 -185.233 -5.54429 nan 0.53 0.00333044 0.00215766 0.403298 0.274104 66 28478 42 1.37969e+07 1.3204e+07 1.36437e+06 4211.00 5.45 1.36982 1.02511 25314 24 10149 58436 2749061 372378 6.29168 nan -209.894 -6.29168 0 0 1.68162e+06 5190.19 0.31 0.71 0.243249 0.205711 +k6_N10_40nm.xml tseng.pre-vpr.blif common 3.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 110 52 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 41848 52 122 1461 1583 1 509 284 13 13 169 clb auto 0.20 3038 0.34 0.00 4.30331 -1151.35 -4.30331 4.30331 0.23 0.00101855 0.000840928 0.116122 0.0910782 32 4735 27 6.52117e+06 5.92834e+06 352895. 2088.14 0.55 0.294288 0.241684 4322 22 2468 7314 316742 64936 5.22444 5.22444 -1305.28 -5.22444 0 0 431135. 2551.09 0.08 0.11 0.0698875 0.0612333 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt index 30d45f589c9..00ba1689b32 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt @@ -1,4 +1,4 @@ -func_multiclock/once -func_multiclock/iterative -func_multiclock/vanilla -func_multiclock/blanket +regression_tests/vtr_reg_nightly_basic/func_multiclock/blanket +regression_tests/vtr_reg_nightly_basic/func_multiclock/iterative +regression_tests/vtr_reg_nightly_basic/func_multiclock/once +regression_tests/vtr_reg_nightly_basic/func_multiclock/vanilla diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/task_list.txt deleted file mode 100644 index 8bf2bc3db9e..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/task_list.txt +++ /dev/null @@ -1,17 +0,0 @@ -regression_tests/vtr_reg_nightly/vpr_reg_mcnc -regression_tests/vtr_reg_nightly/vtr_reg_qor_chain -regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_depop -regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer -regression_tests/vtr_reg_nightly/vtr_func_formal -regression_tests/vtr_reg_nightly/titan_quick_qor -regression_tests/vtr_reg_nightly/titan_other -regression_tests/vtr_reg_nightly/vtr_bidir -regression_tests/vtr_reg_nightly/complex_switch -regression_tests/vtr_reg_nightly/vpr_verify_rr_graph -regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir -regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch -regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan -regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check -regression_tests/vtr_reg_nightly/vtr_timing_update_diff -regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan -regression_tests/vtr_reg_nightly/symbiflow diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/golden_results.txt deleted file mode 100644 index 08900d9d5ef..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/golden_results.txt +++ /dev/null @@ -1,21 +0,0 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time placement_technique reward uniform_percentage median_percentage wmedian_percentage wcent_percentage fr_percentage critUni_percentage centroid_percentage - k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 4.36 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 38776 14 8 926 934 0 489 100 11 11 121 clb auto 0.72 4606 0.40 0.00 4.14102 -29.7523 -4.14102 nan 0.20 0.00119633 0.000925792 0.161892 0.121595 52 7437 24 4.36541e+06 4.20373e+06 379421. 3135.71 1.84 0.693864 0.555835 6938 19 3079 14370 484288 90595 4.83499 nan -34.8915 -4.83499 0 0 499620. 4129.09 0.10 0.22 0.120458 0.108216 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 6.83 -1 -1 -1 -1 -1 -1 -1 -1 -1 100 38 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 47192 38 3 1113 1116 0 660 141 12 12 144 clb auto 1.02 7385 0.50 0.00 4.95175 -14.4002 -4.95175 nan 0.19 0.00132372 0.000956629 0.169375 0.127544 72 12351 45 5.3894e+06 5.3894e+06 636745. 4421.84 3.83 0.772079 0.612161 11456 17 4645 24063 904212 148872 5.55636 nan -16.3985 -5.55636 0 0 794932. 5520.36 0.12 0.24 0.0973796 0.0861951 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 3.96 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 39408 9 19 897 916 0 559 109 11 11 121 clb auto 0.84 6066 0.35 0.00 4.29231 -70.9295 -4.29231 nan 0.16 0.00102617 0.000754225 0.125046 0.0955529 72 10169 35 4.36541e+06 4.36541e+06 523260. 4324.46 1.54 0.445493 0.355552 9121 18 3785 19131 685405 121198 5.08251 nan -82.3409 -5.08251 0 0 653410. 5400.08 0.10 0.20 0.083959 0.0750954 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 6.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 45768 229 197 1364 1561 1 539 497 16 16 256 io auto 0.62 4443 0.64 0.01 2.40107 -604.293 -2.40107 2.40107 0.52 0.0015757 0.0013551 0.205205 0.17354 40 7623 19 1.05632e+07 3.82647e+06 697968. 2726.44 2.92 0.747446 0.656044 7058 12 1744 4785 241404 52708 3.01949 3.01949 -726.043 -3.01949 0 0 870840. 3401.72 0.22 0.16 0.101605 0.0935094 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml clma.pre-vpr.blif common 24.65 -1 -1 -1 -1 -1 -1 -1 -1 -1 306 62 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 92200 62 82 3672 3754 1 2349 450 20 20 400 clb auto 2.74 28739 2.89 0.02 7.33978 -292.565 -7.33978 7.33978 0.73 0.00581983 0.0045519 0.947999 0.61775 92 46890 40 1.74617e+07 1.64916e+07 2.37849e+06 5946.23 14.00 3.33843 2.48872 42225 16 13783 58193 2198678 343498 8.16378 8.16378 -329.46 -8.16378 0 0 3.01539e+06 7538.48 0.62 0.79 0.378636 0.332663 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 4.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 51 256 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 45028 256 245 954 1199 0 581 552 18 18 324 io auto 0.25 4989 0.57 0.01 3.37847 -629.355 -3.37847 nan 0.55 0.00155578 0.00138396 0.170689 0.150943 44 8531 14 1.37969e+07 2.74859e+06 970398. 2995.06 1.46 0.52902 0.483013 7969 12 1965 4152 217807 49587 4.23063 nan -775 -4.23063 0 0 1.26150e+06 3893.53 0.24 0.10 0.059739 0.0563556 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 2.67 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 64 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 38364 64 39 1371 1410 1 542 169 11 11 121 clb auto 0.38 3413 0.32 0.00 4.67654 -912.396 -4.67654 4.67654 0.16 0.00100594 0.000816668 0.12706 0.0994781 46 6130 26 4.36541e+06 3.557e+06 343362. 2837.71 0.94 0.362434 0.297569 5260 13 1999 5620 169131 35211 5.53977 5.53977 -1090.5 -5.53977 0 0 440296. 3638.81 0.07 0.09 0.0650941 0.0594477 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 5.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 45988 229 197 1362 1559 1 566 497 16 16 256 io auto 0.66 4793 0.66 0.01 2.51785 -604.704 -2.51785 2.51785 0.40 0.00154819 0.00135536 0.200854 0.168258 46 7938 19 1.05632e+07 3.82647e+06 786978. 3074.13 2.50 0.734243 0.641832 7482 10 1826 4727 234733 52733 3.19583 3.19583 -717 -3.19583 0 0 1.01084e+06 3948.58 0.17 0.11 0.0688767 0.0644421 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml elliptic.pre-vpr.blif common 8.70 -1 -1 -1 -1 -1 -1 -1 -1 -1 166 131 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 63632 131 114 3421 3535 1 1164 411 15 15 225 clb auto 2.25 10398 1.12 0.01 6.52628 -3784.19 -6.52628 6.52628 0.35 0.00290542 0.00235057 0.415737 0.301601 62 16689 24 9.10809e+06 8.9464e+06 909814. 4043.62 2.83 1.17721 0.93764 15000 17 4999 21128 713315 123027 7.49463 7.49463 -4392.46 -7.49463 0 0 1.12687e+06 5008.33 0.19 0.39 0.260469 0.224137 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 24.83 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 91684 10 10 2659 2669 0 1393 308 19 19 361 clb auto 2.93 26140 1.67 0.01 5.75218 -55.7663 -5.75218 nan 0.66 0.00438337 0.00279442 0.533527 0.352352 92 44132 33 1.55754e+07 1.55215e+07 2.13123e+06 5903.67 15.76 2.52651 1.87954 39597 17 9715 60001 2696762 353002 6.60772 nan -63.286 -6.60772 0 0 2.70169e+06 7483.90 0.52 0.82 0.293592 0.258315 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml ex5p.pre-vpr.blif common 2.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 36372 8 63 761 824 0 435 133 10 10 100 clb auto 0.52 3998 0.30 0.00 3.54271 -155.067 -3.54271 nan 0.12 0.00150999 0.0011755 0.104424 0.0802546 62 6550 31 3.44922e+06 3.34143e+06 366588. 3665.88 1.10 0.323676 0.261994 6094 17 2709 12574 426888 79431 4.1719 nan -186.289 -4.1719 0 0 454102. 4541.02 0.07 0.12 0.0620518 0.0557626 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml frisc.pre-vpr.blif common 9.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 169 20 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 64416 20 116 3175 3291 1 1278 305 15 15 225 clb auto 1.77 13380 1.17 0.01 7.56455 -3941.67 -7.56455 7.56455 0.34 0.00277682 0.00226423 0.429569 0.312356 76 22460 36 9.10809e+06 9.10809e+06 1.08042e+06 4801.85 3.46 1.23017 0.972484 20283 19 6164 25645 1097708 182881 8.69548 8.69548 -4541.25 -8.69548 0 0 1.34805e+06 5991.31 0.22 0.41 0.232291 0.206855 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml misex3.pre-vpr.blif common 3.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 14 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 38188 14 14 828 842 0 472 100 11 11 121 clb auto 0.66 4472 0.29 0.00 4.02064 -52.776 -4.02064 nan 0.16 0.00094524 0.000696414 0.110625 0.0852328 54 7869 46 4.36541e+06 3.88037e+06 393282. 3250.26 1.41 0.414709 0.333625 6576 16 2671 12354 410056 75432 4.89666 nan -62.2285 -4.89666 0 0 511363. 4226.14 0.08 0.13 0.0661113 0.0599437 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml pdc.pre-vpr.blif common 18.83 -1 -1 -1 -1 -1 -1 -1 -1 -1 271 16 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 79064 16 40 2839 2879 0 1511 327 19 19 361 clb auto 2.29 23498 1.77 0.01 6.13416 -223.252 -6.13416 nan 0.64 0.00374336 0.00284388 0.574447 0.377083 84 39816 34 1.55754e+07 1.46053e+07 1.95904e+06 5426.71 10.58 2.48689 1.8409 35391 18 8962 48547 1930691 286226 7.01 nan -249.162 -7.01 0 0 2.48734e+06 6890.13 0.48 0.68 0.303059 0.267959 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml s298.pre-vpr.blif common 2.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 4 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 33628 4 6 726 732 1 380 74 10 10 100 clb auto 0.49 3569 0.24 0.00 5.54077 -44.6464 -5.54077 5.54077 0.12 0.000846487 0.000635962 0.100625 0.0782428 50 5478 26 3.44922e+06 3.44922e+06 295697. 2956.97 0.92 0.335583 0.275197 4975 16 2083 8762 272937 50612 6.18041 6.18041 -52.1211 -6.18041 0 0 379824. 3798.24 0.06 0.10 0.0597808 0.0544635 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 11.39 -1 -1 -1 -1 -1 -1 -1 -1 -1 250 29 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 79632 29 106 4782 4888 1 2018 385 18 18 324 clb auto 2.07 13078 1.69 0.01 4.46817 -3195.71 -4.46817 4.46817 0.56 0.00435607 0.00294557 0.640302 0.441684 52 21680 48 1.37969e+07 1.34735e+07 1.12378e+06 3468.47 4.24 1.86267 1.43077 19009 14 6279 16868 582183 118551 5.45344 5.45344 -3646.72 -5.45344 0 0 1.48031e+06 4568.86 0.27 0.36 0.266878 0.24087 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 10.86 -1 -1 -1 -1 -1 -1 -1 -1 -1 227 38 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 80312 38 304 4422 4726 1 2038 569 18 18 324 clb auto 1.82 13449 1.89 0.02 4.16995 -2665.67 -4.16995 4.16995 0.55 0.00470624 0.00318059 0.6478 0.452736 58 23840 35 1.37969e+07 1.22339e+07 1.26150e+06 3893.53 3.80 1.89616 1.47869 20578 14 6433 17363 638387 131973 5.22573 5.22573 -3068.94 -5.22573 0 0 1.60510e+06 4954.00 0.31 0.36 0.265548 0.241509 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.45 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 41348 41 35 1006 1041 0 599 161 12 12 144 clb auto 0.83 6384 0.44 0.00 4.12452 -119.318 -4.12452 nan 0.20 0.0011811 0.00087419 0.142915 0.109239 66 11228 27 5.3894e+06 4.58099e+06 593979. 4124.86 1.84 0.481825 0.384086 10130 18 4219 21318 758361 129163 4.91293 nan -139.398 -4.91293 0 0 735425. 5107.12 0.11 0.21 0.087897 0.0781507 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml spla.pre-vpr.blif common 12.28 -1 -1 -1 -1 -1 -1 -1 -1 -1 213 16 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 65920 16 46 2232 2278 0 1178 275 17 17 289 clb auto 1.79 15813 1.23 0.01 5.56061 -183.389 -5.56061 nan 0.48 0.00353067 0.00224815 0.419453 0.279048 72 27375 40 1.21262e+07 1.14794e+07 1.37091e+06 4743.65 6.17 1.43321 1.07751 24226 19 6729 36115 1420951 217710 6.47301 nan -214.84 -6.47301 0 0 1.71058e+06 5918.98 0.30 0.50 0.231287 0.204796 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 2.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 52 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 38420 52 122 1461 1583 1 476 237 10 10 100 clb auto 0.41 2412 0.32 0.00 4.20921 -1050.39 -4.20921 4.20921 0.12 0.0010223 0.000849699 0.120894 0.0960136 48 4749 25 3.44922e+06 3.39532e+06 287248. 2872.48 0.82 0.408789 0.338724 4022 12 1351 3243 108746 26426 4.95741 4.95741 -1201.15 -4.95741 0 0 366588. 3665.88 0.06 0.08 0.0620446 0.0568583 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_coffe/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_coffe/config/config.txt deleted file mode 100644 index 62aac9e4992..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_coffe/config/config.txt +++ /dev/null @@ -1,30 +0,0 @@ -# -############################################ -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/COFFE_22nm - -# Add circuits to list to sweep -circuit_list_add=spree.v -circuit_list_add=or1200.v -circuit_list_add=matmul_8x8_fp16.v - -# Add architectures to list to sweep -arch_list_add=agilex_arch.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# How to parse QoR info -qor_parse_file=qor_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements.txt - -#Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_coffe/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_coffe/config/golden_results.txt deleted file mode 100644 index 3ffd76acd50..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_coffe/config/golden_results.txt +++ /dev/null @@ -1,4 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -agilex_arch.xml spree.v common 369.46 0.12 21324 15 0.60 -1 -1 39744 -1 -1 52 45 6 -1 success v8.0.0-rc2-3464-g9db6ef823 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.4.0-67-generic x86_64 2021-03-18T06:37:49 casa51 /home/casauser/Desktop/Most-Updated-VTR/sdamghan/vtr_flow/tasks 2948032 45 32 1272 1229 1 802 136 178 82 14596 -1 mylayout 1.60 8503 0.59 0.00 7.83793 -5746.83 -7.83793 7.83793 196.24 0.0016149 0.00134296 0.289916 0.236667 72 19754 31 6.8487e+08 2.93092e+06 9.91456e+07 6792.65 95.70 0.753445 0.642307 16378 15 4235 12005 2791151 620927 9.33697 9.33697 -7066.84 -9.33697 0 0 1.22277e+08 8377.42 23.24 0.52 0.0990945 0.0915082 -agilex_arch.xml or1200.v common 478.64 0.31 40272 8 3.52 -1 -1 45632 -1 -1 199 385 4 -1 success v8.0.0-rc2-3464-g9db6ef823 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.4.0-67-generic x86_64 2021-03-18T06:37:49 casa51 /home/casauser/Desktop/Most-Updated-VTR/sdamghan/vtr_flow/tasks 2982648 385 394 4867 4602 1 2536 986 178 82 14596 -1 mylayout 5.30 60469 3.72 0.04 9.23583 -11851.8 -9.23583 9.23583 196.03 0.00620323 0.00555837 1.02093 0.888604 98 88585 28 6.8487e+08 7.3856e+06 1.26366e+08 8657.55 179.49 3.12592 2.80556 82552 18 13799 46793 6323987 1182870 10.4046 10.4046 -13466.1 -10.4046 0 0 1.58420e+08 10853.6 31.68 1.25 0.390119 0.366456 -agilex_arch.xml matmul_8x8_fp16.v common 531.50 1.02 75288 4 3.02 -1 -1 55820 -1 -1 252 134 24 -1 success v8.0.0-rc2-3464-g9db6ef823 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.4.0-67-generic x86_64 2021-03-18T06:37:49 casa51 /home/casauser/Desktop/Most-Updated-VTR/sdamghan/vtr_flow/tasks 3001344 134 97 8327 7357 2 3655 523 178 82 14596 -1 mylayout 8.12 39763 3.38 0.02 6.45572 -32299.2 -6.45572 1.92725 196.90 0.00952948 0.00772521 1.77527 1.42404 88 78700 44 6.8487e+08 1.59968e+07 1.15784e+08 7932.56 227.28 5.62023 4.74 64240 19 13490 24272 15930552 3414580 6.89785 2.29033 -36973.3 -6.89785 0 0 1.43607e+08 9838.80 28.11 2.30 0.559657 0.508002 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/golden_results.txt deleted file mode 100644 index e7106ff5a8f..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/golden_results.txt +++ /dev/null @@ -1,22 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 155.64 1.08 127548 18 37.53 -1 -1 70392 -1 -1 1008 133 24 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 287044 133 179 18339 18121 1 9040 1344 39 39 1521 clb auto 17.76 138925 10.78 0.08 17.3291 -132913 -17.3291 17.3291 2.83 0.0233226 0.0202863 3.21433 2.74386 106 195650 27 8.65315e+07 6.74784e+07 1.02794e+07 6758.33 50.36 10.6206 9.26324 182348 15 34912 125847 27216363 6482638 19.2483 19.2483 -152788 -19.2483 0 0 1.30215e+07 8561.12 2.39 4.83 1.43156 1.32714 -k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 392.24 5.03 389328 15 146.30 -1 -1 149032 -1 -1 2712 257 0 11 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 671208 257 32 35908 33296 1 19534 3012 63 63 3969 clb auto 45.14 255913 37.21 0.26 18.1917 -23818.8 -18.1917 18.1917 22.11 0.0516147 0.0463894 6.8373 5.96124 80 392154 29 2.36641e+08 1.50518e+08 2.15027e+07 5417.67 91.80 24.5863 21.5781 366453 20 88192 390830 20471535 3157944 20.5117 20.5117 -26441.9 -20.5117 0 0 2.71248e+07 6834.16 5.61 6.28 3.64364 3.35439 -k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 69.01 0.34 55708 5 26.56 -1 -1 69148 -1 -1 619 36 0 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 162360 36 100 14037 11284 1 3230 755 31 31 961 clb auto 11.53 45897 4.68 0.03 13.3428 -2596.7 -13.3428 13.3428 1.69 0.0114217 0.0101128 1.68256 1.46806 60 76713 48 5.14688e+07 3.33604e+07 3.85800e+06 4014.56 15.24 4.14488 3.63926 66475 13 12384 59651 2545727 332961 15.3759 15.3759 -2979.2 -15.3759 0 0 4.86014e+06 5057.38 0.81 0.91 0.644163 0.596931 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 4.36 0.35 45384 3 0.31 -1 -1 41132 -1 -1 93 142 0 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 39868 142 192 1069 1139 1 566 427 14 14 196 clb auto 0.53 1719 0.51 0.00 2.89823 -451.929 -2.89823 2.89823 0.28 0.00105332 0.000965843 0.18909 0.173081 38 3929 16 9.20055e+06 5.01214e+06 467348. 2384.43 0.76 0.448178 0.414908 3370 10 1156 1738 87127 23536 3.536 3.536 -547.719 -3.536 0 0 593372. 3027.41 0.10 0.05 0.042892 0.041158 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.79 0.03 9840 3 0.18 -1 -1 38064 -1 -1 65 99 1 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 33120 99 130 363 493 1 251 295 12 12 144 clb auto 0.11 617 0.20 0.00 2.00545 -202.179 -2.00545 2.00545 0.17 0.000347656 0.000314547 0.0609896 0.0555735 46 1412 9 5.66058e+06 4.05111e+06 378966. 2631.71 0.42 0.142214 0.131386 1261 9 529 668 43396 14976 2.66687 2.66687 -234.696 -2.66687 0 0 486261. 3376.82 0.08 0.02 0.0133609 0.0128123 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 5.45 0.02 9352 6 0.13 -1 -1 38140 -1 -1 32 162 0 5 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 42768 162 96 1075 884 1 667 295 16 16 256 mult_36 auto 0.27 4733 0.47 0.01 15.5592 -1185.14 -15.5592 15.5592 0.35 0.00164413 0.00155059 0.229015 0.216092 62 10311 45 1.21132e+07 3.70461e+06 968026. 3781.35 2.81 0.720597 0.684741 8377 19 3224 5336 1782353 475161 17.1072 17.1072 -1423.44 -17.1072 0 0 1.20332e+06 4700.46 0.19 0.27 0.0868714 0.0833451 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 5.92 0.02 8604 6 0.08 -1 -1 38144 -1 -1 20 66 0 7 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 45512 66 96 866 607 1 547 189 18 18 324 mult_36 auto 0.29 4560 0.40 0.00 12.009 -735.792 -12.009 12.009 0.48 0.00164024 0.00157172 0.228917 0.219193 54 9621 47 1.57076e+07 3.84988e+06 1.09175e+06 3369.60 3.00 0.714008 0.68718 9058 18 3553 7591 3282454 770442 13.2466 13.2466 -862.815 -13.2466 0 0 1.41842e+06 4377.85 0.23 0.40 0.0773847 0.0749938 -k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 396.33 3.33 219016 100 52.94 -1 -1 107904 -1 -1 2180 114 44 8 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 586796 114 102 38208 33849 1 17938 2448 57 57 3249 clb auto 56.50 239395 32.12 0.23 66.5755 -50925.9 -66.5755 66.5755 17.50 0.0493685 0.0438785 7.43052 6.42444 92 361512 48 1.92089e+08 1.44771e+08 1.98119e+07 6097.84 192.54 24.6545 21.4476 328109 23 72468 273398 39855950 8187728 75.3499 75.3499 -63032 -75.3499 0 0 2.51903e+07 7753.25 4.79 8.67 3.78544 3.42841 -k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 3340.25 27.94 746972 102 477.56 -1 -1 373092 -1 -1 7495 114 167 32 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 2011368 114 102 124755 111050 1 59278 7910 102 102 10404 clb auto 177.54 1072406 247.04 1.51 67.6126 -342686 -67.6126 67.6126 64.41 0.201271 0.179091 29.5944 25.4921 128 1405319 39 6.36957e+08 5.08087e+08 8.68880e+07 8351.40 2161.55 100.542 87.0181 1350075 21 217881 912992 253789873 63051185 76.337 76.337 -476260 -76.337 0 0 1.09718e+08 10545.7 23.53 58.41 13.6383 12.2683 -k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 3241.51 28.65 928600 25 1897.53 -1 -1 376944 -1 -1 7078 36 159 27 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 2451584 36 33 190540 166259 1 61618 7333 99 99 9801 clb auto 176.91 718258 337.06 1.70 42.0812 -275832 -42.0812 42.0812 61.42 0.196016 0.174291 37.2747 32.1758 138 951582 21 6.00857e+08 4.79252e+08 8.73468e+07 8912.03 579.89 138.184 119.724 917221 22 225274 574203 91930691 20227411 45.1932 45.1932 -346416 -45.1932 0 0 1.11488e+08 11375.2 26.23 27.39 13.951 12.6666 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 45.93 0.60 78588 5 4.11 -1 -1 57064 -1 -1 456 506 45 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 318160 506 553 3519 4017 1 3099 1560 50 50 2500 memory auto 3.54 15041 3.96 0.03 6.68635 -1894.57 -6.68635 6.68635 13.09 0.00975899 0.00892439 2.06731 1.87235 38 23149 16 1.47946e+08 4.92362e+07 6.86579e+06 2746.32 10.05 4.61064 4.25515 22207 14 4233 5386 3331744 828056 7.52959 7.52959 -2298.71 -7.52959 0 0 8.69102e+06 3476.41 1.79 0.78 0.451892 0.430249 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 9.00 0.08 17600 2 0.07 -1 -1 37736 -1 -1 29 311 15 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 66704 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.42 8138 0.71 0.01 3.74116 -4094.6 -3.74116 3.74116 1.28 0.00224079 0.00197484 0.335269 0.293725 36 14917 17 4.25198e+07 9.78293e+06 1.94918e+06 2486.20 3.53 0.905895 0.81445 13627 14 3139 3534 2595237 727498 4.23116 4.23116 -4785.8 -4.23116 0 0 2.40571e+06 3068.51 0.45 0.39 0.0997164 0.093212 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 18.13 0.19 32272 4 1.40 -1 -1 41576 -1 -1 193 193 5 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 64092 193 205 2926 2852 1 1458 596 20 20 400 memory auto 2.23 11363 1.73 0.01 4.87719 -2477.32 -4.87719 4.87719 0.60 0.00309363 0.00270934 0.585 0.514648 56 21377 42 2.07112e+07 1.31415e+07 1.41661e+06 3541.53 9.25 1.56124 1.39721 17625 14 4928 12826 996652 229620 5.25923 5.25923 -2945.62 -5.25923 0 0 1.80858e+06 4521.44 0.29 0.27 0.176266 0.166291 -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 29.00 0.30 40356 8 3.32 -1 -1 47836 -1 -1 253 385 2 1 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 99660 385 394 4649 4513 1 2409 1035 27 27 729 io auto 5.71 30379 3.63 0.03 8.13796 -9652.08 -8.13796 8.13796 1.25 0.00614395 0.00563481 0.974168 0.888803 92 44752 19 3.93038e+07 1.51272e+07 4.24291e+06 5820.18 9.15 2.96353 2.72595 42651 19 10128 36430 3172325 595664 8.6066 8.6066 -10895.4 -8.6066 0 0 5.38988e+06 7393.52 0.91 0.77 0.411059 0.38823 -k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 12.97 0.22 32140 3 0.76 -1 -1 44472 -1 -1 111 214 0 8 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 61808 214 305 2963 2869 1 1440 638 19 19 361 io auto 1.82 11058 1.18 0.01 4.28804 -2547.99 -4.28804 4.28804 0.54 0.00327809 0.00301378 0.452357 0.415064 58 23745 38 1.72706e+07 9.15023e+06 1.32779e+06 3678.09 5.46 1.45919 1.35263 19546 16 5825 13540 3597927 808321 4.87643 4.87643 -2976.1 -4.87643 0 0 1.69263e+06 4688.74 0.28 0.55 0.185896 0.177314 -k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 176.54 0.65 38316 3 165.99 -1 -1 95588 -1 -1 156 38 0 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 59996 38 36 2995 2744 1 1210 230 17 17 289 clb auto 1.54 11099 0.96 0.01 8.60024 -2289.89 -8.60024 8.60024 0.42 0.00268266 0.00238109 0.37326 0.327349 66 16854 22 1.34605e+07 8.40746e+06 1.18400e+06 4096.89 2.62 1.13068 1.00608 15692 22 4746 12707 469422 81010 9.99242 9.99242 -2671.82 -9.99242 0 0 1.47169e+06 5092.36 0.24 0.26 0.207061 0.192508 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 7.39 0.10 21400 15 0.54 -1 -1 39460 -1 -1 65 45 3 1 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 45340 45 32 1275 1232 1 827 146 14 14 196 memory auto 1.82 6673 0.48 0.00 10.0822 -6325.59 -10.0822 10.0822 0.27 0.00151357 0.00131468 0.220965 0.191261 72 12424 18 9.20055e+06 5.54311e+06 844708. 4309.73 2.54 0.620034 0.549701 10987 13 3155 8576 1581981 414115 11.6443 11.6443 -7336.6 -11.6443 0 0 1.05868e+06 5401.43 0.16 0.26 0.0910415 0.0858264 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 40.23 1.10 119024 5 4.44 -1 -1 74600 -1 -1 704 157 0 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 238268 157 197 23846 21799 1 6676 1058 33 33 1089 clb auto 6.07 39618 5.22 0.04 2.9308 -13224.6 -2.9308 2.9308 1.92 0.0170934 0.0148804 2.3955 2.05486 50 62630 23 6.0475e+07 3.79415e+07 3.66263e+06 3363.29 9.95 6.51043 5.70708 55668 12 16379 25575 918337 183454 3.69492 3.69492 -15705.8 -3.69492 0 0 4.71657e+06 4331.10 0.80 0.89 0.945921 0.886384 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 89.73 1.03 105076 3 20.89 -1 -1 89012 -1 -1 675 115 0 40 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 260800 115 145 23133 19546 1 9716 975 40 40 1600 mult_36 auto 6.43 81193 6.66 0.05 4.85074 -22294.2 -4.85074 4.85074 2.98 0.0187538 0.0163566 2.84536 2.49603 82 134682 37 9.16046e+07 5.22191e+07 8.58295e+06 5364.35 34.42 9.16026 8.14536 119058 16 33969 51744 22437603 4613086 5.29409 5.29409 -25657.1 -5.29409 0 0 1.07702e+07 6731.38 1.86 3.39 1.10756 1.0344 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 470.22 1.29 149236 3 4.46 -1 -1 206296 -1 -1 1653 149 0 324 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 1491184 149 182 65737 42630 1 35961 2308 104 104 10816 mult_36 auto 21.23 329951 31.98 0.21 14.5498 -61941.6 -14.5498 14.5498 68.09 0.0725127 0.0673415 11.4647 10.4712 90 443033 19 6.67561e+08 2.17385e+08 6.61421e+07 6115.21 265.32 45.5343 41.9549 430675 21 111059 129339 29959568 5987707 15.9808 15.9808 -72553.5 -15.9808 0 0 8.27409e+07 7649.86 18.60 7.66 4.48403 4.21097 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.20 0.03 10080 5 0.09 -1 -1 37680 -1 -1 14 11 0 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-27T00:36:48 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 28936 11 30 313 321 2 118 55 7 7 49 clb auto 0.19 380 0.06 0.00 2.27568 -154.498 -2.27568 2.04477 0.04 0.000275918 0.000231588 0.0376074 0.0323751 30 1183 37 1.07788e+06 754516 77114.5 1573.76 0.20 0.0977514 0.0855348 771 16 577 1036 37069 12535 2.63781 2.28939 -181.689 -2.63781 0 0 95414.1 1947.23 0.01 0.02 0.0185412 0.0172295 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_depop/config/golden_results.txt deleted file mode 100644 index 9603a62bbba..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_depop/config/golden_results.txt +++ /dev/null @@ -1,22 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml arm_core.v common 187.25 1.04 127444 18 36.75 -1 -1 70508 -1 -1 844 133 24 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 305136 133 179 18339 18121 1 8939 1180 36 36 1296 clb memory auto 9.43 133843 10.97 0.08 18.4184 -141279 -18.4184 18.4184 2.50 0.0229132 0.0199845 3.31095 2.83212 146 224959 37 7.21828e+07 5.86395e+07 1.23606e+07 9537.51 89.99 14.4936 12.6468 207535 16 38497 147575 36095601 8273636 20.0278 20.0278 -158267 -20.0278 0 0 1.55729e+07 12016.1 2.68 5.94 1.47278 1.36488 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 411.87 4.89 389256 15 145.12 -1 -1 148924 -1 -1 2307 257 0 11 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 684476 257 32 35908 33296 1 18838 2607 58 58 3364 clb auto 27.78 235429 34.46 0.25 17.4391 -23409.1 -17.4391 17.4391 23.79 0.0516571 0.0464058 6.72323 5.86433 112 479499 41 2.00088e+08 1.28693e+08 2.63593e+07 7835.69 126.73 26.7317 23.4004 442114 21 99544 467606 43136625 7767692 20.4189 20.4189 -26309.7 -20.4189 0 0 3.33056e+07 9900.58 6.95 9.19 3.76089 3.45424 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml blob_merge.v common 74.42 0.32 55600 5 26.37 -1 -1 69372 -1 -1 539 36 0 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 168468 36 100 14037 11284 1 3701 675 29 29 841 clb auto 7.67 46059 4.90 0.03 12.6594 -2401.1 -12.6594 12.6594 1.50 0.0113697 0.0101221 1.77879 1.55494 98 94409 37 4.4999e+07 2.90489e+07 5.54665e+06 6595.30 23.80 6.42558 5.64015 84384 20 15443 69619 5194421 916834 14.3714 14.3714 -2913.99 -14.3714 0 0 6.99642e+06 8319.17 1.17 1.38 0.809104 0.740731 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml boundtop.v common 4.22 0.34 45380 3 0.29 -1 -1 41572 -1 -1 90 142 0 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 40724 142 192 1069 1139 1 529 424 14 14 196 clb auto 0.33 1652 0.47 0.00 2.91405 -454.748 -2.91405 2.91405 0.29 0.00101596 0.000930337 0.178086 0.163008 50 3783 18 9.20055e+06 4.85046e+06 641979. 3275.40 0.85 0.437009 0.40476 3531 11 1197 2084 128194 36276 3.65266 3.65266 -552.825 -3.65266 0 0 827179. 4220.30 0.13 0.06 0.0454842 0.0436016 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.80 0.03 9760 3 0.18 -1 -1 38088 -1 -1 64 99 1 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 32720 99 130 363 493 1 261 294 12 12 144 clb auto 0.08 697 0.20 0.00 2.11495 -207.011 -2.11495 2.11495 0.19 0.000348369 0.00031603 0.0615553 0.056146 42 1903 12 5.66058e+06 3.99722e+06 373597. 2594.42 0.44 0.145309 0.134279 1800 12 675 938 87522 29405 2.95628 2.95628 -261.888 -2.95628 0 0 468675. 3254.69 0.08 0.03 0.0150321 0.0143185 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq1.v common 6.08 0.02 9420 6 0.13 -1 -1 38280 -1 -1 26 162 0 5 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 44148 162 96 1075 884 1 667 289 16 16 256 mult_36 auto 0.26 5078 0.45 0.01 15.3726 -1203.18 -15.3726 15.3726 0.37 0.00159172 0.00150165 0.217858 0.20566 60 11156 33 1.21132e+07 3.38124e+06 1.01260e+06 3955.47 3.41 0.669616 0.636427 9613 24 3616 6215 1828440 447202 17.5186 17.5186 -1462.9 -17.5186 0 0 1.26536e+06 4942.82 0.20 0.28 0.101724 0.0975686 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq2.v common 7.38 0.02 8508 6 0.08 -1 -1 38240 -1 -1 16 66 0 7 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 44272 66 96 866 607 1 533 185 18 18 324 mult_36 auto 0.18 4735 0.39 0.00 12.0481 -714.751 -12.0481 12.0481 0.51 0.00156185 0.00149181 0.225278 0.215582 52 11667 29 1.57076e+07 3.6343e+06 1.14165e+06 3523.62 4.31 0.652578 0.627735 10315 22 4558 9816 5259633 1258198 13.5233 13.5233 -870.647 -13.5233 0 0 1.50318e+06 4639.44 0.25 0.64 0.0893253 0.0865332 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU8PEEng.v common 356.39 3.25 219112 100 52.78 -1 -1 108040 -1 -1 1841 114 44 8 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 607268 114 102 38208 33849 1 17353 2109 52 52 2704 clb auto 40.91 231454 30.60 0.22 66.2277 -52518.7 -66.2277 66.2277 18.20 0.0525876 0.0443016 7.42057 6.35547 126 414532 46 1.58905e+08 1.26502e+08 2.31921e+07 8576.97 166.12 26.4719 22.9515 382076 24 80752 321509 53511812 11238071 73.8205 73.8205 -66754.4 -73.8205 -18.6509 -0.298787 2.92176e+07 10805.3 5.94 10.83 3.89497 3.51774 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU32PEEng.v common 3688.47 27.99 746852 102 475.93 -1 -1 373264 -1 -1 6283 114 167 32 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 2073192 114 102 124755 111050 1 58496 6698 94 94 8836 clb auto 120.74 1038840 228.08 1.44 63.968 -327364 -63.968 63.968 69.33 0.200467 0.178616 28.6759 24.9879 166 1627499 49 5.40921e+08 4.42773e+08 9.94454e+07 11254.6 2577.31 117.347 101.565 1527530 23 242192 1034564 250008716 57569237 76.0612 76.0612 -480995 -76.0612 -53.7561 -0.292146 1.26268e+08 14290.2 29.87 55.24 14.4939 13.0224 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mcml.v common 3379.36 27.64 928572 25 1899.47 -1 -1 377356 -1 -1 6728 36 159 27 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 2273420 36 33 190540 166259 1 60177 6983 97 97 9409 clb auto 143.40 724582 365.42 1.81 39.3272 -247845 -39.3272 39.3272 73.89 0.198517 0.176588 39.423 34.166 150 1097566 40 5.71422e+08 4.60391e+08 9.66696e+07 10274.2 698.69 117.68 102.115 1026180 21 255543 695596 135326112 29284113 42.7203 42.7203 -313582 -42.7203 -0.103902 -0.0259755 1.22193e+08 12986.9 28.82 33.14 13.6095 12.3398 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkDelayWorker32B.v common 52.01 0.58 78644 5 4.10 -1 -1 56812 -1 -1 453 506 45 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 379156 506 553 3519 4017 1 3086 1557 50 50 2500 memory auto 3.21 15906 3.98 0.03 6.63464 -1807.67 -6.63464 6.63464 17.03 0.00947631 0.0086483 2.02448 1.83037 40 24763 18 1.47946e+08 4.90746e+07 7.85310e+06 3141.24 11.63 4.53457 4.1715 23665 16 4699 6227 4255095 1086941 7.29496 7.29496 -2223.41 -7.29496 -5.03631 -0.193229 9.77405e+06 3909.62 2.09 0.90 0.453391 0.428763 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkPktMerge.v common 9.91 0.07 17508 2 0.05 -1 -1 38116 -1 -1 25 311 15 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 69352 311 156 1019 1160 1 954 507 28 28 784 memory auto 0.36 7932 0.70 0.01 3.65703 -4338.92 -3.65703 3.65703 1.39 0.00224839 0.00198333 0.328793 0.287966 40 14723 37 4.25198e+07 9.56735e+06 2.32339e+06 2963.51 4.20 0.979749 0.879163 13500 17 3399 3683 2547833 716874 4.00095 4.00095 -5037.99 -4.00095 -15.6433 -0.322548 2.89875e+06 3697.39 0.54 0.39 0.113703 0.106063 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 15.61 0.17 32120 4 1.37 -1 -1 41652 -1 -1 167 193 5 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 68864 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.11 10697 1.67 0.01 4.1938 -2470.95 -4.1938 4.1938 0.64 0.00301318 0.0026482 0.573855 0.504906 78 21098 24 2.07112e+07 1.17403e+07 2.06176e+06 5154.39 7.68 1.7345 1.55585 18857 15 4972 14066 1481027 326048 4.86803 4.86803 -2859.5 -4.86803 -7.79205 -0.298787 2.60035e+06 6500.87 0.40 0.33 0.185004 0.174222 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml or1200.v common 49.36 0.29 40224 8 3.32 -1 -1 47528 -1 -1 202 385 2 1 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 108164 385 394 4649 4513 1 2346 984 27 27 729 io auto 2.99 30099 3.35 0.03 8.26188 -9666.23 -8.26188 8.26188 1.31 0.00619508 0.00563721 0.934643 0.853705 110 56434 38 3.93038e+07 1.23786e+07 5.33614e+06 7319.81 31.89 3.92552 3.60655 49850 19 11513 40653 5326074 1123118 8.66997 8.66997 -10836.2 -8.66997 0 0 6.77266e+06 9290.34 1.04 1.01 0.407545 0.384812 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 12.10 0.21 32160 3 0.74 -1 -1 44396 -1 -1 100 214 0 8 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 67700 214 305 2963 2869 1 1462 627 19 19 361 io auto 1.04 10916 1.12 0.02 4.47257 -2470.71 -4.47257 4.47257 0.58 0.00325314 0.00297249 0.427366 0.392074 68 25698 40 1.72706e+07 8.5574e+06 1.69273e+06 4689.01 5.37 1.42935 1.32583 21459 19 6285 15322 3278969 748877 4.76857 4.76857 -2933.03 -4.76857 0 0 2.08404e+06 5772.96 0.34 0.52 0.202764 0.192626 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml sha.v common 174.38 0.63 38292 3 163.00 -1 -1 95180 -1 -1 138 38 0 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 59976 38 36 2995 2744 1 1208 212 16 16 256 clb auto 1.19 11256 1.03 0.01 8.87371 -2382.95 -8.87371 8.87371 0.37 0.00262154 0.00231849 0.379138 0.332311 80 21797 26 1.21132e+07 7.43737e+06 1.29183e+06 5046.22 3.86 1.28485 1.14366 19351 22 5540 18113 1095161 241229 10.3694 10.3694 -2917.57 -10.3694 0 0 1.62458e+06 6346.00 0.24 0.33 0.209243 0.194591 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml spree.v common 8.36 0.10 21344 15 0.54 -1 -1 39348 -1 -1 49 45 3 1 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 49056 45 32 1275 1232 1 822 130 14 14 196 memory auto 0.65 6630 0.49 0.00 9.55177 -6480.8 -9.55177 9.55177 0.29 0.00146805 0.00127764 0.231034 0.200329 100 14267 33 9.20055e+06 4.68081e+06 1.19340e+06 6088.79 4.56 0.820973 0.727793 12397 14 3745 10984 1853298 463403 10.4092 10.4092 -7370.27 -10.4092 -17.8589 -0.318417 1.49920e+06 7648.97 0.21 0.28 0.0940894 0.0885721 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision0.v common 41.53 1.06 118912 5 4.36 -1 -1 74660 -1 -1 684 157 0 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 244556 157 197 23846 21799 1 6801 1038 33 33 1089 clb auto 4.63 40314 5.46 0.04 2.95855 -13303.1 -2.95855 2.95855 2.04 0.0164469 0.0143127 2.47104 2.11624 64 68056 41 6.0475e+07 3.68636e+07 5.14656e+06 4725.95 11.77 7.62774 6.68359 64167 14 19652 32945 2075106 479443 3.72591 3.72591 -16028.1 -3.72591 0 0 6.36035e+06 5840.54 1.15 1.09 1.00087 0.933792 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision1.v common 133.86 0.97 105084 3 20.99 -1 -1 89004 -1 -1 642 115 0 40 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 285336 115 145 23133 19546 1 9748 942 40 40 1600 mult_36 auto 4.38 76270 6.86 0.06 4.99955 -21585.1 -4.99955 4.99955 3.25 0.0187086 0.0162909 2.9171 2.55796 88 140299 45 9.16046e+07 5.04406e+07 9.92704e+06 6204.40 78.64 11.9198 10.5858 123303 21 39408 63999 27118412 5502186 5.37438 5.37438 -25122.8 -5.37438 0 0 1.23763e+07 7735.20 2.27 4.08 1.28064 1.18571 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 487.35 1.23 149116 3 4.33 -1 -1 206360 -1 -1 1647 149 0 324 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 1769720 149 182 65737 42630 1 35973 2302 104 104 10816 mult_36 auto 20.76 330013 33.83 0.22 14.5277 -60838.7 -14.5277 14.5277 84.99 0.0740934 0.0689308 11.8726 10.8735 80 478178 22 6.67561e+08 2.17062e+08 6.43241e+07 5947.13 261.35 45.1675 41.6041 446994 18 117664 142709 36786595 7674733 16.6813 16.6813 -72795.8 -16.6813 0 0 8.07606e+07 7466.78 18.94 8.01 4.06519 3.82761 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision3.v common 1.05 0.03 10192 5 0.09 -1 -1 37336 -1 -1 15 11 0 0 success v8.0.0-rc2-3485-gbdf51aa9b Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-44-generic x86_64 2021-03-26T10:28:49 CASA44 /home/casauser/Desktop/Most-Updated-VTRs/sdamghan/vtr_flow/tasks 29604 11 30 313 321 2 108 56 7 7 49 clb auto 0.12 395 0.06 0.00 2.36605 -152.494 -2.36605 1.9999 0.04 0.000299962 0.000258146 0.037683 0.0321939 30 1169 31 1.07788e+06 808410 84241.2 1719.21 0.17 0.0900147 0.0784088 944 17 532 1516 56407 21898 3.07845 2.37233 -183.444 -3.07845 0 0 103128. 2104.65 0.01 0.03 0.0181695 0.0168082 diff --git a/vtr_flow/tasks/arithmetic_tasks/FIR_filters/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters/config/config.txt similarity index 94% rename from vtr_flow/tasks/arithmetic_tasks/FIR_filters/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters/config/config.txt index f36c8c43392..8f57d738514 100644 --- a/vtr_flow/tasks/arithmetic_tasks/FIR_filters/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters/config/config.txt @@ -102,14 +102,17 @@ circuit_list_add=fir_nopipe_52.v # Add architectures to list to sweep arch_list_add=k6_N8_gate_boost_0.2V_22nm.xml -arch_list_add=k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml -arch_list_add=k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml +#arch_list_add=k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml +#arch_list_add=k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml arch_list_add=k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml arch_list_add=k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml # Parse info and how to parse parse_file=vpr_chain.txt +# How to parse QoR info +qor_parse_file=qor_standard.txt + # Pass requirements pass_requirements_file=pass_requirements_chain.txt diff --git a/vtr_flow/tasks/arithmetic_tasks/FIR_filters_frac/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac/config/config.txt similarity index 98% rename from vtr_flow/tasks/arithmetic_tasks/FIR_filters_frac/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac/config/config.txt index e8f7ebe78e4..9cd3cc14274 100644 --- a/vtr_flow/tasks/arithmetic_tasks/FIR_filters_frac/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac/config/config.txt @@ -110,6 +110,9 @@ arch_list_add=k6_frac_uripple_N8_22nm.xml # Parse info and how to parse parse_file=vpr_chain.txt +# How to parse QoR info +qor_parse_file=qor_standard.txt + # Pass requirements pass_requirements_file=pass_requirements_chain.txt diff --git a/vtr_flow/tasks/arithmetic_tasks/adder_trees/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/config.txt similarity index 98% rename from vtr_flow/tasks/arithmetic_tasks/adder_trees/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/config.txt index 52feb579b4a..789e94c56a5 100644 --- a/vtr_flow/tasks/arithmetic_tasks/adder_trees/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/config.txt @@ -81,6 +81,9 @@ arch_list_add=fixed_k6_frac_uripple_N8_22nm.xml # Parse info and how to parse parse_file=vpr_chain.txt +# How to parse QoR info +qor_parse_file=qor_standard.txt + # Pass requirements pass_requirements_file=pass_requirements_chain.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/golden_results.txt new file mode 100644 index 00000000000..b51c607d059 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/golden_results.txt @@ -0,0 +1,541 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_004bits.v common 1.32 0.01 6220 0 0.01 -1 -1 29604 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63096 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_004bits.v common 1.39 0.01 6148 0 0.00 -1 -1 29640 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62892 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_005bits.v common 1.30 0.03 6272 0 0.01 -1 -1 29624 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62988 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_005bits.v common 1.29 0.02 6248 0 0.00 -1 -1 29700 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63076 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_006bits.v common 1.35 0.02 6272 0 0.00 -1 -1 29656 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63032 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_006bits.v common 1.33 0.02 6320 0 0.01 -1 -1 29640 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62972 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_007bits.v common 1.38 0.01 6348 0 0.01 -1 -1 29680 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62940 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_007bits.v common 1.33 0.01 6396 0 0.00 -1 -1 29812 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62940 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_008bits.v common 1.32 0.02 6472 0 0.01 -1 -1 29720 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62960 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_008bits.v common 1.44 0.02 6388 0 0.01 -1 -1 29588 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62960 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_009bits.v common 1.37 0.02 6444 0 0.00 -1 -1 29612 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62812 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_009bits.v common 1.37 0.02 6448 0 0.00 -1 -1 29616 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62780 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_010bits.v common 1.33 0.03 6500 0 0.00 -1 -1 29636 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62880 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_010bits.v common 1.36 0.03 6536 0 0.01 -1 -1 29604 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62900 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_011bits.v common 1.43 0.03 6564 0 0.02 -1 -1 29676 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62968 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_011bits.v common 1.43 0.03 6636 0 0.01 -1 -1 29624 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63084 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_012bits.v common 1.35 0.03 6604 0 0.00 -1 -1 29588 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62740 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_012bits.v common 1.35 0.03 6608 0 0.00 -1 -1 29596 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63132 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_013bits.v common 1.32 0.03 6692 0 0.00 -1 -1 29780 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63068 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_013bits.v common 1.34 0.02 6652 0 0.00 -1 -1 29676 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62848 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_014bits.v common 1.32 0.02 6672 0 0.00 -1 -1 29832 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63016 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_014bits.v common 1.34 0.03 6696 0 0.01 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63020 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_015bits.v common 1.34 0.03 6824 0 0.00 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63044 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_015bits.v common 1.37 0.02 6880 0 0.01 -1 -1 29824 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63136 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_016bits.v common 1.35 0.03 6860 0 0.01 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62736 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_016bits.v common 1.38 0.02 6948 0 0.01 -1 -1 29700 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63176 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_017bits.v common 1.34 0.03 6952 0 0.01 -1 -1 29668 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62780 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_017bits.v common 1.34 0.03 6920 0 0.00 -1 -1 29736 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63112 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_018bits.v common 1.42 0.02 6968 0 0.00 -1 -1 29756 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63020 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_018bits.v common 1.37 0.03 6972 0 0.00 -1 -1 29792 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63220 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_019bits.v common 1.33 0.04 7052 0 0.00 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63192 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_019bits.v common 1.28 0.02 7088 0 0.00 -1 -1 29664 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63124 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_020bits.v common 1.39 0.04 7084 0 0.00 -1 -1 29704 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63196 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_020bits.v common 1.37 0.03 7100 0 0.01 -1 -1 29676 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63032 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_021bits.v common 1.36 0.03 7120 0 0.01 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63268 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_021bits.v common 1.35 0.04 7080 0 0.01 -1 -1 29668 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63196 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_022bits.v common 1.34 0.03 7104 0 0.00 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63064 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_022bits.v common 1.32 0.02 7172 0 0.00 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63204 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_023bits.v common 1.37 0.04 7192 0 0.01 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62848 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_023bits.v common 1.33 0.03 7228 0 0.01 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63252 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_024bits.v common 1.36 0.03 7276 0 0.00 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62840 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_024bits.v common 1.34 0.04 7280 0 0.00 -1 -1 29660 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63096 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_028bits.v common 1.39 0.04 7564 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63132 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_028bits.v common 1.45 0.04 7496 0 0.00 -1 -1 29780 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63044 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_032bits.v common 1.44 0.05 7680 0 0.00 -1 -1 29704 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63372 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_032bits.v common 1.49 0.04 7732 0 0.00 -1 -1 29700 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62912 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_048bits.v common 1.41 0.06 8524 0 0.01 -1 -1 29784 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63264 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_048bits.v common 1.38 0.06 8524 0 0.01 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63484 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_064bits.v common 1.36 0.05 9368 0 0.02 -1 -1 29840 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63512 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_064bits.v common 1.43 0.07 9372 0 0.00 -1 -1 29920 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63488 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_096bits.v common 1.42 0.12 10960 0 0.01 -1 -1 30004 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63064 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_096bits.v common 1.54 0.09 11036 0 0.01 -1 -1 30032 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63084 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_2L_128bits.v common 1.43 0.11 12844 0 0.01 -1 -1 30276 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62756 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_tree_3L_128bits.v common 1.44 0.11 12768 0 0.02 -1 -1 30308 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63172 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_004bits.v common 1.36 0.02 6224 0 0.00 -1 -1 29808 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63636 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_004bits.v common 1.32 0.02 6276 0 0.00 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63536 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_005bits.v common 1.44 0.02 6288 0 0.01 -1 -1 29880 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63092 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_005bits.v common 1.31 0.02 6268 0 0.01 -1 -1 29752 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63524 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_006bits.v common 1.32 0.03 6360 0 0.00 -1 -1 29792 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63164 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_006bits.v common 1.35 0.01 6440 0 0.01 -1 -1 29848 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63316 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_007bits.v common 1.35 0.02 6328 0 0.01 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63436 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_007bits.v common 1.36 0.03 6332 0 0.00 -1 -1 29948 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63472 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_008bits.v common 1.32 0.02 6444 0 0.00 -1 -1 29764 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63128 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_008bits.v common 1.32 0.02 6400 0 0.01 -1 -1 29808 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63432 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_009bits.v common 1.34 0.03 6484 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63420 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_009bits.v common 1.44 0.02 6516 0 0.00 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63480 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_010bits.v common 1.35 0.02 6500 0 0.01 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63672 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_010bits.v common 1.43 0.02 6552 0 0.00 -1 -1 29612 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63592 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_011bits.v common 1.39 0.03 6640 0 0.01 -1 -1 29668 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63432 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_011bits.v common 1.39 0.03 6532 0 0.00 -1 -1 29784 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63664 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_012bits.v common 1.46 0.02 6712 0 0.01 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63308 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.53 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_012bits.v common 1.36 0.03 6668 0 0.01 -1 -1 29760 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63232 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_013bits.v common 1.39 0.03 6716 0 0.00 -1 -1 29800 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63304 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_013bits.v common 1.33 0.02 6660 0 0.00 -1 -1 29720 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63376 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_014bits.v common 1.39 0.03 6740 0 0.01 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63072 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_014bits.v common 1.33 0.03 6736 0 0.00 -1 -1 29888 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63268 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_015bits.v common 1.38 0.03 6788 0 0.01 -1 -1 29780 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63212 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_015bits.v common 1.34 0.03 6712 0 0.01 -1 -1 29836 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63356 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_016bits.v common 1.34 0.03 6784 0 0.01 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63180 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_016bits.v common 1.33 0.03 6764 0 0.00 -1 -1 29732 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63360 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_017bits.v common 1.46 0.04 6880 0 0.01 -1 -1 29812 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63136 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_017bits.v common 1.39 0.03 6868 0 0.00 -1 -1 29736 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63356 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_018bits.v common 1.36 0.02 6896 0 0.00 -1 -1 29844 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63428 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_018bits.v common 1.34 0.03 6836 0 0.00 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63156 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_019bits.v common 1.35 0.02 6904 0 0.00 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63524 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_019bits.v common 1.42 0.03 6972 0 0.00 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63188 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_020bits.v common 1.33 0.03 7112 0 0.01 -1 -1 29748 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63360 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_020bits.v common 1.43 0.03 7004 0 0.01 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63240 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_021bits.v common 1.38 0.03 7116 0 0.01 -1 -1 29752 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63512 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_021bits.v common 1.40 0.03 7096 0 0.01 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63216 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_022bits.v common 1.39 0.03 7080 0 0.01 -1 -1 29764 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63512 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_022bits.v common 1.39 0.02 7076 0 0.01 -1 -1 29732 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63348 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_023bits.v common 1.39 0.03 7200 0 0.01 -1 -1 29732 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63300 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_023bits.v common 1.63 0.03 7200 0 0.01 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63624 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_024bits.v common 1.37 0.04 7148 0 0.00 -1 -1 29820 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63164 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_024bits.v common 1.34 0.02 7172 0 0.01 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63264 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_028bits.v common 1.34 0.04 7420 0 0.00 -1 -1 29820 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63416 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_028bits.v common 1.33 0.03 7288 0 0.01 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63680 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_032bits.v common 1.38 0.04 7432 0 0.01 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63524 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_032bits.v common 1.34 0.03 7488 0 0.01 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63636 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_048bits.v common 1.41 0.05 8196 0 0.01 -1 -1 29840 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63472 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_048bits.v common 1.46 0.06 8096 0 0.01 -1 -1 29720 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63724 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_064bits.v common 1.38 0.05 8872 0 0.01 -1 -1 29952 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63572 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_064bits.v common 1.38 0.07 8800 0 0.01 -1 -1 29872 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63376 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_096bits.v common 1.49 0.07 10116 0 0.01 -1 -1 30060 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64132 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_096bits.v common 1.40 0.08 10024 0 0.02 -1 -1 30084 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63544 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_128bits.v common 1.51 0.15 11472 0 0.01 -1 -1 30320 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63652 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_128bits.v common 1.44 0.11 11448 0 0.01 -1 -1 30388 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63712 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_004bits.v common 1.37 0.02 6248 0 0.00 -1 -1 29676 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63244 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_004bits.v common 1.50 0.02 6288 0 0.00 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63280 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_005bits.v common 1.32 0.02 6352 0 0.01 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63244 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_005bits.v common 1.33 0.02 6396 0 0.01 -1 -1 29700 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63240 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_006bits.v common 1.31 0.02 6320 0 0.01 -1 -1 29892 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63448 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_006bits.v common 1.36 0.02 6400 0 0.00 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63416 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_007bits.v common 1.31 0.02 6484 0 0.00 -1 -1 29820 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63344 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_007bits.v common 1.40 0.01 6336 0 0.00 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63192 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_008bits.v common 1.29 0.01 6396 0 0.01 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63300 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_008bits.v common 1.40 0.03 6452 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63276 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_009bits.v common 1.38 0.02 6508 0 0.01 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62940 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_009bits.v common 1.44 0.02 6496 0 0.00 -1 -1 29752 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63172 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_010bits.v common 1.34 0.03 6536 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63436 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_010bits.v common 1.33 0.02 6564 0 0.01 -1 -1 29624 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62916 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_011bits.v common 1.52 0.02 6608 0 0.01 -1 -1 29668 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63464 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.67 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_011bits.v common 1.39 0.02 6608 0 0.00 -1 -1 29656 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63372 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_012bits.v common 1.35 0.02 6616 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63288 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_012bits.v common 1.34 0.03 6584 0 0.00 -1 -1 29760 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63116 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_013bits.v common 1.38 0.02 6676 0 0.00 -1 -1 29632 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63284 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_013bits.v common 1.38 0.03 6628 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63108 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_014bits.v common 1.44 0.03 6688 0 0.00 -1 -1 29624 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63484 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_014bits.v common 1.33 0.02 6820 0 0.00 -1 -1 29792 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63396 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.01 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_015bits.v common 1.40 0.03 6776 0 0.01 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62944 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_015bits.v common 1.34 0.02 6744 0 0.00 -1 -1 29640 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63584 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_016bits.v common 1.39 0.04 6844 0 0.00 -1 -1 29732 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63068 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_016bits.v common 1.36 0.04 6840 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63236 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_017bits.v common 1.46 0.03 6884 0 0.00 -1 -1 29800 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63096 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.58 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_017bits.v common 1.34 0.03 6872 0 0.01 -1 -1 29776 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63240 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_018bits.v common 1.39 0.02 6844 0 0.00 -1 -1 29796 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63168 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_018bits.v common 1.37 0.02 6936 0 0.00 -1 -1 29808 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62956 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_019bits.v common 1.36 0.02 6936 0 0.00 -1 -1 29856 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63156 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_019bits.v common 1.31 0.03 6968 0 0.01 -1 -1 29820 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62840 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_020bits.v common 1.37 0.04 6952 0 0.01 -1 -1 29824 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63232 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_020bits.v common 1.34 0.03 7036 0 0.01 -1 -1 29880 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63080 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_021bits.v common 1.50 0.04 7020 0 0.01 -1 -1 29720 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63140 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_021bits.v common 1.38 0.03 7048 0 0.01 -1 -1 29800 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63332 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_022bits.v common 1.48 0.03 7060 0 0.01 -1 -1 29836 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63096 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_022bits.v common 1.40 0.03 7084 0 0.00 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63288 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_023bits.v common 1.48 0.03 7192 0 0.00 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63324 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.56 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_023bits.v common 1.38 0.03 7104 0 0.01 -1 -1 29844 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63108 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_024bits.v common 1.36 0.04 7232 0 0.00 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63068 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_024bits.v common 1.35 0.04 7104 0 0.01 -1 -1 29760 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63208 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_028bits.v common 1.40 0.04 7344 0 0.00 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63404 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_028bits.v common 1.38 0.03 7264 0 0.00 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63296 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_032bits.v common 1.36 0.04 7420 0 0.00 -1 -1 29824 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63408 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_032bits.v common 1.34 0.05 7432 0 0.00 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63248 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_048bits.v common 1.33 0.06 8108 0 0.01 -1 -1 29748 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63452 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_048bits.v common 1.31 0.04 8076 0 0.00 -1 -1 29916 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63320 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_064bits.v common 1.37 0.06 8780 0 0.01 -1 -1 30016 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63664 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_064bits.v common 1.38 0.06 8816 0 0.01 -1 -1 30032 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63412 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_096bits.v common 1.47 0.12 10152 0 0.01 -1 -1 29944 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63548 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_096bits.v common 1.41 0.08 10084 0 0.01 -1 -1 29996 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63804 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_128bits.v common 1.41 0.11 11424 0 0.01 -1 -1 30300 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63292 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_128bits.v common 1.49 0.11 11524 0 0.01 -1 -1 30324 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64184 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_004bits.v common 1.30 0.01 6320 0 0.00 -1 -1 29720 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63104 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_004bits.v common 1.42 0.01 6324 0 0.01 -1 -1 29760 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63308 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_005bits.v common 1.33 0.02 6308 0 0.01 -1 -1 29860 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63160 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_005bits.v common 1.73 0.03 6216 0 0.00 -1 -1 29912 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63140 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_006bits.v common 1.41 0.02 6420 0 0.00 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62980 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.53 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_006bits.v common 1.36 0.03 6356 0 0.00 -1 -1 29844 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63012 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_007bits.v common 1.30 0.01 6332 0 0.00 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63232 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_007bits.v common 1.35 0.01 6400 0 0.01 -1 -1 29696 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63640 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_008bits.v common 1.33 0.02 6372 0 0.00 -1 -1 29732 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63328 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.01 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_008bits.v common 1.30 0.02 6404 0 0.01 -1 -1 29676 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63208 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_009bits.v common 1.44 0.03 6544 0 0.01 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63336 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_009bits.v common 1.33 0.02 6460 0 0.00 -1 -1 29672 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63488 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_010bits.v common 1.36 0.02 6444 0 0.00 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63304 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_010bits.v common 1.32 0.01 6600 0 0.00 -1 -1 29648 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63152 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_011bits.v common 1.31 0.02 6644 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63452 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_011bits.v common 1.42 0.03 6564 0 0.01 -1 -1 29648 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63256 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_012bits.v common 1.32 0.02 6684 0 0.00 -1 -1 29720 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63520 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_012bits.v common 1.44 0.03 6664 0 0.01 -1 -1 29760 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63420 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_013bits.v common 1.33 0.02 6704 0 0.00 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63196 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_013bits.v common 1.30 0.02 6672 0 0.00 -1 -1 29668 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63324 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_014bits.v common 1.48 0.03 6644 0 0.00 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63360 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_014bits.v common 1.45 0.02 6716 0 0.01 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63520 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_015bits.v common 1.35 0.03 6768 0 0.01 -1 -1 29640 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63344 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_015bits.v common 1.35 0.03 6764 0 0.01 -1 -1 29624 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63368 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_016bits.v common 1.38 0.03 6820 0 0.01 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63040 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_016bits.v common 1.35 0.03 6864 0 0.00 -1 -1 29704 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63196 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_017bits.v common 1.32 0.03 6848 0 0.00 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63188 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_017bits.v common 1.32 0.03 6860 0 0.00 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63132 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_018bits.v common 1.39 0.03 6840 0 0.00 -1 -1 29820 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63212 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_018bits.v common 1.33 0.03 6848 0 0.00 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63164 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_019bits.v common 1.32 0.02 6932 0 0.00 -1 -1 29784 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62948 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_019bits.v common 1.34 0.04 6932 0 0.00 -1 -1 29736 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62940 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_020bits.v common 1.35 0.04 6912 0 0.00 -1 -1 29760 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63380 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_020bits.v common 1.30 0.02 6988 0 0.00 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63200 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_021bits.v common 1.37 0.03 7032 0 0.00 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63244 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_021bits.v common 1.37 0.03 7028 0 0.00 -1 -1 29828 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63064 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_022bits.v common 1.32 0.03 7032 0 0.01 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63132 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_022bits.v common 1.39 0.03 7152 0 0.00 -1 -1 29776 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63432 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_023bits.v common 1.33 0.04 7156 0 0.00 -1 -1 29752 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63548 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_023bits.v common 1.33 0.04 7100 0 0.01 -1 -1 29784 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63476 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_024bits.v common 1.38 0.04 7112 0 0.01 -1 -1 29752 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63544 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_024bits.v common 1.38 0.02 7164 0 0.01 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63360 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_028bits.v common 1.35 0.04 7396 0 0.00 -1 -1 29840 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63152 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_028bits.v common 1.48 0.03 7368 0 0.00 -1 -1 29760 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63172 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_032bits.v common 1.48 0.03 7480 0 0.01 -1 -1 29824 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63432 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_032bits.v common 1.31 0.04 7460 0 0.02 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63460 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_048bits.v common 1.38 0.06 8180 0 0.01 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63672 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_048bits.v common 1.35 0.04 8272 0 0.01 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63388 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_064bits.v common 1.41 0.05 9088 0 0.01 -1 -1 30084 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63472 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_064bits.v common 1.40 0.08 9016 0 0.01 -1 -1 29976 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63668 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_096bits.v common 1.49 0.11 10484 0 0.01 -1 -1 29980 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63460 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_096bits.v common 1.43 0.08 10464 0 0.01 -1 -1 29988 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63440 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_128bits.v common 1.44 0.11 11964 0 0.01 -1 -1 30340 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63264 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_128bits.v common 1.42 0.11 11956 0 0.01 -1 -1 30288 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63804 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_004bits.v common 1.32 0.02 6280 0 0.00 -1 -1 29656 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63368 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_004bits.v common 1.36 0.02 6264 0 0.01 -1 -1 29720 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63172 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_005bits.v common 1.40 0.01 6236 0 0.00 -1 -1 29832 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63044 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_005bits.v common 1.37 0.03 6288 0 0.00 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63028 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_006bits.v common 1.38 0.02 6264 0 0.01 -1 -1 29784 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63116 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_006bits.v common 1.37 0.02 6340 0 0.01 -1 -1 29916 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63168 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_007bits.v common 1.40 0.03 6328 0 0.01 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62912 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_007bits.v common 1.42 0.03 6360 0 0.01 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63016 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.56 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_008bits.v common 1.34 0.03 6424 0 0.01 -1 -1 29700 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62916 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_008bits.v common 1.38 0.02 6348 0 0.00 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63192 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_009bits.v common 1.43 0.02 6540 0 0.00 -1 -1 29764 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63260 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_009bits.v common 1.41 0.02 6468 0 0.01 -1 -1 29728 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63332 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_010bits.v common 1.45 0.02 6524 0 0.01 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63576 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_010bits.v common 1.37 0.03 6564 0 0.00 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63160 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_011bits.v common 1.34 0.02 6564 0 0.01 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63092 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_011bits.v common 1.33 0.02 6544 0 0.00 -1 -1 29656 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63264 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_012bits.v common 1.35 0.04 6596 0 0.00 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63024 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_012bits.v common 1.33 0.02 6588 0 0.00 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63456 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_013bits.v common 1.32 0.03 6584 0 0.00 -1 -1 29780 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63128 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_013bits.v common 1.36 0.03 6736 0 0.00 -1 -1 29792 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63300 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_014bits.v common 1.32 0.03 6704 0 0.00 -1 -1 29720 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63316 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_014bits.v common 1.32 0.03 6716 0 0.00 -1 -1 29680 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63348 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_015bits.v common 1.32 0.03 6768 0 0.00 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63020 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_015bits.v common 1.49 0.02 6804 0 0.01 -1 -1 29632 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62924 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.53 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_016bits.v common 1.36 0.02 6896 0 0.01 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62824 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_016bits.v common 1.34 0.03 6820 0 0.00 -1 -1 29736 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63260 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_017bits.v common 1.42 0.03 6852 0 0.01 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62792 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_017bits.v common 1.36 0.03 6928 0 0.01 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62956 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_018bits.v common 1.41 0.03 6884 0 0.01 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63012 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_018bits.v common 1.39 0.03 6820 0 0.01 -1 -1 29700 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63060 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_019bits.v common 1.32 0.03 6932 0 0.01 -1 -1 29848 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63060 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_019bits.v common 1.33 0.03 6888 0 0.00 -1 -1 29764 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63468 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_020bits.v common 1.38 0.03 6912 0 0.01 -1 -1 29704 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63256 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_020bits.v common 1.31 0.03 6960 0 0.00 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62956 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_021bits.v common 1.34 0.03 7052 0 0.00 -1 -1 29828 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63192 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_021bits.v common 1.38 0.03 7032 0 0.01 -1 -1 29848 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62884 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_022bits.v common 1.34 0.04 7032 0 0.00 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63172 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_022bits.v common 1.35 0.03 7108 0 0.00 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63388 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_023bits.v common 1.34 0.03 7072 0 0.00 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62984 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_023bits.v common 1.36 0.04 7068 0 0.01 -1 -1 29776 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63128 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_024bits.v common 1.36 0.04 7196 0 0.01 -1 -1 29696 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63364 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_024bits.v common 1.39 0.04 7176 0 0.00 -1 -1 29876 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63384 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_028bits.v common 1.32 0.03 7340 0 0.00 -1 -1 29816 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63200 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_028bits.v common 1.34 0.03 7368 0 0.01 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63424 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_032bits.v common 1.46 0.05 7604 0 0.02 -1 -1 29812 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63392 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_032bits.v common 1.37 0.03 7536 0 0.01 -1 -1 29832 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63084 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_048bits.v common 1.34 0.06 8208 0 0.00 -1 -1 29836 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63448 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_048bits.v common 1.36 0.05 8224 0 0.01 -1 -1 29844 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63600 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_064bits.v common 1.39 0.08 8956 0 0.01 -1 -1 29996 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63740 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_064bits.v common 1.39 0.07 8948 0 0.01 -1 -1 29964 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63292 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_096bits.v common 1.45 0.10 10496 0 0.01 -1 -1 29992 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63020 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_096bits.v common 1.44 0.09 10484 0 0.01 -1 -1 29992 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62952 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_2L_128bits.v common 1.53 0.12 11992 0 0.01 -1 -1 30360 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63000 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_tree_3L_128bits.v common 1.46 0.14 12092 0 0.01 -1 -1 30280 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63108 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_004bits.v common 1.68 0.01 6332 0 0.01 -1 -1 29664 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62260 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.56 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_004bits.v common 1.37 0.03 6264 0 0.00 -1 -1 29696 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63528 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_005bits.v common 1.37 0.02 6288 0 0.00 -1 -1 29900 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62216 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_005bits.v common 1.59 0.02 6324 0 0.00 -1 -1 29856 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63840 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_006bits.v common 1.39 0.02 6372 0 0.00 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62000 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_006bits.v common 1.39 0.02 6392 0 0.01 -1 -1 29876 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62380 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_007bits.v common 1.41 0.02 6396 0 0.01 -1 -1 29904 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62220 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_007bits.v common 1.39 0.02 6468 0 0.01 -1 -1 29852 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62284 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_008bits.v common 1.35 0.03 6420 0 0.01 -1 -1 29704 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62264 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_008bits.v common 1.37 0.02 6568 0 0.00 -1 -1 29728 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62260 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_009bits.v common 1.37 0.03 6464 0 0.00 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64076 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_009bits.v common 1.35 0.01 6408 0 0.00 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62188 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_010bits.v common 1.42 0.02 6484 0 0.00 -1 -1 29784 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62388 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_010bits.v common 1.41 0.02 6480 0 0.01 -1 -1 29828 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64016 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_011bits.v common 1.48 0.03 6656 0 0.01 -1 -1 29732 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62456 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_011bits.v common 1.36 0.03 6656 0 0.00 -1 -1 29608 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62220 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_012bits.v common 1.36 0.03 6620 0 0.01 -1 -1 29736 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64044 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_012bits.v common 1.42 0.03 6660 0 0.00 -1 -1 29704 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63580 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_013bits.v common 1.39 0.02 6664 0 0.01 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62112 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_013bits.v common 1.57 0.03 6704 0 0.01 -1 -1 29704 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62508 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_014bits.v common 1.44 0.02 6716 0 0.01 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62476 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.53 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_014bits.v common 1.37 0.03 6716 0 0.00 -1 -1 29776 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62212 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_015bits.v common 1.37 0.02 6712 0 0.00 -1 -1 29748 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63564 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_015bits.v common 1.38 0.02 6816 0 0.01 -1 -1 29644 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62544 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_016bits.v common 1.38 0.04 6828 0 0.01 -1 -1 29780 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63984 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_016bits.v common 1.42 0.03 6760 0 0.01 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63744 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_017bits.v common 1.36 0.03 6848 0 0.00 -1 -1 29752 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62576 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_017bits.v common 1.43 0.03 6940 0 0.00 -1 -1 29764 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62688 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_018bits.v common 1.63 0.03 6888 0 0.01 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64000 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_018bits.v common 1.41 0.03 6836 0 0.00 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63864 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_019bits.v common 1.41 0.03 6944 0 0.02 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62564 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.53 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_019bits.v common 1.33 0.02 6928 0 0.00 -1 -1 29800 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63812 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_020bits.v common 1.51 0.04 6992 0 0.00 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63852 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_020bits.v common 1.42 0.03 7076 0 0.01 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64216 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_021bits.v common 1.39 0.03 7036 0 0.00 -1 -1 29720 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62412 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_021bits.v common 1.61 0.03 7052 0 0.00 -1 -1 29776 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62416 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_022bits.v common 1.46 0.04 7124 0 0.01 -1 -1 29808 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64240 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_022bits.v common 1.45 0.03 7080 0 0.00 -1 -1 29792 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63952 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_023bits.v common 1.38 0.04 7060 0 0.00 -1 -1 29776 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62472 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_023bits.v common 1.44 0.04 7060 0 0.01 -1 -1 29876 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63740 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_024bits.v common 1.56 0.04 7212 0 0.00 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62160 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_024bits.v common 1.38 0.03 7172 0 0.00 -1 -1 29808 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64024 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_028bits.v common 1.37 0.04 7328 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63764 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_028bits.v common 1.42 0.04 7296 0 0.01 -1 -1 29784 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62356 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.53 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_032bits.v common 1.38 0.04 7500 0 0.01 -1 -1 29756 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 61420 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_032bits.v common 1.43 0.04 7528 0 0.00 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63956 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_048bits.v common 1.46 0.06 8220 0 0.00 -1 -1 29800 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64324 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_048bits.v common 1.38 0.05 8272 0 0.01 -1 -1 29852 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 61504 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_064bits.v common 1.42 0.05 8952 0 0.01 -1 -1 30000 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64040 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_064bits.v common 1.44 0.06 9020 0 0.01 -1 -1 30100 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64288 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_096bits.v common 1.45 0.08 10564 0 0.02 -1 -1 29992 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64148 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_096bits.v common 1.51 0.12 10492 0 0.01 -1 -1 29936 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63816 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_2L_128bits.v common 1.50 0.11 12032 0 0.01 -1 -1 30348 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64756 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_tree_3L_128bits.v common 1.50 0.15 12056 0 0.01 -1 -1 30272 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64332 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_004bits.v common 1.40 0.02 6340 0 0.00 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63920 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_004bits.v common 1.37 0.02 6268 0 0.00 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63944 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_005bits.v common 1.61 0.02 6340 0 0.00 -1 -1 29868 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63816 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_005bits.v common 1.39 0.02 6292 0 0.01 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63796 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_006bits.v common 1.35 0.03 6376 0 0.00 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63796 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_006bits.v common 1.58 0.02 6352 0 0.01 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63580 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_007bits.v common 1.35 0.03 6340 0 0.00 -1 -1 29764 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63772 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_007bits.v common 1.40 0.03 6340 0 0.00 -1 -1 29808 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64024 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_008bits.v common 1.42 0.02 6428 0 0.00 -1 -1 29752 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63948 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_008bits.v common 1.44 0.03 6512 0 0.01 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63508 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_009bits.v common 1.39 0.02 6480 0 0.01 -1 -1 29816 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63440 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_009bits.v common 1.40 0.02 6468 0 0.00 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63856 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_010bits.v common 1.37 0.01 6536 0 0.00 -1 -1 29736 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63620 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_010bits.v common 1.33 0.02 6536 0 0.00 -1 -1 29676 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63852 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_011bits.v common 1.35 0.03 6660 0 0.01 -1 -1 29756 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63864 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_011bits.v common 1.51 0.03 6584 0 0.01 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63588 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_012bits.v common 1.41 0.03 6632 0 0.00 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64020 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_012bits.v common 1.38 0.02 6700 0 0.01 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63688 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_013bits.v common 1.43 0.02 6672 0 0.01 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63692 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_013bits.v common 1.34 0.02 6624 0 0.00 -1 -1 29748 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63628 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_014bits.v common 1.53 0.02 6768 0 0.00 -1 -1 29636 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63820 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_014bits.v common 1.37 0.02 6772 0 0.01 -1 -1 29640 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63780 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_015bits.v common 1.39 0.03 6760 0 0.01 -1 -1 29636 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63848 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_015bits.v common 1.56 0.03 6708 0 0.01 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63896 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_016bits.v common 1.47 0.03 6808 0 0.01 -1 -1 29792 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63992 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_016bits.v common 1.45 0.03 6832 0 0.01 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63868 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_017bits.v common 1.37 0.03 6896 0 0.00 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64008 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_017bits.v common 1.54 0.03 6948 0 0.00 -1 -1 29760 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63776 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_018bits.v common 1.48 0.03 6836 0 0.01 -1 -1 29756 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63668 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_018bits.v common 1.37 0.03 6852 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63968 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_019bits.v common 1.39 0.03 6940 0 0.00 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63812 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_019bits.v common 1.38 0.02 6928 0 0.00 -1 -1 29832 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63728 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_020bits.v common 1.40 0.03 7080 0 0.00 -1 -1 29832 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63632 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_020bits.v common 1.37 0.02 6976 0 0.00 -1 -1 29816 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63732 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_021bits.v common 1.43 0.04 7036 0 0.00 -1 -1 29748 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63620 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_021bits.v common 1.49 0.03 7120 0 0.01 -1 -1 29824 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64120 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_022bits.v common 1.41 0.04 7124 0 0.00 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64128 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_022bits.v common 1.55 0.03 7172 0 0.01 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64236 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_023bits.v common 1.37 0.03 7076 0 0.00 -1 -1 29832 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64036 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_023bits.v common 1.35 0.03 7076 0 0.00 -1 -1 29792 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63712 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_024bits.v common 1.46 0.04 7172 0 0.01 -1 -1 29840 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63748 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_024bits.v common 1.52 0.03 7208 0 0.01 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63968 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_028bits.v common 1.40 0.06 7356 0 0.01 -1 -1 29844 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64016 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_028bits.v common 1.37 0.04 7372 0 0.02 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64084 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_032bits.v common 1.64 0.04 7584 0 0.00 -1 -1 29816 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64188 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_032bits.v common 1.37 0.04 7548 0 0.02 -1 -1 29800 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63640 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_048bits.v common 1.38 0.06 8248 0 0.01 -1 -1 29796 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63924 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_048bits.v common 1.56 0.05 8268 0 0.01 -1 -1 29748 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64020 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_064bits.v common 1.56 0.08 9040 0 0.01 -1 -1 30104 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64344 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_064bits.v common 1.52 0.08 9024 0 0.01 -1 -1 29972 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64604 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_096bits.v common 1.54 0.08 10476 0 0.01 -1 -1 30008 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63920 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_096bits.v common 1.59 0.09 10488 0 0.00 -1 -1 29976 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64124 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_2L_128bits.v common 1.53 0.10 11992 0 0.01 -1 -1 30316 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64508 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_tree_3L_128bits.v common 1.59 0.11 12000 0 0.01 -1 -1 30416 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64476 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_004bits.v common 1.36 0.02 6228 0 0.01 -1 -1 29596 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63436 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_004bits.v common 1.36 0.03 6224 0 0.01 -1 -1 29600 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63204 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_005bits.v common 1.39 0.02 6316 0 0.00 -1 -1 29756 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63364 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_005bits.v common 1.38 0.03 6284 0 0.01 -1 -1 29816 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63520 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_006bits.v common 1.68 0.02 6264 0 0.00 -1 -1 29764 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63548 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_006bits.v common 1.35 0.03 6340 0 0.01 -1 -1 29624 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63676 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_007bits.v common 1.32 0.02 6348 0 0.01 -1 -1 29752 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63344 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_007bits.v common 1.37 0.02 6320 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63476 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_008bits.v common 1.52 0.02 6412 0 0.00 -1 -1 29636 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63196 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_008bits.v common 1.39 0.02 6412 0 0.01 -1 -1 29736 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63364 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_009bits.v common 1.43 0.03 6464 0 0.01 -1 -1 29636 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62944 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_009bits.v common 1.41 0.02 6428 0 0.01 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63156 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_010bits.v common 1.35 0.03 6468 0 0.00 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63108 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_010bits.v common 1.40 0.02 6596 0 0.00 -1 -1 29644 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63536 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_011bits.v common 1.36 0.02 6608 0 0.01 -1 -1 29704 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63376 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_011bits.v common 1.33 0.03 6576 0 0.01 -1 -1 29852 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63116 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_012bits.v common 1.36 0.03 6708 0 0.00 -1 -1 29760 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63492 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_012bits.v common 1.67 0.02 6616 0 0.01 -1 -1 29660 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63112 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_013bits.v common 1.37 0.03 6664 0 0.00 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63288 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_013bits.v common 1.48 0.03 6704 0 0.00 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63464 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_014bits.v common 1.76 0.03 6720 0 0.01 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63444 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_014bits.v common 1.42 0.03 6720 0 0.01 -1 -1 29848 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63264 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_015bits.v common 1.36 0.02 6816 0 0.00 -1 -1 29752 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63568 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_015bits.v common 1.87 0.02 6800 0 0.00 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63172 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.76 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_016bits.v common 1.42 0.03 6872 0 0.00 -1 -1 29728 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63264 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_016bits.v common 1.47 0.03 6908 0 0.00 -1 -1 29720 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63232 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_017bits.v common 1.42 0.02 6956 0 0.00 -1 -1 29676 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63548 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.53 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_017bits.v common 1.39 0.03 6936 0 0.00 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63228 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_018bits.v common 1.42 0.02 6964 0 0.01 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63388 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_018bits.v common 1.33 0.02 6976 0 0.00 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63172 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_019bits.v common 1.37 0.04 7016 0 0.00 -1 -1 29836 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63268 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_019bits.v common 1.36 0.03 7032 0 0.01 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63136 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_020bits.v common 1.38 0.03 7076 0 0.00 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63452 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_020bits.v common 1.32 0.02 7044 0 0.00 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62952 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_021bits.v common 1.41 0.03 7148 0 0.00 -1 -1 29756 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63612 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_021bits.v common 1.41 0.03 7072 0 0.00 -1 -1 29704 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63604 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_022bits.v common 1.41 0.02 7120 0 0.01 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63508 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_022bits.v common 1.36 0.03 7168 0 0.00 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63172 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_023bits.v common 1.38 0.04 7252 0 0.01 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63220 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_023bits.v common 1.37 0.04 7248 0 0.00 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63632 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_024bits.v common 1.39 0.03 7272 0 0.00 -1 -1 29780 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63592 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_024bits.v common 1.48 0.03 7268 0 0.00 -1 -1 29784 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63832 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_028bits.v common 1.46 0.04 7540 0 0.00 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63772 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_028bits.v common 1.50 0.04 7520 0 0.01 -1 -1 29660 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63528 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_032bits.v common 1.42 0.04 7792 0 0.00 -1 -1 29736 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63368 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_032bits.v common 1.42 0.04 7716 0 0.01 -1 -1 29692 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63620 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_048bits.v common 1.53 0.05 8516 0 0.00 -1 -1 29776 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63752 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_048bits.v common 1.43 0.05 8608 0 0.01 -1 -1 29852 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63700 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_064bits.v common 1.48 0.07 9384 0 0.01 -1 -1 29808 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63760 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_064bits.v common 1.46 0.08 9404 0 0.01 -1 -1 29884 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63468 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_096bits.v common 1.72 0.11 10968 0 0.01 -1 -1 29980 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63332 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_096bits.v common 1.52 0.11 10996 0 0.01 -1 -1 30088 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63152 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_2L_128bits.v common 1.45 0.11 12824 0 0.00 -1 -1 30312 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63656 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_tree_3L_128bits.v common 1.51 0.11 12788 0 0.01 -1 -1 30224 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64084 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_004bits.v common 1.36 0.02 6268 0 0.01 -1 -1 29736 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63764 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_004bits.v common 1.38 0.01 6340 0 0.00 -1 -1 29620 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63768 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_005bits.v common 1.40 0.02 6232 0 0.01 -1 -1 29892 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63648 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_005bits.v common 1.44 0.02 6288 0 0.00 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63684 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_006bits.v common 1.50 0.02 6428 0 0.01 -1 -1 29836 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63880 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.56 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_006bits.v common 1.45 0.02 6284 0 0.01 -1 -1 29832 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63624 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_007bits.v common 1.37 0.01 6472 0 0.01 -1 -1 29872 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63412 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_007bits.v common 1.53 0.01 6404 0 0.00 -1 -1 29952 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63664 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_008bits.v common 1.52 0.02 6512 0 0.00 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63660 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.01 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_008bits.v common 1.43 0.02 6424 0 0.00 -1 -1 29700 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63856 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_009bits.v common 1.71 0.02 6560 0 0.00 -1 -1 29728 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63672 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_009bits.v common 1.41 0.02 6496 0 0.00 -1 -1 29736 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63540 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.02 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_010bits.v common 1.47 0.03 6560 0 0.00 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63768 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_010bits.v common 1.43 0.03 6528 0 0.01 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63424 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_011bits.v common 1.37 0.02 6576 0 0.00 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63900 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_011bits.v common 1.46 0.03 6596 0 0.00 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63704 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_012bits.v common 1.36 0.03 6632 0 0.02 -1 -1 29748 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63648 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_012bits.v common 1.42 0.03 6660 0 0.00 -1 -1 29792 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63904 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_013bits.v common 1.54 0.02 6748 0 0.01 -1 -1 29664 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63720 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_013bits.v common 1.43 0.02 6592 0 0.00 -1 -1 29676 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63720 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_014bits.v common 1.38 0.03 6724 0 0.01 -1 -1 29732 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63896 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_014bits.v common 1.41 0.03 6736 0 0.00 -1 -1 29784 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63732 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_015bits.v common 1.35 0.03 6768 0 0.00 -1 -1 29656 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63456 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_015bits.v common 1.38 0.02 6780 0 0.01 -1 -1 29776 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63740 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_016bits.v common 1.60 0.03 6840 0 0.01 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64116 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_016bits.v common 1.44 0.03 6836 0 0.01 -1 -1 29748 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63988 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_017bits.v common 1.52 0.03 6844 0 0.01 -1 -1 29896 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63868 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_017bits.v common 1.36 0.03 6864 0 0.00 -1 -1 29732 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63448 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_018bits.v common 1.52 0.03 6920 0 0.01 -1 -1 29868 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63764 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_018bits.v common 1.36 0.03 6852 0 0.00 -1 -1 29832 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63504 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_019bits.v common 1.50 0.03 6948 0 0.00 -1 -1 29780 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64036 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_019bits.v common 1.74 0.03 7024 0 0.00 -1 -1 29728 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64124 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.01 0 -1 -1 -1 -1 -1 -1 0.64 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_020bits.v common 1.40 0.04 7040 0 0.00 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63528 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_020bits.v common 1.54 0.03 7020 0 0.01 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63680 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_021bits.v common 1.43 0.02 7000 0 0.00 -1 -1 29704 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63760 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_021bits.v common 1.60 0.03 6972 0 0.01 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63948 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_022bits.v common 1.55 0.04 7076 0 0.01 -1 -1 29784 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63824 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_022bits.v common 1.51 0.03 7084 0 0.00 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64016 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_023bits.v common 1.40 0.04 7208 0 0.01 -1 -1 29780 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63628 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_023bits.v common 1.41 0.03 7128 0 0.00 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64012 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_024bits.v common 1.37 0.04 7212 0 0.00 -1 -1 29724 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64024 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_024bits.v common 1.38 0.04 7160 0 0.00 -1 -1 29756 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63944 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_028bits.v common 1.38 0.04 7324 0 0.00 -1 -1 29752 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63680 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_028bits.v common 1.51 0.04 7380 0 0.00 -1 -1 29780 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64040 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_032bits.v common 1.44 0.04 7480 0 0.01 -1 -1 29716 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63984 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_032bits.v common 1.36 0.04 7556 0 0.01 -1 -1 29756 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63604 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_048bits.v common 1.40 0.06 8288 0 0.01 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64024 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_048bits.v common 1.52 0.06 8276 0 0.01 -1 -1 29720 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63880 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_064bits.v common 1.46 0.07 9012 0 0.01 -1 -1 30012 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64324 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_064bits.v common 1.45 0.08 9024 0 0.01 -1 -1 30040 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64188 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_096bits.v common 1.50 0.12 10472 0 0.01 -1 -1 29956 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64244 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_096bits.v common 1.67 0.09 10412 0 0.01 -1 -1 30008 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63956 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_2L_128bits.v common 1.58 0.15 12004 0 0.01 -1 -1 30332 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64244 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_tree_3L_128bits.v common 1.74 0.13 12032 0 0.02 -1 -1 30300 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64488 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_004bits.v common 1.35 0.02 6192 0 0.00 -1 -1 29700 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62744 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_004bits.v common 1.35 0.02 6268 0 0.01 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63328 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_005bits.v common 1.42 0.02 6264 0 0.01 -1 -1 29772 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63088 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_005bits.v common 1.39 0.02 6236 0 0.01 -1 -1 29784 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63580 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.53 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_006bits.v common 1.55 0.02 6348 0 0.01 -1 -1 29924 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62920 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_006bits.v common 1.48 0.02 6360 0 0.00 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63160 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_007bits.v common 1.45 0.02 6444 0 0.00 -1 -1 29880 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63140 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_007bits.v common 1.36 0.02 6468 0 0.00 -1 -1 29848 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63084 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_008bits.v common 1.37 0.03 6476 0 0.00 -1 -1 29740 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63568 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_008bits.v common 1.40 0.02 6444 0 0.01 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63384 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_009bits.v common 1.39 0.02 6472 0 0.00 -1 -1 29656 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63664 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_009bits.v common 1.42 0.02 6480 0 0.00 -1 -1 29672 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63768 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_010bits.v common 1.40 0.05 6608 0 0.00 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63048 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_010bits.v common 1.48 0.02 6564 0 0.00 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62956 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.53 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_011bits.v common 1.54 0.02 6588 0 0.01 -1 -1 29836 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62868 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_011bits.v common 1.48 0.02 6580 0 0.00 -1 -1 29804 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62940 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.58 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_012bits.v common 1.41 0.03 6628 0 0.00 -1 -1 29712 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63544 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_012bits.v common 1.48 0.02 6604 0 0.00 -1 -1 29612 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63284 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.56 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_013bits.v common 1.40 0.03 6652 0 0.00 -1 -1 29688 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62912 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_013bits.v common 1.43 0.02 6748 0 0.00 -1 -1 29792 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62968 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_014bits.v common 1.42 0.02 6808 0 0.01 -1 -1 29780 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63376 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_014bits.v common 1.40 0.03 6728 0 0.00 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63280 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_015bits.v common 1.40 0.03 6764 0 0.00 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63796 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_015bits.v common 1.37 0.04 6852 0 0.02 -1 -1 29756 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63672 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_016bits.v common 1.98 0.03 6824 0 0.00 -1 -1 29788 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63132 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.76 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_016bits.v common 1.73 0.02 6836 0 0.02 -1 -1 29816 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63176 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_017bits.v common 2.06 0.03 6820 0 0.01 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63076 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.83 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_017bits.v common 1.47 0.03 6872 0 0.00 -1 -1 29760 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63516 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_018bits.v common 1.47 0.03 6884 0 0.00 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63544 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_018bits.v common 1.45 0.04 6900 0 0.00 -1 -1 29728 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63156 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_019bits.v common 1.43 0.06 6968 0 0.00 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63712 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_019bits.v common 1.37 0.03 6876 0 0.01 -1 -1 29764 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63652 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_020bits.v common 1.38 0.04 6988 0 0.00 -1 -1 29808 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62740 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_020bits.v common 1.37 0.03 7008 0 0.00 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63624 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_021bits.v common 1.47 0.03 7028 0 0.01 -1 -1 29704 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63936 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_021bits.v common 1.36 0.04 7084 0 0.00 -1 -1 29700 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63640 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_022bits.v common 1.58 0.03 7084 0 0.01 -1 -1 29728 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63756 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.65 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_022bits.v common 1.56 0.03 7096 0 0.01 -1 -1 29684 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62984 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.62 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_023bits.v common 1.56 0.04 7064 0 0.00 -1 -1 29744 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63748 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_023bits.v common 1.40 0.03 7116 0 0.01 -1 -1 29792 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63968 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_024bits.v common 1.36 0.04 7252 0 0.01 -1 -1 29700 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63508 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_024bits.v common 1.44 0.04 7196 0 0.01 -1 -1 29820 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63492 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_028bits.v common 1.64 0.04 7396 0 0.01 -1 -1 29768 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63788 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.56 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_028bits.v common 1.39 0.04 7456 0 0.00 -1 -1 29708 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63608 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_032bits.v common 1.57 0.04 7548 0 0.01 -1 -1 29756 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63828 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_032bits.v common 1.37 0.04 7528 0 0.01 -1 -1 29748 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63836 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_048bits.v common 1.42 0.05 8308 0 0.01 -1 -1 29812 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63536 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_048bits.v common 1.52 0.06 8340 0 0.01 -1 -1 29832 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63772 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_064bits.v common 1.47 0.07 9028 0 0.01 -1 -1 30012 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64224 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_064bits.v common 1.40 0.05 9100 0 0.01 -1 -1 29976 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64136 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_096bits.v common 1.52 0.08 10492 0 0.02 -1 -1 30004 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63260 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_096bits.v common 1.43 0.08 10488 0 0.01 -1 -1 30000 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63320 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_2L_128bits.v common 1.55 0.15 11956 0 0.01 -1 -1 30304 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64436 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_tree_3L_128bits.v common 1.59 0.11 12032 0 0.01 -1 -1 30336 -1 -1 0 0 0 0 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63812 -1 -1 0 0 0 0 0 17 17 289 -1 unnamed_device 0.00 0 -1 -1 -1 -1 -1 -1 0.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 diff --git a/vtr_flow/tasks/arithmetic_tasks/figure_8/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt similarity index 98% rename from vtr_flow/tasks/arithmetic_tasks/figure_8/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt index 62de70655e1..408375e3469 100644 --- a/vtr_flow/tasks/arithmetic_tasks/figure_8/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt @@ -122,6 +122,9 @@ arch_list_add=fixed_k6_frac_uripple_N8_22nm.xml # Parse info and how to parse parse_file=vpr_chain.txt +# How to parse QoR info +qor_parse_file=qor_standard.txt + # Pass requirements pass_requirements_file=pass_requirements_chain.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt new file mode 100644 index 00000000000..65955822dd0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt @@ -0,0 +1,221 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_003bits.v common 1.95 0.02 5848 1 0.03 -1 -1 31960 -1 -1 2 7 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63288 7 4 21 25 1 15 13 17 17 289 -1 unnamed_device 0.00 33 0.01 0.00 0.581048 -5.30553 -0.581048 0.581048 0.54 3.8706e-05 2.9422e-05 0.00294476 0.00216761 24 115 8 6.55708e+06 24110 448715. 1552.65 0.32 0.00727347 0.00535274 94 10 72 72 2697 1018 0.821448 0.821448 -6.74793 -0.821448 0 0 554710. 1919.41 0.14 0.01 0.00161553 0.00125783 10 4 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.97 0.02 5860 2 0.01 -1 -1 31896 -1 -1 2 9 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63420 9 5 28 33 1 21 16 17 17 289 -1 unnamed_device 0.00 47 0.01 0.00 0.819447 -7.38981 -0.819447 0.819447 0.49 5.1123e-05 4.0035e-05 0.00456397 0.00347606 26 140 10 6.55708e+06 24110 477104. 1650.88 0.34 0.010026 0.00763534 146 7 72 77 4128 1362 0.819447 0.819447 -10.1152 -0.819447 0 0 585099. 2024.56 0.14 0.00 0.00140185 0.00111191 13 6 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 2.27 0.01 5856 2 0.02 -1 -1 31704 -1 -1 2 11 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63436 11 6 34 40 1 24 19 17 17 289 -1 unnamed_device 0.01 61 0.01 0.00 0.819447 -9.26524 -0.819447 0.819447 0.57 5.5225e-05 4.232e-05 0.00580249 0.00442758 26 214 27 6.55708e+06 24110 477104. 1650.88 0.41 0.0158588 0.0119746 191 14 113 121 5604 2033 0.902448 0.902448 -13.1534 -0.902448 0 0 585099. 2024.56 0.16 0.01 0.00184443 0.00146097 16 7 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.89 0.01 5884 3 0.03 -1 -1 32024 -1 -1 3 13 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63516 13 7 41 48 1 32 23 17 17 289 -1 unnamed_device 0.01 75 0.01 0.00 1.50711 -12.9658 -1.50711 1.50711 0.47 6.3672e-05 4.9388e-05 0.00582304 0.00448751 26 292 17 6.55708e+06 36165 477104. 1650.88 0.34 0.013503 0.010506 250 10 105 118 5277 1858 1.50711 1.50711 -17.4132 -1.50711 0 0 585099. 2024.56 0.13 0.01 0.00178091 0.0014727 19 9 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.93 0.01 5884 3 0.03 -1 -1 31728 -1 -1 3 15 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63456 15 8 47 55 1 38 26 17 17 289 -1 unnamed_device 0.01 107 0.02 0.00 1.05785 -14.7122 -1.05785 1.05785 0.47 7.3037e-05 5.6856e-05 0.00944114 0.00741292 26 340 13 6.55708e+06 36165 477104. 1650.88 0.35 0.0179303 0.0140886 294 10 157 177 8454 2781 1.05785 1.05785 -19.0394 -1.05785 0 0 585099. 2024.56 0.13 0.01 0.00193967 0.00160521 23 10 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 2.04 0.01 5904 3 0.02 -1 -1 31776 -1 -1 4 17 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63532 17 9 56 65 1 42 30 17 17 289 -1 unnamed_device 0.04 102 0.02 0.00 1.46791 -16.6632 -1.46791 1.46791 0.47 7.7687e-05 6.1471e-05 0.010075 0.00791271 26 449 45 6.55708e+06 48220 477104. 1650.88 0.41 0.0240193 0.0189703 294 17 209 236 9519 3504 1.82851 1.82851 -22.553 -1.82851 0 0 585099. 2024.56 0.13 0.01 0.00313706 0.00259394 25 14 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.99 0.01 5832 4 0.02 -1 -1 31688 -1 -1 4 19 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63272 19 10 60 70 1 48 33 17 17 289 -1 unnamed_device 0.01 130 0.02 0.00 1.50711 -20.4252 -1.50711 1.50711 0.47 8.7764e-05 7.0472e-05 0.00959237 0.00764907 26 450 18 6.55708e+06 48220 477104. 1650.88 0.40 0.020336 0.0162753 420 14 257 308 16735 5350 1.58811 1.58811 -27.6032 -1.58811 0 0 585099. 2024.56 0.13 0.01 0.00281432 0.0023383 29 13 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 2.05 0.01 5868 4 0.02 -1 -1 32224 -1 -1 5 21 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63908 21 11 69 80 1 53 37 17 17 289 -1 unnamed_device 0.02 166 0.02 0.00 1.46791 -23.1376 -1.46791 1.46791 0.47 9.4468e-05 7.6515e-05 0.0101668 0.00788057 26 541 15 6.55708e+06 60275 477104. 1650.88 0.38 0.0213402 0.0169272 477 15 245 337 24004 7553 1.80097 1.80097 -30.2706 -1.80097 0 0 585099. 2024.56 0.15 0.01 0.00335126 0.00281936 33 17 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.99 0.02 5900 5 0.02 -1 -1 32172 -1 -1 5 23 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63968 23 12 73 85 1 58 40 17 17 289 -1 unnamed_device 0.01 267 0.02 0.00 1.95636 -29.9922 -1.95636 1.95636 0.47 9.6366e-05 7.7963e-05 0.00962917 0.00768905 26 665 33 6.55708e+06 60275 477104. 1650.88 0.39 0.0240146 0.0192919 608 14 248 339 18378 5001 2.15756 2.15756 -36.8534 -2.15756 0 0 585099. 2024.56 0.13 0.01 0.00333054 0.00282291 35 16 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 2.02 0.01 5920 5 0.03 -1 -1 32224 -1 -1 6 25 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63912 25 13 82 95 1 66 44 17 17 289 -1 unnamed_device 0.02 276 0.02 0.00 1.7847 -30.9303 -1.7847 1.7847 0.49 0.000117992 9.6898e-05 0.00961572 0.00772843 26 682 10 6.55708e+06 72330 477104. 1650.88 0.39 0.0217871 0.0176982 631 11 240 336 19200 5298 1.9049 1.9049 -38.8243 -1.9049 0 0 585099. 2024.56 0.13 0.01 0.00320303 0.00272718 40 20 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.20 0.02 5932 5 0.05 -1 -1 32012 -1 -1 7 27 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63984 27 14 91 105 1 70 48 17 17 289 -1 unnamed_device 0.02 264 0.04 0.00 1.73384 -33.1569 -1.73384 1.73384 0.47 0.000115042 9.3459e-05 0.0152674 0.0123747 26 814 15 6.55708e+06 84385 477104. 1650.88 0.38 0.0295979 0.024236 714 15 327 518 39676 10307 1.97825 1.97825 -42.1175 -1.97825 0 0 585099. 2024.56 0.13 0.01 0.00426549 0.00363267 42 24 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 2.07 0.01 5860 6 0.05 -1 -1 31772 -1 -1 7 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64040 29 15 95 110 1 74 51 17 17 289 -1 unnamed_device 0.05 252 0.04 0.00 2.23396 -37.6407 -2.23396 2.23396 0.47 0.000119101 9.6736e-05 0.0144524 0.0116896 28 680 12 6.55708e+06 84385 500653. 1732.36 0.39 0.0288784 0.0238034 596 12 279 404 18634 5772 2.27576 2.27576 -45.6679 -2.27576 0 0 612192. 2118.31 0.13 0.01 0.00413012 0.00358671 45 23 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.20 0.01 5876 6 0.03 -1 -1 31700 -1 -1 9 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64076 31 16 104 120 1 80 56 17 17 289 -1 unnamed_device 0.14 274 0.04 0.00 1.95636 -37.2994 -1.95636 1.95636 0.47 0.000126918 0.000103458 0.0164432 0.0133673 30 817 20 6.55708e+06 108495 526063. 1820.29 0.45 0.0330297 0.0271781 580 13 307 464 23691 6939 2.19676 2.19676 -42.7522 -2.19676 0 0 666494. 2306.21 0.15 0.01 0.00426751 0.0036793 50 27 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.07 0.02 5916 7 0.04 -1 -1 31728 -1 -1 7 33 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64184 33 17 108 125 1 86 57 17 17 289 -1 unnamed_device 0.02 431 0.04 0.00 2.64402 -50.2146 -2.64402 2.64402 0.46 0.000130299 0.000106707 0.0172852 0.0140316 30 996 25 6.55708e+06 84385 526063. 1820.29 0.42 0.0349767 0.0288438 880 14 349 509 32781 8064 2.64402 2.64402 -57.0288 -2.64402 0 0 666494. 2306.21 0.15 0.01 0.00458171 0.00395474 51 26 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.47 0.03 6068 7 0.04 -1 -1 31704 -1 -1 8 37 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64324 37 19 127 146 1 101 64 17 17 289 -1 unnamed_device 0.23 642 0.04 0.00 2.61648 -62.625 -2.61648 2.61648 0.47 0.00015059 0.000124989 0.0151511 0.0124392 26 1418 33 6.55708e+06 96440 477104. 1650.88 0.53 0.0382199 0.0317511 1242 13 425 610 57003 13385 2.64602 2.64602 -71.6634 -2.64602 0 0 585099. 2024.56 0.15 0.02 0.00642787 0.00563888 59 35 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.15 0.01 6092 8 0.05 -1 -1 31740 -1 -1 10 41 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64116 41 21 139 160 1 109 72 17 17 289 -1 unnamed_device 0.13 394 0.05 0.00 3.04382 -64.6184 -3.04382 3.04382 0.46 0.000162741 0.000134726 0.0198265 0.0163245 28 1077 13 6.55708e+06 120550 500653. 1732.36 0.39 0.0388116 0.0325314 875 11 381 505 27220 7946 3.16402 3.16402 -74.595 -3.16402 0 0 612192. 2118.31 0.13 0.01 0.00492088 0.0043394 67 37 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.32 0.02 6036 9 0.04 -1 -1 31948 -1 -1 11 45 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64744 45 23 152 175 1 124 79 17 17 289 -1 unnamed_device 0.04 648 0.06 0.00 2.7775 -71.9033 -2.7775 2.7775 0.47 0.000172928 0.000144046 0.0223926 0.0185165 28 1471 21 6.55708e+06 132605 500653. 1732.36 0.48 0.0450264 0.0377496 1299 15 536 740 49945 12340 3.0179 3.0179 -85.5042 -3.0179 0 0 612192. 2118.31 0.16 0.02 0.00764325 0.00666416 74 40 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.35 0.01 6064 10 0.03 -1 -1 32448 -1 -1 11 49 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64356 49 25 165 190 1 131 85 17 17 289 -1 unnamed_device 0.21 697 0.06 0.00 3.31942 -81.5686 -3.31942 3.31942 0.50 0.000188238 0.00015758 0.0241338 0.0201885 26 1573 17 6.55708e+06 132605 477104. 1650.88 0.41 0.0485402 0.04108 1428 12 579 807 46988 12302 3.31942 3.31942 -96.5664 -3.31942 0 0 585099. 2024.56 0.13 0.02 0.0064429 0.00570226 79 43 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 3.69 0.02 6092 11 0.05 -1 -1 31920 -1 -1 14 57 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65224 57 29 199 228 1 157 100 17 17 289 -1 unnamed_device 0.18 743 0.08 0.00 4.09974 -108.242 -4.09974 4.09974 0.46 0.000216269 0.000181125 0.0297964 0.0245991 34 1756 32 6.55708e+06 168770 585099. 2024.56 1.65 0.0965859 0.0814285 1470 68 798 1240 394718 290799 4.24948 4.24948 -122.386 -4.24948 0 0 742403. 2568.87 0.16 0.12 0.0268487 0.0232704 93 57 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.61 0.01 6184 13 0.04 -1 -1 31840 -1 -1 15 65 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64196 65 33 224 257 1 179 113 17 17 289 -1 unnamed_device 0.36 858 0.09 0.00 4.15482 -126.808 -4.15482 4.15482 0.46 0.000269789 0.000230721 0.0337127 0.0283019 32 2011 19 6.55708e+06 180825 554710. 1919.41 0.50 0.065978 0.0563266 1702 14 662 861 68832 17168 4.39522 4.39522 -148.685 -4.39522 0 0 701300. 2426.64 0.16 0.02 0.00870633 0.00774428 107 62 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.16 0.01 6368 19 0.10 -1 -1 32224 -1 -1 24 97 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65704 97 49 340 389 1 265 170 17 17 289 -1 unnamed_device 0.24 1392 0.15 0.00 6.37979 -246.747 -6.37979 6.37979 0.49 0.000351522 0.000303167 0.0493994 0.0420949 34 2935 28 6.55708e+06 289320 585099. 2024.56 0.90 0.138285 0.119435 2646 12 920 1341 89503 22426 6.37979 6.37979 -269.465 -6.37979 0 0 742403. 2568.87 0.16 0.03 0.0122792 0.0111052 160 98 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 4.56 0.02 6528 26 0.07 -1 -1 32328 -1 -1 31 129 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66280 129 65 454 519 1 354 225 17 17 289 -1 unnamed_device 0.16 1795 0.21 0.00 8.17384 -378.67 -8.17384 8.17384 0.48 0.000476021 0.000413955 0.067589 0.0580857 36 3878 47 6.55708e+06 373705 612192. 2118.31 2.09 0.253096 0.222386 3366 61 1459 2122 536730 318887 8.53444 8.53444 -426.872 -8.53444 0 0 782063. 2706.10 0.17 0.19 0.0581629 0.0521495 213 132 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_003bits.v common 0.33 0.02 6120 1 0.01 -1 -1 29808 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21212 7 4 24 25 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.31 0.01 6264 1 0.01 -1 -1 29696 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21100 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.34 0.02 6172 1 0.01 -1 -1 29820 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 20928 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.31 0.01 6164 1 0.01 -1 -1 29772 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21288 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.35 0.04 6264 1 0.00 -1 -1 29832 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21248 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.34 0.01 6232 1 0.01 -1 -1 29816 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21164 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.32 0.02 6272 1 0.01 -1 -1 29716 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21300 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.36 0.02 6196 1 0.01 -1 -1 29780 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21104 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.34 0.01 6188 1 0.01 -1 -1 29864 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21188 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.30 0.01 6152 1 0.00 -1 -1 29868 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21100 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.34 0.01 6428 1 0.01 -1 -1 29880 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21440 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.32 0.01 6168 1 0.01 -1 -1 29860 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21416 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.32 0.01 6184 1 0.01 -1 -1 29860 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21508 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 5 5 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.33 0.02 6140 1 0.00 -1 -1 29880 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21488 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 5 5 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.32 0.01 6472 1 0.01 -1 -1 29776 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21788 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 5 5 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.30 0.01 6224 1 0.00 -1 -1 29880 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21268 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 6 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.35 0.01 6196 1 0.01 -1 -1 29896 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21256 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 6 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.35 0.01 6540 1 0.01 -1 -1 29836 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21612 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 7 7 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.35 0.01 6396 1 0.01 -1 -1 29856 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21740 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8 8 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.35 0.02 6324 1 0.01 -1 -1 29860 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21668 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 9 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.38 0.02 6728 1 0.01 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 22144 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 13 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.40 0.02 6788 1 0.02 -1 -1 30208 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 22392 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 17 17 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_003bits.v common 0.33 0.01 6076 1 0.01 -1 -1 29820 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 20704 7 4 24 25 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.35 0.01 6112 1 0.01 -1 -1 29852 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 20680 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.33 0.01 6080 1 0.00 -1 -1 29704 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 20744 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.34 0.01 6120 1 0.01 -1 -1 29804 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21000 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.32 0.01 6156 1 0.01 -1 -1 29784 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 20676 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.34 0.03 6160 1 0.00 -1 -1 29772 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21080 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.33 0.02 6176 1 0.00 -1 -1 29760 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21020 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.32 0.02 6136 1 0.01 -1 -1 29864 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21196 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.32 0.02 6412 1 0.00 -1 -1 29732 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 20968 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.32 0.02 6276 1 0.01 -1 -1 29632 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21228 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.32 0.02 6432 1 0.02 -1 -1 29820 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21048 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.32 0.01 6120 1 0.00 -1 -1 29896 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21036 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.32 0.01 6292 1 0.01 -1 -1 29744 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21452 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 5 5 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.32 0.01 6252 1 0.00 -1 -1 29880 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21228 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 5 5 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.33 0.01 6268 1 0.01 -1 -1 29804 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21224 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 5 5 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.32 0.01 6292 1 0.01 -1 -1 29832 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21016 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 6 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.31 0.01 6404 1 0.01 -1 -1 29864 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21112 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 6 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.32 0.01 6232 1 0.01 -1 -1 29760 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21356 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 7 7 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.37 0.01 6452 1 0.01 -1 -1 29912 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21688 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8 8 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.34 0.02 6500 1 0.01 -1 -1 29936 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 21324 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 9 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.33 0.02 6612 1 0.01 -1 -1 30140 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 22048 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 13 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.37 0.02 6756 1 0.01 -1 -1 30204 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 22104 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 17 17 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_003bits.v common 1.94 0.01 6208 1 0.00 -1 -1 29768 -1 -1 2 7 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63400 7 4 27 28 1 14 13 17 17 289 -1 unnamed_device 0.01 26 0.01 0.00 0.649848 -5.45453 -0.649848 0.649848 0.50 4.4007e-05 3.4572e-05 0.00373631 0.00267679 20 79 11 6.64007e+06 25116 394039. 1363.46 0.32 0.00534037 0.00395545 82 5 22 22 1245 462 0.83871 0.83871 -6.89693 -0.83871 0 0 477104. 1650.88 0.13 0.00 0.000808519 0.000655982 10 -1 5 5 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.84 0.02 6340 1 0.01 -1 -1 29688 -1 -1 2 9 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63644 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 0.01 41 0.01 0.00 0.671848 -7.32322 -0.671848 0.671848 0.53 5.4759e-05 4.264e-05 0.0050636 0.00394523 20 143 24 6.64007e+06 25116 394039. 1363.46 0.27 0.00795349 0.00617521 117 9 64 64 2715 1026 0.901248 0.901248 -9.46182 -0.901248 0 0 477104. 1650.88 0.11 0.00 0.0013076 0.00105198 13 -1 6 6 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.99 0.01 6136 1 0.01 -1 -1 29740 -1 -1 2 11 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63976 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 0.01 58 0.02 0.00 0.682848 -8.98105 -0.682848 0.682848 0.50 0.000108095 8.698e-05 0.00906689 0.00705146 28 198 23 6.64007e+06 25116 500653. 1732.36 0.40 0.0182899 0.0142912 164 23 217 217 10057 3521 1.04345 1.04345 -12.587 -1.04345 0 0 612192. 2118.31 0.14 0.01 0.00282217 0.0022081 16 -1 7 7 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 2.22 0.03 6036 1 0.00 -1 -1 29656 -1 -1 3 13 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63312 13 7 48 49 1 32 23 17 17 289 -1 unnamed_device 0.01 73 0.02 0.00 0.704848 -11.1591 -0.704848 0.704848 0.57 6.7076e-05 5.3292e-05 0.00742505 0.00577723 26 239 20 6.64007e+06 37674 477104. 1650.88 0.42 0.0171714 0.0133441 195 21 223 223 10203 3609 1.03245 1.03245 -14.9877 -1.03245 0 0 585099. 2024.56 0.13 0.01 0.00309959 0.00247438 19 -1 8 8 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 2.09 0.02 6232 1 0.00 -1 -1 29676 -1 -1 3 15 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63928 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 0.01 115 0.02 0.00 0.944958 -13.6801 -0.944958 0.944958 0.49 7.3853e-05 5.815e-05 0.00848792 0.00667971 30 274 13 6.64007e+06 37674 526063. 1820.29 0.40 0.017088 0.0134237 218 12 116 116 5587 1790 0.932248 0.932248 -16.909 -0.932248 0 0 666494. 2306.21 0.16 0.01 0.00343292 0.00281722 22 -1 9 9 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 2.16 0.01 6092 1 0.01 -1 -1 29740 -1 -1 4 17 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63604 17 9 62 63 1 41 30 17 17 289 -1 unnamed_device 0.02 118 0.03 0.00 0.955958 -15.7312 -0.955958 0.955958 0.53 9.1739e-05 7.4901e-05 0.0117354 0.00938059 32 324 15 6.64007e+06 50232 554710. 1919.41 0.41 0.021389 0.0170478 266 16 210 210 12219 3526 0.856048 0.856048 -19.44 -0.856048 0 0 701300. 2426.64 0.16 0.01 0.00281058 0.00228775 25 -1 10 10 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.02 0.01 6044 1 0.01 -1 -1 29884 -1 -1 4 19 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63944 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 0.02 119 0.02 0.00 0.966958 -17.553 -0.966958 0.966958 0.47 8.624e-05 6.9978e-05 0.00723105 0.00584133 32 345 15 6.64007e+06 50232 554710. 1919.41 0.40 0.0176397 0.0142452 302 14 185 185 10586 3180 0.998248 0.998248 -23.6568 -0.998248 0 0 701300. 2426.64 0.15 0.01 0.00291319 0.00241299 28 -1 11 11 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 2.02 0.01 6112 1 0.00 -1 -1 29644 -1 -1 5 21 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64424 21 11 76 77 1 49 37 17 17 289 -1 unnamed_device 0.02 146 0.03 0.00 0.977958 -19.7463 -0.977958 0.977958 0.48 9.3442e-05 7.5221e-05 0.0122757 0.00986757 32 376 14 6.64007e+06 62790 554710. 1919.41 0.41 0.0229658 0.0185057 336 10 164 164 8244 2497 1.07445 1.07445 -25.6797 -1.07445 0 0 701300. 2426.64 0.15 0.01 0.00246732 0.00206597 31 -1 12 12 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.96 0.01 6224 1 0.02 -1 -1 29616 -1 -1 5 23 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64404 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 0.02 264 0.03 0.00 0.988958 -24.4748 -0.988958 0.988958 0.47 9.9524e-05 8.0542e-05 0.0114486 0.00929469 26 522 8 6.64007e+06 62790 477104. 1650.88 0.36 0.0217873 0.0176757 514 12 239 239 16450 4459 1.00925 1.00925 -31.6101 -1.00925 0 0 585099. 2024.56 0.13 0.01 0.00293043 0.00246207 34 -1 13 13 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 2.13 0.02 6072 1 0.00 -1 -1 29780 -1 -1 5 25 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64468 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 0.02 189 0.04 0.00 0.999958 -24.166 -0.999958 0.999958 0.50 0.000107339 8.6989e-05 0.0151816 0.0123142 32 549 14 6.64007e+06 62790 554710. 1919.41 0.46 0.0276712 0.02256 419 22 368 368 22119 6491 1.03245 1.03245 -29.2659 -1.03245 0 0 701300. 2426.64 0.15 0.01 0.00475391 0.00393254 37 -1 14 14 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.23 0.01 6136 1 0.01 -1 -1 29784 -1 -1 6 27 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64488 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 0.03 201 0.04 0.00 1.01096 -26.1519 -1.01096 1.01096 0.65 0.000113152 9.1606e-05 0.0153636 0.0125768 28 685 25 6.64007e+06 75348 500653. 1732.36 0.41 0.0306077 0.0250507 565 22 448 448 34970 10706 1.17465 1.17465 -35.7769 -1.17465 0 0 612192. 2118.31 0.13 0.02 0.00520512 0.00434877 40 -1 15 15 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 2.27 0.01 6224 1 0.02 -1 -1 29752 -1 -1 6 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64572 29 15 104 105 1 73 50 17 17 289 -1 unnamed_device 0.02 235 0.03 0.00 1.02196 -28.269 -1.02196 1.02196 0.48 0.000115564 9.4686e-05 0.0146595 0.0119975 32 640 16 6.64007e+06 75348 554710. 1919.41 0.45 0.0346993 0.0284845 517 10 303 303 16107 5109 1.07645 1.07645 -34.7382 -1.07645 0 0 701300. 2426.64 0.23 0.01 0.00460597 0.00395284 43 -1 16 16 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.14 0.02 6264 1 0.01 -1 -1 29716 -1 -1 7 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64512 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 0.03 289 0.04 0.00 1.26207 -31.9485 -1.26207 1.26207 0.49 0.000123104 0.000101703 0.0167885 0.0137311 30 704 18 6.64007e+06 87906 526063. 1820.29 0.42 0.0322059 0.0264963 577 17 359 359 20217 5452 1.06345 1.06345 -38.5834 -1.06345 0 0 666494. 2306.21 0.15 0.01 0.00469018 0.00395676 46 -1 17 17 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.13 0.01 6276 1 0.01 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17 17 289 -1 unnamed_device 0.03 553 0.05 0.00 1.29507 -44.6155 -1.29507 1.29507 0.47 0.000142345 0.000119618 0.0184126 0.015334 32 1034 14 6.64007e+06 100464 554710. 1919.41 0.43 0.0351916 0.0295121 976 12 415 415 37149 8201 1.10745 1.10745 -52.7573 -1.10745 0 0 701300. 2426.64 0.15 0.01 0.00429715 0.00368854 55 -1 20 20 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.36 0.01 6244 1 0.01 -1 -1 29956 -1 -1 8 41 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64748 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 0.04 445 0.05 0.00 1.31707 -44.6209 -1.31707 1.31707 0.50 0.000156738 0.000131069 0.020354 0.0169914 30 923 13 6.64007e+06 100464 526063. 1820.29 0.42 0.0384873 0.0321244 774 11 437 437 26076 6988 1.13925 1.13925 -53.3002 -1.13925 0 0 666494. 2306.21 0.22 0.01 0.0043391 0.00378229 61 -1 22 22 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.30 0.02 6288 1 0.01 -1 -1 29860 -1 -1 9 45 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64596 45 23 160 161 1 114 77 17 17 289 -1 unnamed_device 0.02 419 0.06 0.00 1.33907 -48.8774 -1.33907 1.33907 0.47 0.000167765 0.0001417 0.0234944 0.0195977 30 1174 50 6.64007e+06 113022 526063. 1820.29 0.56 0.0606058 0.0508515 917 17 640 640 49626 13196 1.27045 1.27045 -61.775 -1.27045 0 0 666494. 2306.21 0.15 0.02 0.00631254 0.00542219 67 -1 24 24 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.29 0.02 6208 1 0.01 -1 -1 29888 -1 -1 10 49 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64592 49 25 174 175 1 123 84 17 17 289 -1 unnamed_device 0.03 688 0.07 0.00 1.59018 -59.526 -1.59018 1.59018 0.50 0.000181864 0.000151837 0.0247075 0.0206797 30 1293 19 6.64007e+06 125580 526063. 1820.29 0.48 0.0482197 0.0404017 1118 17 524 524 38719 9251 1.20325 1.20325 -68.8787 -1.20325 0 0 666494. 2306.21 0.18 0.03 0.00925961 0.00799272 73 -1 26 26 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.23 0.01 6416 1 0.01 -1 -1 29800 -1 -1 11 57 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65428 57 29 202 203 1 143 97 17 17 289 -1 unnamed_device 0.04 855 0.08 0.00 1.63418 -72.6612 -1.63418 1.63418 0.47 0.000205825 0.000174537 0.0280912 0.0237654 28 1589 15 6.64007e+06 138138 500653. 1732.36 0.48 0.0523243 0.0443608 1433 19 695 695 48976 11707 1.23625 1.23625 -81.4884 -1.23625 0 0 612192. 2118.31 0.13 0.02 0.00818108 0.00706247 85 -1 30 30 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.41 0.01 6344 1 0.01 -1 -1 29868 -1 -1 13 65 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64600 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 0.06 909 0.09 0.00 1.90729 -83.6661 -1.90729 1.90729 0.47 0.00022978 0.000196054 0.0301771 0.0257056 30 1727 19 6.64007e+06 163254 526063. 1820.29 0.50 0.0595458 0.0509796 1461 13 632 632 36731 9462 1.20325 1.20325 -87.2461 -1.20325 0 0 666494. 2306.21 0.23 0.02 0.00712176 0.00625623 97 -1 34 34 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.52 0.01 6512 1 0.01 -1 -1 30248 -1 -1 19 97 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65448 97 49 342 343 1 246 165 17 17 289 -1 unnamed_device 0.04 1547 0.17 0.00 2.54151 -144.124 -2.54151 2.54151 0.48 0.00033189 0.00028761 0.0457497 0.0396005 30 2799 16 6.64007e+06 238602 526063. 1820.29 0.52 0.0889424 0.0772825 2467 14 979 979 65079 15730 1.51625 1.51625 -145.812 -1.51625 0 0 666494. 2306.21 0.20 0.03 0.0111354 0.00987136 145 -1 50 50 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 2.63 0.04 6800 1 0.01 -1 -1 30268 -1 -1 25 129 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66196 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 0.06 1951 0.24 0.00 3.17573 -211.846 -3.17573 3.17573 0.46 0.000443266 0.000389435 0.0617061 0.0539306 32 3956 18 6.64007e+06 313950 554710. 1919.41 0.58 0.120002 0.105639 3444 16 1425 1425 130062 30189 1.70045 1.70045 -203.251 -1.70045 0 0 701300. 2426.64 0.15 0.05 0.0166508 0.0148666 193 -1 66 66 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_003bits.v common 1.83 0.02 6212 1 0.01 -1 -1 29688 -1 -1 2 7 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63540 7 4 27 28 1 14 13 17 17 289 -1 unnamed_device 0.00 26 0.01 0.00 0.649848 -5.45453 -0.649848 0.649848 0.48 4.2689e-05 3.3428e-05 0.00348427 0.00265486 20 85 8 6.65987e+06 25356 394039. 1363.46 0.28 0.00475571 0.00367023 73 6 37 37 1486 612 0.770048 0.770048 -6.77673 -0.770048 0 0 477104. 1650.88 0.12 0.00 0.000872498 0.000703507 10 -1 5 5 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.94 0.01 6136 1 0.01 -1 -1 29756 -1 -1 2 9 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63676 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 0.01 46 0.01 0.00 0.671848 -7.32322 -0.671848 0.671848 0.49 5.5924e-05 4.355e-05 0.005077 0.00394238 26 147 18 6.65987e+06 25356 477104. 1650.88 0.34 0.0114991 0.00880918 117 11 81 81 2624 1074 0.890248 0.890248 -9.24556 -0.890248 0 0 585099. 2024.56 0.13 0.00 0.0014454 0.00115645 13 -1 6 6 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 2.09 0.02 6084 1 0.01 -1 -1 29624 -1 -1 2 11 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63784 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 0.01 57 0.01 0.00 0.682848 -9.10125 -0.682848 0.682848 0.47 6.0468e-05 4.8292e-05 0.00543438 0.00422617 32 168 23 6.65987e+06 25356 554710. 1919.41 0.49 0.0162522 0.0124174 139 19 157 157 7253 2469 0.790989 0.790989 -11.5852 -0.790989 0 0 701300. 2426.64 0.15 0.01 0.00265487 0.00212202 16 -1 7 7 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 2.03 0.03 6088 1 0.01 -1 -1 29780 -1 -1 3 13 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63832 13 7 48 49 1 32 23 17 17 289 -1 unnamed_device 0.01 72 0.01 0.00 0.704848 -11.0389 -0.704848 0.704848 0.48 6.5355e-05 5.1487e-05 0.00640209 0.00500744 26 266 33 6.65987e+06 38034 477104. 1650.88 0.36 0.0163114 0.012617 232 24 280 280 19886 6259 1.13065 1.13065 -16.5577 -1.13065 0 0 585099. 2024.56 0.14 0.01 0.00436445 0.00332188 19 -1 8 8 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.98 0.01 6192 1 0.01 -1 -1 29800 -1 -1 3 15 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63880 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 0.02 102 0.01 0.00 0.944958 -13.6801 -0.944958 0.944958 0.48 7.2328e-05 5.7106e-05 0.00598628 0.00473084 30 300 11 6.65987e+06 38034 526063. 1820.29 0.39 0.0142612 0.0113092 250 13 141 141 6876 2100 0.976248 0.976248 -18.88 -0.976248 0 0 666494. 2306.21 0.14 0.01 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x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64076 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 0.01 135 0.03 0.00 0.966958 -17.553 -0.966958 0.966958 0.59 8.7577e-05 7.062e-05 0.0121552 0.00969414 28 327 11 6.65987e+06 50712 500653. 1732.36 0.39 0.021607 0.0173048 332 12 170 170 10248 3159 0.998248 0.998248 -24.0174 -0.998248 0 0 612192. 2118.31 0.14 0.01 0.00264146 0.00219579 28 -1 11 11 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 2.05 0.01 6144 1 0.01 -1 -1 29796 -1 -1 5 21 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64288 21 11 76 77 1 49 37 17 17 289 -1 unnamed_device 0.01 149 0.03 0.00 0.977958 -19.8665 -0.977958 0.977958 0.47 0.000106452 7.4111e-05 0.0116882 0.00937644 32 409 23 6.65987e+06 63390 554710. 1919.41 0.41 0.0235622 0.0188991 352 12 229 229 13587 3929 0.976248 0.976248 -24.6639 -0.976248 0 0 701300. 2426.64 0.17 0.01 0.00369879 0.00311713 31 -1 12 12 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.11 0.01 6184 1 0.01 -1 -1 29732 -1 -1 5 23 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64132 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 0.01 352 0.03 0.00 0.988958 -26.7586 -0.988958 0.988958 0.54 0.00010323 8.4684e-05 0.0129871 0.0105762 32 586 15 6.65987e+06 63390 554710. 1919.41 0.41 0.0243584 0.0197725 576 14 252 252 21511 4766 0.889048 0.889048 -31.6101 -0.889048 0 0 701300. 2426.64 0.15 0.01 0.00326021 0.00273387 34 -1 13 13 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 2.13 0.02 6256 1 0.01 -1 -1 29804 -1 -1 5 25 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63920 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 0.01 190 0.03 0.00 0.999958 -23.6852 -0.999958 0.999958 0.47 0.000332458 0.000309771 0.0149496 0.0121941 32 563 16 6.65987e+06 63390 554710. 1919.41 0.43 0.0273777 0.0222905 436 12 292 292 15799 4968 1.00925 1.00925 -30.2469 -1.00925 0 0 701300. 2426.64 0.15 0.01 0.00315647 0.00264548 37 -1 14 14 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.12 0.03 6192 1 0.00 -1 -1 29768 -1 -1 6 27 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64256 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 0.01 242 0.03 0.00 1.01096 -26.7529 -1.01096 1.01096 0.49 0.000110096 9.0026e-05 0.0116926 0.0095135 30 599 16 6.65987e+06 76068 526063. 1820.29 0.40 0.0246361 0.0201464 469 9 157 157 9145 2448 0.922048 0.922048 -32.1405 -0.922048 0 0 666494. 2306.21 0.15 0.01 0.00283919 0.00245163 40 -1 15 15 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 2.20 0.02 6204 1 0.00 -1 -1 29776 -1 -1 6 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64436 29 15 104 105 1 73 50 17 17 289 -1 unnamed_device 0.02 261 0.04 0.00 1.02196 -28.7498 -1.02196 1.02196 0.48 0.000116396 9.5559e-05 0.0155417 0.0126717 28 640 16 6.65987e+06 76068 500653. 1732.36 0.42 0.0299041 0.0245829 550 18 334 334 22307 6291 1.02025 1.02025 -36.1848 -1.02025 0 0 612192. 2118.31 0.16 0.02 0.00638481 0.00535542 43 -1 16 16 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.15 0.02 6100 1 0.01 -1 -1 29736 -1 -1 7 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64488 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 0.02 288 0.04 0.00 1.26207 -31.2273 -1.26207 1.26207 0.48 0.000123569 0.000100747 0.0166051 0.0135487 28 725 21 6.65987e+06 88746 500653. 1732.36 0.41 0.0322845 0.0263847 584 17 359 359 23619 6366 1.04025 1.04025 -37.8335 -1.04025 0 0 612192. 2118.31 0.14 0.01 0.004696 0.00395049 46 -1 17 17 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.36 0.01 6308 1 0.01 -1 -1 29848 -1 -1 7 33 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64148 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 0.01 310 0.05 0.00 1.27307 -34.3167 -1.27307 1.27307 0.52 0.000177258 0.000143898 0.0201204 0.0164644 32 727 23 6.65987e+06 88746 554710. 1919.41 0.56 0.0461614 0.0382604 624 11 369 369 22235 6253 1.06225 1.06225 -41.0896 -1.06225 0 0 701300. 2426.64 0.15 0.01 0.0037209 0.00318454 49 -1 18 18 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.19 0.01 6184 1 0.01 -1 -1 29828 -1 -1 8 37 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64456 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 0.01 452 0.05 0.00 1.29507 -41.2498 -1.29507 1.29507 0.49 0.000140277 0.000116991 0.0186693 0.0154832 26 956 16 6.65987e+06 101424 477104. 1650.88 0.44 0.0365254 0.030135 867 15 448 448 32158 8108 1.08425 1.08425 -49.1497 -1.08425 0 0 585099. 2024.56 0.13 0.01 0.00493097 0.00420987 55 -1 20 20 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.28 0.02 6320 1 0.00 -1 -1 29788 -1 -1 8 41 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64780 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 0.02 375 0.05 0.00 1.31707 -44.0199 -1.31707 1.31707 0.48 0.00015352 0.000127194 0.020701 0.0172136 32 1111 22 6.65987e+06 101424 554710. 1919.41 0.48 0.0441389 0.0368212 880 14 558 558 41837 11255 1.24845 1.24845 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VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64444 49 25 174 175 1 123 84 17 17 289 -1 unnamed_device 0.02 609 0.07 0.00 1.59018 -57.2422 -1.59018 1.59018 0.48 0.00019085 0.000160687 0.0230214 0.0191738 28 1352 30 6.65987e+06 126780 500653. 1732.36 0.48 0.0483581 0.0405375 1138 11 547 547 44954 10973 1.16919 1.16919 -66.08 -1.16919 0 0 612192. 2118.31 0.14 0.02 0.0054145 0.004744 73 -1 26 26 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.16 0.02 6572 1 0.01 -1 -1 29828 -1 -1 11 57 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64832 57 29 202 203 1 143 97 17 17 289 -1 unnamed_device 0.02 898 0.08 0.00 1.63418 -74.7046 -1.63418 1.63418 0.47 0.000207053 0.000175723 0.0271476 0.0228251 30 1565 19 6.65987e+06 139458 526063. 1820.29 0.44 0.0523397 0.0444174 1455 16 580 580 46044 10536 1.18125 1.18125 -81.5206 -1.18125 0 0 666494. 2306.21 0.15 0.02 0.00734267 0.0063874 85 -1 30 30 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.22 0.02 6360 1 0.01 -1 -1 29808 -1 -1 13 65 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64364 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 0.02 931 0.10 0.00 1.90729 -85.7095 -1.90729 1.90729 0.47 0.000228338 0.00019526 0.0311728 0.0264843 30 1765 17 6.65987e+06 164814 526063. 1820.29 0.44 0.0586008 0.0500952 1545 11 558 558 39521 9317 1.27945 1.27945 -90.972 -1.27945 0 0 666494. 2306.21 0.15 0.03 0.00982351 0.00862243 97 -1 34 34 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.43 0.01 6508 1 0.01 -1 -1 30116 -1 -1 19 97 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65460 97 49 342 343 1 246 165 17 17 289 -1 unnamed_device 0.03 1354 0.16 0.00 2.54151 -141.961 -2.54151 2.54151 0.47 0.000338554 0.000292834 0.0452489 0.0390888 30 2746 20 6.65987e+06 240882 526063. 1820.29 0.51 0.0874539 0.0760946 2328 13 904 904 67841 16296 1.31245 1.31245 -133.972 -1.31245 0 0 666494. 2306.21 0.15 0.03 0.0106732 0.00959139 145 -1 50 50 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 2.72 0.02 6736 1 0.01 -1 -1 30256 -1 -1 25 129 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66420 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 0.05 2011 0.26 0.00 3.17573 -211.605 -3.17573 3.17573 0.51 0.000464178 0.00041107 0.0647282 0.0562511 32 4091 28 6.65987e+06 316950 554710. 1919.41 0.63 0.132755 0.116625 3486 17 1477 1477 141277 32594 1.71145 1.71145 -201.707 -1.71145 0 0 701300. 2426.64 0.15 0.05 0.0169475 0.0151977 193 -1 66 66 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_003bits.v common 1.95 0.01 6048 1 0.00 -1 -1 29652 -1 -1 1 7 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64592 7 4 27 28 1 12 12 17 17 289 -1 unnamed_device 0.02 23 0.01 0.00 0.723895 -7.02006 -0.723895 0.723895 0.49 4.3828e-05 3.3426e-05 0.00349773 0.00267999 22 90 7 6.95648e+06 14475.7 443629. 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VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64660 11 6 41 42 1 19 18 17 17 289 -1 unnamed_device 0.03 42 0.02 0.00 0.699132 -10.9806 -0.699132 0.699132 0.50 6.0985e-05 4.7049e-05 0.00734898 0.00566765 30 136 13 6.95648e+06 14475.7 556674. 1926.21 0.41 0.0141841 0.0110032 89 9 35 35 1318 532 0.74674 0.74674 -11.4818 -0.74674 0 0 706193. 2443.58 0.15 0.00 0.00150602 0.00124314 8 -1 7 7 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 2.02 0.02 6128 1 0.00 -1 -1 29696 -1 -1 2 13 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64612 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 0.02 58 0.02 0.00 0.738332 -12.4656 -0.738332 0.738332 0.49 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64508 21 11 76 77 1 48 34 17 17 289 -1 unnamed_device 0.01 130 0.02 0.00 0.743132 -19.8824 -0.743132 0.743132 0.49 9.1717e-05 7.5057e-05 0.01098 0.0089089 32 444 13 6.99608e+06 29431.4 586450. 2029.24 0.43 0.0216033 0.0174511 391 11 231 231 14585 4797 0.993732 0.993732 -28.7787 -0.993732 0 0 744469. 2576.02 0.15 0.01 0.00267488 0.00224017 16 -1 12 12 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_011bits.v common 2.13 0.03 6232 1 0.00 -1 -1 29612 -1 -1 3 23 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64800 23 12 83 84 1 54 38 17 17 289 -1 unnamed_device 0.03 147 0.02 0.00 0.754132 -22.4284 -0.754132 0.754132 0.49 9.7136e-05 7.9067e-05 0.00932715 0.00750935 32 564 19 6.99608e+06 44147 586450. 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v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65044 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 0.07 184 0.02 0.00 0.787132 -26.2 -0.787132 0.787132 0.49 0.000108564 8.9037e-05 0.00894846 0.00729021 30 615 16 6.99608e+06 44147 556674. 1926.21 0.41 0.0221635 0.0180761 491 18 355 355 19522 6188 1.01573 1.01573 -36.366 -1.01573 0 0 706193. 2443.58 0.15 0.01 0.00445217 0.00371171 21 -1 15 15 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_014bits.v common 2.49 0.01 6144 1 0.00 -1 -1 29644 -1 -1 3 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64644 29 15 104 105 1 72 47 17 17 289 -1 unnamed_device 0.01 201 0.03 0.00 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64772 37 19 132 133 1 87 60 17 17 289 -1 unnamed_device 0.02 309 0.04 0.00 1.08816 -39.5021 -1.08816 1.08816 0.50 0.000142283 0.000117047 0.017847 0.0146921 34 965 25 6.99608e+06 58862.7 618332. 2139.56 0.75 0.0486829 0.0402362 740 17 464 464 45870 11145 1.27533 1.27533 -52.3382 -1.27533 0 0 787024. 2723.27 0.16 0.02 0.00557792 0.00477617 28 -1 20 20 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_020bits.v common 2.52 0.02 6216 1 0.01 -1 -1 29844 -1 -1 4 41 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64872 41 21 146 147 1 94 66 17 17 289 -1 unnamed_device 0.02 427 0.04 0.00 1.11016 -44.6284 -1.11016 1.11016 0.49 0.00015513 0.000129997 0.0151762 0.0126855 34 1109 15 6.99608e+06 58862.7 618332. 2139.56 0.77 0.0465545 0.0386945 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VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65320 49 25 174 175 1 118 79 17 17 289 -1 unnamed_device 0.02 741 0.06 0.00 1.15416 -63.2828 -1.15416 1.15416 0.51 0.000189095 0.000151127 0.0232426 0.0195964 34 1490 19 6.99608e+06 73578.4 618332. 2139.56 0.78 0.0605266 0.0508421 1360 14 605 605 64379 13536 1.29303 1.29303 -79.1779 -1.29303 0 0 787024. 2723.27 0.20 0.02 0.00613643 0.00534527 37 -1 26 26 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 2.78 0.01 6472 1 0.01 -1 -1 29916 -1 -1 6 57 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65192 57 29 202 203 1 141 92 17 17 289 -1 unnamed_device 0.05 759 0.07 0.00 1.19816 -71.3375 -1.19816 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Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64640 13 7 48 49 1 33 22 17 17 289 -1 unnamed_device 0.04 81 0.01 0.00 0.707773 -12.7322 -0.707773 0.707773 0.48 6.5972e-05 5.2239e-05 0.00470014 0.00371357 30 254 18 6.87369e+06 27947.7 556674. 1926.21 0.40 0.0130744 0.0102717 240 12 172 172 9263 2884 0.925373 0.925373 -17.6202 -0.925373 0 0 706193. 2443.58 0.14 0.01 0.00197177 0.00158982 14 -1 8 8 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_007bits.v common 2.14 0.01 6116 1 0.00 -1 -1 29732 -1 -1 3 15 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64272 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 0.05 111 0.02 0.00 0.953803 -15.6907 -0.953803 0.953803 0.56 7.428e-05 5.798e-05 0.00948948 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64428 27 14 97 98 1 67 45 17 17 289 -1 unnamed_device 0.04 209 0.03 0.00 1.0198 -29.4395 -1.0198 1.0198 0.49 0.000110922 9.043e-05 0.0146687 0.011999 32 714 24 6.87369e+06 55895.4 586450. 2029.24 0.45 0.0299892 0.0243685 573 14 392 392 30869 8307 1.28397 1.28397 -40.7095 -1.28397 0 0 744469. 2576.02 0.15 0.01 0.00385211 0.00322844 28 -1 15 15 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 2.30 0.01 6304 1 0.01 -1 -1 29760 -1 -1 4 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64668 29 15 104 105 1 74 48 17 17 289 -1 unnamed_device 0.07 403 0.03 0.00 1.0308 -35.6075 -1.0308 1.0308 0.48 0.00011876 9.6653e-05 0.0144571 0.0118453 32 886 16 6.87369e+06 55895.4 586450. 2029.24 0.43 0.0281473 0.0230666 800 21 473 473 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Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64604 33 17 118 119 1 83 55 17 17 289 -1 unnamed_device 0.07 305 0.04 0.00 1.28783 -37.0379 -1.28783 1.28783 0.50 0.000180418 0.000149591 0.0179042 0.0147608 30 788 20 6.87369e+06 69869.2 556674. 1926.21 0.44 0.0341219 0.0280166 654 12 410 410 24955 7142 1.21167 1.21167 -47.1668 -1.21167 0 0 706193. 2443.58 0.14 0.01 0.00396857 0.00337565 34 -1 18 18 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_018bits.v common 2.21 0.01 6280 1 0.01 -1 -1 29836 -1 -1 5 37 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64804 37 19 132 133 1 89 61 17 17 289 -1 unnamed_device 0.06 335 0.05 0.00 1.30983 -42.9835 -1.30983 1.30983 0.49 0.00014454 0.000119105 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unnamed_device 0.09 547 0.07 0.00 1.61086 -60.8024 -1.61086 1.61086 0.49 0.000177849 0.000150448 0.0241201 0.0202631 30 1328 50 6.87369e+06 97816.9 556674. 1926.21 0.54 0.0558627 0.0470893 1072 15 658 658 48225 12018 1.28667 1.28667 -72.2691 -1.28667 0 0 706193. 2443.58 0.14 0.02 0.00616324 0.00530011 50 -1 26 26 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 2.77 0.02 6368 1 0.01 -1 -1 29796 -1 -1 8 57 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65308 57 29 202 203 1 142 94 17 17 289 -1 unnamed_device 0.09 713 0.08 0.00 1.65486 -75.2827 -1.65486 1.65486 0.49 0.000207825 0.000176376 0.0280892 0.0237669 34 1665 37 6.87369e+06 111791 618332. 2139.56 0.83 0.0764862 0.064683 1337 17 787 787 67127 15855 1.35267 1.35267 -86.4518 -1.35267 0 0 787024. 2723.27 0.16 0.02 0.00767162 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65656 97 49 342 343 1 247 159 17 17 289 -1 unnamed_device 0.08 1572 0.16 0.00 2.57995 -157.876 -2.57995 2.57995 0.49 0.000336681 0.000292457 0.0457182 0.0395705 34 3279 22 6.87369e+06 181660 618332. 2139.56 0.89 0.118625 0.103014 2851 18 1277 1277 127508 28356 1.67197 1.67197 -168.884 -1.67197 0 0 787024. 2723.27 0.16 0.04 0.0130748 0.0115436 98 -1 50 50 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_064bits.v common 3.75 0.02 6856 1 0.03 -1 -1 30304 -1 -1 17 129 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66364 129 65 454 455 1 329 211 17 17 289 -1 unnamed_device 0.09 1823 0.24 0.00 3.22602 -224.654 -3.22602 3.22602 0.54 0.000443152 0.00039122 0.0617023 0.0538896 34 4706 29 6.87369e+06 237555 618332. 2139.56 1.55 0.170829 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GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64036 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 0.02 39 0.01 0.00 0.663773 -8.00422 -0.663773 0.663773 0.51 5.1193e-05 4.0462e-05 0.00463903 0.00356712 20 132 16 6.89349e+06 28187.7 414966. 1435.87 0.28 0.00676181 0.00519589 125 7 71 71 2539 952 0.914373 0.914373 -10.8861 -0.914373 0 0 503264. 1741.40 0.14 0.00 0.00114344 0.000926048 10 -1 6 6 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_005bits.v common 1.97 0.02 6236 1 0.01 -1 -1 29684 -1 -1 2 11 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63948 11 6 41 42 1 27 19 17 17 289 -1 unnamed_device 0.03 58 0.01 0.00 0.724973 -10.4154 -0.724973 0.724973 0.48 6.2789e-05 4.9173e-05 0.00616413 0.00478933 26 217 26 6.89349e+06 28187.7 503264. 1741.40 0.37 0.0146735 0.0113094 195 19 192 192 10901 3645 1.05067 1.05067 -14.2322 -1.05067 0 0 618332. 2139.56 0.13 0.01 0.00247021 0.00191899 12 -1 7 7 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_006bits.v common 2.09 0.01 6108 1 0.00 -1 -1 29800 -1 -1 2 13 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63964 13 7 48 49 1 33 22 17 17 289 -1 unnamed_device 0.03 81 0.01 0.00 0.746973 -12.756 -0.746973 0.746973 0.49 6.5237e-05 5.1353e-05 0.00500956 0.00397322 30 263 8 6.89349e+06 28187.7 556674. 1926.21 0.41 0.0124686 0.00976124 233 10 141 141 7364 2376 0.936373 0.936373 -17.1449 -0.936373 0 0 706193. 2443.58 0.15 0.01 0.00172554 0.00139534 14 -1 8 8 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 2.16 0.02 6148 1 0.01 -1 -1 29796 -1 -1 3 15 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64412 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 0.08 110 0.02 0.00 0.971003 -15.8019 -0.971003 0.971003 0.57 7.1612e-05 5.6433e-05 0.00974229 0.00763712 26 306 12 6.89349e+06 42281.5 503264. 1741.40 0.37 0.0181631 0.0140981 274 22 224 224 15506 4837 1.13187 1.13187 -20.8495 -1.13187 0 0 618332. 2139.56 0.13 0.01 0.00327656 0.0025851 17 -1 9 9 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 2.12 0.02 6244 1 0.00 -1 -1 29640 -1 -1 3 17 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64236 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 0.04 120 0.02 0.00 0.982003 -17.9908 -0.982003 0.982003 0.49 7.9545e-05 6.2885e-05 0.0104623 0.00829876 32 295 14 6.89349e+06 42281.5 586450. 2029.24 0.42 0.0198698 0.015807 236 13 126 126 6967 2321 0.82202 0.82202 -19.6685 -0.82202 0 0 744469. 2576.02 0.15 0.01 0.0023938 0.00195695 18 -1 10 10 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 2.17 0.02 6060 1 0.01 -1 -1 29704 -1 -1 3 19 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64160 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 0.04 132 0.02 0.00 0.993003 -20.0258 -0.993003 0.993003 0.48 9.3203e-05 7.5242e-05 0.0112731 0.00901987 32 384 16 6.89349e+06 42281.5 586450. 2029.24 0.42 0.0216585 0.0173805 296 11 162 162 7780 2426 1.12087 1.12087 -25.1785 -1.12087 0 0 744469. 2576.02 0.15 0.01 0.00239013 0.00199065 20 -1 11 11 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 2.11 0.02 6112 1 0.01 -1 -1 29744 -1 -1 3 21 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64184 21 11 76 77 1 48 35 17 17 289 -1 unnamed_device 0.05 144 0.02 0.00 1.004 -22.3223 -1.004 1.004 0.48 9.3226e-05 7.4321e-05 0.0110623 0.00888861 28 444 27 6.89349e+06 42281.5 531479. 1839.03 0.40 0.0235568 0.0188496 379 9 177 177 11371 3124 1.16487 1.16487 -29.3561 -1.16487 0 0 648988. 2245.63 0.14 0.01 0.00238193 0.00198913 22 -1 12 12 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 2.21 0.01 6276 1 0.01 -1 -1 29644 -1 -1 4 23 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64572 23 12 83 84 1 53 39 17 17 289 -1 unnamed_device 0.04 153 0.02 0.00 1.015 -25.1311 -1.015 1.015 0.49 0.000101006 8.2533e-05 0.0105424 0.0085574 32 509 15 6.89349e+06 56375.4 586450. 2029.24 0.47 0.0220477 0.0179096 406 11 238 238 14984 4448 1.03337 1.03337 -31.7698 -1.03337 0 0 744469. 2576.02 0.15 0.01 0.00278821 0.00235401 24 -1 13 13 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_012bits.v common 2.17 0.01 6128 1 0.01 -1 -1 29776 -1 -1 4 25 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64168 25 13 90 91 1 60 42 17 17 289 -1 unnamed_device 0.06 182 0.02 0.00 1.026 -26.3219 -1.026 1.026 0.50 0.000104965 8.5714e-05 0.0106933 0.00876665 28 594 16 6.89349e+06 56375.4 531479. 1839.03 0.44 0.0230882 0.0187528 503 14 281 281 18777 5433 1.16967 1.16967 -36.9887 -1.16967 0 0 648988. 2245.63 0.13 0.01 0.00342107 0.00283033 26 -1 14 14 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_013bits.v common 2.30 0.01 6096 1 0.01 -1 -1 29728 -1 -1 4 27 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64516 27 14 97 98 1 67 45 17 17 289 -1 unnamed_device 0.04 209 0.04 0.00 1.037 -29.6539 -1.037 1.037 0.50 0.000110711 8.9836e-05 0.0153536 0.0125428 32 744 23 6.89349e+06 56375.4 586450. 2029.24 0.55 0.0301372 0.0245071 581 10 312 312 23181 6339 1.17587 1.17587 -37.6296 -1.17587 0 0 744469. 2576.02 0.15 0.01 0.00295994 0.00249538 28 -1 15 15 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 2.53 0.01 6220 1 0.01 -1 -1 29860 -1 -1 4 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64524 29 15 104 105 1 74 48 17 17 289 -1 unnamed_device 0.06 223 0.04 0.00 1.048 -31.0777 -1.048 1.048 0.48 0.000118266 9.6655e-05 0.0159364 0.0130443 36 703 22 6.89349e+06 56375.4 648988. 2245.63 0.81 0.0461662 0.0376471 576 15 438 438 28050 7635 1.19317 1.19317 -38.9764 -1.19317 0 0 828058. 2865.25 0.16 0.01 0.00425519 0.00360543 31 -1 16 16 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 2.33 0.02 6156 1 0.01 -1 -1 29652 -1 -1 5 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64632 31 16 111 112 1 80 52 17 17 289 -1 unnamed_device 0.13 276 0.04 0.00 1.29403 -34.1654 -1.29403 1.29403 0.48 0.000121367 9.955e-05 0.0158653 0.012994 30 714 12 6.89349e+06 70469.2 556674. 1926.21 0.42 0.0303916 0.0250234 582 17 390 390 26092 7206 1.21787 1.21787 -43.0839 -1.21787 0 0 706193. 2443.58 0.15 0.02 0.00482074 0.00405535 33 -1 17 17 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 2.31 0.01 6324 1 0.00 -1 -1 29772 -1 -1 5 33 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64708 33 17 118 119 1 83 55 17 17 289 -1 unnamed_device 0.09 345 0.04 0.00 1.30503 -39.3087 -1.30503 1.30503 0.48 0.000130493 0.000105058 0.0173681 0.0142938 28 911 14 6.89349e+06 70469.2 531479. 1839.03 0.50 0.0391736 0.0322435 807 12 401 401 32687 8251 1.33217 1.33217 -51.7529 -1.33217 0 0 648988. 2245.63 0.13 0.01 0.00375941 0.00318734 34 -1 18 18 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 2.22 0.02 6204 1 0.00 -1 -1 29916 -1 -1 5 37 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64928 37 19 132 133 1 89 61 17 17 289 -1 unnamed_device 0.06 339 0.05 0.00 1.32703 -43.4092 -1.32703 1.32703 0.49 0.000140206 0.000115472 0.0186766 0.0154993 32 981 24 6.89349e+06 70469.2 586450. 2029.24 0.46 0.0370234 0.0307432 808 14 419 419 36882 9206 1.11467 1.11467 -52.776 -1.11467 0 0 744469. 2576.02 0.15 0.01 0.00464076 0.00397084 38 -1 20 20 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 2.67 0.02 6308 1 0.01 -1 -1 29832 -1 -1 6 41 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65044 41 21 146 147 1 101 68 17 17 289 -1 unnamed_device 0.06 387 0.05 0.00 1.34903 -49.1825 -1.34903 1.34903 0.53 0.00015474 0.000128804 0.0200574 0.0166682 34 1188 18 6.89349e+06 84563 618332. 2139.56 0.71 0.0516834 0.0428844 947 12 518 518 44599 11262 1.27927 1.27927 -60.722 -1.27927 0 0 787024. 2723.27 0.16 0.02 0.00484429 0.00417526 42 -1 22 22 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 2.38 0.01 6192 1 0.01 -1 -1 29812 -1 -1 6 45 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65152 45 23 160 161 1 115 74 17 17 289 -1 unnamed_device 0.14 725 0.06 0.00 1.37103 -61.8517 -1.37103 1.37103 0.48 0.000167945 0.000140425 0.0217573 0.0182254 30 1423 13 6.89349e+06 84563 556674. 1926.21 0.44 0.040672 0.034165 1263 12 503 503 37568 8479 1.16487 1.16487 -69.2433 -1.16487 0 0 706193. 2443.58 0.20 0.02 0.00520239 0.00452019 47 -1 24 24 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 2.48 0.02 6416 1 0.01 -1 -1 29792 -1 -1 7 49 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64740 49 25 174 175 1 124 81 17 17 289 -1 unnamed_device 0.06 703 0.07 0.00 1.62806 -67.3457 -1.62806 1.62806 0.48 0.000179493 0.000151077 0.0235492 0.0197561 34 1391 20 6.89349e+06 98656.9 618332. 2139.56 0.69 0.0609231 0.0513061 1294 16 602 602 53571 11859 1.33687 1.33687 -77.447 -1.33687 0 0 787024. 2723.27 0.16 0.02 0.00647471 0.00556979 50 -1 26 26 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 2.60 0.02 6272 1 0.01 -1 -1 29892 -1 -1 8 57 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65112 57 29 202 203 1 142 94 17 17 289 -1 unnamed_device 0.10 799 0.07 0.00 1.67206 -79.3888 -1.67206 1.67206 0.48 0.000203212 0.000173664 0.0269774 0.0229023 34 1741 18 6.89349e+06 112751 618332. 2139.56 0.72 0.0683166 0.0577572 1484 13 684 684 70807 15659 1.34797 1.34797 -88.684 -1.34797 0 0 787024. 2723.27 0.16 0.02 0.00628032 0.00546365 58 -1 30 30 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 2.62 0.01 6516 1 0.01 -1 -1 29852 -1 -1 9 65 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64480 65 33 230 231 1 165 107 17 17 289 -1 unnamed_device 0.07 977 0.09 0.00 1.95109 -94.4586 -1.95109 1.95109 0.48 0.000227999 0.000194072 0.0307487 0.0261548 34 1960 19 6.89349e+06 126845 618332. 2139.56 0.73 0.0778222 0.0661746 1738 14 741 741 66270 14998 1.35462 1.35462 -103.345 -1.35462 0 0 787024. 2723.27 0.16 0.02 0.00782069 0.0068379 66 -1 34 34 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 2.80 0.01 6648 1 0.01 -1 -1 30196 -1 -1 13 97 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65444 97 49 342 343 1 247 159 17 17 289 -1 unnamed_device 0.07 1481 0.16 0.00 2.59715 -157.439 -2.59715 2.59715 0.49 0.000330158 0.000286501 0.0450613 0.0390134 34 3026 21 6.89349e+06 183220 618332. 2139.56 0.81 0.115299 0.100051 2727 16 1025 1025 103368 22673 1.64997 1.64997 -164.23 -1.64997 0 0 787024. 2723.27 0.16 0.03 0.0118596 0.0105566 98 -1 50 50 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 3.64 0.02 6808 1 0.02 -1 -1 30392 -1 -1 17 129 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66536 129 65 454 455 1 329 211 17 17 289 -1 unnamed_device 0.09 1845 0.24 0.00 3.24322 -227.249 -3.24322 3.24322 0.54 0.000523751 0.000467586 0.0631629 0.0553011 34 4619 28 6.89349e+06 239595 618332. 2139.56 1.47 0.17001 0.1491 3667 15 1462 1462 160581 34176 1.76462 1.76462 -218.795 -1.76462 0 0 787024. 2723.27 0.16 0.05 0.0150903 0.013459 130 -1 66 66 0 0 diff --git a/vtr_flow/tasks/arithmetic_tasks/multless_consts/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/config.txt similarity index 93% rename from vtr_flow/tasks/arithmetic_tasks/multless_consts/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/config.txt index 57cd80080fd..37f1c2cc28d 100644 --- a/vtr_flow/tasks/arithmetic_tasks/multless_consts/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/config.txt @@ -142,8 +142,11 @@ circuit_list_add=mult_128.v # Add architectures to list to sweep arch_list_add=fixed_k6_N8_gate_boost_0.2V_22nm.xml -arch_list_add=fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml -arch_list_add=fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml + +#Lookahead architectures fail in vpr at the packing stage after removing unused inputs. +#arch_list_add=fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml +#arch_list_add=fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml + arch_list_add=fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml arch_list_add=fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml arch_list_add=fixed_k6_frac_2ripple_N8_22nm.xml @@ -155,6 +158,9 @@ arch_list_add=fixed_k6_frac_uripple_N8_22nm.xml # Parse info and how to parse parse_file=vpr_chain.txt +# How to parse QoR info +qor_parse_file=qor_standard.txt + # Pass requirements pass_requirements_file=pass_requirements_chain.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt new file mode 100644 index 00000000000..aec2a8e94e1 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt @@ -0,0 +1,1025 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 5.26 0.02 6964 14 0.20 -1 -1 33008 -1 -1 26 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65152 32 32 280 312 1 204 90 17 17 289 -1 unnamed_device 0.20 1090 0.12 0.00 6.5589 -123.745 -6.5589 6.5589 0.53 0.000361569 0.000313968 0.050692 0.0429327 36 2976 26 6.55708e+06 313430 612192. 2118.31 2.88 0.152805 0.13039 2476 28 1730 5597 398493 128752 6.9221 6.9221 -147.352 -6.9221 0 0 782063. 2706.10 0.16 0.09 0.0246308 0.0217896 186 185 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 3.60 0.02 7008 14 0.24 -1 -1 32448 -1 -1 30 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65056 30 32 277 309 1 214 92 17 17 289 -1 unnamed_device 0.35 1264 0.11 0.00 6.78504 -135.691 -6.78504 6.78504 0.46 0.000357448 0.000309764 0.0442622 0.0370296 32 3667 40 6.55708e+06 361650 554710. 1919.41 0.80 0.1095 0.0934911 3019 69 2926 9779 1306709 666384 7.30764 7.30764 -156.1 -7.30764 0 0 701300. 2426.64 0.17 0.39 0.0701947 0.0617858 189 186 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 3.96 0.03 6952 11 0.17 -1 -1 32652 -1 -1 25 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65172 32 32 274 306 1 208 89 17 17 289 -1 unnamed_device 0.32 1315 0.11 0.00 5.56972 -117.95 -5.56972 5.56972 0.47 0.000353293 0.000306047 0.0428092 0.0358221 36 3346 17 6.55708e+06 301375 612192. 2118.31 1.59 0.128684 0.109532 2872 18 1286 4321 246995 56440 5.84932 5.84932 -135.132 -5.84932 0 0 782063. 2706.10 0.16 0.05 0.017253 0.0154937 180 179 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_004.v common 5.50 0.02 6900 12 0.29 -1 -1 32632 -1 -1 29 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65640 29 32 269 301 1 203 90 17 17 289 -1 unnamed_device 0.29 1104 0.12 0.00 6.34544 -115.686 -6.34544 6.34544 0.54 0.000360823 0.000312255 0.047982 0.0402853 36 3578 36 6.55708e+06 349595 612192. 2118.31 2.95 0.179596 0.153827 2730 18 1410 4391 240003 58232 6.70604 6.70604 -135.835 -6.70604 0 0 782063. 2706.10 0.16 0.05 0.017968 0.0161138 185 180 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_005.v common 4.09 0.02 6856 13 0.26 -1 -1 33108 -1 -1 34 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65624 32 32 317 349 1 247 98 17 17 289 -1 unnamed_device 0.33 1593 0.16 0.00 6.35004 -132.511 -6.35004 6.35004 0.48 0.000407204 0.000351958 0.0644527 0.0542158 30 4686 42 6.55708e+06 409870 526063. 1820.29 1.54 0.145994 0.12442 3464 17 1678 4896 266354 62066 6.87004 6.87004 -154.17 -6.87004 0 0 666494. 2306.21 0.15 0.06 0.020113 0.0181371 223 222 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 5.22 0.02 6988 12 0.20 -1 -1 32540 -1 -1 34 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65160 32 32 299 331 1 232 98 17 17 289 -1 unnamed_device 0.39 1470 0.14 0.00 5.99204 -123.594 -5.99204 5.99204 0.47 0.000378721 0.000326908 0.056183 0.0473985 36 3869 48 6.55708e+06 409870 612192. 2118.31 2.61 0.172385 0.147402 3169 39 1386 4468 504544 215109 6.3231 6.3231 -142.77 -6.3231 0 0 782063. 2706.10 0.16 0.13 0.0331781 0.0293981 209 204 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 3.46 0.02 6700 12 0.16 -1 -1 32196 -1 -1 27 27 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65056 27 32 210 242 1 167 86 17 17 289 -1 unnamed_device 0.21 971 0.10 0.00 5.89678 -107.416 -5.89678 5.89678 0.47 0.000291292 0.000250874 0.0399722 0.0335213 28 2946 48 6.55708e+06 325485 500653. 1732.36 1.18 0.0982051 0.0838949 2384 42 1128 3493 563505 291721 6.25738 6.25738 -125.417 -6.25738 0 0 612192. 2118.31 0.13 0.14 0.0258995 0.022734 136 125 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_008.v common 6.14 0.02 6988 11 0.19 -1 -1 32664 -1 -1 28 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65224 31 32 264 296 1 200 91 17 17 289 -1 unnamed_device 0.26 1167 0.14 0.00 5.38078 -109.227 -5.38078 5.38078 0.58 0.000330921 0.000284406 0.0571167 0.0474529 36 3182 36 6.55708e+06 337540 612192. 2118.31 3.52 0.169961 0.144059 2629 32 1246 4052 416376 168684 5.62118 5.62118 -127.716 -5.62118 0 0 782063. 2706.10 0.16 0.10 0.0245366 0.0216183 175 171 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 3.16 0.03 6772 12 0.18 -1 -1 32168 -1 -1 25 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64964 31 32 234 266 1 190 88 17 17 289 -1 unnamed_device 0.29 1157 0.11 0.00 5.66098 -121.179 -5.66098 5.66098 0.48 0.00033089 0.000285786 0.0428234 0.0358008 32 3133 45 6.55708e+06 301375 554710. 1919.41 0.82 0.101749 0.0870112 2685 20 1118 2990 303649 102234 5.78318 5.78318 -137.861 -5.78318 0 0 701300. 2426.64 0.15 0.07 0.0157767 0.0140569 145 141 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_010.v common 4.01 0.03 6704 13 0.15 -1 -1 32552 -1 -1 25 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64824 32 32 253 285 1 194 89 17 17 289 -1 unnamed_device 0.24 1131 0.14 0.00 6.22784 -133.447 -6.22784 6.22784 0.50 0.000333273 0.000286936 0.0587067 0.0497968 36 3019 24 6.55708e+06 301375 612192. 2118.31 1.42 0.142004 0.121598 2489 16 1079 2981 173518 41269 6.73558 6.73558 -155.622 -6.73558 0 0 782063. 2706.10 0.16 0.04 0.015226 0.0137438 162 158 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_011.v common 3.18 0.02 6808 12 0.15 -1 -1 32428 -1 -1 22 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64948 30 32 217 249 1 169 84 17 17 289 -1 unnamed_device 0.27 901 0.10 0.00 6.10964 -119.164 -6.10964 6.10964 0.51 0.000296853 0.000254745 0.0430479 0.0363719 28 2831 48 6.55708e+06 265210 500653. 1732.36 0.93 0.1003 0.085476 2202 16 963 2364 139131 33674 6.22984 6.22984 -139.9 -6.22984 0 0 612192. 2118.31 0.14 0.04 0.0127655 0.0114286 130 126 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_012.v common 3.75 0.03 6816 12 0.15 -1 -1 32260 -1 -1 21 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64940 32 32 227 259 1 176 85 17 17 289 -1 unnamed_device 0.24 1000 0.10 0.00 5.57738 -120.852 -5.57738 5.57738 0.53 0.000305845 0.000261795 0.0420112 0.0352921 28 3402 36 6.55708e+06 253155 500653. 1732.36 1.49 0.0983948 0.0836356 2468 27 1074 2804 236337 72887 6.01898 6.01898 -145.075 -6.01898 0 0 612192. 2118.31 0.13 0.06 0.0188575 0.0167084 138 132 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_013.v common 4.27 0.02 6880 13 0.25 -1 -1 32768 -1 -1 30 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65588 32 32 306 338 1 235 94 17 17 289 -1 unnamed_device 0.27 1405 0.14 0.00 6.4799 -132.734 -6.4799 6.4799 0.48 0.000398118 0.000342444 0.0592766 0.0498963 36 3403 19 6.55708e+06 361650 612192. 2118.31 1.75 0.158237 0.135064 2925 16 1383 4036 226403 54202 6.85276 6.85276 -152.582 -6.85276 0 0 782063. 2706.10 0.18 0.10 0.0324293 0.0288227 212 211 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_014.v common 6.40 0.02 6880 14 0.32 -1 -1 32892 -1 -1 29 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65512 32 32 302 334 1 235 93 17 17 289 -1 unnamed_device 0.48 1296 0.13 0.00 7.16556 -145.099 -7.16556 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65196 29 32 236 268 1 192 90 17 17 289 -1 unnamed_device 0.37 962 0.13 0.00 5.77858 -120.219 -5.77858 5.77858 0.48 0.000380762 0.000327504 0.0510695 0.0433667 30 3262 35 6.55708e+06 349595 526063. 1820.29 1.58 0.109158 0.0929906 2227 18 1246 3156 160150 41160 6.01898 6.01898 -138.979 -6.01898 0 0 666494. 2306.21 0.14 0.04 0.0150297 0.0135109 159 147 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_105.v common 3.37 0.03 6768 11 0.12 -1 -1 32492 -1 -1 22 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65348 32 32 231 263 1 179 86 17 17 289 -1 unnamed_device 0.35 993 0.11 0.00 5.75104 -117.55 -5.75104 5.75104 0.47 0.000321959 0.0002573 0.0452835 0.0378502 30 2816 21 6.55708e+06 265210 526063. 1820.29 1.08 0.0912294 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VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65412 29 32 221 253 1 166 85 17 17 289 -1 unnamed_device 0.21 939 0.11 0.00 4.86478 -97.3409 -4.86478 4.86478 0.47 0.000301109 0.000247963 0.0428619 0.0356218 34 2775 45 6.55708e+06 289320 585099. 2024.56 1.49 0.128008 0.108443 2133 16 934 2687 157408 37686 5.38478 5.38478 -115.174 -5.38478 0 0 742403. 2568.87 0.16 0.04 0.0132139 0.011904 138 132 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_108.v common 4.45 0.03 6712 14 0.14 -1 -1 32504 -1 -1 24 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65016 32 32 240 272 1 179 88 17 17 289 -1 unnamed_device 0.34 948 0.11 0.00 6.4387 -127.865 -6.4387 6.4387 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2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65092 32 32 259 291 1 202 91 17 17 289 -1 unnamed_device 0.20 1156 0.12 0.00 6.42444 -134.013 -6.42444 6.42444 0.48 0.000343284 0.000297286 0.0492414 0.0419057 36 3132 39 6.55708e+06 325485 612192. 2118.31 1.67 0.144523 0.123982 2478 15 1111 2952 168024 41837 6.42444 6.42444 -146.528 -6.42444 0 0 782063. 2706.10 0.16 0.04 0.0153163 0.0137915 167 164 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_115.v common 4.12 0.02 6932 13 0.21 -1 -1 32500 -1 -1 29 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65208 32 32 277 309 1 220 93 17 17 289 -1 unnamed_device 0.19 1353 0.13 0.00 6.2793 -132.202 -6.2793 6.2793 0.48 0.000356854 0.000308603 0.0523825 0.0440639 38 3451 19 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64872 27 32 275 232 1 135 79 17 17 289 -1 unnamed_device 0.06 729 0.12 0.00 2.7079 -83.0755 -2.7079 2.7079 0.58 0.000268376 0.000234744 0.0457377 0.0393274 32 1561 19 6.64007e+06 251160 554710. 1919.41 0.47 0.0800245 0.0690028 1442 23 1063 1841 118070 28425 2.82497 2.82497 -97.9212 -2.82497 0 0 701300. 2426.64 0.15 0.04 0.013329 0.0116932 100 26 54 27 27 27 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.64 0.02 7100 1 0.01 -1 -1 29996 -1 -1 34 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65272 31 32 319 244 1 185 97 17 17 289 -1 unnamed_device 0.09 891 0.16 0.00 2.7339 -87.1235 -2.7339 2.7339 0.47 0.000308788 0.000269481 0.0537864 0.0458454 30 2222 22 6.64007e+06 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2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66000 32 32 367 284 1 192 100 17 17 289 -1 unnamed_device 0.11 922 0.19 0.00 3.36336 -112.661 -3.36336 3.36336 0.48 0.000395434 0.000352179 0.0650605 0.0562849 30 2500 39 6.64007e+06 452088 526063. 1820.29 0.77 0.123887 0.107123 1793 21 1243 1882 120246 27749 3.55743 3.55743 -131.975 -3.55743 0 0 666494. 2306.21 0.14 0.04 0.0159743 0.0141642 147 31 91 32 32 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 2.64 0.02 7176 1 0.03 -1 -1 30420 -1 -1 38 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65512 32 32 461 376 1 196 102 17 17 289 -1 unnamed_device 0.15 918 0.18 0.00 3.07805 -102.745 -3.07805 3.07805 0.48 0.000382778 0.000335607 0.0623918 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2.57 0.02 7068 1 0.01 -1 -1 29980 -1 -1 22 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65452 32 32 334 252 1 187 86 17 17 289 -1 unnamed_device 0.07 891 0.16 0.00 3.65376 -111.983 -3.65376 3.65376 0.47 0.000453427 0.000397035 0.0611435 0.0532148 30 2331 25 6.64007e+06 276276 526063. 1820.29 0.62 0.107919 0.0936173 1747 20 1219 2038 118199 29706 3.72162 3.72162 -131.796 -3.72162 0 0 666494. 2306.21 0.14 0.04 0.0149967 0.0133577 138 -1 122 32 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.27 0.02 6656 1 0.01 -1 -1 29948 -1 -1 13 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 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Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65356 32 32 408 320 1 197 101 17 17 289 -1 unnamed_device 0.08 889 0.15 0.00 3.43916 -115.732 -3.43916 3.43916 0.49 0.000367884 0.000325595 0.0499842 0.0428622 30 2578 22 6.64007e+06 464646 526063. 1820.29 0.67 0.0992504 0.0855423 1931 21 1664 2705 131373 33725 3.69963 3.69963 -139.043 -3.69963 0 0 666494. 2306.21 0.15 0.04 0.016885 0.015032 155 54 64 32 64 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.35 0.02 7116 1 0.01 -1 -1 30008 -1 -1 16 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65268 32 32 295 247 1 149 80 17 17 289 -1 unnamed_device 0.06 740 0.09 0.00 2.45379 -85.4803 -2.45379 2.45379 0.48 0.000288644 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65024 32 32 284 226 1 166 82 17 17 289 -1 unnamed_device 0.06 916 0.16 0.00 2.8039 -102.89 -2.8039 2.8039 0.58 0.000282688 0.000246541 0.0573078 0.0492882 32 2004 21 6.64007e+06 226044 554710. 1919.41 0.62 0.103383 0.0894381 1901 17 1370 2146 154700 35850 3.06717 3.06717 -126.234 -3.06717 0 0 701300. 2426.64 0.15 0.04 0.0116627 0.010308 125 -1 96 32 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 2.50 0.02 6936 1 0.01 -1 -1 30220 -1 -1 31 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65328 31 32 305 251 1 162 94 17 17 289 -1 unnamed_device 0.08 872 0.14 0.00 2.7427 -96.6859 -2.7427 2.7427 0.50 0.000284652 0.000248541 0.0454333 0.0388655 32 2034 19 6.64007e+06 389298 554710. 1919.41 0.49 0.0817954 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v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65336 32 32 424 311 1 229 105 17 17 289 -1 unnamed_device 0.12 1227 0.20 0.00 3.41716 -120.15 -3.41716 3.41716 0.47 0.000384355 0.000339481 0.0626278 0.054006 30 2696 20 6.64007e+06 514878 526063. 1820.29 0.55 0.113313 0.098087 2296 21 1644 2655 154430 34107 3.56142 3.56142 -139.109 -3.56142 0 0 666494. 2306.21 0.14 0.04 0.0180996 0.0160478 181 26 128 32 27 27 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 2.94 0.02 7012 1 0.01 -1 -1 30112 -1 -1 37 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65548 32 32 404 318 1 198 101 17 17 289 -1 unnamed_device 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66088 31 32 457 373 1 193 86 17 17 289 -1 unnamed_device 0.25 1128 0.17 0.00 4.21121 -123.426 -4.21121 4.21121 0.50 0.000384399 0.000339964 0.0652219 0.0568469 32 2454 18 6.64007e+06 288834 554710. 1919.41 0.59 0.120889 0.105309 2214 18 1252 2079 129039 30316 4.09268 4.09268 -148.44 -4.09268 0 0 701300. 2426.64 0.15 0.04 0.0162585 0.0144681 150 111 0 0 124 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.64 0.02 7272 1 0.02 -1 -1 30196 -1 -1 23 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65496 31 32 415 335 1 188 86 17 17 289 -1 unnamed_device 0.19 750 0.14 0.00 4.04401 -105.585 -4.04401 4.04401 0.48 0.000372862 0.000329033 0.0552543 0.0482078 32 2505 25 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232 105 17 17 289 -1 unnamed_device 0.12 1250 0.20 0.00 3.35016 -119.194 -3.35016 3.35016 0.47 0.000427694 0.000378801 0.0657559 0.0567638 32 2818 22 6.64007e+06 514878 554710. 1919.41 0.54 0.122293 0.10639 2396 19 1861 2890 190238 41680 3.56143 3.56143 -137.719 -3.56143 0 0 701300. 2426.64 0.15 0.05 0.0189123 0.0167845 185 91 62 32 96 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.59 0.03 6972 1 0.02 -1 -1 30244 -1 -1 18 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65172 31 32 307 252 1 158 81 17 17 289 -1 unnamed_device 0.13 752 0.12 0.00 3.0343 -96.7196 -3.0343 3.0343 0.53 0.0002885 0.000252382 0.0458065 0.0396744 32 1883 16 6.64007e+06 226044 554710. 1919.41 0.49 0.0821887 0.0710932 1660 22 1111 1755 134706 30679 3.07817 3.07817 -117.006 -3.07817 0 0 701300. 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2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65704 32 32 398 314 1 196 98 17 17 289 -1 unnamed_device 0.09 1036 0.18 0.00 2.9841 -96.8691 -2.9841 2.9841 0.60 0.000361062 0.000317385 0.0607285 0.0517485 32 2576 24 6.64007e+06 426972 554710. 1919.41 0.58 0.115053 0.0986658 2318 19 1580 2663 183810 42001 3.04797 3.04797 -117.72 -3.04797 0 0 701300. 2426.64 0.15 0.05 0.0159032 0.0140491 149 54 62 32 62 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 2.60 0.03 7008 1 0.01 -1 -1 30032 -1 -1 22 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65568 32 32 346 258 1 194 86 17 17 289 -1 unnamed_device 0.06 975 0.17 0.00 3.41716 -118.828 -3.41716 3.41716 0.49 0.000336408 0.000296483 0.0581981 0.0506668 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7128 1 0.01 -1 -1 30124 -1 -1 36 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66036 32 32 396 312 1 194 100 17 17 289 -1 unnamed_device 0.12 943 0.19 0.00 2.7647 -96.5063 -2.7647 2.7647 0.47 0.000412356 0.00036676 0.0643335 0.0550403 32 2329 24 6.64007e+06 452088 554710. 1919.41 0.52 0.111963 0.0963189 1981 20 1504 2531 167335 37864 2.79857 2.79857 -114.385 -2.79857 0 0 701300. 2426.64 0.15 0.04 0.0163518 0.0144559 147 58 64 32 60 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.68 0.02 7212 1 0.01 -1 -1 30156 -1 -1 39 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65512 32 32 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Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65844 31 32 451 369 1 193 99 17 17 289 -1 unnamed_device 0.16 1001 0.20 0.00 3.76575 -111.673 -3.76575 3.76575 0.50 0.00038092 0.000332277 0.0684562 0.0588733 30 2746 21 6.64007e+06 452088 526063. 1820.29 0.60 0.120303 0.103762 2111 18 1132 2025 116956 27423 3.66143 3.66143 -131.361 -3.66143 0 0 666494. 2306.21 0.14 0.04 0.0158469 0.0140701 147 110 0 0 122 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.70 0.02 7080 1 0.02 -1 -1 30348 -1 -1 22 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66076 32 32 433 347 1 195 86 17 17 289 -1 unnamed_device 0.15 984 0.17 0.00 3.50235 -109.497 -3.50235 3.50235 0.49 0.00038556 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66144 31 32 427 343 1 189 96 17 17 289 -1 unnamed_device 0.16 1045 0.18 0.00 3.63355 -117.353 -3.63355 3.63355 0.49 0.000380003 0.000334812 0.0642125 0.0555636 32 2439 21 6.64007e+06 414414 554710. 1919.41 0.52 0.112806 0.0979949 2042 20 1486 2410 156535 36059 3.78762 3.78762 -141.103 -3.78762 0 0 701300. 2426.64 0.15 0.04 0.0172843 0.015345 147 79 31 31 93 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 2.55 0.02 7256 1 0.02 -1 -1 30340 -1 -1 32 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65292 30 32 407 331 1 182 94 17 17 289 -1 unnamed_device 0.10 822 0.17 0.00 3.0573 -89.9701 -3.0573 3.0573 0.49 0.000370384 0.000322149 0.0599598 0.0517462 32 2355 25 6.64007e+06 401856 554710. 1919.41 0.53 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v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65316 29 32 391 320 1 179 97 17 17 289 -1 unnamed_device 0.10 689 0.13 0.00 2.7859 -82.2878 -2.7859 2.7859 0.47 0.000380122 0.000327849 0.0528478 0.0452862 36 1685 30 6.64007e+06 452088 612192. 2118.31 1.12 0.14192 0.122025 1309 22 1325 2129 116004 30052 2.64257 2.64257 -91.7889 -2.64257 0 0 782063. 2706.10 0.16 0.04 0.0165243 0.0145579 136 81 26 26 85 29 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 2.57 0.02 6784 1 0.02 -1 -1 29940 -1 -1 17 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64900 32 32 284 226 1 156 81 17 17 289 -1 unnamed_device 0.10 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65192 32 32 316 268 1 158 94 17 17 289 -1 unnamed_device 0.13 792 0.14 0.00 3.0573 -93.2996 -3.0573 3.0573 0.49 0.000287768 0.000249103 0.047171 0.0400662 26 2011 25 6.64007e+06 376740 477104. 1650.88 0.69 0.089153 0.0758833 1697 16 821 1316 98600 23440 2.78257 2.78257 -106.914 -2.78257 0 0 585099. 2024.56 0.13 0.03 0.0124118 0.0108988 112 47 32 32 54 27 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 2.45 0.03 6944 1 0.01 -1 -1 30004 -1 -1 18 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64884 31 32 277 222 1 160 81 17 17 289 -1 unnamed_device 0.08 844 0.12 0.00 2.8321 -98.7011 -2.8321 2.8321 0.47 0.000287675 0.00025202 0.0453812 0.0393628 28 1972 21 6.64007e+06 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2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66056 32 32 494 379 1 232 106 17 17 289 -1 unnamed_device 0.12 1300 0.24 0.00 3.94095 -122.256 -3.94095 3.94095 0.51 0.00042714 0.00037715 0.0745004 0.0643821 28 3627 30 6.64007e+06 527436 500653. 1732.36 1.16 0.140994 0.121561 3003 22 1988 3598 284595 61536 3.73963 3.73963 -144.796 -3.73963 0 0 612192. 2118.31 0.17 0.06 0.021443 0.019003 185 85 62 31 95 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 2.79 0.03 7164 1 0.02 -1 -1 30604 -1 -1 22 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65540 31 32 457 373 1 188 85 17 17 289 -1 unnamed_device 0.16 803 0.18 0.00 3.70016 -112.181 -3.70016 3.70016 0.47 0.000394211 0.000348909 0.0704391 0.0614791 30 2106 22 6.64007e+06 276276 526063. 1820.29 0.67 0.146195 0.127224 1657 22 1178 1999 112037 28451 3.81582 3.81582 -134.188 -3.81582 0 0 666494. 2306.21 0.15 0.04 0.019569 0.0172286 145 105 0 0 124 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 2.48 0.02 6960 1 0.01 -1 -1 29984 -1 -1 16 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65488 32 32 356 305 1 150 80 17 17 289 -1 unnamed_device 0.14 710 0.12 0.00 2.9543 -89.5331 -2.9543 2.9543 0.48 0.000318604 0.000280531 0.0473165 0.0411184 32 1954 18 6.64007e+06 200928 554710. 1919.41 0.54 0.090202 0.078194 1690 22 1058 1734 126360 28798 2.74257 2.74257 -110.059 -2.74257 0 0 701300. 2426.64 0.16 0.04 0.0153116 0.0135224 108 86 0 0 89 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 3.12 0.02 6996 1 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x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65360 32 32 406 319 1 200 104 17 17 289 -1 unnamed_device 0.14 997 0.31 0.00 2.7929 -98.631 -2.7929 2.7929 0.59 0.000651712 0.000563761 0.103056 0.0887796 32 2292 23 6.64007e+06 502320 554710. 1919.41 0.74 0.167097 0.144693 1944 23 1609 2416 160032 36612 2.78757 2.78757 -113.859 -2.78757 0 0 701300. 2426.64 0.15 0.04 0.0181777 0.016003 157 61 63 32 64 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.43 0.02 6904 1 0.01 -1 -1 30096 -1 -1 18 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64952 29 32 291 242 1 134 79 17 17 289 -1 unnamed_device 0.05 542 0.11 0.00 2.7361 -84.445 -2.7361 2.7361 0.47 0.000281409 0.000246092 0.0481952 0.0416153 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1 0.01 -1 -1 30160 -1 -1 38 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65280 31 32 367 283 1 196 101 17 17 289 -1 unnamed_device 0.07 972 0.19 0.00 3.59956 -114.245 -3.59956 3.59956 0.47 0.000339053 0.000296605 0.0599751 0.0514386 30 2215 23 6.64007e+06 477204 526063. 1820.29 0.52 0.105127 0.0907238 1938 23 1483 2583 150695 34765 3.57443 3.57443 -133.743 -3.57443 0 0 666494. 2306.21 0.14 0.04 0.0182413 0.0161989 152 29 93 31 31 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 2.40 0.02 7080 1 0.00 -1 -1 30220 -1 -1 31 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65064 29 32 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x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64856 31 32 310 264 1 147 80 17 17 289 -1 unnamed_device 0.14 604 0.14 0.00 2.70619 -81.8301 -2.70619 2.70619 0.48 0.000283878 0.000247641 0.0596716 0.0513646 30 1703 21 6.64007e+06 213486 526063. 1820.29 0.51 0.0975561 0.0839238 1308 18 854 1360 73877 19205 2.64057 2.64057 -95.5541 -2.64057 0 0 666494. 2306.21 0.14 0.03 0.0117763 0.0104683 106 49 31 31 53 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 3.34 0.01 7132 1 0.01 -1 -1 30168 -1 -1 33 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65608 32 32 384 308 1 184 97 17 17 289 -1 unnamed_device 0.15 804 0.19 0.00 2.7379 -90.5781 -2.7379 2.7379 0.57 0.000489211 0.000423189 0.0662335 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0.03 6936 1 0.01 -1 -1 30112 -1 -1 18 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64816 32 32 334 280 1 160 82 17 17 289 -1 unnamed_device 0.09 793 0.14 0.00 2.55679 -89.6661 -2.55679 2.55679 0.57 0.000308305 0.000269341 0.0521648 0.044761 26 2126 36 6.64007e+06 226044 477104. 1650.88 0.59 0.100645 0.0863009 1776 18 1109 1727 121212 27861 2.84377 2.84377 -111.643 -2.84377 0 0 585099. 2024.56 0.13 0.03 0.0128599 0.0113343 115 54 32 32 60 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 2.46 0.03 6940 1 0.01 -1 -1 30056 -1 -1 18 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65164 32 32 340 284 1 164 82 17 17 289 -1 unnamed_device 0.12 821 0.11 0.00 2.7819 -97.9745 -2.7819 2.7819 0.50 0.000567322 0.000516808 0.0398761 0.0344223 28 2194 22 6.64007e+06 226044 500653. 1732.36 0.52 0.081144 0.0700318 1923 18 1194 1936 134954 31254 2.85597 2.85597 -117.171 -2.85597 0 0 612192. 2118.31 0.13 0.04 0.013157 0.0115629 121 60 32 32 62 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.80 0.03 7020 1 0.01 -1 -1 30428 -1 -1 38 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65412 32 32 408 320 1 198 102 17 17 289 -1 unnamed_device 0.11 1019 0.20 0.00 3.33916 -118.283 -3.33916 3.33916 0.51 0.000356462 0.000312354 0.0668309 0.0574713 28 2648 26 6.64007e+06 477204 500653. 1732.36 0.72 0.120065 0.103192 2312 22 1913 2768 224550 48842 3.64343 3.64343 -142.797 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Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65396 32 32 470 382 1 200 103 17 17 289 -1 unnamed_device 0.17 1078 0.17 0.00 3.34716 -119.058 -3.34716 3.34716 0.47 0.000386868 0.000341404 0.0592834 0.050811 32 2620 25 6.64007e+06 489762 554710. 1919.41 0.54 0.112042 0.0966625 2348 23 1932 2893 230523 51379 3.71643 3.71643 -146.932 -3.71643 0 0 701300. 2426.64 0.15 0.06 0.0198404 0.0174472 158 117 0 0 128 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 3.09 0.02 6872 1 0.01 -1 -1 30068 -1 -1 17 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64880 31 32 261 214 1 146 80 17 17 289 -1 unnamed_device 0.05 620 0.10 0.00 2.50628 -81.4677 -2.50628 2.50628 0.50 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65916 32 32 402 317 1 196 101 17 17 289 -1 unnamed_device 0.10 889 0.15 0.00 2.8299 -96.6404 -2.8299 2.8299 0.47 0.000391522 0.00034778 0.0487105 0.0417319 30 2157 16 6.64007e+06 464646 526063. 1820.29 0.51 0.0927467 0.08015 1759 17 1195 1803 81842 21685 2.82857 2.82857 -113.978 -2.82857 0 0 666494. 2306.21 0.15 0.03 0.0144888 0.0128914 151 59 61 32 64 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 2.81 0.02 7276 1 0.03 -1 -1 30488 -1 -1 45 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66176 32 32 501 383 1 232 109 17 17 289 -1 unnamed_device 0.15 1223 0.21 0.00 4.02462 -139.549 -4.02462 4.02462 0.47 0.000420166 0.000371735 0.0671314 0.0578782 28 3199 23 6.64007e+06 565110 500653. 1732.36 0.59 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v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65092 30 32 299 247 1 137 79 17 17 289 -1 unnamed_device 0.07 738 0.10 0.00 2.9683 -94.8986 -2.9683 2.9683 0.47 0.000288246 0.000252799 0.0408689 0.035553 30 1670 19 6.64007e+06 213486 526063. 1820.29 0.63 0.0844362 0.0733931 1397 17 761 1144 66712 15365 2.71377 2.71377 -106.652 -2.71377 0 0 666494. 2306.21 0.14 0.03 0.0115285 0.0102402 97 29 60 30 30 30 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 2.54 0.02 6952 1 0.00 -1 -1 29980 -1 -1 18 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64848 32 32 315 257 1 167 82 17 17 289 -1 unnamed_device 0.12 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65972 31 32 423 341 1 193 101 17 17 289 -1 unnamed_device 0.12 807 0.20 0.00 3.0933 -95.7283 -3.0933 3.0933 0.51 0.00037014 0.000325962 0.0765853 0.0652267 30 2682 32 6.64007e+06 477204 526063. 1820.29 1.20 0.165052 0.142387 1852 22 1655 2511 155803 39054 3.26777 3.26777 -118.014 -3.26777 0 0 666494. 2306.21 0.16 0.05 0.0206602 0.0183349 147 88 29 29 93 31 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 2.86 0.02 7224 1 0.01 -1 -1 30412 -1 -1 34 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65732 32 32 439 351 1 194 98 17 17 289 -1 unnamed_device 0.22 1117 0.25 0.00 3.16364 -112.842 -3.16364 3.16364 0.56 0.000384809 0.000340315 0.088042 0.076223 32 2629 26 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0.02 7196 1 0.01 -1 -1 30288 -1 -1 34 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65560 32 32 388 310 1 186 98 17 17 289 -1 unnamed_device 0.11 1038 0.16 0.00 2.80553 -98.2969 -2.80553 2.80553 0.47 0.000335052 0.000292776 0.053716 0.046085 28 2486 21 6.65987e+06 431052 500653. 1732.36 0.65 0.106925 0.092081 2179 21 1476 2287 172688 38971 3.19165 3.19165 -120.717 -3.19165 0 0 612192. 2118.31 0.13 0.04 0.0162278 0.0142434 141 50 54 32 64 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 3.15 0.02 7232 1 0.01 -1 -1 30256 -1 -1 22 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65656 29 32 347 271 1 184 83 17 17 289 -1 unnamed_device 0.11 900 0.15 0.00 3.4643 -103.034 -3.4643 3.4643 0.47 0.000325796 0.000284008 0.0560178 0.0486103 36 1837 24 6.65987e+06 278916 612192. 2118.31 1.08 0.13056 0.112756 1654 21 1474 2506 144471 35201 3.52317 3.52317 -123.784 -3.52317 0 0 782063. 2706.10 0.18 0.06 0.0255961 0.0226245 138 25 87 29 29 29 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 4.10 0.03 7172 1 0.02 -1 -1 30028 -1 -1 20 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65692 32 32 377 289 1 195 84 17 17 289 -1 unnamed_device 0.18 829 0.15 0.00 3.30796 -110.619 -3.30796 3.30796 0.52 0.000356384 0.000314383 0.0618993 0.0540013 38 2345 25 6.65987e+06 253560 638502. 2209.35 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65200 29 32 316 268 1 154 91 17 17 289 -1 unnamed_device 0.17 821 0.14 0.00 2.23164 -75.9619 -2.23164 2.23164 0.48 0.000305188 0.000254364 0.0506072 0.0427916 28 1933 24 6.65987e+06 380340 500653. 1732.36 0.56 0.0905634 0.0771625 1788 19 951 1625 112591 26636 2.18751 2.18751 -90.5771 -2.18751 0 0 612192. 2118.31 0.14 0.03 0.0131297 0.0115655 109 55 29 29 57 29 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 3.84 0.03 7344 1 0.02 -1 -1 30168 -1 -1 39 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65784 32 32 424 311 1 229 103 17 17 289 -1 unnamed_device 0.27 1052 0.19 0.00 3.41716 -115.034 -3.41716 3.41716 0.47 0.000377486 0.000333004 0.0651421 0.0562517 28 3519 42 6.65987e+06 494442 500653. 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30128 -1 -1 28 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65752 31 32 355 304 1 156 91 17 17 289 -1 unnamed_device 0.28 903 0.12 0.00 2.71958 -88.9927 -2.71958 2.71958 0.47 0.0003044 0.000264532 0.0408044 0.0344904 26 2234 20 6.65987e+06 354984 477104. 1650.88 0.61 0.0816704 0.0695248 1975 20 1158 1794 144940 32488 2.73245 2.73245 -110.968 -2.73245 0 0 585099. 2024.56 0.13 0.04 0.0137988 0.0120215 113 77 0 0 89 31 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 2.67 0.02 7120 1 0.02 -1 -1 30116 -1 -1 21 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65380 31 32 393 311 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Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65388 31 32 393 311 1 193 95 17 17 289 -1 unnamed_device 0.18 1071 0.16 0.00 2.98304 -98.9753 -2.98304 2.98304 0.49 0.000369502 0.000324747 0.0544231 0.0467372 34 2459 22 6.65987e+06 405696 585099. 2024.56 0.90 0.131478 0.113241 2179 19 1307 2164 137695 33125 2.92871 2.92871 -113.987 -2.92871 0 0 742403. 2568.87 0.15 0.04 0.0161014 0.0143597 145 58 60 31 62 31 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 2.73 0.03 7060 1 0.01 -1 -1 30484 -1 -1 35 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65684 32 32 408 320 1 198 99 17 17 289 -1 unnamed_device 0.18 1041 0.18 0.00 3.06544 -109.243 -3.06544 3.06544 0.47 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65796 31 32 397 313 1 196 99 17 17 289 -1 unnamed_device 0.22 936 0.18 0.00 3.3069 -109.634 -3.3069 3.3069 0.47 0.000344793 0.00030232 0.058827 0.0504637 28 3028 34 6.65987e+06 456408 500653. 1732.36 1.29 0.117445 0.100325 2343 27 1965 3312 378949 113386 3.67257 3.67257 -135.253 -3.67257 0 0 612192. 2118.31 0.14 0.08 0.0218188 0.0191083 150 59 62 31 62 31 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.59 0.02 7108 1 0.01 -1 -1 30308 -1 -1 33 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65344 32 32 398 314 1 196 97 17 17 289 -1 unnamed_device 0.11 1118 0.18 0.00 2.89404 -97.2503 -2.89404 2.89404 0.47 0.000356589 0.000313652 0.0594014 0.0512613 28 2690 17 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65752 32 32 396 312 1 194 99 17 17 289 -1 unnamed_device 0.26 1064 0.15 0.00 2.7647 -101.314 -2.7647 2.7647 0.54 0.000361613 0.00031487 0.0495129 0.0424525 26 2867 43 6.65987e+06 443730 477104. 1650.88 1.10 0.115394 0.0994612 2349 19 1560 2617 192829 43459 3.04997 3.04997 -126.82 -3.04997 0 0 585099. 2024.56 0.13 0.05 0.01613 0.0142937 146 58 64 32 60 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.74 0.02 7012 1 0.02 -1 -1 30180 -1 -1 37 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65784 32 32 406 319 1 200 101 17 17 289 -1 unnamed_device 0.18 1094 0.21 0.00 2.63244 -96.2885 -2.63244 2.63244 0.47 0.000628465 0.000528803 0.0715072 0.060894 32 2626 18 6.65987e+06 469086 554710. 1919.41 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65656 31 32 337 253 1 196 98 17 17 289 -1 unnamed_device 0.07 1129 0.18 0.00 3.40616 -116.378 -3.40616 3.40616 0.47 0.000326905 0.000287569 0.0564841 0.0487839 28 2936 43 6.65987e+06 443730 500653. 1732.36 0.94 0.115938 0.100346 2516 21 1602 2682 236491 50119 3.61223 3.61223 -139.915 -3.61223 0 0 612192. 2118.31 0.13 0.06 0.0178829 0.0157653 150 -1 124 31 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 2.73 0.03 7200 1 0.02 -1 -1 30328 -1 -1 34 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65400 32 32 408 320 1 197 98 17 17 289 -1 unnamed_device 0.18 929 0.18 0.00 3.2739 -111.645 -3.2739 3.2739 0.49 0.000363328 0.000320051 0.0602955 0.0519462 32 2925 21 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common 2.68 0.02 7004 1 0.01 -1 -1 30112 -1 -1 37 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65772 32 32 400 316 1 196 101 17 17 289 -1 unnamed_device 0.22 1068 0.19 0.00 3.10864 -106.184 -3.10864 3.10864 0.47 0.000357031 0.000314623 0.0605569 0.0521935 32 2726 23 6.65987e+06 469086 554710. 1919.41 0.53 0.109052 0.0944261 2259 24 1795 2940 208701 47072 3.43791 3.43791 -126.405 -3.43791 0 0 701300. 2426.64 0.15 0.05 0.0191885 0.0169351 148 62 60 30 64 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 2.57 0.02 6980 1 0.01 -1 -1 30024 -1 -1 18 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65288 30 32 299 247 1 156 80 17 17 289 -1 unnamed_device 0.15 615 0.13 0.00 2.7819 -89.1296 -2.7819 2.7819 0.47 0.000282223 0.000246766 0.0480051 0.0415279 32 1944 24 6.65987e+06 228204 554710. 1919.41 0.51 0.0866873 0.0749148 1514 23 1419 2201 162715 39982 3.12617 3.12617 -110.764 -3.12617 0 0 701300. 2426.64 0.17 0.04 0.0145256 0.0127395 112 29 60 30 30 30 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 2.65 0.02 7168 1 0.01 -1 -1 30188 -1 -1 22 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65396 30 32 386 306 1 191 84 17 17 289 -1 unnamed_device 0.22 920 0.16 0.00 3.36736 -111.701 -3.36736 3.36736 0.47 0.000353701 0.000312416 0.0604598 0.0527269 32 2275 22 6.65987e+06 278916 554710. 1919.41 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182 92 17 17 289 -1 unnamed_device 0.26 930 0.20 0.00 3.0353 -91.1427 -3.0353 3.0353 0.47 0.000359228 0.000316842 0.0733949 0.0634695 30 2182 20 6.65987e+06 380340 526063. 1820.29 0.57 0.121949 0.105545 1784 20 942 1583 91448 21417 2.93496 2.93496 -107.559 -2.93496 0 0 666494. 2306.21 0.14 0.03 0.0165761 0.014764 136 83 26 26 90 30 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 2.77 0.02 7208 1 0.00 -1 -1 30240 -1 -1 21 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65940 32 32 408 320 1 198 85 17 17 289 -1 unnamed_device 0.21 1009 0.16 0.00 3.2179 -112.246 -3.2179 3.2179 0.48 0.000555781 0.000508855 0.059969 0.0524389 32 2897 24 6.65987e+06 266238 554710. 1919.41 0.60 0.111161 0.0969684 2361 23 2132 3699 322930 70494 3.96797 3.96797 -140.311 -3.96797 0 0 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Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65012 32 32 284 226 1 157 80 17 17 289 -1 unnamed_device 0.11 739 0.10 0.00 2.7819 -96.8505 -2.7819 2.7819 0.48 0.00028234 0.000247195 0.0352462 0.0305004 32 2042 25 6.65987e+06 202848 554710. 1919.41 0.52 0.0772733 0.0669964 1828 22 1423 2183 179936 42601 3.02797 3.02797 -124.04 -3.02797 0 0 701300. 2426.64 0.15 0.04 0.0145228 0.012897 116 -1 96 32 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 2.98 0.03 7056 1 0.01 -1 -1 30088 -1 -1 33 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65676 32 32 408 320 1 194 97 17 17 289 -1 unnamed_device 0.32 1088 0.17 0.00 3.40616 -119.825 -3.40616 3.40616 0.55 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fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 2.61 0.02 6960 1 0.01 -1 -1 30132 -1 -1 29 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65560 32 32 316 268 1 158 93 17 17 289 -1 unnamed_device 0.25 927 0.14 0.00 2.72758 -89.9249 -2.72758 2.72758 0.53 0.000283513 0.000245102 0.0462528 0.0393726 30 1795 20 6.65987e+06 367662 526063. 1820.29 0.49 0.0875108 0.0752416 1621 18 775 1181 67120 16047 2.55105 2.55105 -103.769 -2.55105 0 0 666494. 2306.21 0.14 0.03 0.012139 0.0107756 111 47 32 32 54 27 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 2.49 0.02 7152 1 0.01 -1 -1 29976 -1 -1 18 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65140 31 32 277 222 1 160 81 17 17 289 -1 unnamed_device 0.08 810 0.12 0.00 2.7317 -95.9773 -2.7317 2.7317 0.47 0.000274158 0.000239839 0.0463549 0.0401445 32 2099 32 6.65987e+06 228204 554710. 1919.41 0.58 0.0939026 0.081658 1700 23 1564 2514 166728 39254 3.02917 3.02917 -116.554 -3.02917 0 0 701300. 2426.64 0.15 0.04 0.0143829 0.0126049 118 -1 93 31 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 3.30 0.03 7060 1 0.01 -1 -1 30000 -1 -1 32 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65804 32 32 382 304 1 188 96 17 17 289 -1 unnamed_device 0.24 773 0.14 0.00 3.05399 -98.1934 -3.05399 3.05399 0.48 0.000338073 0.000294872 0.0554577 0.0475181 34 2555 28 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65468 30 32 374 298 1 184 94 17 17 289 -1 unnamed_device 0.20 790 0.15 0.00 2.95004 -87.2328 -2.95004 2.95004 0.50 0.00035615 0.000297957 0.059136 0.0504591 32 2406 35 6.65987e+06 405696 554710. 1919.41 0.74 0.123573 0.105984 1701 22 1431 2053 150475 38245 3.13425 3.13425 -110.62 -3.13425 0 0 701300. 2426.64 0.15 0.04 0.0174048 0.0154052 136 47 60 30 56 30 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.23 0.02 7172 1 0.01 -1 -1 30116 -1 -1 20 27 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64900 27 32 275 232 1 143 79 17 17 289 -1 unnamed_device 0.08 645 0.11 0.00 2.9371 -80.1248 -2.9371 2.9371 0.47 0.000273435 0.000240033 0.0419933 0.0363307 26 1596 19 6.65987e+06 253560 477104. 1650.88 0.44 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65448 32 32 335 291 1 154 81 17 17 289 -1 unnamed_device 0.26 816 0.12 0.00 2.97218 -86.7839 -2.97218 2.97218 0.47 0.000297796 0.00025988 0.0464933 0.0400962 28 1936 21 6.65987e+06 215526 500653. 1732.36 0.56 0.0859419 0.0739483 1608 21 1103 1571 109792 25578 2.65651 2.65651 -102.71 -2.65651 0 0 612192. 2118.31 0.14 0.04 0.0146543 0.0127811 111 79 0 0 82 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 2.97 0.03 7076 1 0.01 -1 -1 30196 -1 -1 37 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66004 31 32 367 283 1 196 100 17 17 289 -1 unnamed_device 0.10 1019 0.18 0.00 3.30984 -108.835 -3.30984 3.30984 0.48 0.00033593 0.000293275 0.0567091 0.0488804 34 2435 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65616 31 32 389 309 1 189 98 17 17 289 -1 unnamed_device 0.17 923 0.18 0.00 2.9951 -97.3706 -2.9951 2.9951 0.47 0.000366097 0.000312334 0.0629488 0.0537974 32 2042 19 6.65987e+06 443730 554710. 1919.41 0.51 0.108783 0.0937231 1795 22 1657 2256 153247 35468 2.82957 2.82957 -113.197 -2.82957 0 0 701300. 2426.64 0.15 0.04 0.0173956 0.0153653 141 60 58 31 62 31 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.49 0.02 6996 1 0.01 -1 -1 30056 -1 -1 16 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65412 31 32 310 264 1 148 79 17 17 289 -1 unnamed_device 0.22 821 0.12 0.00 2.49487 -83.6096 -2.49487 2.49487 0.47 0.000284581 0.00024803 0.0453176 0.0390863 28 2203 18 6.65987e+06 202848 500653. 1732.36 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64968 32 32 377 319 1 156 80 17 17 289 -1 unnamed_device 0.16 700 0.12 0.00 2.8021 -97.9 -2.8021 2.8021 0.47 0.000352158 0.000309499 0.0541787 0.0471034 32 2088 39 6.65987e+06 202848 554710. 1919.41 0.66 0.107857 0.0936367 1606 22 1335 1873 153255 35957 3.19217 3.19217 -121.888 -3.19217 0 0 701300. 2426.64 0.16 0.05 0.019892 0.0174466 115 93 0 0 96 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.58 0.03 7056 1 0.00 -1 -1 30188 -1 -1 35 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65396 32 32 402 317 1 196 99 17 17 289 -1 unnamed_device 0.19 975 0.15 0.00 2.63244 -92.5623 -2.63244 2.63244 0.47 0.0003606 0.000315492 0.0483197 0.0413981 32 2462 23 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2.42 0.02 6716 1 0.01 -1 -1 29916 -1 -1 15 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64032 30 32 249 232 1 118 77 17 17 289 -1 unnamed_device 0.16 522 0.08 0.00 1.98838 -62.9533 -1.98838 1.98838 0.47 0.000238347 0.00020544 0.0359024 0.0307399 32 1385 32 6.65987e+06 190170 554710. 1919.41 0.51 0.0701224 0.059986 1058 22 680 952 75649 18823 1.82185 1.82185 -73.8745 -1.82185 0 0 701300. 2426.64 0.15 0.03 0.0112386 0.00974263 83 51 0 0 53 30 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.35 0.03 6944 1 0.01 -1 -1 29968 -1 -1 16 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65068 30 32 299 247 1 137 78 17 17 289 -1 unnamed_device 0.06 586 0.12 0.00 2.81584 -85.4189 -2.81584 2.81584 0.49 0.000289052 0.000253443 0.0509068 0.0440336 32 1604 24 6.65987e+06 202848 554710. 1919.41 0.49 0.0895531 0.0775389 1305 23 1192 1771 131535 31654 2.72051 2.72051 -101.48 -2.72051 0 0 701300. 2426.64 0.15 0.04 0.0149545 0.0131805 96 29 60 30 30 30 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 2.56 0.02 6900 1 0.02 -1 -1 29928 -1 -1 18 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65352 32 32 315 257 1 167 82 17 17 289 -1 unnamed_device 0.11 816 0.14 0.00 2.7647 -97.4679 -2.7647 2.7647 0.47 0.000302808 0.000264776 0.0513688 0.0445768 32 2539 21 6.65987e+06 228204 554710. 1919.41 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66412 32 32 388 310 1 179 83 17 17 289 -1 unnamed_device 0.63 976 0.11 0.00 3.04869 -113.012 -3.04869 3.04869 0.48 0.00033069 0.00028871 0.0494052 0.0424916 38 2845 33 6.95648e+06 275038 678818. 2348.85 3.47 0.134775 0.115387 2240 46 2257 3289 697757 310247 4.51766 4.51766 -152.361 -4.51766 0 0 902133. 3121.57 0.17 0.16 0.0317984 0.0277004 77 50 54 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_004.v common 3.92 0.02 7048 1 0.01 -1 -1 30156 -1 -1 16 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65996 29 32 347 271 1 176 77 17 17 289 -1 unnamed_device 0.30 883 0.11 0.00 3.4027 -109.285 -3.4027 3.4027 0.48 0.000331024 0.000290182 0.0509525 0.0441949 46 2499 41 6.95648e+06 231611 828058. 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65668 32 32 404 318 1 200 103 17 17 289 -1 unnamed_device 2.60 1018 0.19 0.00 2.91945 -106.055 -2.91945 2.91945 0.48 0.000380863 0.000321421 0.0627013 0.0535433 32 2598 23 6.87369e+06 544980 586450. 2029.24 0.55 0.111648 0.0960337 2090 20 1753 2597 206267 46747 3.02726 3.02726 -123.513 -3.02726 0 0 744469. 2576.02 0.15 0.05 0.0164135 0.0144162 154 62 62 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_037.v common 5.89 0.03 6916 1 0.01 -1 -1 30188 -1 -1 31 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65216 31 32 355 304 1 160 94 17 17 289 -1 unnamed_device 3.06 848 0.15 0.00 2.78925 -96.5614 -2.78925 2.78925 0.49 0.000297536 0.000257833 0.0507906 0.0431016 34 2088 22 6.87369e+06 433189 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65656 30 32 328 276 1 161 80 17 17 289 -1 unnamed_device 2.23 856 0.12 0.00 2.75195 -97.2328 -2.75195 2.75195 0.48 0.0003209 0.000281982 0.046936 0.0406886 34 2040 19 6.87369e+06 251529 618332. 2139.56 0.86 0.110338 0.0950373 1828 19 1311 2174 162707 37858 2.97426 2.97426 -117.952 -2.97426 0 0 787024. 2723.27 0.16 0.04 0.0131534 0.0113639 110 58 30 30 60 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_074.v common 6.35 0.02 6908 1 0.01 -1 -1 30076 -1 -1 17 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65412 32 32 362 309 1 163 81 17 17 289 -1 unnamed_device 2.74 729 0.11 0.00 2.72515 -92.4606 -2.72515 2.72515 0.49 0.000317197 0.00027724 0.0502598 0.0435053 36 2450 43 6.87369e+06 237555 648988. 2245.63 1.70 0.135627 0.115584 1671 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on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65764 32 32 408 320 1 202 102 17 17 289 -1 unnamed_device 4.35 983 0.17 0.00 3.44779 -118.764 -3.44779 3.44779 0.48 0.000360636 0.000317826 0.0535032 0.0458203 28 3126 33 6.87369e+06 531006 531479. 1839.03 1.07 0.111214 0.094922 2556 23 2141 3814 324046 73870 4.0147 4.0147 -156.986 -4.0147 0 0 648988. 2245.63 0.16 0.08 0.0221001 0.019184 156 57 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_077.v common 8.09 0.03 7092 1 0.02 -1 -1 30060 -1 -1 37 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66084 32 32 408 320 1 202 101 17 17 289 -1 unnamed_device 3.37 975 0.18 0.00 3.44779 -118.929 -3.44779 3.44779 0.48 0.000376514 0.000330742 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106 0 0 128 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_082.v common 4.54 0.02 7224 1 0.02 -1 -1 30288 -1 -1 33 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66464 31 32 427 343 1 196 96 17 17 289 -1 unnamed_device 1.81 985 0.19 0.00 3.66544 -117.515 -3.66544 3.66544 0.48 0.00038408 0.000338015 0.066551 0.0577131 32 2867 29 6.87369e+06 461137 586450. 2029.24 0.61 0.119731 0.103646 2205 25 1934 3251 250857 62492 4.046 4.046 -149.48 -4.046 0 0 744469. 2576.02 0.20 0.10 0.0343694 0.0302491 150 79 31 31 93 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_083.v common 4.81 0.02 7208 1 0.01 -1 -1 30296 -1 -1 32 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65460 30 32 407 331 1 188 94 17 17 289 -1 unnamed_device 1.99 1002 0.16 0.00 2.81125 -97.028 -2.81125 2.81125 0.48 0.000360282 0.000317513 0.0563315 0.0483206 34 2542 20 6.87369e+06 447163 618332. 2139.56 0.87 0.133532 0.114906 2103 20 1627 2620 183046 44107 2.97596 2.97596 -119.888 -2.97596 0 0 787024. 2723.27 0.16 0.05 0.0160005 0.0140075 141 83 26 26 90 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_084.v common 9.07 0.03 7128 1 0.02 -1 -1 30192 -1 -1 21 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65588 32 32 408 320 1 202 85 17 17 289 -1 unnamed_device 5.17 915 0.19 0.00 3.44779 -122.129 -3.44779 3.44779 0.54 0.000532491 0.000464218 0.0725443 0.0628534 34 3240 45 6.87369e+06 293451 618332. 2139.56 1.76 0.200315 0.172884 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7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65612 32 32 284 226 1 168 80 17 17 289 -1 unnamed_device 0.79 789 0.12 0.00 2.78015 -100.92 -2.78015 2.78015 0.50 0.00029069 0.000253572 0.0467099 0.0405533 34 2345 22 6.87369e+06 223581 618332. 2139.56 0.98 0.114196 0.0983592 1932 22 1561 2395 186213 44314 3.12146 3.12146 -128.039 -3.12146 0 0 787024. 2723.27 0.16 0.04 0.0139485 0.0122339 114 -1 96 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_087.v common 6.99 0.02 7204 1 0.01 -1 -1 30120 -1 -1 37 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65944 32 32 408 320 1 202 101 17 17 289 -1 unnamed_device 4.21 1117 0.18 0.00 3.40379 -123.137 -3.40379 3.40379 0.51 0.000366434 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unnamed_device 0.90 730 0.15 0.00 2.76295 -95.6398 -2.76295 2.76295 0.59 0.000274418 0.00024057 0.0540207 0.0464735 32 2352 36 6.87369e+06 237555 586450. 2029.24 0.73 0.105578 0.0907921 1752 23 1517 2415 183946 42844 3.25486 3.25486 -127.774 -3.25486 0 0 744469. 2576.02 0.15 0.04 0.0135223 0.0118207 112 -1 93 31 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_091.v common 5.47 0.03 7116 1 0.01 -1 -1 30128 -1 -1 35 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65924 32 32 382 304 1 194 99 17 17 289 -1 unnamed_device 2.83 994 0.17 0.00 3.37999 -116.206 -3.37999 3.37999 0.49 0.00036 0.000314437 0.0594288 0.0510954 28 2569 24 6.87369e+06 489084 531479. 1839.03 0.65 0.106565 0.0917915 2237 22 1749 2543 214152 46704 3.9657 3.9657 -144.105 -3.9657 0 0 648988. 2245.63 0.14 0.05 0.0162215 0.0141538 144 56 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66192 32 32 400 286 1 232 105 17 17 289 -1 unnamed_device 0.73 1277 0.17 0.00 3.98354 -137.218 -3.98354 3.98354 0.53 0.000378044 0.000332155 0.0549254 0.0472801 28 3271 26 6.87369e+06 572927 531479. 1839.03 0.94 0.112566 0.0972189 2779 21 2305 3740 278886 65802 4.97545 4.97545 -181.787 -4.97545 0 0 648988. 2245.63 0.13 0.06 0.0174446 0.0153899 183 -1 156 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_094.v common 5.49 0.03 7092 1 0.02 -1 -1 30260 -1 -1 32 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65380 30 32 374 298 1 188 94 17 17 289 -1 unnamed_device 2.28 941 0.14 0.00 2.82225 -95.3465 -2.82225 2.82225 0.60 0.000350453 0.000297731 0.0470851 0.0401274 26 2764 46 6.87369e+06 447163 503264. 1741.40 1.15 0.11249 0.0959753 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7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 67092 32 32 494 379 1 233 105 17 17 289 -1 unnamed_device 2.55 1182 0.22 0.00 3.39279 -117.001 -3.39279 3.39279 0.48 0.000420917 0.000370549 0.0729044 0.062715 30 3956 29 6.87369e+06 572927 556674. 1926.21 1.43 0.137629 0.11823 2596 21 1939 3388 231098 52509 3.7341 3.7341 -141.747 -3.7341 0 0 706193. 2443.58 0.14 0.05 0.0194676 0.0171892 184 85 62 31 95 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_097.v common 5.83 0.02 7324 1 0.01 -1 -1 30512 -1 -1 23 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66088 31 32 457 373 1 198 86 17 17 289 -1 unnamed_device 2.87 960 0.17 0.00 3.97274 -124.655 -3.97274 3.97274 0.49 0.000398731 0.000353999 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65876 32 32 406 319 1 201 106 17 17 289 -1 unnamed_device 2.42 1100 0.17 0.00 2.77395 -103.059 -2.77395 2.77395 0.50 0.000373111 0.0003274 0.0571206 0.0490852 28 2563 24 6.87369e+06 586901 531479. 1839.03 0.52 0.105636 0.0912301 2366 20 1631 2662 181354 43218 3.20756 3.20756 -131.262 -3.20756 0 0 648988. 2245.63 0.14 0.05 0.0165357 0.01446 157 61 63 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 4.14 0.02 6872 1 0.01 -1 -1 30128 -1 -1 20 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65764 29 32 291 242 1 155 81 17 17 289 -1 unnamed_device 1.46 740 0.15 0.00 2.78015 -91.6249 -2.78015 2.78015 0.59 0.000323094 0.00028628 0.0588174 0.0506026 30 1554 18 6.87369e+06 279477 556674. 1926.21 0.58 0.102957 0.0887712 1263 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on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65616 31 32 367 283 1 197 102 17 17 289 -1 unnamed_device 1.45 899 0.18 0.00 3.39279 -112.773 -3.39279 3.39279 0.49 0.000333656 0.000292811 0.0563887 0.0482658 32 3290 50 6.87369e+06 544980 586450. 2029.24 0.86 0.121946 0.104647 2025 21 1865 3107 245054 61301 4.013 4.013 -142.69 -4.013 0 0 744469. 2576.02 0.15 0.06 0.0160592 0.0140465 152 29 93 31 31 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_107.v common 5.33 0.02 6988 1 0.02 -1 -1 30232 -1 -1 32 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65592 29 32 301 258 1 148 93 17 17 289 -1 unnamed_device 2.74 750 0.15 0.00 2.70795 -87.0581 -2.70795 2.70795 0.48 0.000273218 0.000238127 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65284 32 32 334 280 1 164 81 17 17 289 -1 unnamed_device 2.28 672 0.12 0.00 2.47912 -86.3192 -2.47912 2.47912 0.48 0.000306873 0.000268297 0.0483759 0.0418043 34 2562 31 6.87369e+06 237555 618332. 2139.56 1.19 0.119521 0.102414 1605 22 1343 2106 166937 40871 2.85996 2.85996 -108.193 -2.85996 0 0 787024. 2723.27 0.16 0.04 0.0142441 0.0124266 110 54 32 32 60 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_114.v common 6.01 0.02 6844 1 0.01 -1 -1 30160 -1 -1 16 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65296 32 32 340 284 1 166 80 17 17 289 -1 unnamed_device 2.84 714 0.12 0.00 2.75195 -96.38 -2.75195 2.75195 0.48 0.000306373 0.000267843 0.0518509 0.0448499 40 1794 33 6.87369e+06 223581 706193. 2443.58 1.31 0.126122 0.108181 1696 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7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65996 29 32 371 297 1 183 95 17 17 289 -1 unnamed_device 2.07 922 0.17 0.00 2.74095 -91.9182 -2.74095 2.74095 0.48 0.000342481 0.000295057 0.0602617 0.0514198 30 2096 21 6.87369e+06 475111 556674. 1926.21 0.52 0.103325 0.0887425 1710 16 1019 1632 82264 20718 2.82066 2.82066 -109.215 -2.82066 0 0 706193. 2443.58 0.15 0.03 0.012777 0.011366 141 54 56 29 58 29 + fixed_k6_frac_ripple_N8_22nm.xml mult_117.v common 7.64 0.02 7088 1 0.01 -1 -1 30336 -1 -1 40 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66400 32 32 470 382 1 202 104 17 17 289 -1 unnamed_device 4.58 938 0.16 0.00 3.44599 -117.227 -3.44599 3.44599 0.49 0.000388327 0.00034102 0.0543426 0.0464234 34 2695 30 6.87369e+06 558954 618332. 2139.56 1.08 0.14495 0.124515 2132 22 2002 3251 205807 51654 3.9456 3.9456 -150.14 -3.9456 0 0 787024. 2723.27 0.16 0.05 0.0185402 0.0162191 157 117 0 0 128 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_118.v common 3.15 0.02 7008 1 0.01 -1 -1 30028 -1 -1 16 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65224 31 32 261 214 1 155 79 17 17 289 -1 unnamed_device 0.59 737 0.15 0.00 2.44612 -85.5706 -2.44612 2.44612 0.50 0.000263489 0.000229183 0.0602857 0.052075 32 2194 37 6.87369e+06 223581 586450. 2029.24 0.64 0.101976 0.087806 1675 20 1178 1802 164404 37890 3.24386 3.24386 -113.079 -3.24386 0 0 744469. 2576.02 0.15 0.04 0.0118254 0.010325 104 -1 85 31 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_119.v common 4.90 0.03 7156 1 0.01 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153 59 61 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_122.v common 7.37 0.03 7240 1 0.02 -1 -1 30428 -1 -1 47 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 67124 32 32 501 383 1 236 111 17 17 289 -1 unnamed_device 4.12 1261 0.20 0.00 4.02754 -141.189 -4.02754 4.02754 0.49 0.000426081 0.000376443 0.0644689 0.0554 28 3437 27 6.87369e+06 656770 531479. 1839.03 1.12 0.127641 0.109902 3041 23 2628 4178 364269 81055 4.91515 4.91515 -183.048 -4.91515 0 0 648988. 2245.63 0.17 0.07 0.0208934 0.01829 190 81 64 32 96 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_123.v common 3.98 0.02 6744 1 0.01 -1 -1 30044 -1 -1 14 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65356 30 32 249 232 1 118 76 17 17 289 -1 unnamed_device 1.76 701 0.08 0.00 2.28291 -78.7967 -2.28291 2.28291 0.48 0.00024318 0.000210061 0.0351027 0.0300778 32 1649 27 6.87369e+06 195634 586450. 2029.24 0.48 0.0672402 0.0574204 1409 19 730 1037 91018 21001 2.11902 2.11902 -93.0475 -2.11902 0 0 744469. 2576.02 0.15 0.03 0.0102079 0.00877849 72 51 0 0 53 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_124.v common 3.49 0.03 6992 1 0.02 -1 -1 30080 -1 -1 18 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65164 30 32 299 247 1 158 80 17 17 289 -1 unnamed_device 0.80 672 0.12 0.00 2.78935 -94.2596 -2.78935 2.78935 0.48 0.000287794 0.000253038 0.0472577 0.0410838 34 1761 22 6.87369e+06 251529 618332. 2139.56 0.78 0.108187 0.0932533 1517 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7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65040 25 32 259 222 1 139 94 17 17 289 -1 unnamed_device 0.63 709 0.14 0.00 2.69695 -77.7363 -2.69695 2.69695 0.51 0.000247699 0.000214822 0.0458503 0.038875 32 1774 23 6.87369e+06 517032 586450. 2029.24 0.49 0.0780068 0.0663388 1490 21 1024 1568 133399 29564 2.90196 2.90196 -95.7407 -2.90196 0 0 744469. 2576.02 0.19 0.03 0.0110667 0.00950061 106 19 50 25 25 25 + fixed_k6_frac_ripple_N8_22nm.xml mult_127.v common 6.10 0.02 7188 1 0.01 -1 -1 30340 -1 -1 21 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66184 32 32 433 347 1 200 85 17 17 289 -1 unnamed_device 2.80 840 0.14 0.00 3.39279 -115.959 -3.39279 3.39279 0.52 0.000382083 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0.00 -1 -1 30464 -1 -1 29 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66124 32 32 439 351 1 295 93 17 17 289 -1 unnamed_device 1.68 1303 0.24 0.00 4.09224 -140.916 -4.09224 4.09224 0.58 0.000551086 0.000480841 0.0823999 0.0713847 34 3724 38 6.89349e+06 408721 618332. 2139.56 1.75 0.214284 0.184759 2708 23 2580 3059 225429 51629 4.65275 4.65275 -165.273 -4.65275 0 0 787024. 2723.27 0.16 0.05 0.0187036 0.0163962 192 80 32 32 96 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_002.v common 4.46 0.03 7160 1 0.02 -1 -1 30284 -1 -1 29 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65756 30 32 412 333 1 262 91 17 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0.0130881 167 50 54 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_004.v common 4.17 0.03 7060 1 0.01 -1 -1 30264 -1 -1 25 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65336 29 32 347 271 1 209 86 17 17 289 -1 unnamed_device 1.29 1077 0.14 0.00 3.65595 -118.117 -3.65595 3.65595 0.50 0.000323254 0.000284642 0.0482922 0.0418358 34 2760 30 6.89349e+06 352346 618332. 2139.56 0.94 0.124797 0.107169 2240 21 1703 2629 176571 41572 4.15226 4.15226 -144.254 -4.15226 0 0 787024. 2723.27 0.16 0.04 0.0147699 0.0129979 148 25 87 29 29 29 + fixed_k6_frac_uripple_N8_22nm.xml mult_005.v common 5.44 0.02 7196 1 0.02 -1 -1 30092 -1 -1 24 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65428 32 32 377 289 1 233 88 17 17 289 -1 unnamed_device 1.80 1246 0.18 0.00 4.13624 -141.151 -4.13624 4.13624 0.49 0.000447223 0.000396693 0.0627276 0.0548585 36 3411 25 6.89349e+06 338252 648988. 2245.63 1.64 0.146703 0.127067 2892 21 2583 4406 334947 71908 4.44425 4.44425 -169.166 -4.44425 0 0 828058. 2865.25 0.17 0.06 0.0159571 0.0140364 163 31 96 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_006.v common 4.53 0.03 7144 1 0.02 -1 -1 30176 -1 -1 41 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65484 32 32 403 317 1 257 105 17 17 289 -1 unnamed_device 1.54 1371 0.19 0.00 3.58259 -119.395 -3.58259 3.58259 0.48 0.000370715 0.000325615 0.0588318 0.0506239 34 3534 37 6.89349e+06 577847 618332. 2139.56 0.99 0.145304 0.125099 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65244 32 32 424 311 1 254 91 17 17 289 -1 unnamed_device 1.76 1323 0.21 0.00 3.73615 -131.888 -3.73615 3.73615 0.51 0.000381685 0.00033531 0.0705079 0.0611196 34 3677 50 6.89349e+06 380534 618332. 2139.56 1.60 0.180244 0.155165 2903 22 2151 3467 268731 59570 4.32776 4.32776 -163.557 -4.32776 0 0 787024. 2723.27 0.19 0.06 0.0191346 0.0164739 184 26 128 32 27 27 + fixed_k6_frac_uripple_N8_22nm.xml mult_036.v common 4.84 0.03 7024 1 0.01 -1 -1 30116 -1 -1 25 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65712 32 32 404 318 1 260 89 17 17 289 -1 unnamed_device 1.45 1272 0.18 0.00 3.39994 -121.955 -3.39994 3.39994 0.48 0.000383842 0.000321406 0.0646717 0.0556245 36 3127 22 6.89349e+06 352346 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v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65800 31 32 393 311 1 246 89 17 17 289 -1 unnamed_device 2.30 1162 0.14 0.00 3.38219 -112.428 -3.38219 3.38219 0.48 0.000358243 0.000316893 0.0499627 0.0434241 34 3134 24 6.89349e+06 366440 618332. 2139.56 0.96 0.127904 0.110319 2561 22 1934 2819 228152 52677 3.6803 3.6803 -141.388 -3.6803 0 0 787024. 2723.27 0.16 0.05 0.0172649 0.0151959 170 59 60 30 62 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_039.v common 5.44 0.03 7336 1 0.01 -1 -1 30388 -1 -1 31 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66196 31 32 457 373 1 307 94 17 17 289 -1 unnamed_device 1.63 1493 0.20 0.00 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65800 32 32 408 320 1 264 91 17 17 289 -1 unnamed_device 1.66 1260 0.17 0.00 3.76105 -132.338 -3.76105 3.76105 0.48 0.000341436 0.00030008 0.0592549 0.0512428 34 3361 49 6.89349e+06 380534 618332. 2139.56 1.15 0.151131 0.129808 2671 23 2104 2668 195202 45182 4.25266 4.25266 -161.656 -4.25266 0 0 787024. 2723.27 0.16 0.05 0.0172486 0.0151072 178 42 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_043.v common 6.04 0.02 7436 1 0.02 -1 -1 30316 -1 -1 31 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66984 32 32 497 381 1 321 95 17 17 289 -1 unnamed_device 1.85 1435 0.20 0.00 4.11298 -135.822 -4.11298 4.11298 0.50 0.000430474 0.000383134 0.0704351 0.0615717 36 4405 32 6.89349e+06 436909 648988. 2245.63 2.09 0.17958 0.154976 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GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65436 31 32 397 313 1 251 90 17 17 289 -1 unnamed_device 1.38 1135 0.17 0.00 4.03914 -130.627 -4.03914 4.03914 0.49 0.000493803 0.000425117 0.0624376 0.0536434 38 3091 25 6.89349e+06 380534 678818. 2348.85 1.61 0.146579 0.125639 2249 21 1753 2188 165048 41408 4.26285 4.26285 -149.979 -4.26285 0 0 902133. 3121.57 0.17 0.05 0.0163079 0.0143432 168 59 62 31 62 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_046.v common 5.75 0.02 7072 1 0.02 -1 -1 30280 -1 -1 28 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65356 32 32 398 314 1 254 92 17 17 289 -1 unnamed_device 1.52 1251 0.19 0.00 3.64679 -123.436 -3.64679 3.64679 0.51 0.000362261 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VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65400 32 32 313 256 1 198 84 17 17 289 -1 unnamed_device 1.43 780 0.12 0.00 2.97485 -103.213 -2.97485 2.97485 0.52 0.00028901 0.000251505 0.0479332 0.0412923 38 2207 35 6.89349e+06 281877 678818. 2348.85 1.89 0.119651 0.101908 1553 21 1183 1609 103419 25874 2.89486 2.89486 -117.595 -2.89486 0 0 902133. 3121.57 0.17 0.03 0.0130005 0.0113612 127 20 63 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_056.v common 4.13 0.03 7068 1 0.02 -1 -1 29972 -1 -1 22 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65136 32 32 371 315 1 249 86 17 17 289 -1 unnamed_device 1.15 1056 0.15 0.00 3.36819 -113.616 -3.36819 3.36819 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65112 32 32 284 226 1 168 97 17 17 289 -1 unnamed_device 0.46 697 0.14 0.00 2.97285 -102.615 -2.97285 2.97285 0.51 0.000278769 0.000243364 0.0473919 0.0404614 38 2164 34 6.89349e+06 465097 678818. 2348.85 1.92 0.121609 0.103427 1612 23 1305 2147 145489 35985 3.23576 3.23576 -123.365 -3.23576 0 0 902133. 3121.57 0.17 0.04 0.0131146 0.0114093 123 -1 96 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_063.v common 6.00 0.02 7376 1 0.01 -1 -1 30452 -1 -1 28 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65848 32 32 439 321 1 267 92 17 17 289 -1 unnamed_device 1.70 1270 0.18 0.00 4.33489 -144.285 -4.33489 4.33489 0.48 0.000395562 0.000349783 0.0694527 0.0605526 40 3361 26 6.89349e+06 394628 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v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65036 30 32 299 247 1 185 81 17 17 289 -1 unnamed_device 1.03 818 0.10 0.00 2.94965 -97.7253 -2.94965 2.94965 0.48 0.000282797 0.000246885 0.0371795 0.0319632 34 2278 23 6.89349e+06 267783 618332. 2139.56 0.82 0.0979761 0.0839389 1788 18 1314 1780 112411 27419 3.14876 3.14876 -119.925 -3.14876 0 0 787024. 2723.27 0.16 0.03 0.0115767 0.0101324 121 29 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_066.v common 4.99 0.02 7232 1 0.02 -1 -1 30160 -1 -1 31 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65668 29 32 397 323 1 254 92 17 17 289 -1 unnamed_device 1.56 1301 0.21 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65332 30 32 299 247 1 183 81 17 17 289 -1 unnamed_device 1.46 925 0.13 0.00 3.20646 -106.547 -3.20646 3.20646 0.48 0.000284159 0.000248349 0.0482676 0.0417708 34 2412 21 6.89349e+06 267783 618332. 2139.56 0.84 0.109283 0.0939928 2017 18 1208 1717 141579 30930 3.3557 3.3557 -128.004 -3.3557 0 0 787024. 2723.27 0.16 0.03 0.0117859 0.0103333 121 29 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_080.v common 5.17 0.02 7172 1 0.01 -1 -1 30128 -1 -1 26 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65256 30 32 386 306 1 241 88 17 17 289 -1 unnamed_device 2.06 1055 0.17 0.00 3.92648 -126.993 -3.92648 3.92648 0.48 0.000353798 0.000312324 0.064535 0.0559067 36 2715 22 6.89349e+06 366440 648988. 2245.63 1.19 0.14279 0.122954 2265 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GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66036 31 32 427 343 1 278 92 17 17 289 -1 unnamed_device 1.47 1252 0.18 0.00 4.20654 -137.111 -4.20654 4.20654 0.49 0.00036971 0.000327075 0.0620118 0.0538921 36 2903 30 6.89349e+06 408721 648988. 2245.63 1.45 0.149579 0.128813 2174 20 2051 2586 147960 37821 4.41635 4.41635 -156.949 -4.41635 0 0 828058. 2865.25 0.20 0.04 0.0165509 0.0146064 185 79 31 31 93 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_083.v common 5.21 0.03 7160 1 0.01 -1 -1 30324 -1 -1 28 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65984 30 32 407 331 1 261 90 17 17 289 -1 unnamed_device 1.78 1054 0.15 0.00 3.44329 -107.559 -3.44329 3.44329 0.48 0.000358452 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0.0155402 174 62 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_088.v common 6.76 0.03 7112 1 0.01 -1 -1 30124 -1 -1 25 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65688 32 32 408 320 1 263 89 17 17 289 -1 unnamed_device 2.13 1122 0.16 0.00 4.10498 -137.69 -4.10498 4.10498 0.48 0.00036696 0.000323792 0.0629138 0.0542843 38 3783 35 6.89349e+06 352346 678818. 2348.85 2.67 0.156066 0.133659 2426 23 2451 3407 244656 57774 5.14165 5.14165 -172.045 -5.14165 0 0 902133. 3121.57 0.17 0.06 0.0179143 0.0157653 176 62 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_089.v common 4.43 0.03 6976 1 0.01 -1 -1 30180 -1 -1 19 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65280 32 32 316 268 1 204 83 17 17 289 -1 unnamed_device 1.38 844 0.11 0.00 2.7541 -91.2491 -2.7541 2.7541 0.48 0.000280373 0.000243553 0.0443593 0.0382116 38 2387 38 6.89349e+06 267783 678818. 2348.85 1.18 0.122473 0.104788 1721 20 1273 1566 110287 26966 3.05956 3.05956 -107.991 -3.05956 0 0 902133. 3121.57 0.17 0.03 0.0124712 0.0109 128 47 32 32 54 27 + fixed_k6_frac_uripple_N8_22nm.xml mult_090.v common 3.02 0.03 6900 1 0.01 -1 -1 30064 -1 -1 17 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64968 31 32 277 222 1 164 80 17 17 289 -1 unnamed_device 0.67 822 0.11 0.00 2.84755 -99.0989 -2.84755 2.84755 0.48 0.000276419 0.000242944 0.0399785 0.0345444 32 2162 23 6.89349e+06 239595 586450. 2029.24 0.52 0.0753826 0.0650971 1725 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0.000266149 0.0566241 0.0485618 38 2690 28 6.89349e+06 281877 678818. 2348.85 2.50 0.147237 0.12638 2163 23 1537 2089 213148 54329 2.96891 2.96891 -114.369 -2.96891 0 0 902133. 3121.57 0.17 0.05 0.0151188 0.013225 136 54 32 32 60 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_114.v common 4.24 0.03 7000 1 0.01 -1 -1 30060 -1 -1 19 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65316 32 32 340 284 1 218 83 17 17 289 -1 unnamed_device 1.11 1021 0.13 0.00 3.1044 -107.068 -3.1044 3.1044 0.48 0.000304717 0.000265493 0.0498018 0.0429049 34 3045 37 6.89349e+06 267783 618332. 2139.56 1.05 0.123916 0.105839 2293 21 1743 2114 172920 39213 3.36316 3.36316 -128.309 -3.36316 0 0 787024. 2723.27 0.16 0.04 0.0139289 0.0121508 138 60 32 32 62 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_115.v common 4.88 0.03 7112 1 0.02 -1 -1 30524 -1 -1 28 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66016 32 32 408 320 1 264 92 17 17 289 -1 unnamed_device 1.25 1031 0.14 0.00 3.78125 -125.579 -3.78125 3.78125 0.48 0.000352137 0.000310074 0.0507169 0.0439372 36 3171 46 6.89349e+06 394628 648988. 2245.63 1.63 0.144312 0.123432 2320 24 2176 2688 214606 48653 4.22446 4.22446 -154.433 -4.22446 0 0 828058. 2865.25 0.16 0.05 0.0179239 0.0156745 178 49 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_116.v common 3.72 0.03 7264 1 0.02 -1 -1 30236 -1 -1 27 29 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65448 29 32 371 297 1 231 88 17 17 289 -1 unnamed_device 1.23 1188 0.15 0.00 2.96685 -99.2813 -2.96685 2.96685 0.49 0.00033776 0.000297208 0.054466 0.0469196 30 2745 20 6.89349e+06 380534 556674. 1926.21 0.55 0.0976694 0.0838902 2155 18 1469 2008 134965 29507 2.94026 2.94026 -115.726 -2.94026 0 0 706193. 2443.58 0.14 0.04 0.0137726 0.0120794 158 54 56 29 58 29 + fixed_k6_frac_uripple_N8_22nm.xml mult_117.v common 5.24 0.02 7196 1 0.03 -1 -1 30364 -1 -1 29 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66428 32 32 470 382 1 315 93 17 17 289 -1 unnamed_device 1.40 1330 0.20 0.00 4.11918 -135.21 -4.11918 4.11918 0.59 0.000401406 0.00035373 0.0750103 0.0651783 38 3507 40 6.89349e+06 408721 678818. 2348.85 1.61 0.203538 0.175929 2667 23 2552 2974 193703 46037 4.61549 4.61549 -164.506 -4.61549 0 0 902133. 3121.57 0.17 0.05 0.0190712 0.0167232 203 117 0 0 128 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_118.v common 2.78 0.03 6904 1 0.02 -1 -1 30088 -1 -1 16 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64992 31 32 261 214 1 155 79 17 17 289 -1 unnamed_device 0.48 714 0.11 0.00 2.34777 -84.5304 -2.34777 2.34777 0.48 0.00026202 0.000227942 0.0424728 0.0367208 30 1982 23 6.89349e+06 225501 556674. 1926.21 0.48 0.0763491 0.0659204 1598 19 849 1377 82458 19841 2.63831 2.63831 -108.848 -2.63831 0 0 706193. 2443.58 0.14 0.03 0.0108714 0.0094959 104 -1 85 31 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_119.v common 4.79 0.02 7092 1 0.01 -1 -1 30000 -1 -1 28 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65988 32 32 419 339 1 274 92 17 17 289 -1 unnamed_device 1.66 1382 0.19 0.00 4.50338 -149.401 -4.50338 4.50338 0.48 0.000371126 0.000328233 0.064109 0.0555244 34 3617 45 6.89349e+06 394628 618332. 2139.56 1.12 0.15917 0.1364 2800 18 2130 2805 195368 46213 5.15034 5.15034 -175.889 -5.15034 0 0 787024. 2723.27 0.16 0.05 0.0156082 0.0138424 180 89 28 28 92 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_120.v common 4.95 0.03 6960 1 0.01 -1 -1 29972 -1 -1 24 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65492 32 32 377 319 1 259 88 17 17 289 -1 unnamed_device 1.77 1305 0.13 0.00 3.83248 -135.135 -3.83248 3.83248 0.48 0.000339341 0.00029609 0.0463846 0.0399855 34 3448 27 6.89349e+06 338252 618332. 2139.56 1.23 0.123866 0.105913 2797 23 2807 3472 292658 63218 4.39939 4.39939 -166.585 -4.39939 0 0 787024. 2723.27 0.16 0.06 0.0166114 0.014564 161 93 0 0 96 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_121.v common 6.27 0.03 7088 1 0.00 -1 -1 30172 -1 -1 26 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65268 32 32 402 317 1 253 90 17 17 289 -1 unnamed_device 1.43 1094 0.16 0.00 3.00785 -104.42 -3.00785 3.00785 0.48 0.000356407 0.000314102 0.0585518 0.0507803 36 3328 47 6.89349e+06 366440 648988. 2245.63 2.90 0.179776 0.154548 2247 21 1677 2361 208573 52778 3.03916 3.03916 -126.569 -3.03916 0 0 828058. 2865.25 0.16 0.05 0.0175875 0.0154335 172 59 61 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 4.70 0.02 7276 1 0.01 -1 -1 30432 -1 -1 32 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66808 32 32 501 383 1 322 96 17 17 289 -1 unnamed_device 1.37 1489 0.23 0.00 4.40399 -146.526 -4.40399 4.40399 0.48 0.00047693 0.000427311 0.0794146 0.0684967 38 3353 30 6.89349e+06 451003 678818. 2348.85 1.25 0.193845 0.167512 2766 20 2109 2535 168807 37286 4.8783 4.8783 -176.048 -4.8783 0 0 902133. 3121.57 0.17 0.05 0.0186702 0.016506 223 81 64 32 96 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 3.68 0.02 6844 1 0.01 -1 -1 29960 -1 -1 16 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65236 30 32 249 232 1 160 78 17 17 289 -1 unnamed_device 1.14 667 0.08 0.00 2.55272 -76.4495 -2.55272 2.55272 0.48 0.000233832 0.000202628 0.0328783 0.0280139 34 1742 20 6.89349e+06 225501 618332. 2139.56 0.79 0.0816224 0.0691289 1379 20 727 753 55732 13683 2.68996 2.68996 -90.6946 -2.68996 0 0 787024. 2723.27 0.16 0.02 0.0102567 0.008916 93 51 0 0 53 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 3.53 0.02 7192 1 0.01 -1 -1 30060 -1 -1 21 30 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65464 30 32 299 247 1 181 83 17 17 289 -1 unnamed_device 0.95 957 0.13 0.00 3.47009 -117.109 -3.47009 3.47009 0.49 0.000293184 0.000258548 0.0495974 0.0430557 30 2084 49 6.89349e+06 295971 556674. 1926.21 0.56 0.0995609 0.0861516 1781 20 1089 1651 117361 25664 3.4135 3.4135 -134.948 -3.4135 0 0 706193. 2443.58 0.20 0.05 0.0209695 0.0184099 124 29 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_125.v common 6.63 0.03 6996 1 0.01 -1 -1 29932 -1 -1 19 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65620 32 32 315 257 1 199 83 17 17 289 -1 unnamed_device 1.97 826 0.16 0.00 3.42319 -115.141 -3.42319 3.42319 0.58 0.000435188 0.000377279 0.0586795 0.0505743 38 2581 48 6.89349e+06 267783 678818. 2348.85 2.54 0.16666 0.143468 1805 20 1647 2790 189078 44767 3.6814 3.6814 -138.978 -3.6814 0 0 902133. 3121.57 0.17 0.04 0.0134421 0.0117775 129 31 64 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 3.21 0.02 6876 1 0.01 -1 -1 30120 -1 -1 24 25 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65360 25 32 259 222 1 162 81 17 17 289 -1 unnamed_device 0.97 700 0.11 0.00 3.0462 -83.3765 -3.0462 3.0462 0.48 0.000247529 0.000215619 0.0396451 0.0338382 28 1816 22 6.89349e+06 338252 531479. 1839.03 0.47 0.0715424 0.0611536 1580 21 1119 1577 108866 26119 3.18081 3.18081 -101.91 -3.18081 0 0 648988. 2245.63 0.14 0.03 0.0116866 0.0101482 107 19 50 25 25 25 + fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 5.67 0.02 7140 1 0.01 -1 -1 30244 -1 -1 28 32 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66220 32 32 433 347 1 288 92 17 17 289 -1 unnamed_device 2.18 1454 0.19 0.00 3.70605 -126.1 -3.70605 3.70605 0.48 0.000377549 0.000334299 0.0634961 0.0554605 36 3565 30 6.89349e+06 394628 648988. 2245.63 1.51 0.154794 0.133707 3001 20 2250 3270 229559 51946 4.01296 4.01296 -154.548 -4.01296 0 0 828058. 2865.25 0.16 0.05 0.0166733 0.0146913 190 84 32 32 94 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 4.57 0.02 7260 1 0.01 -1 -1 30164 -1 -1 28 31 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65800 31 32 423 341 1 274 91 17 17 289 -1 unnamed_device 1.51 1448 0.18 0.00 3.84049 -131.027 -3.84049 3.84049 0.48 0.000372702 0.000330169 0.0632396 0.0548932 34 3547 25 6.89349e+06 394628 618332. 2139.56 1.08 0.145722 0.125588 2959 21 2288 3207 237783 53951 4.34919 4.34919 -158.882 -4.34919 0 0 787024. 2723.27 0.16 0.05 0.0173253 0.0152015 182 88 29 29 93 31 diff --git a/vtr_flow/tasks/arithmetic_tasks/open_cores/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/config.txt similarity index 73% rename from vtr_flow/tasks/arithmetic_tasks/open_cores/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/config.txt index b5a0a0e8afc..7ee3239e85b 100644 --- a/vtr_flow/tasks/arithmetic_tasks/open_cores/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/config.txt @@ -11,21 +11,25 @@ archs_dir=arch/COFFE_22nm # Add circuits to list to sweep + circuit_list_add=Md5Core.v -circuit_list_add=rc4.v -circuit_list_add=cordic.v -circuit_list_add=pipelined_fft_64.v +circuit_list_add=cordic.v +#Odin issue, Issue#1738 +#circuit_list_add=pipelined_fft_64.v # Add architectures to list to sweep arch_list_add=k6_N8_gate_boost_0.2V_22nm.xml -arch_list_add=k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml -arch_list_add=k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml +#arch_list_add=k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml +#arch_list_add=k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml arch_list_add=k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml arch_list_add=k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml # Parse info and how to parse parse_file=vpr_chain.txt +# How to parse QoR info +qor_parse_file=qor_standard.txt + # Pass requirements pass_requirements_file=pass_requirements_chain.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt new file mode 100644 index 00000000000..e30318bd686 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt @@ -0,0 +1,7 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 561.02 12.61 123256 27 15.63 -1 -1 138616 -1 -1 5890 641 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1078456 641 128 52347 52475 1 24691 6659 91 91 8281 clb auto 183.27 311456 97.61 0.73 12.9118 -34123.7 -12.9118 12.9118 60.54 0.0612485 0.0531831 9.89888 7.98251 68 446733 33 2.5209e+08 7.10084e+07 3.55803e+07 4296.62 115.29 29.0224 24.2581 413889 15 107844 232243 17228674 3275078 13.5733 13.5733 -36053.1 -13.5733 0 0 4.43124e+07 5351.09 17.45 7.01 3.10422 2.73974 42410 15098 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 2.63 0.05 9232 11 0.22 -1 -1 33360 -1 -1 46 54 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68536 54 51 469 520 1 312 151 10 10 100 clb auto 0.10 2313 0.18 0.00 4.9488 -207.159 -4.9488 4.9488 0.12 0.000597627 0.000481519 0.0596217 0.0487068 50 4972 26 1.91864e+06 554530 264954. 2649.54 0.98 0.208444 0.176477 4461 18 1872 8041 459971 107312 5.4296 5.4296 -231.493 -5.4296 0 0 317040. 3170.40 0.06 0.09 0.0309584 0.0277996 359 359 -1 -1 -1 -1 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 607.06 14.22 110532 1 3.85 -1 -1 168832 -1 -1 5784 641 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1157952 641 128 63843 53443 1 24861 6553 90 90 8100 clb auto 25.54 316995 276.94 1.44 6.22442 -24286.9 -6.22442 6.22442 62.02 0.0532843 0.045816 10.7799 8.54605 74 434562 33 2.53171e+08 7.26417e+07 3.72985e+07 4604.75 143.62 33.4074 27.4978 404856 16 94493 167001 17536749 3023582 5.98868 5.98868 -24820.3 -5.98868 0 0 4.63728e+07 5725.03 21.12 6.61 2.89675 2.52044 43404 3440 12624 36 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 3.94 0.03 9476 4 0.12 -1 -1 32748 -1 -1 42 54 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68448 54 51 517 516 1 301 147 10 10 100 clb auto 1.26 1956 0.23 0.00 3.71205 -184.501 -3.71205 3.71205 0.12 0.000574395 0.000498369 0.0721433 0.060153 46 4447 39 1.94278e+06 527436 244280. 2442.80 1.22 0.242678 0.20723 3739 19 1588 6261 340386 80664 3.89654 3.89654 -203.39 -3.89654 0 0 298105. 2981.05 0.05 0.08 0.0346354 0.0316723 315 291 60 18 54 18 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 625.14 14.11 110688 1 3.82 -1 -1 168784 -1 -1 5776 641 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1162892 641 128 63843 53443 1 24860 6545 90 90 8100 clb auto 40.93 291391 280.06 1.61 5.37451 -23306.6 -5.37451 5.37451 60.87 0.054596 0.0465628 10.929 8.59823 74 411779 35 2.53845e+08 7.32344e+07 3.72985e+07 4604.75 142.06 34.1954 28.0112 382561 32 106569 186826 20333947 3932009 4.92089 4.92089 -23833.3 -4.92089 0 0 4.63728e+07 5725.03 21.20 9.48 4.82742 4.16577 43450 3440 12624 36 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 3.54 0.04 9428 4 0.12 -1 -1 32784 -1 -1 41 54 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68496 54 51 517 516 1 305 146 10 10 100 clb auto 0.90 2002 0.23 0.00 3.55653 -181.169 -3.55653 3.55653 0.13 0.000587628 0.000480292 0.0682492 0.0566937 46 4376 40 1.94854e+06 519798 244280. 2442.80 1.13 0.228573 0.194694 3684 16 1518 5647 297195 70804 3.76303 3.76303 -198.452 -3.76303 0 0 298105. 2981.05 0.06 0.09 0.0400905 0.0367294 314 291 60 18 54 18 diff --git a/vtr_flow/tasks/arithmetic_tasks/open_cores_frac/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/config.txt similarity index 87% rename from vtr_flow/tasks/arithmetic_tasks/open_cores_frac/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/config.txt index 1eca685c6ea..78eae31d19e 100644 --- a/vtr_flow/tasks/arithmetic_tasks/open_cores_frac/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/config.txt @@ -12,9 +12,9 @@ archs_dir=arch/timing/fraclut_carrychain # Add circuits to list to sweep circuit_list_add=Md5Core.v -circuit_list_add=rc4.v circuit_list_add=cordic.v -circuit_list_add=pipelined_fft_64.v +#Odin issue, Issue#1738 +#circuit_list_add=pipelined_fft_64.v # Add architectures to list to sweep arch_list_add=k6_frac_2ripple_N8_22nm.xml @@ -26,6 +26,9 @@ arch_list_add=k6_frac_uripple_N8_22nm.xml # Parse info and how to parse parse_file=vpr_chain.txt +# How to parse QoR info +qor_parse_file=qor_standard.txt + # Pass requirements pass_requirements_file=pass_requirements_chain.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt new file mode 100644 index 00000000000..9e6d5ca835a --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt @@ -0,0 +1,11 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_2ripple_N8_22nm.xml Md5Core.v common 1401.09 12.82 110636 1 3.92 -1 -1 168768 -1 -1 3149 641 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 832960 641 128 63843 53443 1 24210 3918 67 67 4489 clb auto 1024.51 257678 97.94 0.67 7.03324 -23933.4 -7.03324 7.03324 34.57 0.0518919 0.0436921 9.8926 7.92152 100 358371 35 1.40629e+08 4.55847e+07 2.79005e+07 6215.31 172.08 33.0484 27.0956 322840 17 109932 151911 15705252 2647903 6.5711 6.5711 -24866.8 -6.5711 0 0 3.55909e+07 7928.48 13.35 6.28 3.07102 2.68229 23365 3440 12624 36 0 0 + k6_frac_2ripple_N8_22nm.xml cordic.v common 6.67 0.05 9448 4 0.12 -1 -1 32808 -1 -1 30 54 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66408 54 51 517 516 1 317 135 9 9 81 clb auto 3.35 1786 0.18 0.00 3.60225 -193.015 -3.60225 3.60225 0.09 0.000555036 0.000479567 0.0645623 0.0537161 58 4054 30 1.45065e+06 434271 237595. 2933.27 1.94 0.302544 0.256863 3564 19 1968 6980 420492 96927 3.69482 3.69482 -209.853 -3.69482 0 0 298762. 3688.42 0.05 0.09 0.0320876 0.029091 223 291 60 18 54 18 + k6_frac_2uripple_N8_22nm.xml Md5Core.v common 1150.69 13.45 110600 1 5.01 -1 -1 168716 -1 -1 3156 641 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 824796 641 128 63843 53443 1 24164 3925 67 67 4489 clb auto 767.73 248943 112.74 0.79 6.4024 -23443.5 -6.4024 6.4024 37.70 0.0547589 0.0469342 10.2701 8.18759 98 347080 49 1.41393e+08 4.64435e+07 2.75098e+07 6128.27 157.99 35.5373 29.0405 310960 25 102684 143997 15311899 2541405 6.50111 6.50111 -24262.2 -6.50111 0 0 3.50293e+07 7803.36 13.67 7.25 4.05496 3.49547 23381 3440 12624 36 0 0 + k6_frac_2uripple_N8_22nm.xml cordic.v common 2.90 0.05 9440 4 0.17 -1 -1 32812 -1 -1 33 54 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66568 54 51 517 516 1 311 138 9 9 81 clb auto 0.28 1793 0.23 0.00 3.4018 -184.903 -3.4018 3.4018 0.11 0.000875609 0.000744989 0.078312 0.0646235 62 4103 25 1.45905e+06 485618 249781. 3083.72 1.07 0.287054 0.246727 3296 20 1754 6505 345120 79736 3.6993 3.6993 -207.149 -3.6993 0 0 310465. 3832.90 0.05 0.09 0.0359982 0.0326228 229 291 60 18 54 18 + k6_frac_N8_22nm.xml Md5Core.v common 1122.00 12.85 123268 27 16.36 -1 -1 138760 -1 -1 3468 641 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 871668 641 128 52347 52475 1 23476 4237 70 70 4900 clb auto 815.87 271607 57.03 0.41 12.5111 -34057.6 -12.5111 12.5111 36.04 0.0562456 0.0478112 9.56146 7.4156 88 402162 32 1.54829e+08 4.67209e+07 2.76661e+07 5646.14 126.54 35.023 29.0631 371959 17 112389 234005 19871258 3560692 13.6319 13.6319 -36742.1 -13.6319 0 0 3.43899e+07 7018.34 11.62 8.01 3.61036 3.1926 24733 15098 -1 -1 -1 -1 + k6_frac_N8_22nm.xml cordic.v common 2.46 0.05 9324 11 0.20 -1 -1 33308 -1 -1 34 54 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68104 54 51 469 520 1 316 139 9 9 81 clb auto 0.18 2134 0.19 0.00 5.44943 -213.884 -5.44943 5.44943 0.10 0.00056618 0.00048761 0.0639681 0.0524048 66 4356 21 1.41552e+06 458048 266717. 3292.80 0.80 0.209942 0.178962 3913 16 1744 7138 398320 89544 5.57473 5.57473 -231.21 -5.57473 0 0 334415. 4128.58 0.05 0.08 0.0298234 0.0270818 265 359 -1 -1 -1 -1 + k6_frac_ripple_N8_22nm.xml Md5Core.v common 1224.28 12.95 110696 1 4.27 -1 -1 168748 -1 -1 3940 641 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 993924 641 128 63843 53443 1 22919 4709 75 75 5625 clb auto 757.70 270606 220.85 0.98 6.32261 -22561.4 -6.32261 6.32261 48.97 0.0601633 0.0455592 11.3615 8.64267 78 375908 50 1.79437e+08 5.50544e+07 2.85911e+07 5082.87 118.04 36.3026 29.3732 349542 19 107390 181645 17899008 3256227 5.48606 5.48606 -22688.5 -5.48606 0 0 3.58571e+07 6374.60 14.98 6.93 3.2123 2.76456 29971 3440 12624 36 0 0 + k6_frac_ripple_N8_22nm.xml cordic.v common 4.49 0.05 9536 4 0.15 -1 -1 32768 -1 -1 32 54 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66820 54 51 517 516 1 308 137 9 9 81 clb auto 2.08 1828 0.24 0.00 3.66598 -188.823 -3.66598 3.66598 0.10 0.000566407 0.000494002 0.0786461 0.0659278 56 4061 38 1.43308e+06 447163 231774. 2861.41 0.96 0.289468 0.248626 3481 17 1649 5644 322384 79351 3.82685 3.82685 -199.294 -3.82685 0 0 286113. 3532.26 0.04 0.07 0.0281784 0.0255084 235 291 60 18 54 18 + k6_frac_uripple_N8_22nm.xml Md5Core.v common 990.97 12.86 110588 1 4.17 -1 -1 168756 -1 -1 4048 641 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1002212 641 128 63843 53443 1 24269 4817 76 76 5776 clb auto 479.88 296023 224.50 1.15 6.5534 -24047.2 -6.5534 6.5534 48.44 0.0571196 0.0490958 11.4279 8.97106 70 397234 36 1.87279e+08 5.70491e+07 2.68464e+07 4647.92 162.79 29.0834 23.4987 360992 20 98345 139760 15050421 2633583 6.0668 6.0668 -23950.1 -6.0668 0 0 3.38185e+07 5855.01 13.08 6.67 3.49072 3.01266 30740 3440 12624 36 0 0 + k6_frac_uripple_N8_22nm.xml cordic.v common 2.70 0.04 9444 4 0.13 -1 -1 32740 -1 -1 33 54 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68360 54 51 517 516 1 307 138 9 9 81 clb auto 0.53 1849 0.23 0.00 3.77313 -188.652 -3.77313 3.77313 0.10 0.00105296 0.000866028 0.0725099 0.0598183 58 4197 23 1.43728e+06 465097 237595. 2933.27 0.78 0.213566 0.180988 3534 18 1928 7033 401761 94430 3.66891 3.66891 -202.048 -3.66891 0 0 298762. 3688.42 0.05 0.09 0.0294513 0.0264488 250 291 60 18 54 18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/config.txt new file mode 100644 index 00000000000..a08c2cb054d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/config.txt @@ -0,0 +1,43 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Power +script_params=-power -track_memory_usage +cmos_tech_behavior=PTM_45nm/45nm.xml + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/power + +# Add circuits to list to sweep +circuit_list_add=ch_intrinsics.v +circuit_list_add=diffeq1.v +circuit_list_add=LU8PEEng.v + +# Add architectures to list to sweep +arch_list_add=k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml +arch_list_add=k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml + +arch_list_add=k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml +arch_list_add=k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml + +arch_list_add=k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml +arch_list_add=k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml + +arch_list_add=k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml +arch_list_add=k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml + +arch_list_add=k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml +arch_list_add=k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml + +# Parse info and how to parse +parse_file=vpr_power.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements_power.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt new file mode 100644 index 00000000000..4d0d283ad55 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt @@ -0,0 +1,31 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.63 0.05 9356 3 0.20 -1 -1 36268 -1 -1 68 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65424 99 130 363 493 1 256 298 12 12 144 clb auto 0.06 706 0.26 0.00 1.86328 -198.021 -1.86328 1.86328 0.18 0.000419318 0.000367215 0.0724357 0.0627192 46 1510 15 5.66058e+06 4.21279e+06 378970. 2631.74 0.48 0.166593 0.147535 1419 13 512 678 54408 17907 2.4649 2.4649 -230.915 -2.4649 0 0 486261. 3376.82 0.08 0.03 0.0156866 0.0143839 0.00814 0.2379 0.08094 0.6811 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 10.01 0.04 9184 15 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/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65748 99 130 363 493 1 260 297 12 12 144 clb auto 0.06 657 0.27 0.00 2.08915 -200.289 -2.08915 2.08915 0.18 0.00042992 0.000375917 0.0728606 0.0630416 46 1482 12 5.66058e+06 4.1589e+06 378970. 2631.74 0.47 0.166281 0.147076 1398 10 523 698 65113 21840 2.65239 2.65239 -232.095 -2.65239 0 0 486261. 3376.82 0.07 0.03 0.0138592 0.0127383 0.008628 0.2081 0.07103 0.7208 + k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml diffeq1.v common 10.01 0.04 9156 15 0.29 -1 -1 34664 -1 -1 39 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 69968 162 96 999 932 1 691 302 16 16 256 mult_36 auto 0.21 5251 0.58 0.01 19.8123 -1650.45 -19.8123 19.8123 0.38 0.00159268 0.00144558 0.250374 0.223986 50 12858 46 1.21132e+07 4.08187e+06 780512. 3048.87 5.34 0.782082 0.709604 10140 17 3290 6677 2292108 576545 22.6424 22.6424 -1935.34 -22.6424 0 0 1.00276e+06 3917.05 0.17 0.39 0.0816575 0.076216 0.008079 0.347 0.01579 0.6372 + k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 866.83 19.21 227604 129 250.95 -1 -1 101016 -1 -1 1877 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 579976 114 102 29578 29304 1 15659 2145 53 53 2809 clb auto 169.89 221743 42.86 0.28 71.3576 -57618.6 -71.3576 71.3576 21.03 0.0574484 0.0488587 9.1366 6.63697 102 325437 31 1.63647e+08 1.28443e+08 1.86097e+07 6625.03 244.34 31.1239 24.0672 300817 19 61105 238533 36092549 7289219 81.9871 81.9871 -70436.7 -81.9871 -17.3169 -0.29436 2.33362e+07 8307.64 6.87 13.06 4.13199 3.43182 0.1052 0.4073 0.01001 0.5827 + k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.60 0.05 9320 3 0.20 -1 -1 36328 -1 -1 67 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65580 99 130 363 493 1 270 297 12 12 144 clb auto 0.06 718 0.26 0.00 2.05624 -200.755 -2.05624 2.05624 0.18 0.000417629 0.000365052 0.0716246 0.0619868 48 1561 9 5.66058e+06 4.1589e+06 394078. 2736.65 0.47 0.161618 0.143018 1438 11 543 707 50455 15973 2.664 2.664 -236.599 -2.664 0 0 503207. 3494.49 0.08 0.03 0.0145078 0.0133671 0.007874 0.2493 0.0787 0.672 + k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 10.46 0.03 9168 15 0.32 -1 -1 34728 -1 -1 38 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 76044 162 96 999 932 1 689 301 16 16 256 mult_36 auto 0.30 5405 0.59 0.01 19.7682 -1693.3 -19.7682 19.7682 0.39 0.00172524 0.00157701 0.253983 0.227352 48 12726 37 1.21132e+07 4.02797e+06 756778. 2956.16 5.70 0.748289 0.678298 10220 19 3442 6774 2124797 514940 22.553 22.553 -2007.56 -22.553 0 0 968034. 3781.38 0.16 0.37 0.0897037 0.0834903 0.007899 0.3544 0.01649 0.6291 + k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 921.14 19.11 227608 129 252.50 -1 -1 100928 -1 -1 1924 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 580360 114 102 29578 29304 1 16180 2192 53 53 2809 clb auto 159.69 224489 44.48 0.28 71.2744 -56000.3 -71.2744 71.2744 20.60 0.0549514 0.0469312 9.13918 6.65698 100 332884 44 1.63647e+08 1.30976e+08 1.82848e+07 6509.36 313.70 33.5744 26.0789 304020 19 62324 243877 41459064 9020565 81.2603 81.2603 -70341.9 -81.2603 -14.1037 -0.292146 2.30694e+07 8212.69 6.70 14.55 4.23321 3.56935 0.105 0.4083 0.01022 0.5815 + k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 2.78 0.05 9336 3 0.27 -1 -1 36264 -1 -1 67 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65468 99 130 363 493 1 270 297 12 12 144 clb auto 0.06 718 0.26 0.00 2.05624 -200.755 -2.05624 2.05624 0.18 0.000420908 0.000368174 0.0730985 0.0633299 48 1574 8 5.66058e+06 4.1589e+06 394078. 2736.65 0.46 0.161759 0.143247 1431 8 538 704 49349 15661 2.664 2.664 -232.19 -2.664 0 0 503207. 3494.49 0.08 0.02 0.0121469 0.0112471 0.008829 0.222 0.07019 0.7078 + k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 9.37 0.04 9116 15 0.44 -1 -1 34692 -1 -1 38 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 70176 162 96 999 932 1 689 301 16 16 256 mult_36 auto 0.22 5405 0.51 0.01 19.7682 -1693.3 -19.7682 19.7682 0.39 0.00160732 0.0014656 0.218296 0.195461 46 14514 50 1.21132e+07 4.02797e+06 727248. 2840.81 4.57 0.547105 0.496063 10716 20 3769 7590 2200078 535329 22.5606 22.5606 -1929.83 -22.5606 0 0 934704. 3651.19 0.17 0.41 0.0977464 0.0910634 0.00818 0.3412 0.01568 0.6432 + k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 876.67 19.17 227592 129 250.37 -1 -1 100872 -1 -1 1844 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 575120 114 102 29578 29304 1 15488 2112 52 52 2704 clb auto 182.04 218897 48.82 0.34 70.1192 -51431.5 -70.1192 70.1192 19.57 0.0715634 0.061258 11.2038 8.26545 102 319152 33 1.58905e+08 1.26664e+08 1.78867e+07 6614.90 247.52 34.0276 26.4384 293704 19 59621 235362 44721484 9984605 79.8495 79.8495 -65611.6 -79.8495 -12.7907 -0.295467 2.24325e+07 8296.04 6.85 14.55 4.14727 3.46928 0.1049 0.3984 0.01026 0.5913 diff --git a/vtr_flow/tasks/timing_small/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/config.txt old mode 100755 new mode 100644 similarity index 64% rename from vtr_flow/tasks/timing_small/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/config.txt index a46642435e4..7fa2d120cae --- a/vtr_flow/tasks/timing_small/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/config.txt @@ -1,44 +1,45 @@ -# -############################################ +############################################## # Configuration file for running experiments ############################################## +script_params=-power + +cmos_tech_behavior=PTM_45nm/45nm.xml + # Path to directory of circuits to use circuits_dir=benchmarks/verilog # Path to directory of architectures to use -archs_dir=arch/timing +archs_dir=arch/power # Add circuits to list to sweep -#circuit_list_add=bgm.v +circuit_list_add=bgm.v circuit_list_add=blob_merge.v circuit_list_add=boundtop.v circuit_list_add=ch_intrinsics.v circuit_list_add=diffeq1.v circuit_list_add=diffeq2.v -#circuit_list_add=LU8PEEng.v +circuit_list_add=LU8PEEng.v #circuit_list_add=LU32PEEng.v #circuit_list_add=LU64PEEng.v -#circuit_list_add=mcml.v circuit_list_add=mkDelayWorker32B.v circuit_list_add=mkPktMerge.v circuit_list_add=mkSMAdapter4B.v circuit_list_add=or1200.v circuit_list_add=raygentop.v circuit_list_add=sha.v -#circuit_list_add=stereovision0.v -#circuit_list_add=stereovision1.v -#circuit_list_add=stereovision2.v +circuit_list_add=mcml.v +#circuit_list_add=tpu.16x16.int8.v #circuit_list_add=stereovision3.v # Add architectures to list to sweep -arch_list_add=k6_frac_N10_mem32K_40nm.xml +arch_list_add=k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml # Parse info and how to parse -parse_file=vpr_standard.txt +parse_file=vpr_power.txt -# Pass requirements -pass_requirements_file=pass_requirements.txt - -script_params=-lut_size 6 +# How to parse QoR info +qor_parse_file=qor_standard.txt +# Pass requirements +pass_requirements_file=pass_requirements_power.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt new file mode 100644 index 00000000000..393c965070f --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt @@ -0,0 +1,15 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 867.00 22.44 392720 22 456.35 -1 -1 152760 -1 -1 2577 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 695172 257 32 32168 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-2850.16 -9.86001 0 0 5.07014e+06 5633.48 1.14 1.18 0.688574 0.601627 0.0241 0.394 0.04131 0.5647 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 4.66 0.73 46956 2 0.35 -1 -1 37108 -1 -1 84 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66384 114 192 455 647 1 309 390 13 13 169 clb auto 0.07 749 0.36 0.00 1.5681 -199.971 -1.5681 1.5681 0.23 0.000602313 0.000526597 0.10156 0.0887043 38 1909 18 6.63067e+06 4.5271e+06 384612. 2275.81 0.59 0.241964 0.216609 1613 8 646 807 49022 15408 2.13287 2.13287 -254.934 -2.13287 0 0 489150. 2894.38 0.08 0.03 0.0163022 0.0151565 0.006178 0.4297 0.1195 0.4508 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.76 0.05 9320 3 0.20 -1 -1 36188 -1 -1 68 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65168 99 130 363 493 1 256 298 12 12 144 clb auto 0.06 706 0.27 0.00 1.86328 -198.021 -1.86328 1.86328 0.18 0.0004578 0.000403482 0.0740588 0.0639477 46 1510 15 5.66058e+06 4.21279e+06 378970. 2631.74 0.50 0.17219 0.152097 1419 13 512 678 54408 17907 2.4649 2.4649 -230.915 -2.4649 0 0 486261. 3376.82 0.11 0.03 0.0160871 0.0147732 0.00814 0.2379 0.08094 0.6811 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 8.61 0.03 9224 15 0.33 -1 -1 34572 -1 -1 39 162 0 5 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 77360 162 96 999 932 1 698 302 16 16 256 mult_36 auto 0.22 5215 0.63 0.01 20.0279 -1731.76 -20.0279 20.0279 0.47 0.00157608 0.00143934 0.278083 0.247898 50 11710 30 1.21132e+07 4.08187e+06 780512. 3048.87 3.70 0.779349 0.707608 9689 15 2920 5783 1711731 425773 22.9164 22.9164 -1951.82 -22.9164 0 0 1.00276e+06 3917.05 0.20 0.31 0.0749135 0.0702716 0.007591 0.3632 0.01662 0.6202 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq2.v common 7.12 0.03 8328 14 0.24 -1 -1 33584 -1 -1 26 66 0 7 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 70032 66 96 719 590 1 525 195 18 18 324 mult_36 auto 0.16 4839 0.37 0.00 15.5034 -893.993 -15.5034 15.5034 0.53 0.00144263 0.00134169 0.190362 0.173766 50 10126 22 1.57076e+07 4.17324e+06 1.01953e+06 3146.70 2.74 0.568759 0.526111 9219 16 2344 5156 2185950 507264 18.2221 18.2221 -1041.48 -18.2221 0 0 1.31112e+06 4046.65 0.23 0.36 0.0694535 0.0653959 0.009383 0.3437 0.02034 0.6359 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 789.29 21.52 227556 129 251.35 -1 -1 100896 -1 -1 2016 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 591360 114 102 29578 29304 1 16033 2284 54 54 2916 clb auto 22.37 233317 45.57 0.27 70.0908 -60679 -70.0908 70.0908 22.90 0.0537894 0.045836 8.8044 6.54388 104 338815 35 1.70873e+08 1.35934e+08 1.97479e+07 6772.27 307.40 32.3532 25.5337 315352 20 64444 251879 56108125 13858139 81.2538 81.2538 -73871.7 -81.2538 -12.6553 -0.198548 2.50445e+07 8588.64 6.73 20.99 4.16556 3.43053 0.1065 0.4335 0.01057 0.5559 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkDelayWorker32B.v common 66.02 0.81 78884 5 6.89 -1 -1 52424 -1 -1 456 506 47 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 320016 506 553 3285 3838 1 3022 1562 50 50 2500 memory auto 3.03 15018 5.12 0.04 5.96658 -1843.78 -5.96658 5.96658 18.84 0.011865 0.0107543 2.59753 2.3255 38 22736 27 1.47946e+08 5.03323e+07 6.86584e+06 2746.33 13.33 5.73711 5.23719 22040 16 4096 5145 3590122 925407 6.60387 6.60387 -2306.35 -6.60387 -4.22558 -0.295467 8.69095e+06 3476.38 2.47 1.10 0.530714 0.499249 0.1833 0.1385 0.03978 0.8217 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkPktMerge.v common 13.35 0.11 17044 2 0.08 -1 -1 33840 -1 -1 26 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 90676 311 156 972 1128 1 953 508 28 28 784 memory auto 0.36 8591 0.88 0.01 3.97992 -4268.71 -3.97992 3.97992 1.70 0.00251892 0.0021629 0.391523 0.329552 38 14938 15 4.25198e+07 9.62124e+06 2.03942e+06 2601.30 4.95 1.07268 0.9353 13839 16 2583 2995 3100698 901390 4.55746 4.55746 -5261.91 -4.55746 -19.8376 -0.322548 2.58559e+06 3297.95 0.57 0.65 0.116211 0.105436 0.08119 0.1583 0.01766 0.824 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkSMAdapter4B.v common 16.66 0.28 31932 7 2.65 -1 -1 37968 -1 -1 168 193 5 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 84748 193 205 2232 2437 1 1223 571 20 20 400 memory auto 0.75 9324 1.54 0.01 4.44075 -2589.41 -4.44075 4.44075 0.70 0.00303621 0.00237592 0.549264 0.437613 50 17629 34 2.07112e+07 1.17942e+07 1.26944e+06 3173.59 4.89 1.44796 1.21204 15071 15 4684 11657 1041882 233393 4.99386 4.99386 -3047.65 -4.99386 -9.22808 -0.342703 1.63222e+06 4080.54 0.34 0.44 0.227839 0.206644 0.03046 0.2113 0.02596 0.7628 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 68.02 0.59 40880 27 5.07 -1 -1 43988 -1 -1 246 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 120604 385 394 3979 4310 1 2366 1028 27 27 729 io auto 2.04 30806 5.39 0.04 12.8666 -11507.1 -12.8666 12.8666 1.67 0.00796698 0.00700203 2.04343 1.65559 76 52143 50 3.93038e+07 1.47499e+07 3.58343e+06 4915.54 40.94 4.75948 4.0721 45756 15 10811 38343 4397984 935571 14.4395 14.4395 -12847 -14.4395 0 0 4.48127e+06 6147.14 1.09 1.22 0.409397 0.370199 0.02253 0.4559 0.02645 0.5177 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml raygentop.v common 24.33 0.34 33052 8 1.82 -1 -1 40508 -1 -1 135 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 86864 214 305 2625 2741 1 1491 663 22 22 484 mult_36 auto 0.78 12730 1.31 0.01 4.36407 -2392.08 -4.36407 4.36407 0.94 0.00349859 0.00309413 0.437934 0.374035 54 29305 42 2.50602e+07 1.08397e+07 1.67900e+06 3469.01 11.54 1.84401 1.62942 22068 15 6598 15260 3949561 907892 4.97912 4.97912 -3006.33 -4.97912 0 0 2.18083e+06 4505.84 0.43 0.82 0.193884 0.178171 0.02233 0.4743 0.04534 0.4803 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 556.53 0.79 38084 20 530.17 -1 -1 95436 -1 -1 229 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 96576 38 36 3404 3440 1 1277 303 20 20 400 clb auto 1.28 14051 1.42 0.01 11.4453 -4263.51 -11.4453 11.4453 0.70 0.00382206 0.00315702 0.585971 0.425203 58 24122 36 2.07112e+07 1.23417e+07 1.47096e+06 3677.41 10.31 1.94801 1.55296 20434 17 5277 21230 697197 117307 13.441 13.441 -4982 -13.441 0 0 1.87544e+06 4688.60 0.34 0.40 0.257579 0.225983 0.01068 0.3887 0.03202 0.5793 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 10319.98 61.51 954284 75 8539.25 -1 -1 447928 -1 -1 7355 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1930112 36 33 134466 132924 1 42731 7610 102 102 10404 clb auto 63.93 523379 210.79 1.21 58.9597 -331654 -58.9597 58.9597 85.11 0.174684 0.146822 30.3166 22.918 82 733160 42 6.36957e+08 4.94176e+08 5.83608e+07 5609.45 845.06 98.6798 78.332 677500 21 167473 518593 81968438 17553658 64.9338 64.9338 -432445 -64.9338 -0.789768 -0.17036 7.31293e+07 7028.96 21.64 28.03 11.6943 10.0828 0.2977 0.3711 0.0137 0.6152 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/symbiflow/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/symbiflow/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/symbiflow/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/symbiflow/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt new file mode 100644 index 00000000000..0074292af29 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt @@ -0,0 +1,17 @@ +#Refer to Issue #1770 for details. +#regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees + +regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc +regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch +regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch +regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8 +regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters +regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac +regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts +regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores +regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac +regression_tests/vtr_reg_nightly_test1/symbiflow +regression_tests/vtr_reg_nightly_test1/power_extended_arch_list +regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list +regression_tests/vtr_reg_nightly_test1/vpr_ispd + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/config.txt index 940a0f32268..1ab08c71eac 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/config.txt @@ -11,12 +11,12 @@ archs_dir=arch/ispd # Add circuits to list to sweep circuit_list_add=FPGA-example1.blif -circuit_list_add=FPGA-example2.blif -circuit_list_add=FPGA-example3.blif -circuit_list_add=FPGA-example4.blif circuit_list_add=clk_design1.blif circuit_list_add=clk_design2.blif circuit_list_add=clk_design3.blif +circuit_list_add=FPGA-example2.blif +circuit_list_add=FPGA-example3.blif +circuit_list_add=FPGA-example4.blif circuit_list_add=clk_design4.blif circuit_list_add=clk_design5.blif diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/golden_results.txt new file mode 100644 index 00000000000..3d7a2ed394d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/golden_results.txt @@ -0,0 +1,10 @@ + arch circuit script_params vtr_flow_elapsed_time error num_IO num_CLB num_DSP num_BRAM vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time + ultrascale_ispd.xml FPGA-example1.blif common 101.17 72 220 2 2 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 5384092 51 20 3417 3407 1 3287 296 168 480 80640 -1 ultrascale_ispd 4.99 29850 0.81 0.01 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 + ultrascale_ispd.xml clk_design1.blif common 112.15 109 592 2 2 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 5407588 57 20 9969 9959 30 9711 705 168 480 80640 -1 ultrascale_ispd 9.12 67741 3.44 0.02 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 + ultrascale_ispd.xml clk_design2.blif common 389.92 244 5837 10 10 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 5895896 137 60 100115 100025 45 97978 6101 168 480 80640 -1 ultrascale_ispd 93.81 1228924 191.90 1.16 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 + ultrascale_ispd.xml clk_design3.blif common 1917.84 374 22993 50 96 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 7113792 217 120 400080 399454 35 390926 23513 168 480 80640 -1 ultrascale_ispd 249.26 6265294 1541.16 8.85 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 + ultrascale_ispd.xml FPGA-example2.blif common 4286.23 456 39262 200 400 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 7961780 303 150 545542 542692 1 539559 40318 168 480 80640 -1 ultrascale_ispd 821.67 12825040 3322.00 18.04 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 + ultrascale_ispd.xml FPGA-example3.blif common 4014.77 606 30856 200 500 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 7736816 403 200 431203 428403 1 429172 32162 168 480 80640 -1 ultrascale_ispd 626.78 21241641 3250.48 19.45 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 + ultrascale_ispd.xml FPGA-example4.blif common 5719.23 -1 -1 -1 -1 exited with return code 1 v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 6038156 403 200 850587 844787 1 -1 -1 168 480 -1 -1 -1 5701.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + ultrascale_ispd.xml clk_design4.blif common 4013.53 484 39151 150 366 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 8290268 292 150 685438 683387 40 669318 40151 168 480 80640 -1 ultrascale_ispd 443.56 11666561 3417.94 19.26 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 + ultrascale_ispd.xml clk_design5.blif common 6861.38 515 51693 420 885 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 9394248 307 150 948147 942073 56 928185 53513 168 480 80640 -1 ultrascale_ispd 643.52 14614799 6045.16 31.67 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt new file mode 100644 index 00000000000..867c1dab380 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt @@ -0,0 +1,21 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 3.44 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 71968 14 8 926 934 0 489 100 11 11 121 clb auto 0.59 4606 0.32 0.00 4.14102 -29.7523 -4.14102 nan 0.16 0.00110303 0.000853863 0.13314 0.105384 52 7437 24 4.36541e+06 4.20373e+06 379421. 3135.71 1.34 0.463591 0.376734 6938 19 3079 14370 484288 90595 4.83499 nan -34.8915 -4.83499 0 0 499620. 4129.09 0.08 0.16 0.0868834 0.0757929 + k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 5.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 100 38 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 72252 38 3 1113 1116 0 660 141 12 12 144 clb auto 1.06 7385 0.53 0.00 4.95175 -14.4002 -4.95175 nan 0.19 0.00137339 0.00103165 0.1835 0.143426 72 12351 45 5.3894e+06 5.3894e+06 636745. 4421.84 2.00 0.636364 0.516804 11456 17 4645 24063 904212 148872 5.55636 nan -16.3985 -5.55636 0 0 794932. 5520.36 0.12 0.24 0.101648 0.0908761 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.75 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 71844 9 19 897 916 0 559 109 11 11 121 clb auto 1.01 6066 0.46 0.00 4.29231 -70.9295 -4.29231 nan 0.19 0.00115877 0.000891984 0.181013 0.142644 72 10169 35 4.36541e+06 4.36541e+06 523260. 4324.46 1.96 0.660823 0.545616 9121 18 3785 19131 685405 121198 5.08251 nan -82.3409 -5.08251 0 0 653410. 5400.08 0.09 0.19 0.0835726 0.0752013 + k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 5.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 71796 229 197 1364 1561 1 539 497 16 16 256 io auto 0.74 4443 0.81 0.01 2.40107 -604.293 -2.40107 2.40107 0.41 0.0027944 0.00245669 0.283526 0.239774 40 7623 19 1.05632e+07 3.82647e+06 697968. 2726.44 2.04 0.91241 0.805425 7058 12 1744 4785 241404 52708 3.01949 3.01949 -726.043 -3.01949 0 0 870840. 3401.72 0.16 0.12 0.0769539 0.0714275 + k6_frac_N10_40nm.xml clma.pre-vpr.blif common 25.77 -1 -1 -1 -1 -1 -1 -1 -1 -1 306 62 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 109888 62 82 3672 3754 1 2349 450 20 20 400 clb auto 2.88 28739 2.80 0.02 7.33978 -292.565 -7.33978 7.33978 0.78 0.00535795 0.00430039 0.90086 0.625353 92 46890 40 1.74617e+07 1.64916e+07 2.37849e+06 5946.23 14.95 3.7652 2.92496 42225 16 13783 58193 2198678 343498 8.16378 8.16378 -329.46 -8.16378 0 0 3.01539e+06 7538.48 0.57 0.79 0.392962 0.34562 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 4.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 51 256 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66688 256 245 954 1199 0 581 552 18 18 324 io auto 0.24 4989 0.56 0.01 3.37847 -629.355 -3.37847 nan 0.55 0.00165859 0.00148747 0.18154 0.161538 44 8531 14 1.37969e+07 2.74859e+06 970398. 2995.06 1.54 0.600651 0.550646 7969 12 1965 4152 217807 49587 4.23063 nan -775 -4.23063 0 0 1.26150e+06 3893.53 0.25 0.14 0.0814747 0.0769288 + k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 2.98 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 64 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 70048 64 39 1371 1410 1 542 169 11 11 121 clb auto 0.40 3413 0.33 0.00 4.67654 -912.396 -4.67654 4.67654 0.16 0.00112205 0.000934451 0.141238 0.113756 46 6130 26 4.36541e+06 3.557e+06 343362. 2837.71 1.00 0.412951 0.346273 5260 13 1999 5620 169131 35211 5.53977 5.53977 -1090.5 -5.53977 0 0 440296. 3638.81 0.08 0.13 0.0924228 0.0845461 + k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 5.11 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 71668 229 197 1362 1559 1 566 497 16 16 256 io auto 0.67 4793 0.76 0.01 2.51785 -604.704 -2.51785 2.51785 0.44 0.00187093 0.00167223 0.272921 0.229148 46 7938 19 1.05632e+07 3.82647e+06 786978. 3074.13 1.63 0.783703 0.688119 7482 10 1826 4727 234733 52733 3.19583 3.19583 -717 -3.19583 0 0 1.01084e+06 3948.58 0.21 0.11 0.0745403 0.0698473 + k6_frac_N10_40nm.xml elliptic.pre-vpr.blif common 9.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 166 131 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 91456 131 114 3421 3535 1 1164 411 15 15 225 clb auto 2.42 10398 1.17 0.01 6.52628 -3784.19 -6.52628 6.52628 0.45 0.00316671 0.00260468 0.470256 0.34649 62 16689 24 9.10809e+06 8.9464e+06 909814. 4043.62 2.88 1.27953 1.02568 15000 17 4999 21128 713315 123027 7.49463 7.49463 -4392.46 -7.49463 0 0 1.12687e+06 5008.33 0.18 0.35 0.234877 0.205336 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 23.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 97492 10 10 2659 2669 0 1393 308 19 19 361 clb auto 3.05 26140 1.73 0.02 5.75218 -55.7663 -5.75218 nan 0.63 0.00744015 0.0058247 0.578256 0.402009 92 44132 33 1.55754e+07 1.55215e+07 2.13123e+06 5903.67 13.72 2.54972 1.95686 39597 17 9715 60001 2696762 353002 6.60772 nan -63.286 -6.60772 0 0 2.70169e+06 7483.90 0.57 0.87 0.329233 0.29153 + k6_frac_N10_40nm.xml ex5p.pre-vpr.blif common 3.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68544 8 63 761 824 0 435 133 10 10 100 clb auto 0.62 3998 0.34 0.00 3.54271 -155.067 -3.54271 nan 0.15 0.00100409 0.000792216 0.133496 0.105256 62 6550 31 3.44922e+06 3.34143e+06 366588. 3665.88 1.10 0.368646 0.303455 6094 17 2709 12574 426888 79431 4.1719 nan -186.289 -4.1719 0 0 454102. 4541.02 0.07 0.13 0.0655286 0.0591958 + k6_frac_N10_40nm.xml frisc.pre-vpr.blif common 9.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 169 20 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 90640 20 116 3175 3291 1 1278 305 15 15 225 clb auto 1.78 13380 1.19 0.01 7.56455 -3941.67 -7.56455 7.56455 0.33 0.00304637 0.00254392 0.457239 0.344978 76 22460 36 9.10809e+06 9.10809e+06 1.08042e+06 4801.85 3.55 1.33179 1.078 20283 19 6164 25645 1097708 182881 8.69548 8.69548 -4541.25 -8.69548 0 0 1.34805e+06 5991.31 0.23 0.56 0.337532 0.3042 + k6_frac_N10_40nm.xml misex3.pre-vpr.blif common 4.28 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 14 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 70048 14 14 828 842 0 472 100 11 11 121 clb auto 0.78 4472 0.39 0.00 4.02064 -52.776 -4.02064 nan 0.18 0.00137209 0.000987841 0.159545 0.124835 54 7869 46 4.36541e+06 3.88037e+06 393282. 3250.26 1.77 0.686607 0.573602 6576 16 2671 12354 410056 75432 4.89666 nan -62.2285 -4.89666 0 0 511363. 4226.14 0.08 0.17 0.0951289 0.0866438 + k6_frac_N10_40nm.xml pdc.pre-vpr.blif common 19.66 -1 -1 -1 -1 -1 -1 -1 -1 -1 271 16 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 99812 16 40 2839 2879 0 1511 327 19 19 361 clb auto 2.41 23498 1.84 0.01 6.13416 -223.252 -6.13416 nan 0.62 0.00416181 0.00326704 0.62494 0.434793 84 39816 34 1.55754e+07 1.46053e+07 1.95904e+06 5426.71 10.81 2.58351 1.98286 35391 18 8962 48547 1930691 286226 7.01 nan -249.162 -7.01 0 0 2.48734e+06 6890.13 0.53 0.78 0.352337 0.312052 + k6_frac_N10_40nm.xml s298.pre-vpr.blif common 3.06 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 4 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 69864 4 6 726 732 1 380 74 10 10 100 clb auto 0.56 3569 0.31 0.00 5.54077 -44.6464 -5.54077 5.54077 0.15 0.000932039 0.000725018 0.144332 0.114633 50 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Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 103256 38 304 4422 4726 1 2038 569 18 18 324 clb auto 2.16 13449 1.89 0.02 4.16995 -2665.67 -4.16995 4.16995 0.53 0.00511993 0.00362562 0.670431 0.488695 58 23840 35 1.37969e+07 1.22339e+07 1.26150e+06 3893.53 3.58 1.85408 1.46664 20578 14 6433 17363 638387 131973 5.22573 5.22573 -3068.94 -5.22573 0 0 1.60510e+06 4954.00 0.29 0.37 0.278756 0.251954 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.56 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 70788 41 35 1006 1041 0 599 161 12 12 144 clb auto 0.85 6384 0.45 0.00 4.12452 -119.318 -4.12452 nan 0.22 0.00120979 0.000929262 0.152542 0.120736 66 11228 27 5.3894e+06 4.58099e+06 593979. 4124.86 1.79 0.507734 0.413392 10130 18 4219 21318 758361 129163 4.91293 nan -139.398 -4.91293 0 0 735425. 5107.12 0.11 0.20 0.0896483 0.0802677 + k6_frac_N10_40nm.xml spla.pre-vpr.blif common 12.27 -1 -1 -1 -1 -1 -1 -1 -1 -1 213 16 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 89544 16 46 2232 2278 0 1178 275 17 17 289 clb auto 1.81 15813 1.20 0.01 5.56061 -183.389 -5.56061 nan 0.46 0.00321703 0.00232273 0.404551 0.294928 72 27375 40 1.21262e+07 1.14794e+07 1.37091e+06 4743.65 6.17 1.49004 1.16823 24226 19 6729 36115 1420951 217710 6.47301 nan -214.84 -6.47301 0 0 1.71058e+06 5918.98 0.29 0.50 0.237402 0.211617 + k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 2.61 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 52 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 72288 52 122 1461 1583 1 476 237 10 10 100 clb auto 0.41 2412 0.32 0.00 4.20921 -1050.39 -4.20921 4.20921 0.12 0.00111235 0.000945949 0.128769 0.104966 48 4749 25 3.44922e+06 3.39532e+06 287248. 2872.48 0.83 0.437326 0.368397 4022 12 1351 3243 108746 26426 4.95741 4.95741 -1201.15 -4.95741 0 0 366588. 3665.88 0.06 0.08 0.0641406 0.0592094 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt new file mode 100644 index 00000000000..9dfe620405b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt @@ -0,0 +1,9 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time num_fpu + hard_fpu_arch_timing.xml bfly.v common 3.52 0.04 7084 1 0.03 -1 -1 30800 -1 -1 0 193 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 67968 193 64 833 649 1 353 260 24 24 576 io auto 1.73 4892 0.34 0.00 2.985 -1328.73 -2.985 2.985 0.04 0.00144852 0.00132865 0.177888 0.163098 6891 -1 -1 -1 -1 1.06129e+06 103149 1.28794e+06 2236.02 3 2.985 2.985 -1361.67 -2.985 -40.8482 -0.0851 0.43 0.202384 0.186478 0.34 3 + hard_fpu_arch_timing.xml bgm.v common 6.06 0.05 8748 1 0.03 -1 -1 31424 -1 -1 0 257 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 78524 257 32 1281 693 1 788 298 38 38 1444 block_FPU auto 0.55 14344 0.70 0.00 2.985 -3028.35 -2.985 2.985 0.16 0.00303771 0.0028378 0.413442 0.386031 19702 -1 -1 -1 -1 2.90196e+06 309448 3.35777e+06 2325.33 5 2.985 2.985 -3248.97 -2.985 -54.94 -0.0851 2.54 0.475865 0.446046 1.12 9 + hard_fpu_arch_timing.xml dscg.v common 7.53 0.03 7028 1 0.02 -1 -1 30640 -1 -1 0 129 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65924 129 64 769 585 1 513 198 32 32 1024 block_FPU auto 3.94 7523 0.34 0.00 2.985 -1389.44 -2.985 2.985 0.15 0.00139943 0.0012798 0.190532 0.174037 11263 -1 -1 -1 -1 2.063e+06 171916 2.37490e+06 2319.23 4 2.985 2.985 -1536.22 -2.985 -21.8252 -0.0851 1.62 0.218576 0.200755 0.71 5 + hard_fpu_arch_timing.xml fir.v common 34.82 0.04 7436 1 0.03 -1 -1 31112 -1 -1 37 161 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64984 161 32 993 808 1 545 234 30 30 900 block_FPU auto 32.20 6139 0.35 0.00 2.985 -1334.95 -2.985 2.985 0.07 0.00133228 0.00120622 0.178816 0.161419 9043 -1 -1 -1 -1 1.6779e+06 222344 2.03108e+06 2256.75 8 2.985 2.985 -1438.53 -2.985 -39.3898 -0.0851 0.87 0.218407 0.198698 0.60 4 + hard_fpu_arch_timing.xml mm3.v common 2.16 0.02 6592 1 0.01 -1 -1 30420 -1 -1 0 193 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64444 193 32 545 422 1 289 227 21 21 441 io auto 0.91 3334 0.23 0.00 2.985 -795.73 -2.985 2.985 0.03 0.000961119 0.000880146 0.116958 0.106907 4395 -1 -1 -1 -1 809148 68766.3 979092. 2220.16 5 2.985 2.985 -808.623 -2.985 -21.7856 -0.0851 0.26 0.136236 0.125258 0.24 2 + hard_fpu_arch_timing.xml ode.v common 32.26 0.04 7812 1 0.07 -1 -1 34064 -1 -1 151 130 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 69096 130 72 1194 1103 1 589 355 19 19 361 io auto 30.45 4509 0.45 0.00 2.985 -1330.22 -2.985 2.985 0.03 0.00133385 0.001185 0.18753 0.165111 6764 -1 -1 -1 -1 653279 414890 795482. 2203.55 10 2.985 2.985 -1412.7 -2.985 -51.2306 -0.0851 0.46 0.234493 0.208738 0.18 2 + hard_fpu_arch_timing.xml syn2.v common 3.64 0.03 7156 1 0.02 -1 -1 30516 -1 -1 0 161 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63668 161 128 641 490 1 479 293 30 30 900 block_FPU auto 1.09 7529 0.40 0.00 2.985 -1497.01 -2.985 2.985 0.07 0.00160695 0.00149225 0.199129 0.184509 10184 -1 -1 -1 -1 1.6779e+06 137533 2.03108e+06 2256.75 5 2.985 2.985 -1576.57 -2.985 -16.078 -0.0851 0.81 0.231911 0.215941 0.56 4 + hard_fpu_arch_timing.xml syn7.v common 36.71 0.08 9744 1 0.04 -1 -1 32256 -1 -1 0 161 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 120036 161 128 1921 499 1 1697 310 54 54 2916 block_FPU auto 2.40 52707 1.87 0.02 2.985 -8069.08 -2.985 2.985 0.40 0.00742665 0.00695402 1.21809 1.1486 70035 -1 -1 -1 -1 6.08571e+06 722046 6.89978e+06 2366.18 7 2.985 2.985 -8846.29 -2.985 -33.8127 -0.0851 27.77 1.41257 1.3364 2.55 21 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt new file mode 100644 index 00000000000..18d7da6128e --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt @@ -0,0 +1,8 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time + soft_fpu_arch_timing.xml bfly.v common 209.34 3.55 172016 60 98.70 -1 -1 86072 -1 -1 6915 193 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 421132 193 64 24163 24227 1 18280 7172 86 86 7396 clb auto 4.75 224057 69.57 0.48 36.3673 -17014 -36.3673 36.3673 1.30 0.0345782 0.0298013 5.12497 3.72355 373034 -1 -1 -1 -1 1.61728e+07 1.58496e+07 1.77311e+07 2397.39 31 38.4344 38.4344 -18002.8 -38.4344 -53.1016 -0.0851 10.80 8.32891 6.32924 8.04 + soft_fpu_arch_timing.xml bgm.v common 1108.43 22.96 415804 60 672.95 -1 -1 198732 -1 -1 17932 257 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 975984 257 32 61892 61924 1 47401 18221 136 136 18496 clb auto 13.86 624222 315.19 2.01 36.3406 -43484.4 -36.3406 36.3406 4.27 0.0939644 0.0799397 13.4415 10.0182 1010525 -1 -1 -1 -1 4.11556e+07 4.11006e+07 4.47194e+07 2417.79 32 39.2474 39.2474 -46199.2 -39.2474 -78.9829 -0.0851 30.34 22.3465 17.1669 18.65 + soft_fpu_arch_timing.xml dscg.v common 187.68 3.53 172428 60 96.10 -1 -1 85312 -1 -1 6472 129 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 402876 129 64 22456 22520 1 16929 6665 83 83 6889 clb auto 4.20 204966 53.50 0.38 34.9764 -14868.2 -34.9764 34.9764 1.14 0.0309782 0.0263939 4.54343 3.23535 344955 -1 -1 -1 -1 1.50382e+07 1.48343e+07 1.65016e+07 2395.36 34 38.5028 38.5028 -15844.8 -38.5028 -46.6351 -0.0851 10.77 7.72947 5.76568 6.80 + soft_fpu_arch_timing.xml fir.v common 175.32 2.59 152636 60 83.96 -1 -1 81724 -1 -1 6576 161 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 407704 161 32 22750 22782 1 17239 6769 84 84 7056 clb auto 5.28 209929 54.52 0.41 34.2885 -15011.3 -34.2885 34.2885 1.14 0.0331567 0.0285013 4.43226 3.20271 348788 -1 -1 -1 -1 1.54118e+07 1.50726e+07 1.69066e+07 2396.05 31 37.511 37.511 -15968.2 -37.511 -52.5806 -0.0851 10.77 7.55211 5.69191 6.22 + soft_fpu_arch_timing.xml mm3.v common 96.96 1.46 110528 60 40.18 -1 -1 66740 -1 -1 4729 193 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 301096 193 32 16498 16530 1 12703 4954 71 71 5041 clb auto 3.10 145773 31.10 0.24 34.7085 -10616.8 -34.7085 34.7085 0.71 0.0214427 0.0184057 3.09962 2.17903 246911 -1 -1 -1 -1 1.09126e+07 1.08393e+07 1.20254e+07 2385.52 34 37.0018 37.0018 -11230.2 -37.0018 -30.3281 -0.0851 7.60 5.35525 4.01892 4.33 + soft_fpu_arch_timing.xml ode.v common 86.54 1.38 111644 60 33.34 -1 -1 60588 -1 -1 4046 130 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 253596 130 72 14280 14352 1 10655 4248 66 66 4356 clb auto 3.04 123737 29.10 0.21 33.8953 -11304.7 -33.8953 33.8953 0.76 0.0187799 0.015886 2.86835 2.06363 205726 -1 -1 -1 -1 9.38847e+06 9.27387e+06 1.03689e+07 2380.36 33 36.3614 36.3614 -11942.9 -36.3614 -62.9571 -0.0851 6.40 4.89539 3.70307 4.51 + soft_fpu_arch_timing.xml syn2.v common 246.18 3.98 192136 59 118.73 -1 -1 90300 -1 -1 7281 161 -1 -1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 438952 161 128 25307 25435 1 19423 7570 88 88 7744 clb auto 4.92 238655 79.75 0.68 34.6875 -19395.1 -34.6875 34.6875 1.47 0.0501929 0.0436112 5.31494 3.9728 394789 -1 -1 -1 -1 1.69521e+07 1.66885e+07 1.85753e+07 2398.67 41 37.243 37.243 -20432.3 -37.243 -38.0503 -0.0851 16.05 10.5235 8.01329 7.65 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/complex_switch/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/complex_switch/config/config.txt index 194fd4c4983..4d43c00bf52 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/complex_switch/config/config.txt @@ -14,8 +14,6 @@ circuit_list_add=bgm.v circuit_list_add=blob_merge.v circuit_list_add=boundtop.v circuit_list_add=LU8PEEng.v -circuit_list_add=LU32PEEng.v -circuit_list_add=mcml.v circuit_list_add=mkDelayWorker32B.v circuit_list_add=mkSMAdapter4B.v circuit_list_add=or1200.v @@ -24,6 +22,8 @@ circuit_list_add=sha.v circuit_list_add=stereovision0.v circuit_list_add=stereovision1.v circuit_list_add=stereovision2.v +circuit_list_add=LU32PEEng.v +circuit_list_add=mcml.v # Add architectures to list to sweep arch_list_add=k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/complex_switch/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/complex_switch/config/golden_results.txt diff --git a/vtr_flow/tasks/func_multiclock/blanket/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt similarity index 100% rename from vtr_flow/tasks/func_multiclock/blanket/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt diff --git a/vtr_flow/tasks/func_multiclock/blanket/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/func_multiclock/blanket/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt diff --git a/vtr_flow/tasks/func_multiclock/iterative/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt similarity index 100% rename from vtr_flow/tasks/func_multiclock/iterative/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt diff --git a/vtr_flow/tasks/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/func_multiclock/iterative/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt diff --git a/vtr_flow/tasks/multiclock_mcnc/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt similarity index 100% rename from vtr_flow/tasks/multiclock_mcnc/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt new file mode 100644 index 00000000000..dabe58c85d0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt @@ -0,0 +1,11 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml bigkey.blif common 5.28 -1 -1 3 0.34 -1 -1 35056 -1 -1 53 229 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 46028 229 197 1023 1220 1 510 479 16 16 256 io auto 0.21 3413 0.56 0.00 2.1735 -526.299 -2.1735 2.1735 0.39 0.00138821 0.00120378 0.19781 0.168309 40 6116 17 1.05632e+07 2.85638e+06 697968. 2726.44 2.40 0.722292 0.640772 5568 9 1309 2279 135603 31763 2.49868 2.49868 -621.799 -2.49868 0 0 870840. 3401.72 0.16 0.07 0.0510449 0.0478126 +k6_frac_N10_40nm.xml clma.blif common 5.08 -1 -1 7 2.05 -1 -1 39340 -1 -1 77 36 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 32676 36 82 542 624 1 390 195 11 11 121 clb auto 0.35 2039 0.33 0.00 4.11584 -147.948 -4.11584 4.11584 0.15 0.000539492 0.000452693 0.106625 0.0857617 40 4434 24 4.36541e+06 4.14984e+06 303235. 2506.08 1.15 0.303278 0.252285 3724 17 2001 6967 214647 45904 4.75061 4.75061 -182.205 -4.75061 0 0 379421. 3135.71 0.06 0.06 0.0359416 0.0326671 +k6_frac_N10_40nm.xml diffeq.blif common 3.20 -1 -1 8 0.40 -1 -1 34060 -1 -1 51 64 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 34940 64 39 941 980 1 450 154 10 10 100 clb auto 0.42 2664 0.24 0.00 4.29897 -783.884 -4.29897 4.29897 0.12 0.000839617 0.000669735 0.100486 0.0795009 46 5017 28 3.44922e+06 2.74859e+06 276332. 2763.32 1.05 0.326802 0.269909 4217 16 1848 5381 166684 35585 4.95374 4.95374 -932.485 -4.95374 0 0 354105. 3541.05 0.05 0.08 0.0542635 0.0494947 +k6_frac_N10_40nm.xml dsip.blif common 6.16 -1 -1 3 0.30 -1 -1 34940 -1 -1 68 229 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 47348 229 197 1135 1332 1 648 494 16 16 256 io auto 0.53 4829 0.66 0.01 2.11998 -540.899 -2.11998 2.11998 0.39 0.0015698 0.00130015 0.210921 0.176933 36 9346 20 1.05632e+07 3.66479e+06 638738. 2495.07 2.79 0.723593 0.631411 8188 14 2350 5770 322638 68924 2.64997 2.64997 -662.41 -2.64997 0 0 786978. 3074.13 0.15 0.12 0.076965 0.0713829 +k6_frac_N10_40nm.xml elliptic.blif common 10.48 -1 -1 10 1.16 -1 -1 37272 -1 -1 133 131 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 56752 131 114 2471 2585 1 967 378 14 14 196 clb auto 1.84 9009 0.83 0.01 6.26362 -3059.17 -6.26362 6.26362 0.28 0.00212795 0.00173305 0.286733 0.219064 64 15845 47 7.76074e+06 7.1679e+06 810706. 4136.26 4.27 1.22946 1.00099 14220 16 4723 20791 818717 140043 7.05815 7.05815 -3531.55 -7.05815 0 0 1.00880e+06 5146.95 0.16 0.27 0.154401 0.13779 +k6_frac_N10_40nm.xml frisc.blif common 13.84 -1 -1 12 1.91 -1 -1 37256 -1 -1 153 20 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62524 20 116 2477 2593 1 1097 289 15 15 225 clb auto 2.14 12755 0.94 0.01 6.79269 -3257.02 -6.79269 6.79269 0.34 0.00217438 0.00179657 0.327538 0.24583 76 21374 38 9.10809e+06 8.24578e+06 1.08042e+06 4801.85 6.09 1.27911 1.034 19100 16 5620 24310 1037891 171913 8.29693 8.29693 -3979.77 -8.29693 0 0 1.34805e+06 5991.31 0.22 0.35 0.179872 0.160752 +k6_frac_N10_40nm.xml s298.blif common 3.83 -1 -1 8 0.53 -1 -1 34316 -1 -1 62 4 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 34504 4 6 671 677 1 352 72 10 10 100 clb auto 0.56 3591 0.22 0.00 4.75477 -39.1418 -4.75477 4.75477 0.12 0.000769266 0.000586248 0.09084 0.0707559 52 5575 27 3.44922e+06 3.34143e+06 305142. 3051.42 1.47 0.36114 0.295188 5399 17 2374 11722 416659 74881 5.56322 5.56322 -46.7971 -5.56322 0 0 401807. 4018.07 0.06 0.11 0.0543908 0.049368 +k6_frac_N10_40nm.xml s38417.blif common 12.03 -1 -1 6 2.75 -1 -1 42360 -1 -1 177 29 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63792 29 106 3450 3556 1 1202 312 16 16 256 clb auto 1.56 8615 1.15 0.01 3.98518 -2557.22 -3.98518 3.98518 0.39 0.00302166 0.00218012 0.456703 0.332458 46 14847 24 1.05632e+07 9.53924e+06 786978. 3074.13 3.52 1.37805 1.08296 13205 15 5027 16599 520957 107073 4.83175 4.83175 -2954.7 -4.83175 0 0 1.01084e+06 3948.58 0.17 0.30 0.238471 0.215337 +k6_frac_N10_40nm.xml s38584.1.blif common 12.46 -1 -1 6 2.08 -1 -1 40804 -1 -1 194 38 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66920 38 304 3256 3560 1 1587 536 16 16 256 clb auto 1.98 10122 1.65 0.01 3.64177 -2138.5 -3.64177 3.64177 0.40 0.00317473 0.00262755 0.578661 0.434442 58 18006 25 1.05632e+07 1.04554e+07 977637. 3818.90 3.81 1.57474 1.25106 15785 16 5100 13564 505628 106920 4.7203 4.7203 -2481.9 -4.7203 0 0 1.24374e+06 4858.37 0.21 0.26 0.211794 0.191547 +k6_frac_N10_40nm.xml tseng.blif common 2.48 -1 -1 7 0.23 -1 -1 34700 -1 -1 34 52 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 31260 52 122 664 786 1 355 208 8 8 64 io clb auto 0.41 1686 0.21 0.00 3.70214 -536.987 -3.70214 3.70214 0.07 0.000641877 0.000544632 0.0739312 0.060713 58 3324 47 1.94018e+06 1.8324e+06 203254. 3175.84 0.73 0.26935 0.22784 2902 11 1075 2671 103928 28289 4.55633 4.55633 -641.099 -4.55633 0 0 258247. 4035.11 0.04 0.07 0.046514 0.0424413 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh new file mode 100755 index 00000000000..454c7ccc7a1 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh @@ -0,0 +1,29 @@ +#!/bin/bash + +RUN_SCRIPT='/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/scripts/run_vtr_task.py' +PARSE_SCRIPT='/home/ahmadi55/vtr-verilog-to-routing/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py' +check='0' +for top_dir in *;do + if [ -d "$top_dir" ]; then + echo "outer dir: $top_dir" + for inner_dir in $top_dir/*;do + if grep -q "config" <<< "$inner_dir";then + check=1 + break + fi + if grep -q "table_X" <<< "$inner_dir";then + check=1 + continue + fi + echo "$inner_dir" >>~/Desktop/timing_results1.txt + (time $RUN_SCRIPT $inner_dir) >>~/Desktop/run-results_test.txt 2>>~/Desktop/timing_results1_test.txt + + done + echo "$outer_dir" + if [[ "$check" == "1" ]]; then + echo "$top_dir" >>~/Desktop/timing_results1_test.txt + (time $RUN_SCRIPT $top_dir) >>~/Desktop/run-results_test.txt 2>>~/Desktop/timing_results1_test.txt + + fi + fi +done diff --git a/vtr_flow/tasks/func_multiclock/once/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt similarity index 100% rename from vtr_flow/tasks/func_multiclock/once/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt diff --git a/vtr_flow/tasks/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/func_multiclock/once/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt diff --git a/vtr_flow/tasks/func_multiclock/vanilla/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt similarity index 93% rename from vtr_flow/tasks/func_multiclock/vanilla/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt index 36fd176f177..f8a0852037d 100644 --- a/vtr_flow/tasks/func_multiclock/vanilla/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt @@ -1,6 +1,7 @@ ############################################## # Configuration file for running experiments ############################################## + script_params=-use_odin_simulation # Path to directory of circuits to use @@ -24,4 +25,4 @@ parse_file=vpr_standard.txt qor_parse_file=qor_standard.txt # Pass requirements -pass_requirements_file=pass_requirements.txt \ No newline at end of file +pass_requirements_file=pass_requirements.txt diff --git a/vtr_flow/tasks/func_multiclock/vanilla/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/func_multiclock/vanilla/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt new file mode 100644 index 00000000000..2a63a31ba2b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt @@ -0,0 +1,14 @@ +regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer +regression_tests/vtr_reg_nightly_test2/vtr_func_formal +regression_tests/vtr_reg_nightly_test2/vtr_bidir +regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph +regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir +regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch +regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan +regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check +regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff +regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan +regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc +regression_tests/vtr_reg_nightly_test2/titan_other +regression_tests/vtr_reg_nightly_test2/titan_quick_qor + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/config.txt index dce672e8b8c..02b7620d5c4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/config.txt @@ -22,19 +22,6 @@ archs_dir=arch/titan #Largest benchmarks, excluded #circuit_list_add=gaussianblur_stratixiv_arch_timing.blif -#Large benchmarks -circuit_list_add=directrf_stratixiv_arch_timing.blif -circuit_list_add=bitcoin_miner_stratixiv_arch_timing.blif -circuit_list_add=LU230_stratixiv_arch_timing.blif -circuit_list_add=sparcT1_chip2_stratixiv_arch_timing.blif -circuit_list_add=LU_Network_stratixiv_arch_timing.blif - -#Small benchmarks -circuit_list_add=neuron_stratixiv_arch_timing.blif -circuit_list_add=sparcT1_core_stratixiv_arch_timing.blif -circuit_list_add=stereo_vision_stratixiv_arch_timing.blif -circuit_list_add=cholesky_mc_stratixiv_arch_timing.blif - #Mixed order of large and small circuit_list_add=gsm_switch_stratixiv_arch_timing.blif circuit_list_add=mes_noc_stratixiv_arch_timing.blif @@ -50,6 +37,19 @@ circuit_list_add=segmentation_stratixiv_arch_timing.blif circuit_list_add=SLAM_spheric_stratixiv_arch_timing.blif circuit_list_add=des90_stratixiv_arch_timing.blif +#Small benchmarks +circuit_list_add=neuron_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_core_stratixiv_arch_timing.blif +circuit_list_add=stereo_vision_stratixiv_arch_timing.blif +circuit_list_add=cholesky_mc_stratixiv_arch_timing.blif + +#Large benchmarks +circuit_list_add=directrf_stratixiv_arch_timing.blif +circuit_list_add=bitcoin_miner_stratixiv_arch_timing.blif +circuit_list_add=LU230_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_chip2_stratixiv_arch_timing.blif +circuit_list_add=LU_Network_stratixiv_arch_timing.blif + # Add architectures to list to sweep arch_list_add=stratixiv_arch.timing.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt diff --git a/vtr_flow/tasks/timing_chain/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/config.txt similarity index 67% rename from vtr_flow/tasks/timing_chain/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/config.txt index 8b026d7c07e..4d43c00bf52 100644 --- a/vtr_flow/tasks/timing_chain/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/config.txt @@ -7,22 +7,14 @@ circuits_dir=benchmarks/verilog # Path to directory of architectures to use -archs_dir=arch/timing +archs_dir=arch/complex_switch # Add circuits to list to sweep -circuit_list_add=arm_core.v circuit_list_add=bgm.v circuit_list_add=blob_merge.v circuit_list_add=boundtop.v -circuit_list_add=ch_intrinsics.v -circuit_list_add=diffeq1.v -circuit_list_add=diffeq2.v circuit_list_add=LU8PEEng.v -circuit_list_add=LU32PEEng.v -#circuit_list_add=LU64PEEng.v -circuit_list_add=mcml.v circuit_list_add=mkDelayWorker32B.v -circuit_list_add=mkPktMerge.v circuit_list_add=mkSMAdapter4B.v circuit_list_add=or1200.v circuit_list_add=raygentop.v @@ -30,16 +22,20 @@ circuit_list_add=sha.v circuit_list_add=stereovision0.v circuit_list_add=stereovision1.v circuit_list_add=stereovision2.v -circuit_list_add=stereovision3.v +circuit_list_add=LU32PEEng.v +circuit_list_add=mcml.v # Add architectures to list to sweep -arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml +arch_list_add=k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml # Parse info and how to parse -parse_file=vpr_chain.txt +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_fixed_chan_width.txt # Pass requirements -pass_requirements_file=pass_requirements_chain.txt +pass_requirements_file=pass_requirements_fixed_chan_width.txt -script_params=-lut_size 6 +script_params=-track_memory_usage --route_chan_width 200 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt new file mode 100644 index 00000000000..6ca50b206f7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt @@ -0,0 +1,15 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml bgm.v common 771.69 20.24 392552 33 440.50 -1 -1 152620 -1 -1 5518 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 848880 257 32 44336 43851 1 42630 5818 80 80 6400 clb auto 8.01 380622 169.43 1.19 11.7092 -17497.4 -11.7092 11.7092 1.71 0.0884606 0.0650463 10.8219 7.9193 629302 -1 -1 -1 -1 3.53436e+07 2.2827e+07 7.29424e+07 11397.2 22 13.5217 13.5217 -20134.9 -13.5217 0 0 34.01 16.0006 12.1513 68.04 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml blob_merge.v common 112.77 0.46 59268 29 71.86 -1 -1 67792 -1 -1 1320 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 235260 36 100 10431 10531 1 9865 1456 41 41 1681 clb auto 1.25 86784 13.51 0.10 8.5404 -2112.82 -8.5404 8.5404 0.35 0.0158736 0.0138493 2.41144 1.78231 133541 -1 -1 -1 -1 8.95136e+06 5.148e+06 1.84779e+07 10992.2 17 9.80674 9.80674 -2510.99 -9.80674 0 0 4.16 3.39286 2.6091 13.69 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml boundtop.v common 3.66 0.68 46848 3 0.36 -1 -1 37188 -1 -1 95 114 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 67744 114 192 467 659 1 374 401 13 13 169 clb auto 0.04 939 0.40 0.00 0.936379 -133.58 -0.936379 0.936379 0.01 0.000594977 0.000532766 0.098618 0.0869176 1418 -1 -1 -1 -1 666600 370500 1.59550e+06 9440.85 10 1.2773 1.2773 -158.922 -1.2773 0 0 0.05 0.115571 0.102519 0.59 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU8PEEng.v common 566.38 18.49 226892 206 237.61 -1 -1 99564 -1 -1 4460 114 83 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 874692 114 102 38946 38672 1 36247 4767 86 86 7396 memory auto 7.46 361378 138.53 0.85 64.8355 -42040.9 -64.8355 64.8355 2.10 0.0691949 0.058838 11.7896 8.69223 512938 -1 -1 -1 -1 4.18276e+07 2.52125e+07 8.44414e+07 11417.2 22 72.5688 72.5688 -74126.1 -72.5688 -91.783 -0.36083 52.67 16.6473 12.5492 81.25 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkDelayWorker32B.v common 103.59 0.85 78184 6 7.33 -1 -1 52456 -1 -1 556 506 80 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 584556 506 553 3331 3884 1 3325 1695 82 82 6724 memory auto 1.27 19665 5.42 0.03 5.41315 -1403.25 -5.41315 5.41315 1.74 0.0117211 0.0106427 2.59157 2.32237 22244 -1 -1 -1 -1 3.85878e+07 8.78824e+06 7.66484e+07 11399.2 22 5.80412 5.80412 -1685.69 -5.80412 -22.0148 -0.295672 2.05 3.23264 2.91985 69.61 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkSMAdapter4B.v common 23.03 0.25 31836 11 2.59 -1 -1 37612 -1 -1 290 193 10 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 144644 193 205 2764 2969 1 2139 698 37 37 1369 memory auto 0.35 15446 2.92 0.02 3.89872 -2235.27 -3.89872 3.89872 0.25 0.00337253 0.00287862 0.74301 0.58971 23806 -1 -1 -1 -1 7.45627e+06 1.95848e+06 1.49196e+07 10898.2 17 4.18699 4.18699 -2538.95 -4.18699 -21.4015 -0.375057 1.04 0.930111 0.754237 11.96 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml or1200.v common 23.89 0.51 40752 45 4.81 -1 -1 43800 -1 -1 537 385 4 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 124740 385 394 5238 5569 1 4569 1321 27 27 729 io clb auto 0.76 44444 6.09 0.05 12.7514 -9719.77 -12.7514 12.7514 0.12 0.00857623 0.00773889 1.35067 1.06773 64764 -1 -1 -1 -1 4.06709e+06 2.54409e+06 7.75339e+06 10635.7 18 13.7756 13.7756 -11602 -13.7756 0 0 2.19 1.81771 1.48902 5.94 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 13.70 0.39 32764 12 1.53 -1 -1 37312 -1 -1 238 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 103668 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 0.39 16418 1.91 0.02 3.92422 -1914.18 -3.92422 3.92422 0.10 0.00342281 0.00303294 0.462853 0.392242 24730 -1 -1 -1 -1 3.88769e+06 1.9974e+06 7.17610e+06 10615.5 17 4.06116 4.06116 -2255.58 -4.06116 0 0 1.55 0.651302 0.564926 5.24 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml sha.v common 488.98 0.94 38088 31 474.19 -1 -1 95480 -1 -1 415 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 95616 38 36 4183 4219 1 3300 489 24 24 576 clb auto 0.50 25354 2.63 0.02 9.82213 -3175.08 -9.82213 9.82213 0.08 0.0050131 0.00345827 0.628781 0.44583 42061 -1 -1 -1 -1 2.72374e+06 1.6185e+06 6.03346e+06 10474.8 21 11.2064 11.2064 -3705.85 -11.2064 0 0 1.38 0.920023 0.691661 3.63 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision0.v common 152.42 1.63 121828 7 97.58 -1 -1 75204 -1 -1 1804 157 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 340568 157 197 22240 22437 1 13748 2158 47 47 2209 clb auto 2.06 84220 16.98 0.13 2.22026 -8656.91 -2.22026 2.22026 0.48 0.0191037 0.0160881 2.79218 2.11565 117937 -1 -1 -1 -1 1.16296e+07 7.0356e+06 2.45588e+07 11117.6 20 2.72481 2.72481 -10955.7 -2.72481 0 0 4.12 4.11575 3.25302 19.70 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision1.v common 141.02 2.33 108996 10 55.12 -1 -1 78708 -1 -1 1727 113 0 44 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 480632 113 145 23279 21144 1 16131 2029 62 62 3844 mult_36 auto 2.47 135603 19.55 0.15 4.15694 -16481.2 -4.15694 4.15694 0.88 0.0213202 0.0181428 3.16265 2.42147 178625 -1 -1 -1 -1 2.17057e+07 1.19625e+07 4.33614e+07 11280.3 14 4.46736 4.46736 -20025.7 -4.46736 0 0 9.64 4.2939 3.4091 37.10 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision2.v common 1003.65 2.70 163904 26 344.30 -1 -1 188664 -1 -1 5847 149 0 324 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 2591312 149 182 65520 55100 1 55662 6502 166 166 27556 mult_36 auto 10.40 721467 179.24 1.19 13.2018 -50280.1 -13.2018 13.2018 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12904 36 318 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 3031436 36 33 149539 147997 1 103102 13318 169 169 28561 memory auto 30.81 1295530 594.14 3.44 55.8928 -206808 -55.8928 55.8928 11.53 0.211047 0.178323 35.255 27.2243 1245163 -1 -1 -1 -1 1.64515e+08 7.98601e+07 3.31299e+08 11599.7 23 60.1743 60.1743 -330799 -60.1743 -0.4572 -0.188293 76.96 48.8242 38.3795 361.41 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt new file mode 100644 index 00000000000..5a58cab89f2 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt @@ -0,0 +1,7 @@ +regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain +regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop +regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off +regression_tests/vtr_reg_nightly_test3/vtr_reg_qor +regression_tests/vtr_reg_nightly_test3/complex_switch + + diff --git a/vtr_flow/tasks/timing/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/config.txt similarity index 95% rename from vtr_flow/tasks/timing/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/config.txt index d5b3985d02a..59f086f1d79 100644 --- a/vtr_flow/tasks/timing/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/config.txt @@ -17,10 +17,7 @@ circuit_list_add=boundtop.v circuit_list_add=ch_intrinsics.v circuit_list_add=diffeq1.v circuit_list_add=diffeq2.v -circuit_list_add=LU8PEEng.v -circuit_list_add=LU32PEEng.v #circuit_list_add=LU64PEEng.v -circuit_list_add=mcml.v circuit_list_add=mkDelayWorker32B.v circuit_list_add=mkPktMerge.v circuit_list_add=mkSMAdapter4B.v @@ -31,6 +28,9 @@ circuit_list_add=stereovision0.v circuit_list_add=stereovision1.v circuit_list_add=stereovision2.v circuit_list_add=stereovision3.v +circuit_list_add=LU8PEEng.v +circuit_list_add=LU32PEEng.v +circuit_list_add=mcml.v # Add architectures to list to sweep arch_list_add=k6_frac_N10_mem32K_40nm.xml @@ -38,6 +38,9 @@ arch_list_add=k6_frac_N10_mem32K_40nm.xml # Parse info and how to parse parse_file=vpr_chain.txt +# How to parse QoR info +qor_parse_file=qor_standard.txt + # Pass requirements pass_requirements_file=pass_requirements_chain.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt new file mode 100644 index 00000000000..f1f228d55d4 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt @@ -0,0 +1,21 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total 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v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66528 114 192 455 647 1 312 388 13 13 169 clb auto 0.10 758 0.34 0.00 1.70835 -203.113 -1.70835 1.70835 0.22 0.000587763 0.000521508 0.0974554 0.0855581 36 2211 20 6.63067e+06 4.41931e+06 367804. 2176.36 0.63 0.267535 0.240387 1762 13 705 924 61330 17686 2.27648 2.27648 -247.759 -2.27648 0 0 456028. 2698.39 0.08 0.04 0.0224819 0.020933 181 175 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.14 0.05 9352 3 0.18 -1 -1 36176 -1 -1 65 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 67784 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 605 0.25 0.00 2.08915 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k6_frac_N10_mem32K_40nm.xml diffeq2.v common 7.21 0.03 8272 14 0.22 -1 -1 33504 -1 -1 29 66 0 7 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 70372 66 96 719 590 1 525 198 18 18 324 mult_36 auto 0.20 4790 0.42 0.00 15.3213 -871.24 -15.3213 15.3213 0.53 0.00142258 0.00131792 0.213241 0.194395 38 11682 25 1.57076e+07 4.33493e+06 803540. 2480.06 3.62 0.608828 0.560131 9918 19 2890 6341 2431166 578423 18.1641 18.1641 -1024.59 -18.1641 0 0 1.01953e+06 3146.70 0.24 0.54 0.122003 0.115066 246 323 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml mkDelayWorker32B.v common 59.22 0.83 78924 5 6.63 -1 -1 52444 -1 -1 456 506 47 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 319148 506 553 3285 3838 1 3022 1562 50 50 2500 memory auto 2.96 13844 5.04 0.03 5.95267 -1737.1 -5.95267 5.95267 17.66 0.0118126 0.0103652 2.55061 2.28117 38 21834 15 1.47946e+08 5.03323e+07 6.86584e+06 2746.33 12.72 5.35924 4.88777 20620 16 4027 5047 3622996 886535 6.85724 6.85724 -2206.18 -6.85724 -7.78106 -0.293253 8.69095e+06 3476.38 2.35 1.11 0.541692 0.509102 1053 407 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml mkPktMerge.v common 10.90 0.10 17112 2 0.07 -1 -1 33768 -1 -1 27 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 91464 311 156 972 1128 1 953 509 28 28 784 memory auto 0.35 7827 0.88 0.01 3.90797 -4026.08 -3.90797 3.90797 1.69 0.00260608 0.00221904 0.376442 0.316511 36 14479 14 4.25198e+07 9.67514e+06 1.94918e+06 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-1 254 385 2 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 108276 385 394 3979 4310 1 2380 1036 27 27 729 io auto 2.79 32239 3.72 0.03 13.0151 -11494.2 -13.0151 13.0151 1.60 0.00722842 0.00641284 1.18302 0.977425 76 53278 33 3.93038e+07 1.51811e+07 3.58343e+06 4915.54 25.09 3.43543 2.98034 47028 16 10623 38195 3911075 744236 14.7237 14.7237 -13187.9 -14.7237 0 0 4.48127e+06 6147.14 1.00 1.08 0.419843 0.385341 2290 2782 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml raygentop.v common 19.26 0.34 32992 8 1.39 -1 -1 40580 -1 -1 104 214 0 9 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 89292 214 305 2625 2741 1 1440 632 22 22 484 mult_36 auto 1.55 11858 1.26 0.01 4.2149 -2326.88 -4.2149 4.2149 0.90 0.00320048 0.00282062 0.449556 0.38649 50 27613 37 2.50602e+07 9.16898e+06 1.56759e+06 3238.82 9.84 1.41439 1.24776 21526 18 6421 14585 3598061 779432 4.73537 4.73537 -3011.83 -4.73537 0 0 2.01671e+06 4166.75 0.38 0.67 0.197503 0.182965 907 1153 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml sha.v common 509.88 0.74 38160 20 489.55 -1 -1 95376 -1 -1 208 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 99132 38 36 3404 3440 1 1290 282 19 19 361 clb auto 1.70 13833 1.29 0.01 11.3756 -4060.62 -11.3756 11.3756 0.61 0.00378694 0.00319439 0.530398 0.396903 56 23225 39 1.72706e+07 1.121e+07 1.27879e+06 3542.35 9.01 1.89694 1.53034 20487 17 5327 19874 693200 118538 13.9599 13.9599 -4596.68 -13.9599 0 0 1.63234e+06 4521.70 0.28 0.39 0.267423 0.237982 2026 2480 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision0.v common 140.84 1.50 122064 5 92.52 -1 -1 75212 -1 -1 744 157 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 247784 157 197 21024 21221 1 6987 1098 34 34 1156 clb auto 6.49 46419 6.37 0.05 2.82568 -12604 -2.82568 2.82568 2.67 0.0165799 0.0134665 2.54385 1.92206 52 73212 43 6.50233e+07 4.00974e+07 4.04437e+06 3498.59 17.38 7.95666 6.35335 65366 14 19246 32302 1362296 259411 3.20194 3.20194 -14793.7 -3.20194 0 0 5.32397e+06 4605.51 1.22 1.23 1.09056 0.984477 6997 9532 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision1.v common 180.82 2.16 109124 6 54.89 -1 -1 78740 -1 -1 761 113 0 44 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 307052 113 145 21818 19683 1 9787 1063 40 40 1600 mult_36 auto 7.48 85270 8.77 0.07 5.22041 -22246.3 -5.22041 5.22041 3.87 0.0210482 0.0152255 3.16878 2.35576 80 133607 44 9.16046e+07 5.84383e+07 8.41679e+06 5260.49 80.59 11.7169 9.44018 121434 14 30149 50085 21046263 4281969 5.57068 5.57068 -25174.1 -5.57068 0 0 1.06125e+07 6632.80 3.20 4.66 1.28018 1.14993 7407 9170 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision2.v common 897.38 2.29 163944 17 365.23 -1 -1 188704 -1 -1 2285 149 0 324 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1517848 149 182 57159 46739 1 35655 2940 104 104 10816 mult_36 auto 27.76 451074 64.50 0.34 17.6426 -61785.4 -17.6426 17.6426 92.84 0.100465 0.0794607 14.3589 11.5035 70 613267 31 6.67561e+08 2.51439e+08 5.35869e+07 4954.41 245.65 37.6616 31.3652 571390 14 120311 203530 42045578 8585896 19.4369 19.4369 -72495.7 -19.4369 0 0 6.74310e+07 6234.38 21.69 12.60 4.9889 4.47075 21927 28492 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision3.v common 1.56 0.06 9696 4 0.10 -1 -1 33008 -1 -1 13 11 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64440 11 30 262 292 2 110 54 7 7 49 clb auto 0.09 348 0.06 0.00 2.24517 -154.275 -2.24517 2.08568 0.04 0.000309725 0.000253058 0.0364888 0.0291824 30 985 35 1.07788e+06 700622 77118.5 1573.85 0.32 0.130356 0.106775 718 11 379 582 25764 8842 2.56549 2.31105 -184.613 -2.56549 0 0 95414.1 1947.23 0.01 0.02 0.0142156 0.0127868 100 149 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml LU8PEEng.v common 701.75 19.08 227572 129 250.46 -1 -1 100908 -1 -1 2010 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 582060 114 102 29578 29304 1 15347 2278 54 54 2916 clb auto 28.05 221461 35.17 0.24 71.8736 -53930.2 -71.8736 71.8736 19.22 0.0531899 0.0448971 8.1004 5.97275 92 336935 48 1.70873e+08 1.35611e+08 1.77525e+07 6087.96 302.42 30.7472 23.9288 303826 18 61022 244114 36691481 7210279 81.5132 81.5132 -67282.9 -81.5132 -13.076 -0.172573 2.25674e+07 7739.16 6.59 11.19 3.88633 3.25067 18822 21469 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml LU32PEEng.v common 6591.72 171.14 770456 128 1295.71 -1 -1 298652 -1 -1 7148 114 167 32 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1935556 114 102 102506 101104 1 53933 7563 100 100 10000 clb auto 111.89 1071446 402.64 2.22 70.431 -335083 -70.431 70.431 84.33 0.244124 0.205221 38.6299 29.1065 130 1413041 49 6.13558e+08 4.89384e+08 8.42269e+07 8422.69 4276.21 123.739 97.1904 1339131 17 201056 864744 264365622 66736099 80.9022 80.9022 -471894 -80.9022 -18.7674 -0.174787 1.06720e+08 10672.0 39.10 93.87 15.3636 12.9703 67544 75921 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml mcml.v common 9471.77 58.17 954224 75 8089.65 -1 -1 447736 -1 -1 5471 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1777584 36 33 134466 132924 1 39621 5726 92 92 8464 memory auto 60.91 461290 211.90 1.43 59.9576 -267814 -59.9576 59.9576 72.62 0.241895 0.199789 35.8385 27.4086 86 665760 47 5.19428e+08 3.92651e+08 4.94424e+07 5841.49 818.94 123.573 99.3805 621808 20 143897 442932 81621596 18954953 65.7645 65.7645 -385403 -65.7645 -0.298423 -0.0270824 6.25744e+07 7393.01 17.11 28.95 14.0116 12.2481 52921 82783 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/config.txt index e69c169c2ed..a95d6d618c4 100755 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/config.txt @@ -17,9 +17,6 @@ circuit_list_add=boundtop.v circuit_list_add=ch_intrinsics.v circuit_list_add=diffeq1.v circuit_list_add=diffeq2.v -circuit_list_add=LU8PEEng.v -circuit_list_add=LU32PEEng.v -circuit_list_add=mcml.v circuit_list_add=mkDelayWorker32B.v circuit_list_add=mkPktMerge.v circuit_list_add=mkSMAdapter4B.v @@ -31,6 +28,9 @@ circuit_list_add=stereovision0.v circuit_list_add=stereovision1.v circuit_list_add=stereovision2.v circuit_list_add=stereovision3.v +circuit_list_add=LU8PEEng.v +circuit_list_add=LU32PEEng.v +circuit_list_add=mcml.v # Add architectures to list to sweep arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt new file mode 100644 index 00000000000..924fa1896a7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt @@ -0,0 +1,22 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 262.46 1.47 127248 18 72.96 -1 -1 66864 -1 -1 1008 133 24 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 316396 133 179 18339 18121 1 9040 1344 39 39 1521 clb auto 21.70 138925 15.95 0.10 17.3291 -132913 -17.3291 17.3291 3.86 0.0288542 0.0238943 4.81648 3.51316 106 195650 27 8.65315e+07 6.74784e+07 1.02794e+07 6758.33 97.84 16.215 12.6909 182348 15 34912 125847 27216363 6482638 19.2483 19.2483 -152788 -19.2483 0 0 1.30215e+07 8561.12 3.42 7.08 1.92621 1.67433 + k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 598.74 13.19 388948 15 242.79 -1 -1 147364 -1 -1 2712 257 0 11 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 758148 257 32 35908 33296 1 19534 3012 63 63 3969 clb auto 56.01 255913 65.48 0.43 18.1917 -23818.8 -18.1917 18.1917 30.40 0.0630532 0.0540353 9.80952 7.11497 80 392154 29 2.36641e+08 1.50518e+08 2.15027e+07 5417.67 132.15 34.8362 26.9502 366453 20 88192 390830 20471535 3157944 20.5117 20.5117 -26441.9 -20.5117 0 0 2.71248e+07 6834.16 7.42 9.28 4.96389 4.28045 + k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 98.46 0.44 55336 5 41.42 -1 -1 59452 -1 -1 619 36 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 187724 36 100 14037 11284 1 3230 755 31 31 961 clb auto 14.20 45897 5.99 0.04 13.3428 -2596.7 -13.3428 13.3428 2.24 0.0138176 0.0114936 2.28377 1.65722 60 76713 48 5.14688e+07 3.33604e+07 3.85800e+06 4014.56 22.54 5.92607 4.56216 66475 13 12384 59651 2545727 332961 15.3759 15.3759 -2979.2 -15.3759 0 0 4.86014e+06 5057.38 0.94 1.19 0.781403 0.676632 + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 5.56 0.50 45120 3 0.40 -1 -1 37732 -1 -1 93 142 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 73404 142 192 1069 1139 1 566 427 14 14 196 clb auto 0.63 1719 0.64 0.00 2.89823 -451.929 -2.89823 2.89823 0.28 0.00110834 0.000980132 0.223991 0.195133 38 3929 16 9.20055e+06 5.01214e+06 467348. 2384.43 0.90 0.490064 0.435151 3370 10 1156 1738 87127 23536 3.536 3.536 -547.719 -3.536 0 0 593372. 3027.41 0.10 0.06 0.0450392 0.0423867 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.49 0.05 9360 3 0.28 -1 -1 36172 -1 -1 65 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66604 99 130 363 493 1 251 295 12 12 144 clb auto 0.17 617 0.28 0.00 2.00545 -202.179 -2.00545 2.00545 0.21 0.000424589 0.000371396 0.0800614 0.069436 46 1412 9 5.66058e+06 4.05111e+06 378966. 2631.71 0.47 0.175151 0.155279 1261 9 529 668 43396 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a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt new file mode 100644 index 00000000000..495d3b05744 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt @@ -0,0 +1,22 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time 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2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1882036 149 182 65737 42630 1 35973 2302 104 104 10816 mult_36 auto 25.74 330013 49.95 0.29 14.5277 -60838.7 -14.5277 14.5277 109.17 0.0710758 0.0628898 12.6533 10.3349 80 478178 22 6.67561e+08 2.17062e+08 6.43241e+07 5947.13 235.17 39.8139 33.4269 446994 18 117664 142709 36786595 7674733 16.6813 16.6813 -72795.8 -16.6813 0 0 8.07606e+07 7466.78 25.10 10.53 4.4168 3.91473 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision3.v common 1.48 0.05 9784 5 0.11 -1 -1 33036 -1 -1 15 11 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 67176 11 30 313 321 2 108 56 7 7 49 clb auto 0.14 395 0.08 0.00 2.36605 -152.494 -2.36605 1.9999 0.04 0.000358432 0.000292409 0.0463688 0.0376352 30 1169 31 1.07788e+06 808410 84241.2 1719.21 0.20 0.107548 0.0891058 944 17 532 1516 56407 21898 3.07845 2.37233 -183.444 -3.07845 0 0 103128. 2104.65 0.01 0.03 0.020892 0.0188297 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_large/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_large/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_large/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_large/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt new file mode 100644 index 00000000000..aa9fe3d89b2 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt @@ -0,0 +1,22 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 269.81 1.48 127116 18 68.27 -1 -1 66568 -1 -1 1008 133 24 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 351672 133 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betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 73516 142 192 1069 1139 1 566 427 14 14 196 clb auto 0.63 1719 0.57 0.00 2.89823 -451.929 -2.89823 2.89823 0.28 0.00109467 0.000972948 0.195215 0.170313 38 3929 16 9.20055e+06 5.01214e+06 467348. 2384.43 1.64 0.54282 0.483482 3370 10 1156 1738 87127 23536 3.536 3.536 -547.719 -3.536 0 0 593372. 3027.41 0.10 0.06 0.0461998 0.0434643 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.22 0.05 9432 3 0.19 -1 -1 36200 -1 -1 65 99 1 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66664 99 130 363 493 1 251 295 12 12 144 clb auto 0.13 617 0.25 0.00 2.00545 -202.179 -2.00545 2.00545 0.18 0.000428766 0.000375707 0.0721075 0.0625634 46 1412 9 5.66058e+06 4.05111e+06 378966. 2631.71 0.42 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7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 72192 66 96 866 607 1 547 189 18 18 324 mult_36 auto 0.35 4560 0.41 0.00 12.009 -735.792 -12.009 12.009 0.52 0.0014174 0.00132161 0.204848 0.188121 60 9415 21 1.57076e+07 3.84988e+06 1.22123e+06 3769.23 5.88 0.687682 0.638521 8603 17 2397 4657 1890034 439154 13.181 13.181 -845.871 -13.181 0 0 1.53789e+06 4746.57 0.26 0.30 0.0693529 0.0657309 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 479.27 7.49 218888 100 85.94 -1 -1 103964 -1 -1 2180 114 44 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 688176 114 102 38208 33849 1 17938 2448 57 57 3249 clb auto 67.56 239395 71.22 0.50 66.5755 -50925.9 -66.5755 66.5755 24.28 0.100265 0.0839475 14.2333 10.5167 92 361512 48 1.92089e+08 1.44771e+08 1.98119e+07 6097.84 167.92 39.0305 29.9848 328109 23 72468 273398 39855950 8187728 75.3499 75.3499 -63032 -75.3499 0 0 2.51903e+07 7753.25 6.70 13.57 5.43985 4.49789 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 3460.88 81.65 746632 102 807.97 -1 -1 358852 -1 -1 7495 114 167 32 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 2381312 114 102 124755 111050 1 59278 7910 102 102 10404 clb auto 217.77 1072406 485.23 2.74 67.6126 -342686 -67.6126 67.6126 92.31 0.258025 0.214171 43.9533 32.1826 128 1405319 39 6.36957e+08 5.08087e+08 8.68880e+07 8351.40 1524.24 198.521 153.641 1350075 21 217881 912992 253789873 63051185 76.337 76.337 -476260 -76.337 0 0 1.09718e+08 10545.7 33.11 91.44 18.9702 15.7474 + k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5064.63 57.54 928552 25 3403.75 -1 -1 373104 -1 -1 7078 36 159 27 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 2394848 36 33 190540 166259 1 61618 7333 99 99 9801 clb auto 219.72 718258 618.26 3.00 42.0812 -275832 -42.0812 42.0812 86.36 0.23051 0.192622 48.7536 36.0398 138 951582 21 6.00857e+08 4.79252e+08 8.73468e+07 8912.03 457.91 154.37 119.977 917221 22 225274 574203 91930691 20227411 45.1932 45.1932 -346416 -45.1932 0 0 1.11488e+08 11375.2 43.80 41.12 18.3494 15.6474 + k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 76.58 0.79 78332 5 5.90 -1 -1 53132 -1 -1 456 506 45 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 335340 506 553 3519 4017 1 3099 1560 50 50 2500 memory auto 4.49 15041 4.80 0.04 6.68635 -1894.57 -6.68635 6.68635 18.16 0.0114787 0.0103772 2.43774 2.17687 38 23149 16 1.47946e+08 4.92362e+07 6.86579e+06 2746.32 28.48 5.92539 5.40792 22207 14 4233 5386 3331744 828056 7.52959 7.52959 -2298.71 -7.52959 0 0 8.69102e+06 3476.41 2.30 1.00 0.522626 0.494679 + k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 11.81 0.11 17348 2 0.07 -1 -1 33996 -1 -1 29 311 15 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 94692 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.48 8138 0.84 0.01 3.74116 -4094.6 -3.74116 3.74116 1.58 0.00247621 0.00212405 0.376246 0.316773 36 14917 17 4.25198e+07 9.78293e+06 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v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 118512 385 394 4649 4513 1 2409 1035 27 27 729 io auto 6.90 30379 4.46 0.04 8.13796 -9652.08 -8.13796 8.13796 1.52 0.00778595 0.0069791 1.38242 1.11181 88 45660 42 3.93038e+07 1.51272e+07 4.08947e+06 5609.70 160.25 6.5954 5.6945 42817 18 10128 34970 3224301 629152 8.72434 8.72434 -10837.7 -8.72434 0 0 5.12776e+06 7033.96 1.15 1.02 0.473228 0.433429 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 16.26 0.34 32004 3 0.90 -1 -1 40236 -1 -1 111 214 0 8 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 94072 214 305 2963 2869 1 1440 638 19 19 361 io auto 2.17 11058 1.30 0.01 4.28804 -2547.99 -4.28804 4.28804 0.59 0.00347113 0.00307978 0.466541 0.400197 58 23745 38 1.72706e+07 9.15023e+06 1.32779e+06 3678.09 7.20 1.56228 1.37605 19546 16 5825 13540 3597927 808321 4.87643 4.87643 -2976.1 -4.87643 0 0 1.69263e+06 4688.74 0.30 0.67 0.195534 0.18203 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 254.32 0.74 37996 3 235.25 -1 -1 95040 -1 -1 156 38 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 93376 38 36 2995 2744 1 1210 230 17 17 289 clb auto 2.15 11099 1.21 0.01 8.60024 -2289.89 -8.60024 8.60024 0.57 0.00286613 0.00243424 0.504352 0.391189 66 16854 22 1.34605e+07 8.40746e+06 1.18400e+06 4096.89 8.69 2.16811 1.76894 15692 22 4746 12707 469422 81010 9.99242 9.99242 -2671.82 -9.99242 0 0 1.47169e+06 5092.36 0.25 0.32 0.237773 0.213212 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 11.39 0.16 21036 15 0.66 -1 -1 35172 -1 -1 65 45 3 1 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 77936 45 32 1275 1232 1 827 146 14 14 196 memory auto 2.13 6673 0.55 0.00 10.0822 -6325.59 -10.0822 10.0822 0.28 0.00163847 0.00137079 0.247235 0.201216 72 12424 18 9.20055e+06 5.54311e+06 844708. 4309.73 5.35 0.904368 0.764839 10987 13 3155 8576 1581981 414115 11.6443 11.6443 -7336.6 -11.6443 0 0 1.05868e+06 5401.43 0.16 0.33 0.107953 0.0999341 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 92.23 1.43 118520 5 9.32 -1 -1 71236 -1 -1 704 157 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 271852 157 197 23846 21799 1 6676 1058 33 33 1089 clb auto 7.46 39618 6.23 0.05 2.9308 -13224.6 -2.9308 2.9308 2.55 0.0167976 0.0139089 2.72218 2.05998 50 62630 23 6.0475e+07 3.79415e+07 3.66263e+06 3363.29 50.73 11.3202 9.09089 55668 12 16379 25575 918337 183454 3.69492 3.69492 -15705.8 -3.69492 0 0 4.71657e+06 4331.10 1.02 1.12 1.08857 0.993885 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 168.50 1.33 104660 3 43.29 -1 -1 84672 -1 -1 675 115 0 40 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 321752 115 145 23133 19546 1 9716 975 40 40 1600 mult_36 auto 7.65 81193 8.04 0.06 4.85074 -22294.2 -4.85074 4.85074 3.91 0.0200686 0.0147713 3.09128 2.32254 82 134682 37 9.16046e+07 5.22191e+07 8.58295e+06 5364.35 81.91 12.8131 10.3486 119058 16 33969 51744 22437603 4613086 5.29409 5.29409 -25657.1 -5.29409 0 0 1.07702e+07 6731.38 2.47 4.83 1.29502 1.15861 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 500.44 1.66 148876 3 7.04 -1 -1 202128 -1 -1 1653 149 0 324 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1611520 149 182 65737 42630 1 35961 2308 104 104 10816 mult_36 auto 25.24 329951 42.93 0.27 14.5498 -61941.6 -14.5498 14.5498 91.37 0.0708359 0.0629052 11.9827 9.79984 80 453123 49 6.67561e+08 2.17385e+08 5.94869e+07 5499.90 235.52 45.2121 38.3272 431667 19 116030 135785 30345597 6109739 15.9454 15.9454 -72300.2 -15.9454 0 0 7.49726e+07 6931.63 24.72 9.60 4.52948 4.02549 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.77 0.05 9804 5 0.09 -1 -1 33052 -1 -1 14 11 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66940 11 30 313 321 2 118 55 7 7 49 clb auto 0.22 380 0.08 0.00 2.27568 -154.498 -2.27568 2.04477 0.04 0.000351492 0.000288388 0.0444322 0.0361463 36 848 30 1.07788e+06 754516 87745.0 1790.71 0.35 0.146989 0.12221 724 16 494 874 35494 12201 2.63781 2.28739 -185.002 -2.63781 0 0 109473. 2234.15 0.01 0.03 0.0202377 0.0182262 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/task_list.txt index 8b601361abf..543a2df55bc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/task_list.txt @@ -1,6 +1,2 @@ regression_tests/vtr_reg_weekly/vtr_reg_titan_he -regression_tests/vtr_reg_weekly/vtr_reg_titan -regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off -regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch -regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch -regression_tests/vtr_reg_weekly/vpr_ispd + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/config/golden_results.txt deleted file mode 100644 index dcb2af15e4e..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/config/golden_results.txt +++ /dev/null @@ -1,10 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time error num_IO num_CLB num_DSP num_BRAM vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -ultrascale_ispd.xml FPGA-example1.blif common 86.14 72 220 2 2 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run006/ultrascale_ispd.xml/FPGA-example1.blif/common 4503904 51 20 3417 3407 1 3287 296 168 480 80640 -1 ultrascale_ispd 5.12 29531 1.43 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -ultrascale_ispd.xml FPGA-example2.blif common 6525.35 456 39262 200 400 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run006/ultrascale_ispd.xml/FPGA-example2.blif/common 6991428 303 150 545542 542692 1 539559 40318 168 480 80640 -1 ultrascale_ispd 796.83 5830359 5599.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -ultrascale_ispd.xml FPGA-example3.blif common 5953.24 606 30856 200 500 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run006/ultrascale_ispd.xml/FPGA-example3.blif/common 6621500 403 200 431203 428403 1 429172 32162 168 480 80640 -1 ultrascale_ispd 600.24 16335580 5231.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -ultrascale_ispd.xml FPGA-example4.blif common 5969.83 -1 -1 -1 -1 v8.0.0-1603-g6c2a712a0 exited with return code 1 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run006/ultrascale_ispd.xml/FPGA-example4.blif/common 5716480 403 200 850587 844787 1 -1 -1 168 480 -1 -1 -1 5951.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -ultrascale_ispd.xml clk_design1.blif common 99.95 109 592 2 2 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run006/ultrascale_ispd.xml/clk_design1.blif/common 4538928 57 20 9969 9959 30 9711 705 168 480 80640 -1 ultrascale_ispd 9.11 63424 5.84 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -ultrascale_ispd.xml clk_design2.blif common 442.45 244 5837 10 10 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run006/ultrascale_ispd.xml/clk_design2.blif/common 4994744 137 60 100115 100025 45 97978 6101 168 480 80640 -1 ultrascale_ispd 89.88 924709 265.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -ultrascale_ispd.xml clk_design3.blif common 2963.32 374 22993 50 96 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run006/ultrascale_ispd.xml/clk_design3.blif/common 6291636 217 120 400080 399454 35 390926 23513 168 480 80640 -1 ultrascale_ispd 244.17 4772904 2608.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -ultrascale_ispd.xml clk_design4.blif common 6361.80 484 39151 150 366 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run006/ultrascale_ispd.xml/clk_design4.blif/common 7329188 292 150 685438 683387 40 669318 40151 168 480 80640 -1 ultrascale_ispd 443.76 8539380 5788.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -ultrascale_ispd.xml clk_design5.blif common 10669.51 515 51693 420 885 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run006/ultrascale_ispd.xml/clk_design5.blif/common 8046876 307 150 948147 942073 56 928185 53513 168 480 80640 -1 ultrascale_ispd 627.98 12115275 9883.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/config/golden_results.txt deleted file mode 100644 index e9c40ad4a96..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/config/golden_results.txt +++ /dev/null @@ -1,9 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time num_fpu -hard_fpu_arch_timing.xml bfly.v common 3.85 0.03 6836 1 0.02 -1 -1 30788 -1 -1 0 193 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run007/hard_fpu_arch_timing.xml/bfly.v/common 41324 193 64 833 649 1 353 260 24 24 576 io auto 1.60 5479 0.47 2.985 -1309 -2.985 7356 533 720 5115089 2516883 1.06129e+06 103149 1.28794e+06 2236.02 14 2.985 2.985 -1359.91 -2.985 -40.8482 -0.0851 0.83 3 -hard_fpu_arch_timing.xml bgm.v common 12.51 0.05 8216 1 0.04 -1 -1 31428 -1 -1 0 257 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run007/hard_fpu_arch_timing.xml/bgm.v/common 69084 257 32 1281 693 1 1021 299 38 38 1444 block_FPU auto 4.94 16818 1.05 2.985 -3092.78 -2.985 23580 1845 2464 24033547 12730674 2.90196e+06 343832 3.35777e+06 2325.33 14 2.985 2.985 -3439.47 -2.985 -25.1662 -0.0851 4.43 10 -hard_fpu_arch_timing.xml dscg.v common 8.35 0.03 6548 1 0.02 -1 -1 30788 -1 -1 0 129 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run007/hard_fpu_arch_timing.xml/dscg.v/common 50908 129 64 769 585 1 513 198 32 32 1024 block_FPU auto 3.70 7404 0.55 2.985 -1358.14 -2.985 11339 888 1271 14835699 9019222 2.063e+06 171916 2.37490e+06 2319.23 15 2.985 2.985 -1521.9 -2.985 -21.7856 -0.0851 2.68 5 -hard_fpu_arch_timing.xml fir.v common 32.67 0.03 6900 1 0.03 -1 -1 31124 -1 -1 37 161 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run007/hard_fpu_arch_timing.xml/fir.v/common 47448 161 32 993 808 1 545 234 30 30 900 block_FPU auto 30.00 6341 0.49 2.985 -1322.93 -2.985 9179 922 1051 5806849 2682821 1.6779e+06 222344 2.03108e+06 2256.75 7 2.985 2.985 -1445.92 -2.985 -39.3105 -0.0851 0.87 4 -hard_fpu_arch_timing.xml mm3.v common 2.16 0.02 6152 1 0.01 -1 -1 30444 -1 -1 0 193 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run007/hard_fpu_arch_timing.xml/mm3.v/common 34940 193 32 545 422 1 289 227 21 21 441 io auto 0.88 3143 0.29 2.985 -793.636 -2.985 4259 423 423 1836814 649845 809148 68766.3 979092. 2220.16 10 2.985 2.985 -805.207 -2.985 -21.8252 -0.0851 0.25 2 -hard_fpu_arch_timing.xml ode.v common 31.31 0.04 7360 1 0.04 -1 -1 33796 -1 -1 151 130 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run007/hard_fpu_arch_timing.xml/ode.v/common 40916 130 72 1194 1103 1 589 355 19 19 361 io auto 29.45 4575 0.58 2.985 -1330.9 -2.985 6750 1318 1419 3312472 1427922 653279 414890 795482. 2203.55 15 2.985 2.985 -1420.57 -2.985 -51.2702 -0.0851 0.48 2 -hard_fpu_arch_timing.xml syn2.v common 3.99 0.02 6680 1 0.01 -1 -1 30456 -1 -1 0 161 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run007/hard_fpu_arch_timing.xml/syn2.v/common 47692 161 128 641 490 1 479 293 30 30 900 block_FPU auto 1.02 8131 0.57 2.985 -1450.95 -2.985 10687 863 1091 7542802 3863286 1.6779e+06 137533 2.03108e+06 2256.75 7 2.985 2.985 -1575.36 -2.985 -16.1177 -0.0851 1.16 4 -hard_fpu_arch_timing.xml syn7.v common 25.15 0.07 9180 1 0.03 -1 -1 32616 -1 -1 0 161 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run007/hard_fpu_arch_timing.xml/syn7.v/common 119996 161 128 1921 499 1 1697 310 54 54 2916 block_FPU auto 2.28 43036 2.26 2.985 -7784.21 -2.985 59257 3441 5987 83419518 47524140 6.08571e+06 722046 6.89978e+06 2366.18 8 2.985 2.985 -8558.99 -2.985 -33.6146 -0.0851 16.55 21 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt deleted file mode 100755 index 28756d9da64..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt +++ /dev/null @@ -1,8 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -soft_fpu_arch_timing.xml bfly.v common 227.72 3.67 165780 60 87.22 -1 -1 85992 -1 -1 6856 193 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run007/soft_fpu_arch_timing.xml/bfly.v/common 371044 193 64 23996 24060 1 18159 7113 85 85 7225 clb auto 4.85 229576 99.06 34.9974 -17204.8 -34.9974 377103 185156 511027 54906914 6524451 1.579e+07 1.57144e+07 1.73164e+07 2396.73 43 37.5946 37.5946 -18163.7 -37.5946 -52.2272 -0.0851 15.43 -soft_fpu_arch_timing.xml bgm.v common 1381.80 25.53 397372 60 677.97 -1 -1 198084 -1 -1 17930 257 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run007/soft_fpu_arch_timing.xml/bgm.v/common 941704 257 32 62096 62128 1 47778 18219 136 136 18496 clb auto 15.84 598700 581.34 40.6175 -42909.1 -40.6175 971247 340469 1011134 105591814 12709686 4.11556e+07 4.1096e+07 4.47194e+07 2417.79 31 43.4142 43.4142 -45610.5 -43.4142 -79.3117 -0.0851 32.62 -soft_fpu_arch_timing.xml dscg.v common 218.88 3.44 166640 60 88.72 -1 -1 85520 -1 -1 6510 129 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run007/soft_fpu_arch_timing.xml/dscg.v/common 362464 129 64 22497 22561 1 17043 6703 83 83 6889 clb auto 4.58 211488 92.08 35.727 -15025.3 -35.727 353851 155280 452404 49831959 5827141 1.50382e+07 1.49214e+07 1.65016e+07 2395.36 37 38.6815 38.6815 -15914.7 -38.6815 -48.0364 -0.0851 13.31 -soft_fpu_arch_timing.xml fir.v common 203.98 2.91 147132 59 80.93 -1 -1 81552 -1 -1 6565 161 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run007/soft_fpu_arch_timing.xml/fir.v/common 364492 161 32 22903 22935 1 17506 6758 84 84 7056 clb auto 5.02 203899 85.99 34.467 -14743.1 -34.467 343991 161443 448499 46795749 5672656 1.54118e+07 1.50474e+07 1.69066e+07 2396.05 35 37.3323 37.3323 -15630.1 -37.3323 -51.5873 -0.0851 12.19 -soft_fpu_arch_timing.xml mm3.v common 111.52 1.48 107028 60 41.07 -1 -1 67068 -1 -1 4687 193 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run007/soft_fpu_arch_timing.xml/mm3.v/common 291816 193 32 16466 16498 1 12558 4912 71 71 5041 clb auto 3.39 144472 47.19 35.7479 -10616.6 -35.7479 243643 107135 300026 30691050 3729034 1.09126e+07 1.0743e+07 1.20254e+07 2385.52 26 38.366 38.366 -11248.8 -38.366 -30.5555 -0.0851 7.10 -soft_fpu_arch_timing.xml ode.v common 89.14 1.44 108120 59 31.97 -1 -1 53756 -1 -1 4036 130 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run007/soft_fpu_arch_timing.xml/ode.v/common 230240 130 72 14268 14340 1 10622 4238 66 66 4356 clb auto 2.75 124480 35.73 33.234 -11156.3 -33.234 208591 94664 268114 28283104 3422889 9.38847e+06 9.25095e+06 1.03689e+07 2380.36 33 36.0724 36.0724 -11724.5 -36.0724 -62.8441 -0.0851 6.95 -soft_fpu_arch_timing.xml syn2.v common 251.89 4.75 187236 60 107.19 -1 -1 90592 -1 -1 7226 161 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run007/soft_fpu_arch_timing.xml/syn2.v/common 386644 161 128 25115 25243 1 19176 7515 88 88 7744 clb auto 5.27 238778 100.95 36.1887 -19539.1 -36.1887 392464 188900 531400 55404964 6720407 1.69521e+07 1.65624e+07 1.85753e+07 2398.67 42 38.634 38.634 -20661.3 -38.634 -37.6131 -0.0851 15.57 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/config/golden_results.txt deleted file mode 100644 index 8eac76261a2..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/config/golden_results.txt +++ /dev/null @@ -1,22 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time 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betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run007/k6_frac_N10_frac_chain_mem32K_40nm.xml/boundtop.v/common 43916 142 192 1071 1141 1 560 426 14 14 196 clb auto 0.61 1696 0.89 2.91391 -445.169 -2.91391 34 3981 14 9.20055e+06 4.95825e+06 429196. 2189.78 1.47 3444 14 1284 2018 93022 25079 3.39108 3.39108 -545.825 -3.39108 0 0 527839. 2693.05 0.07 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.22 0.04 8880 3 0.20 -1 -1 36252 -1 -1 65 99 1 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run007/k6_frac_N10_frac_chain_mem32K_40nm.xml/ch_intrinsics.v/common 36304 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 635 0.44 1.86439 -198.325 -1.86439 48 1372 10 5.66058e+06 4.05111e+06 394078. 2736.65 0.47 1259 8 580 750 46400 15459 2.4004 2.4004 -228.324 -2.4004 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betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run007/k6_frac_N10_frac_chain_mem32K_40nm.xml/LU32PEEng.v/common 2148072 114 102 124854 111149 1 59091 7906 102 102 10404 clb auto 220.04 1021773 752.26 68.7353 -327692 -68.7353 124 1400339 42 6.36957e+08 5.07872e+08 8.44220e+07 8114.38 1633.41 1323028 22 213582 894393 215512368 52740904 78.3285 78.3285 -462946 -78.3285 0 0 1.06940e+08 10278.8 77.35 -k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5516.75 23.81 873912 24 3314.68 -1 -1 372876 -1 -1 7103 36 159 27 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run007/k6_frac_N10_frac_chain_mem32K_40nm.xml/mcml.v/common 2417228 36 33 190959 166678 1 61855 7358 100 100 10000 clb auto 204.39 720967 928.73 40.562 -267244 -40.562 144 973829 23 6.13558e+08 4.80599e+08 9.27426e+07 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2964 2870 1 1438 634 19 19 361 io auto 2.15 11432 2.30 4.31218 -2475.36 -4.31218 58 24848 40 1.72706e+07 8.93466e+06 1.32779e+06 3678.09 10.22 20523 18 6049 13718 3496664 806645 4.78735 4.78735 -2995.2 -4.78735 0 0 1.69263e+06 4688.74 0.65 -k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 258.12 0.66 36256 3 242.08 -1 -1 91696 -1 -1 156 38 0 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run007/k6_frac_N10_frac_chain_mem32K_40nm.xml/sha.v/common 71848 38 36 2995 2744 1 1210 230 17 17 289 clb auto 1.86 11128 1.87 8.63389 -2451.33 -8.63389 74 16247 24 1.34605e+07 8.40746e+06 1.29327e+06 4475.00 6.14 15777 23 4883 12799 483157 82370 10.176 10.176 -2919.88 -10.176 0 0 1.62379e+06 5618.64 0.40 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 11.49 0.15 19892 15 0.64 -1 -1 34916 -1 -1 65 45 3 1 v8.0.0-1603-g6c2a712a0 success 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/home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run007/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision2.v/common 1346672 149 182 65737 42630 1 35961 2308 104 104 10816 mult_36 auto 24.51 354530 147.58 15.2766 -65075.8 -15.2766 80 479767 32 6.67561e+08 2.17385e+08 5.94869e+07 5499.90 171.55 459283 19 116678 136912 35553120 7131594 16.7863 16.7863 -76139.3 -16.7863 0 0 7.49726e+07 6931.63 12.42 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.73 0.05 9348 5 0.10 -1 -1 33252 -1 -1 14 11 0 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run007/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 32700 11 30 313 321 2 117 55 7 7 49 clb auto 0.23 382 0.12 2.2748 -152.784 -2.2748 34 850 21 1.07788e+06 754516 84249.8 1719.38 0.33 685 9 365 632 21602 7821 2.54033 2.31797 -175.101 -2.54033 0 0 103542. 2113.11 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/config/config.txt deleted file mode 100644 index b35806f42cc..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/config/config.txt +++ /dev/null @@ -1,63 +0,0 @@ -############################################ -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/titan_blif - -# Path to directory of architectures to use -archs_dir=arch/titan - -# Add circuits to list to sweep -# Note that the circuits are roughly sorted so that some small -# circuits run first (to detect early failures), followed by larger -# circuits (so they do not start last) - -#Largest benchmarks, which have potential to unroute or time-out -circuit_list_add=gaussianblur_stratixiv_arch_timing.blif - -#Large benchmarks -circuit_list_add=directrf_stratixiv_arch_timing.blif -circuit_list_add=bitcoin_miner_stratixiv_arch_timing.blif -circuit_list_add=LU230_stratixiv_arch_timing.blif -circuit_list_add=sparcT1_chip2_stratixiv_arch_timing.blif -circuit_list_add=LU_Network_stratixiv_arch_timing.blif - -#Small benchmarks -circuit_list_add=neuron_stratixiv_arch_timing.blif -circuit_list_add=sparcT1_core_stratixiv_arch_timing.blif -circuit_list_add=stereo_vision_stratixiv_arch_timing.blif -circuit_list_add=cholesky_mc_stratixiv_arch_timing.blif - -#Mixed order of large and small -circuit_list_add=gsm_switch_stratixiv_arch_timing.blif -circuit_list_add=mes_noc_stratixiv_arch_timing.blif -circuit_list_add=dart_stratixiv_arch_timing.blif -circuit_list_add=denoise_stratixiv_arch_timing.blif -circuit_list_add=sparcT2_core_stratixiv_arch_timing.blif -circuit_list_add=cholesky_bdti_stratixiv_arch_timing.blif -circuit_list_add=minres_stratixiv_arch_timing.blif -circuit_list_add=stap_qrd_stratixiv_arch_timing.blif -circuit_list_add=openCV_stratixiv_arch_timing.blif -circuit_list_add=bitonic_mesh_stratixiv_arch_timing.blif -circuit_list_add=segmentation_stratixiv_arch_timing.blif -circuit_list_add=SLAM_spheric_stratixiv_arch_timing.blif -circuit_list_add=des90_stratixiv_arch_timing.blif - -# Add architectures to list to sweep -arch_list_add=stratixiv_arch.timing.xml - -# Parse info and how to parse -parse_file=vpr_titan.txt - -# How to parse QoR info -qor_parse_file=qor_vpr_titan.txt - -# Pass requirements -pass_requirements_file=pass_requirements_vpr_titan.txt - -#The Titan benchmarks are run at a fixed channel width of 300 to simulate a Stratix IV-like routing architecture -#A large number of routing iterations is set to ensure the router doesn't give up to easily on the larger benchmarks -#To be more run-time comparable to commercial tools like Quartus, we run with higher placer effort (inner_num=2) and lower astar_fac (1.0) -#Set a 48hr timeout so they don't run forever -script_params=-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map -timeout 172800 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/config/golden_results.txt deleted file mode 100644 index 1b774cce5f2..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/config/golden_results.txt +++ /dev/null @@ -1,24 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -stratixiv_arch.timing.xml gaussianblur_stratixiv_arch_timing.blif common 54325.83 558 104911 2 12 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/gaussianblur_stratixiv_arch_timing.blif/common 29335900 166 392 1872320 1859014 1 1211091 105483 399 296 118104 LAB auto 7674.05 22599907 42575.87 224.79 878.625 -7.86417e+07 -878.625 878.625 5.11373 3.2867 820.494 533.01 31535329 3964408 20296950 10275455254 1382785116 0 0 2.38992e+09 20235.7 24 870.539 870.539 -1.11959e+08 -870.539 0 0 1700.31 1134.94 777.934 -stratixiv_arch.timing.xml directrf_stratixiv_arch_timing.blif common 17102.08 319 61450 240 2535 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/directrf_stratixiv_arch_timing.blif/common 17934728 62 257 1374456 930989 2 679939 64544 317 235 74495 M9K auto 997.77 12249060 13596.14 64.56 10.4806 -2.80095e+06 -10.4806 9.39137 2.33826 1.74501 460.458 327.913 13955806 1895607 3396577 5132904157 840202091 0 0 1.42890e+09 19181.1 15 11.4112 10.0672 -3.60917e+06 -11.4112 0 0 981.11 567.373 416.71 -stratixiv_arch.timing.xml bitcoin_miner_stratixiv_arch_timing.blif common 16110.51 385 32463 0 1331 0 1 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/bitcoin_miner_stratixiv_arch_timing.blif/common 12276260 353 32 1446409 1087537 2 848822 34180 225 167 37575 LAB auto 801.12 10288275 13797.35 82.94 6.849 -1.58449e+06 -6.849 0.789461 2.21826 1.56866 331.226 234.44 11623988 2630178 3848392 4044615549 610108617 0 0 7.28440e+08 19386.3 34 8.78656 0.992725 -2.08083e+06 -8.78656 0 0 681.80 524.146 388.921 -stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 8480.17 373 16585 116 5040 16 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/LU230_stratixiv_arch_timing.blif/common 18015052 178 195 663067 568001 2 413013 22130 430 319 137170 M9K auto 1009.96 15088834 4398.96 22.14 24.2639 -4.46683e+06 -24.2639 9.92669 2.07434 1.52222 344.961 243.172 17214668 1167740 2323256 3021870810 553369148 0 0 2.85688e+09 20827.3 16 24.5892 10.6449 -7.49842e+06 -24.5892 0 0 584.00 439.605 321.432 -stratixiv_arch.timing.xml sparcT1_chip2_stratixiv_arch_timing.blif common 22492.00 1891 33543 3 506 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/sparcT1_chip2_stratixiv_arch_timing.blif/common 12158512 815 1076 764693 760412 1423 418656 35943 279 207 57753 io auto 1537.21 6558526 6894.16 45.35 20.9235 -5.29225e+06 -20.9235 1.14034 6.78305 6.11403 909.498 812.868 7946954 1202979 3951674 2591649337 315911324 0 0 1.11162e+09 19247.9 27 21.6103 1.22526 -6.10548e+06 -21.6103 0 0 676.51 1324.19 1196.64 -stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 7242.78 405 31090 112 1175 0 2 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/LU_Network_stratixiv_arch_timing.blif/common 10661404 85 185 721554 630079 28 404578 32784 220 163 35860 LAB auto 800.40 4562111 5383.15 29.18 6.64648 -1.81662e+06 -6.64648 1.10615 2.17246 1.58126 356.085 253.59 5751752 895421 1893895 1742751851 293521170 0 0 6.95754e+08 19402.0 18 7.44247 1.15999 -2.1301e+06 -7.44247 0 0 305.92 466.344 344.374 -stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 518.46 77 3116 89 136 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/neuron_stratixiv_arch_timing.blif/common 2829520 42 35 119888 86875 1 51143 3418 129 96 12384 DSP auto 84.24 578032 170.75 0.80 7.51447 -217377 -7.51447 7.51447 0.195447 0.170063 29.381 23.9048 751169 106182 174573 247181469 51951277 0 0 2.43110e+08 19631.0 12 8.10257 8.10257 -276029 -8.10257 0 0 35.82 38.5637 32.1671 -stratixiv_arch.timing.xml sparcT1_core_stratixiv_arch_timing.blif common 757.23 310 3932 1 128 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/sparcT1_core_stratixiv_arch_timing.blif/common 2105040 173 137 92814 91975 1 57417 4371 82 61 5002 LAB auto 261.98 919207 323.79 2.11 7.91799 -521189 -7.91799 7.91799 0.206145 0.166551 32.5505 22.4246 1242109 219480 781234 594257462 77905583 0 0 9.74073e+07 19473.7 18 8.2717 8.2717 -617668 -8.2717 0 0 68.62 45.6556 33.2682 -stratixiv_arch.timing.xml stereo_vision_stratixiv_arch_timing.blif common 497.13 506 3238 76 113 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/stereo_vision_stratixiv_arch_timing.blif/common 2653952 172 334 127090 94090 3 61780 3933 129 96 12384 DSP auto 69.34 552796 175.69 0.91 7.90709 -147122 -7.90709 3.04131 0.177697 0.127749 24.0684 16.9072 624560 132182 196043 182850215 26539188 0 0 2.43110e+08 19631.0 15 8.1769 3.21988 -170761 -8.1769 0 0 24.76 32.6189 24.1721 -stratixiv_arch.timing.xml cholesky_mc_stratixiv_arch_timing.blif common 696.79 262 4746 59 444 16 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/cholesky_mc_stratixiv_arch_timing.blif/common 3080780 111 151 140214 108592 1 66048 5527 125 93 11625 M9K auto 113.07 828961 269.67 1.49 6.72673 -426254 -6.72673 6.72673 0.240206 0.200394 38.8911 28.8483 1172151 156587 347763 595805524 139369856 0 0 2.28063e+08 19618.3 18 7.38873 7.38873 -555508 -7.38873 0 0 99.34 54.0613 41.8143 -stratixiv_arch.timing.xml gsm_switch_stratixiv_arch_timing.blif common 4390.61 136 21477 0 1848 0 1 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/gsm_switch_stratixiv_arch_timing.blif/common 9538416 100 36 504627 490068 5 201500 23462 255 189 48195 M9K auto 704.57 4224517 2604.99 14.32 9.5402 -2.51832e+06 -9.5402 3.85175 1.04032 0.748215 183.449 119.348 5338922 506559 1537118 1158593253 187016053 0 0 9.29962e+08 19295.8 14 10.1644 4.20583 -3.15938e+06 -10.1644 0 0 205.04 234.804 161.067 -stratixiv_arch.timing.xml mes_noc_stratixiv_arch_timing.blif common 7590.45 5 23767 0 800 0 8 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/mes_noc_stratixiv_arch_timing.blif/common 8769136 3 2 577696 547568 17 346014 24580 193 143 27599 LAB auto 1340.26 3807488 5325.21 34.17 13.112 -4.19166e+06 -13.112 8.499 2.12067 1.4885 295.505 205.797 5089474 857934 2524901 2168308749 242372215 0 0 5.39298e+08 19540.5 17 14.2152 9.0782 -4.90118e+06 -14.2152 0 0 340.10 396.281 288.589 -stratixiv_arch.timing.xml dart_stratixiv_arch_timing.blif common 1576.90 69 7014 0 530 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/dart_stratixiv_arch_timing.blif/common 3972660 23 46 223304 202401 1 132117 7613 138 102 14076 M9K auto 364.81 1915296 839.36 5.56 13.8661 -1.5694e+06 -13.8661 13.8661 0.5488 0.420259 79.6996 55.5284 2315178 365188 928257 800073199 105465602 0 0 2.76641e+08 19653.4 15 14.4922 14.4922 -1.91254e+06 -14.4922 0 0 108.77 108.946 80.125 -stratixiv_arch.timing.xml denoise_stratixiv_arch_timing.blif common 4867.02 852 14045 24 359 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/denoise_stratixiv_arch_timing.blif/common 5469508 264 588 355537 274786 1 219008 15280 150 111 16650 LAB auto 380.61 2657013 3839.19 22.32 886.392 -1.09452e+06 -886.392 886.392 0.866923 0.630033 128.85 93.3497 3208108 927383 2877986 2387152428 278024256 0 0 3.27533e+08 19671.7 24 873.404 873.404 -1.30496e+06 -873.404 0 0 262.02 184.444 138.199 -stratixiv_arch.timing.xml sparcT2_core_stratixiv_arch_timing.blif common 3866.21 451 14741 0 260 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/sparcT2_core_stratixiv_arch_timing.blif/common 5049644 239 212 302755 300220 1 185037 15452 153 113 17289 LAB auto 673.81 3685890 2546.25 19.15 10.9188 -1.01249e+06 -10.9188 10.9188 0.76817 0.592124 111.324 78.1221 4699882 676774 2611591 2091540827 275972166 0 0 3.40245e+08 19679.8 20 11.4723 11.4723 -1.32008e+06 -11.4723 0 0 290.48 160.268 117.566 -stratixiv_arch.timing.xml cholesky_bdti_stratixiv_arch_timing.blif common 1914.49 162 9699 132 600 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/cholesky_bdti_stratixiv_arch_timing.blif/common 5248444 94 68 331744 255478 1 156337 10593 169 125 21125 DSP auto 283.47 1829761 995.39 5.97 8.46905 -1.02346e+06 -8.46905 8.46905 0.54146 0.4403 85.9673 62.5028 2522901 376004 795047 1333683528 287660368 0 0 4.15904e+08 19687.8 19 9.034 9.034 -1.37038e+06 -9.034 0 0 210.53 120.705 92.2217 -stratixiv_arch.timing.xml minres_stratixiv_arch_timing.blif common 2331.85 229 7827 78 1459 0 1 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/minres_stratixiv_arch_timing.blif/common 6654196 129 100 316623 257480 3 183891 9594 225 167 37575 M9K auto 353.91 2247326 1126.37 6.18 8.3053 -735956 -8.3053 4.79086 0.724682 0.524834 107.119 78.3004 2968490 417129 825315 916680596 166487995 0 0 7.28440e+08 19386.3 13 8.93194 5.11164 -961199 -8.93194 0 0 142.82 138.092 104.616 -stratixiv_arch.timing.xml stap_qrd_stratixiv_arch_timing.blif common 2445.28 150 15893 75 553 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/stap_qrd_stratixiv_arch_timing.blif/common 4663808 68 82 284051 234177 1 143550 16671 158 117 18486 LAB auto 256.46 2168655 1692.60 8.52 6.26249 -853337 -6.26249 6.26249 0.503327 0.40387 93.8759 68.482 2720473 333016 841070 952749766 172532608 0 0 3.64007e+08 19691.0 16 6.8316 6.8316 -1.14133e+06 -6.8316 0 0 142.97 123.73 92.9597 -stratixiv_arch.timing.xml openCV_stratixiv_arch_timing.blif common 2031.20 208 7151 213 785 40 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/openCV_stratixiv_arch_timing.blif/common 5976520 106 102 279132 212552 1 168734 8397 209 155 32395 DSP auto 320.65 2685497 905.34 6.58 10.4525 -1.03507e+06 -10.4525 10.4525 0.59565 0.497014 88.4703 66.6987 3407017 472493 1044513 1309875731 245229707 0 0 6.29758e+08 19440.0 14 11.2704 11.2704 -1.31974e+06 -11.2704 0 0 211.29 118.186 92.1362 -stratixiv_arch.timing.xml bitonic_mesh_stratixiv_arch_timing.blif common 2709.50 119 7206 85 1664 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/bitonic_mesh_stratixiv_arch_timing.blif/common 6948252 87 32 233978 190746 1 147040 9074 242 179 43318 M9K auto 483.88 3881388 1155.53 8.46 13.048 -1.96544e+06 -13.048 13.048 0.873846 0.633046 112.738 82.4582 5007121 520235 1675441 1922751757 348954514 0 0 8.37664e+08 19337.6 16 13.6482 13.6482 -2.34229e+06 -13.6482 0 0 297.31 155.456 118.855 -stratixiv_arch.timing.xml segmentation_stratixiv_arch_timing.blif common 1660.86 441 6925 15 481 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/segmentation_stratixiv_arch_timing.blif/common 3561688 72 369 178312 137832 1 108441 7862 136 101 13736 M9K auto 183.73 1331079 1082.53 6.17 874.166 -476778 -874.166 874.166 0.391911 0.284246 58.5934 42.7101 1680683 464528 1463960 1248508067 148195106 0 0 2.69876e+08 19647.3 24 855.619 855.619 -596430 -855.619 0 0 132.76 83.7489 63.0299 -stratixiv_arch.timing.xml SLAM_spheric_stratixiv_arch_timing.blif common 1063.73 479 5394 37 0 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/SLAM_spheric_stratixiv_arch_timing.blif/common 2578224 323 156 140638 111354 1 76831 5910 95 70 6650 LAB auto 184.85 1130777 653.72 3.20 81.2267 -347590 -81.2267 81.2267 0.326305 0.235822 49.7434 35.7233 1454555 238013 787994 746060068 105389867 0 0 1.29896e+08 19533.2 18 79.833 79.833 -380596 -79.833 0 0 86.07 66.951 50.0447 -stratixiv_arch.timing.xml des90_stratixiv_arch_timing.blif common 1255.90 117 4186 44 860 0 0 success v8.0.0-2036-gb5ccf1b32 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-08T11:35:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run008/stratixiv_arch.timing.xml/des90_stratixiv_arch_timing.blif/common 4065000 85 32 138853 110549 1 88035 5207 171 127 21717 M9K auto 263.18 1733266 449.95 2.74 11.7913 -1.0041e+06 -11.7913 11.7913 0.386353 0.325799 55.6199 41.6631 2354585 295453 903620 954811942 172128166 0 0 4.27406e+08 19680.7 18 12.4542 12.4542 -1.16595e+06 -12.4542 0 0 135.86 79.3483 62.145 diff --git a/vtr_flow/tasks/timing/config/golden_results.txt b/vtr_flow/tasks/timing/config/golden_results.txt deleted file mode 100644 index 57a6c6b4571..00000000000 --- a/vtr_flow/tasks/timing/config/golden_results.txt +++ /dev/null @@ -1,21 +0,0 @@ -arch circuit vpr_status min_chan_width critical_path_delay pack_time place_time min_chan_width_route_time crit_path_route_time routed_wirelength num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_clb num_io num_outputs num_memories num_mult num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length error -k6_frac_N10_mem32K_40nm.xml arm_core.v success 114 18.5971 37.65 57.42 755.52 35.40 257516 19617 19796 9200 1073 133 179 40 0 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml bgm.v success 106 20.8882 56.82 102.09 217.25 15.87 405780 26797 26312 14500 1969 257 32 0 11 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml blob_merge.v success 74 10.6432 9.70 9.50 34.51 2.39 80984 6406 6506 2880 520 36 100 0 0 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml boundtop.v success 60 5.84455 3.55 3.50 6.89 0.71 24578 4028 4220 1851 192 275 192 1 0 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v success 42 3.5255 0.16 0.28 0.70 0.07 2555 419 549 298 19 99 130 1 0 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml diffeq1.v success 50 22.4462 0.44 0.85 3.96 0.66 13929 1001 938 708 36 162 96 0 5 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml diffeq2.v success 46 18.0707 0.36 0.82 8.78 0.68 10911 651 587 469 25 66 96 0 5 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml LU8PEEng.v success 126 111.704 49.12 85.69 1141.42 39.38 458276 30101 29827 16737 1818 114 102 44 8 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml LU32PEEng.v success 214 112.149 216.37 672.65 42959.31 541.72 2102620 100107 98705 55230 6212 114 102 167 32 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mcml.v success 114 76.8248 142.48 433.82 6731.23 116.97 1186665 149022 147480 48186 6016 36 33 159 27 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkDelayWorker32B.v success 38 8.1742 2.65 10.75 22.32 2.64 38427 3923 4476 3430 111 506 553 44 0 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkPktMerge.v success 40 4.96958 0.57 1.59 14.17 1.00 15109 978 1134 953 11 311 156 15 0 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkSMAdapter4B.v success 52 5.2635 2.19 2.37 7.09 0.68 19845 2635 2840 1323 124 193 205 5 0 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml or1200.v success 76 14.1005 4.55 6.46 65.23 2.07 61556 4181 4512 2440 247 385 394 2 1 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml raygentop.v success 72 5.25213 3.16 3.74 17.84 1.77 33443 3827 3943 1911 170 239 305 1 7 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml sha.v success 58 14.3193 2.29 2.37 10.43 0.62 22742 3185 3221 1285 182 38 36 0 0 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml stereovision0.v success 58 4.19256 9.46 17.05 23.40 2.36 87252 23659 23856 7356 833 157 197 0 0 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml stereovision1.v success 104 6.04754 12.70 23.43 149.20 11.03 188062 24212 22077 11123 911 133 145 0 38 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml stereovision2.v success 138 16.4898 33.34 123.74 4370.02 56.33 801246 55423 46443 33203 2263 149 182 0 201 -1 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml stereovision3.v success 36 2.97931 0.14 0.11 0.29 0.03 811 287 317 115 12 11 30 0 0 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/timing_chain/config/golden_results.txt b/vtr_flow/tasks/timing_chain/config/golden_results.txt deleted file mode 100644 index b1f34dc8334..00000000000 --- a/vtr_flow/tasks/timing_chain/config/golden_results.txt +++ /dev/null @@ -1,21 +0,0 @@ -arch circuit vpr_status min_chan_width critical_path_delay pack_time place_time min_chan_width_route_time crit_path_route_time routed_wirelength num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_clb num_io num_outputs num_memories num_mult num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length error -k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v success 110 20.5369 62.73 58.18 683.52 27.83 248987 20229 20011 9198 1069 133 179 40 0 -1 435 35 36 27 -k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v success 84 23.4729 88.07 111.01 174.38 13.79 377364 29851 27995 15552 2095 257 32 0 11 -1 2198 25 3240 10 -k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v success 72 15.2812 32.00 11.57 42.85 2.73 103148 12387 9631 3825 611 36 100 0 0 -1 538 13 3216 12 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v success 58 5.86811 5.31 3.81 4.55 0.70 24591 4608 4563 1980 204 275 192 1 0 -1 218 19 91 15 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v success 44 3.56986 0.24 0.27 0.67 0.07 2342 419 549 296 19 99 130 1 0 -1 0 0 0 0 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v success 48 17.5333 0.56 0.78 8.15 0.69 13848 1066 879 661 30 162 96 0 5 -1 66 33 66 33 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v success 48 13.0202 0.26 0.64 9.33 0.69 9625 781 593 471 20 66 96 0 5 -1 66 33 66 33 -k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v success 120 86.5162 96.56 124.76 985.87 33.32 427271 35117 32079 16620 2016 114 102 44 8 -1 1359 26 1892 47 -k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v success 196 85.5651 394.73 993.69 49684.87 338.31 2103755 114032 105592 53836 6769 114 102 167 32 -1 3671 26 4578 47 -k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v success 128 45.3524 256.95 759.11 5438.61 149.65 1290551 187219 163035 60168 6116 36 33 159 27 -1 9131 65 15178 65 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v success 40 8.48925 3.15 10.12 20.52 2.04 37914 4161 4658 3500 117 506 553 44 0 -1 734 33 82 17 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v success 40 4.54311 0.72 1.42 9.18 0.86 15156 1019 1160 963 12 311 156 15 0 -1 45 5 0 0 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v success 58 5.4566 4.64 2.44 7.37 0.69 23530 3230 3155 1548 143 193 205 5 0 -1 365 33 66 17 -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v success 86 9.7377 7.84 5.90 34.79 1.87 55683 4903 4736 2602 242 385 394 2 1 -1 360 65 174 65 -k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v success 72 4.88307 3.48 3.66 13.76 1.53 35142 4606 4224 2222 184 239 305 1 8 -1 530 32 50 16 -k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v success 62 10.3457 3.04 2.08 7.50 0.66 20526 3318 3067 1206 167 38 36 0 0 -1 305 33 4 4 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v success 56 4.58963 9.08 12.76 23.80 1.93 73194 26293 24246 6736 833 157 197 0 0 -1 2802 18 118 18 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v success 100 6.04865 9.95 16.05 116.17 8.27 163598 25666 22079 10440 901 133 145 0 38 -1 2340 19 48 2 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v success 124 15.2419 28.80 97.59 1621.72 51.23 687512 64376 43213 34107 1882 149 182 0 201 -1 13267 32 576 32 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v success 36 3.25614 0.36 0.12 0.38 0.04 1221 352 360 150 15 11 30 0 0 -1 28 11 0 0 diff --git a/vtr_flow/tasks/timing_small/config/golden_results.txt b/vtr_flow/tasks/timing_small/config/golden_results.txt deleted file mode 100644 index ad3a8eae515..00000000000 --- a/vtr_flow/tasks/timing_small/config/golden_results.txt +++ /dev/null @@ -1,12 +0,0 @@ -arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem -k6_frac_N10_mem32K_40nm.xml blob_merge.v 30d086154 success 6406 6506 2880 656 29 29 520 36 100 0 0 100779 8.85445 -2577.18 -8.85445 74 80984 11 77336 13 10.6432 -2881.52 -10.6432 0 0 4.4999e+07 2.80249e+07 4.04182e+06 4805.97 5.07312e+06 6032.25 0.33 0.12 -1 -1 -1 14.01 13.77 53.72 3.88 98.97 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml boundtop.v 30d086154 success 4028 4220 1851 660 18 18 192 275 192 1 0 32588 5.01577 -4623.72 -5.01577 60 24578 14 21279 17 5.84455 -5219.63 -5.84455 -0.0211448 -0.0144466 1.57076e+07 1.08956e+07 1.22123e+06 3769.23 1.53793e+06 4746.71 0.50 0.09 -1 -1 -1 5.39 5.65 10.56 0.99 26.85 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v 30d086154 success 419 549 298 249 10 10 19 99 130 1 0 2262 2.74023 -250.655 -2.74023 42 2555 21 2250 12 3.5255 -318.677 -3.5255 0 0 3.92691e+06 1.57199e+06 236681. 2366.81 297605. 2976.05 0.05 0.01 -1 -1 -1 0.19 0.46 0.87 0.13 2.60 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml diffeq1.v 30d086154 success 1001 938 708 299 16 16 36 162 96 0 5 10296 19.5971 -1477.51 -19.5971 50 13929 27 10621 23 22.4462 -1741.17 -22.4462 0 0 1.21132e+07 3.92018e+06 780512. 3048.87 1.03597e+06 4046.75 0.04 0.00 -1 -1 -1 0.52 1.21 5.98 1.14 10.14 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml diffeq2.v 30d086154 success 651 587 469 192 16 16 25 66 96 0 5 7349 15.6403 -875.132 -15.6403 46 10911 45 8624 22 18.0707 -1038.63 -18.0707 0 0 1.21132e+07 3.32735e+06 727248. 2840.81 934704. 3651.19 0.02 0.00 -1 -1 -1 0.43 0.93 12.78 1.24 16.52 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkDelayWorker32B.v 30d086154 success 3923 4476 3430 1214 50 50 111 506 553 44 0 82124 7.71157 -2076.11 -7.71157 38 38427 15 36529 19 8.1742 -2382.87 -8.1742 -12.1939 -0.29436 1.47946e+08 3.00942e+07 6.86584e+06 2746.33 8.69095e+06 3476.38 1.08 0.14 -1 -1 -1 3.50 15.30 31.44 3.88 62.00 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkPktMerge.v 30d086154 success 978 1134 953 493 28 28 11 311 156 15 0 21490 4.57794 -4412.53 -4.57794 40 15109 13 13720 14 4.96958 -5017.29 -4.96958 -18.7112 -0.341744 4.25198e+07 8.81283e+06 2.13295e+06 2720.61 2.67004e+06 3405.67 0.25 0.02 -1 -1 -1 0.88 2.35 20.11 1.51 26.44 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkSMAdapter4B.v 30d086154 success 2635 2840 1323 527 20 20 124 193 205 5 0 24074 4.79897 -3057.27 -4.79897 52 19845 44 17520 15 5.2635 -3476.07 -5.2635 -11.0596 -0.339827 2.07112e+07 9.42286e+06 1.31074e+06 3276.84 1.72518e+06 4312.96 0.25 0.05 -1 -1 -1 2.82 3.34 10.23 0.99 20.64 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml or1200.v 30d086154 success 4181 4512 2440 1029 27 27 247 385 394 2 1 70507 12.5957 -12523.3 -12.5957 76 61556 12 50055 15 14.1005 -13933.5 -14.1005 0 0 3.93038e+07 1.48038e+07 3.58343e+06 4915.54 4.48127e+06 6147.14 0.54 0.08 -1 -1 -1 6.27 9.85 84.54 2.53 108.36 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml raygentop.v 30d086154 success 3827 3943 1911 722 19 19 170 239 305 1 7 33954 4.68017 -3551.22 -4.68017 72 33443 12 28555 17 5.25213 -4009.91 -5.25213 -0.452504 -0.0215478 1.72706e+07 1.2482e+07 1.63234e+06 4521.70 2.04538e+06 5665.88 0.21 0.07 -1 -1 -1 3.61 4.57 22.54 2.11 35.75 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml sha.v 30d086154 success 3185 3221 1285 256 18 18 182 38 36 0 0 24674 11.8757 -5758.56 -11.8757 58 22742 11 19595 16 14.3193 -6596.91 -14.3193 0 0 1.57076e+07 9.80871e+06 1.18155e+06 3646.76 1.50617e+06 4648.66 0.80 0.13 -1 -1 -1 2.69 2.85 13.10 0.75 26.55 -1 -1 -1