diff --git a/vpr/src/pack/cluster.cpp b/vpr/src/pack/cluster.cpp index de4487212f0..e1f5aa726fe 100644 --- a/vpr/src/pack/cluster.cpp +++ b/vpr/src/pack/cluster.cpp @@ -1179,6 +1179,76 @@ static void alloc_and_load_pb_stats(t_pb* pb, const int feasible_block_array_siz } /*****************************************/ +/** + * Cleans up a pb after unsuccessful molecule packing + * + * Recursively frees pbs from a t_pb tree. The given root pb itself is not + * deleted. + * + * If a pb object has its children allocated then before freeing them the + * function checks if there is no atom that corresponds to any of them. The + * check is performed only for leaf (primitive) pbs. The function recurses for + * non-primitive pbs. + * + * The cleaning itself includes deleting all child pbs, resetting mode of the + * pb and also freeing its name. This prepares the pb for another round of + * molecule packing tryout. + */ +static bool cleanup_pb(t_pb* pb) { + bool can_free = true; + + /* Recursively check if there are any children with already assigned atoms */ + if (pb->child_pbs != nullptr) { + const t_mode* mode = &pb->pb_graph_node->pb_type->modes[pb->mode]; + VTR_ASSERT(mode != nullptr); + + /* Check each mode */ + for (int i = 0; i < mode->num_pb_type_children; ++i) { + /* Check each child */ + if (pb->child_pbs[i] != nullptr) { + for (int j = 0; j < mode->pb_type_children[i].num_pb; ++j) { + t_pb* pb_child = &pb->child_pbs[i][j]; + t_pb_type* pb_type = pb_child->pb_graph_node->pb_type; + + /* Primitive, check occupancy */ + if (pb_type->num_modes == 0) { + if (pb_child->name != nullptr) { + can_free = false; + } + } + + /* Non-primitive, recurse */ + else { + if (!cleanup_pb(pb_child)) { + can_free = false; + } + } + } + } + } + + /* Free if can */ + if (can_free) { + for (int i = 0; i < mode->num_pb_type_children; ++i) { + if (pb->child_pbs[i] != nullptr) { + delete[] pb->child_pbs[i]; + } + } + + delete[] pb->child_pbs; + pb->child_pbs = nullptr; + pb->mode = 0; + + if (pb->name) { + free(pb->name); + pb->name = nullptr; + } + } + } + + return can_free; +} + /** * Try pack molecule into current cluster */ @@ -1358,6 +1428,12 @@ static enum e_block_pack_status try_pack_molecule(t_cluster_placement_stats* clu revert_place_atom_block(molecule->atom_block_ids[i], router_data, atom_molecules); } } + + /* Packing failed, but a part of the pb tree is still allocated and pbs have their modes set. + * Before trying to pack next molecule the unused pbs need to be freed and, the most important, + * their modes reset. This task is performed by the cleanup_pb() function below. */ + cleanup_pb(pb); + } else { VTR_LOGV(verbosity > 3, "\t\tPASSED pack molecule\n"); } diff --git a/vtr_flow/arch/timing/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/vtr_flow/arch/timing/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml new file mode 100644 index 00000000000..864a78886e9 --- /dev/null +++ b/vtr_flow/arch/timing/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -0,0 +1,702 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_top.a2f_o io_top.f2a_i io_top.clk io_top.sc_in io_top.sc_out io_top.reset + + + + + + + + + + + + + + + + + + + + + + io_right.a2f_o io_right.f2a_i io_right.clk io_right.sc_in io_right.sc_out io_right.reset + + + + + + + + + + + + + + + + + + + + + + io_bottom.a2f_o io_bottom.f2a_i io_bottom.clk io_bottom.sc_in io_bottom.sc_out io_bottom.reset + + + + + + + + + + + + + + + + + + + + + + io_left.a2f_o io_left.f2a_i io_left.clk io_left.sc_in io_left.sc_out io_left.reset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk clb.reset + clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I[11:0] + clb.I[23:12] + clb.reg_out clb.sc_out clb.cout clb.cout_copy + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 + 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/benchmarks/microbenchmarks/reg_4x32.blif b/vtr_flow/benchmarks/microbenchmarks/reg_4x32.blif new file mode 100644 index 00000000000..cba1de3decd --- /dev/null +++ b/vtr_flow/benchmarks/microbenchmarks/reg_4x32.blif @@ -0,0 +1,200 @@ +.model top +.inputs clk inp[0] inp[1] inp[2] inp[3] inp[4] inp[5] inp[6] inp[7] inp[8] inp[9] inp[10] inp[11] inp[12] inp[13] inp[14] inp[15] inp[16] inp[17] inp[18] inp[19] inp[20] inp[21] inp[22] inp[23] inp[24] inp[25] inp[26] inp[27] inp[28] inp[29] inp[30] inp[31] +.outputs out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[30] out[31] +.names $false +.names $true +1 +.names $undef +.latch r3[21] r4[21] re clk 2 +.latch r3[22] r4[22] re clk 2 +.latch r3[23] r4[23] re clk 2 +.latch r3[24] r4[24] re clk 2 +.latch r3[25] r4[25] re clk 2 +.latch r3[26] r4[26] re clk 2 +.latch r3[27] r4[27] re clk 2 +.latch r3[28] r4[28] re clk 2 +.latch r3[29] r4[29] re clk 2 +.latch r3[30] r4[30] re clk 2 +.latch r3[31] r4[31] re clk 2 +.latch r2[0] r3[0] re clk 2 +.latch r2[1] r3[1] re clk 2 +.latch r2[2] r3[2] re clk 2 +.latch r2[3] r3[3] re clk 2 +.latch r2[4] r3[4] re clk 2 +.latch r2[5] r3[5] re clk 2 +.latch r2[6] r3[6] re clk 2 +.latch r2[7] r3[7] re clk 2 +.latch r2[8] r3[8] re clk 2 +.latch r2[9] r3[9] re clk 2 +.latch r2[10] r3[10] re clk 2 +.latch r2[11] r3[11] re clk 2 +.latch r2[12] r3[12] re clk 2 +.latch r2[13] r3[13] re clk 2 +.latch r2[14] r3[14] re clk 2 +.latch r2[15] r3[15] re clk 2 +.latch r2[16] r3[16] re clk 2 +.latch r2[17] r3[17] re clk 2 +.latch r2[18] r3[18] re clk 2 +.latch r2[19] r3[19] re clk 2 +.latch r2[20] r3[20] re clk 2 +.latch r2[21] r3[21] re clk 2 +.latch r2[22] r3[22] re clk 2 +.latch r2[23] r3[23] re clk 2 +.latch r2[24] r3[24] re clk 2 +.latch r2[25] r3[25] re clk 2 +.latch r2[26] r3[26] re clk 2 +.latch r2[27] r3[27] re clk 2 +.latch r2[28] r3[28] re clk 2 +.latch r2[29] r3[29] re clk 2 +.latch r2[30] r3[30] re clk 2 +.latch r2[31] r3[31] re clk 2 +.latch r1[0] r2[0] re clk 2 +.latch r1[1] r2[1] re clk 2 +.latch r1[2] r2[2] re clk 2 +.latch r1[3] r2[3] re clk 2 +.latch r1[4] r2[4] re clk 2 +.latch r1[5] r2[5] re clk 2 +.latch r1[6] r2[6] re clk 2 +.latch r1[7] r2[7] re clk 2 +.latch r1[8] r2[8] re clk 2 +.latch r1[9] r2[9] re clk 2 +.latch r1[10] r2[10] re clk 2 +.latch r1[11] r2[11] re clk 2 +.latch r1[12] r2[12] re clk 2 +.latch r1[13] r2[13] re clk 2 +.latch r1[14] r2[14] re clk 2 +.latch r1[15] r2[15] re clk 2 +.latch r1[16] r2[16] re clk 2 +.latch r1[17] r2[17] re clk 2 +.latch r1[18] r2[18] re clk 2 +.latch r1[19] r2[19] re clk 2 +.latch r1[20] r2[20] re clk 2 +.latch r1[21] r2[21] re clk 2 +.latch r1[22] r2[22] re clk 2 +.latch r1[23] r2[23] re clk 2 +.latch r1[24] r2[24] re clk 2 +.latch r1[25] r2[25] re clk 2 +.latch r1[26] r2[26] re clk 2 +.latch r1[27] r2[27] re clk 2 +.latch r1[28] r2[28] re clk 2 +.latch r1[29] r2[29] re clk 2 +.latch r1[30] r2[30] re clk 2 +.latch r1[31] r2[31] re clk 2 +.latch inp[0] r1[0] re clk 2 +.latch inp[1] r1[1] re clk 2 +.latch inp[2] r1[2] re clk 2 +.latch inp[3] r1[3] re clk 2 +.latch inp[4] r1[4] re clk 2 +.latch inp[5] r1[5] re clk 2 +.latch inp[6] r1[6] re clk 2 +.latch inp[7] r1[7] re clk 2 +.latch inp[8] r1[8] re clk 2 +.latch inp[9] r1[9] re clk 2 +.latch inp[10] r1[10] re clk 2 +.latch inp[11] r1[11] re clk 2 +.latch inp[12] r1[12] re clk 2 +.latch inp[13] r1[13] re clk 2 +.latch inp[14] r1[14] re clk 2 +.latch inp[15] r1[15] re clk 2 +.latch inp[16] r1[16] re clk 2 +.latch inp[17] r1[17] re clk 2 +.latch inp[18] r1[18] re clk 2 +.latch inp[19] r1[19] re clk 2 +.latch inp[20] r1[20] re clk 2 +.latch inp[21] r1[21] re clk 2 +.latch inp[22] r1[22] re clk 2 +.latch inp[23] r1[23] re clk 2 +.latch inp[24] r1[24] re clk 2 +.latch inp[25] r1[25] re clk 2 +.latch inp[26] r1[26] re clk 2 +.latch inp[27] r1[27] re clk 2 +.latch inp[28] r1[28] re clk 2 +.latch inp[29] r1[29] re clk 2 +.latch inp[30] r1[30] re clk 2 +.latch inp[31] r1[31] re clk 2 +.latch r3[0] r4[0] re clk 2 +.latch r3[1] r4[1] re clk 2 +.latch r3[2] r4[2] re clk 2 +.latch r3[3] r4[3] re clk 2 +.latch r3[4] r4[4] re clk 2 +.latch r3[5] r4[5] re clk 2 +.latch r3[6] r4[6] re clk 2 +.latch r3[7] r4[7] re clk 2 +.latch r3[8] r4[8] re clk 2 +.latch r3[9] r4[9] re clk 2 +.latch r3[10] r4[10] re clk 2 +.latch r3[11] r4[11] re clk 2 +.latch r3[12] r4[12] re clk 2 +.latch r3[13] r4[13] re clk 2 +.latch r3[14] r4[14] re clk 2 +.latch r3[15] r4[15] re clk 2 +.latch r3[16] r4[16] re clk 2 +.latch r3[17] r4[17] re clk 2 +.latch r3[18] r4[18] re clk 2 +.latch r3[19] r4[19] re clk 2 +.latch r3[20] r4[20] re clk 2 +.names r4[0] out[0] +1 1 +.names r4[1] out[1] +1 1 +.names r4[2] out[2] +1 1 +.names r4[3] out[3] +1 1 +.names r4[4] out[4] +1 1 +.names r4[5] out[5] +1 1 +.names r4[6] out[6] +1 1 +.names r4[7] out[7] +1 1 +.names r4[8] out[8] +1 1 +.names r4[9] out[9] +1 1 +.names r4[10] out[10] +1 1 +.names r4[11] out[11] +1 1 +.names r4[12] out[12] +1 1 +.names r4[13] out[13] +1 1 +.names r4[14] out[14] +1 1 +.names r4[15] out[15] +1 1 +.names r4[16] out[16] +1 1 +.names r4[17] out[17] +1 1 +.names r4[18] out[18] +1 1 +.names r4[19] out[19] +1 1 +.names r4[20] out[20] +1 1 +.names r4[21] out[21] +1 1 +.names r4[22] out[22] +1 1 +.names r4[23] out[23] +1 1 +.names r4[24] out[24] +1 1 +.names r4[25] out[25] +1 1 +.names r4[26] out[26] +1 1 +.names r4[27] out[27] +1 1 +.names r4[28] out[28] +1 1 +.names r4[29] out[29] +1 1 +.names r4[30] out[30] +1 1 +.names r4[31] out[31] +1 1 +.end diff --git a/vtr_flow/scripts/python_libs/vtr/flow.py b/vtr_flow/scripts/python_libs/vtr/flow.py index e5ceb323582..9a62e1334cd 100644 --- a/vtr_flow/scripts/python_libs/vtr/flow.py +++ b/vtr_flow/scripts/python_libs/vtr/flow.py @@ -13,10 +13,10 @@ class VtrStage(Enum): Enum class for the VTR stages\ """ - odin = 1 - abc = 2 - ace = 3 - vpr = 4 + ODIN = 1 + ABC = 2 + ACE = 3 + VPR = 4 def __le__(self, other): if self.__class__ is other.__class__: @@ -34,8 +34,8 @@ def run( architecture_file, circuit_file, power_tech_file=None, - start_stage=VtrStage.odin, - end_stage=VtrStage.vpr, + start_stage=VtrStage.ODIN, + end_stage=VtrStage.VPR, command_runner=vtr.CommandRunner(), temp_dir=Path("./temp"), odin_args=None, @@ -175,7 +175,7 @@ def run( # # RTL Elaboration & Synthesis # - if should_run_stage(VtrStage.odin, start_stage, end_stage) and circuit_file.suffixes != ".blif": + if should_run_stage(VtrStage.ODIN, start_stage, end_stage) and circuit_file.suffixes != ".blif": vtr.odin.run( architecture_copy, next_stage_netlist, @@ -195,7 +195,7 @@ def run( # # Logic Optimization & Technology Mapping # - if should_run_stage(VtrStage.abc, start_stage, end_stage): + if should_run_stage(VtrStage.ABC, start_stage, end_stage): vtr.abc.run( architecture_copy, next_stage_netlist, @@ -216,7 +216,7 @@ def run( if power_tech_file: # The user provided a tech file, so do power analysis - if should_run_stage(VtrStage.ace, start_stage, end_stage): + if should_run_stage(VtrStage.ACE, start_stage, end_stage): vtr.ace.run( next_stage_netlist, old_netlist=post_odin_netlist, @@ -241,7 +241,7 @@ def run( # # Pack/Place/Route # - if should_run_stage(VtrStage.vpr, start_stage, end_stage): + if should_run_stage(VtrStage.VPR, start_stage, end_stage): # Copy the input netlist for input to vpr shutil.copyfile(str(next_stage_netlist), str(pre_vpr_netlist)) route_fixed_w = "route_chan_width" in vpr_args diff --git a/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py b/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py index 174eb88956a..6b371ea6f02 100755 --- a/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py +++ b/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py @@ -566,5 +566,5 @@ def find_latest_run_dir(config): if __name__ == "__main__": - retval = vtr_command_main(sys.argv[1:]) - sys.exit(retval) + RETVAL = vtr_command_main(sys.argv[1:]) + sys.exit(RETVAL) diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py index a1f515a9e84..13b1346caed 100755 --- a/vtr_flow/scripts/run_vtr_flow.py +++ b/vtr_flow/scripts/run_vtr_flow.py @@ -19,6 +19,8 @@ BASIC_VERBOSITY = 1 +VTR_STAGES = ["odin", "abc", "ace", "vpr"] + # pylint: disable=too-few-public-methods class VtrStageArgparseAction(argparse.Action): """ @@ -27,13 +29,13 @@ class VtrStageArgparseAction(argparse.Action): def __call__(self, parser, namespace, value, option_string=None): if value == "odin": - setattr(namespace, self.dest, vtr.VtrStage.odin) + setattr(namespace, self.dest, vtr.VtrStage.ODIN) elif value == "abc": - setattr(namespace, self.dest, vtr.VtrStage.abc) + setattr(namespace, self.dest, vtr.VtrStage.ABC) elif value == "vpr": - setattr(namespace, self.dest, vtr.VtrStage.vpr) + setattr(namespace, self.dest, vtr.VtrStage.VPR) elif value == "lec": - setattr(namespace, self.dest, vtr.VtrStage.lec) + setattr(namespace, self.dest, vtr.VtrStage.LEC) else: raise argparse.ArgumentError(self, "Invalid VTR stage '" + value + "'") @@ -107,8 +109,8 @@ def vtr_command_argparser(prog=None): parser.add_argument( "-start", "-starting_stage", - choices=str(list(vtr.VtrStage)), - default=vtr.VtrStage.odin, + choices=VTR_STAGES, + default=vtr.VtrStage.ODIN, action=VtrStageArgparseAction, help="Starting stage of the VTR flow.", ) @@ -129,8 +131,8 @@ def vtr_command_argparser(prog=None): parser.add_argument( "-end", "-ending_stage", - choices=str(list(vtr.VtrStage)), - default=vtr.VtrStage.vpr, + choices=VTR_STAGES, + default=vtr.VtrStage.VPR, action=VtrStageArgparseAction, help="Ending stage of the VTR flow.", ) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/config.txt new file mode 100644 index 00000000000..af567cfcfa4 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/config.txt @@ -0,0 +1,28 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/microbenchmarks + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=reg_4x32.blif + +# Add architectures to list to sweep +arch_list_add=k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Script parameters +script_params_common = -starting_stage vpr +script_params = --pack diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt new file mode 100644 index 00000000000..96899233e90 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time placement_technique reward uniform_percentage median_percentage wmedian_percentage wcent_percentage fr_percentage critUni_percentage centroid_percentage +k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml reg_4x32.blif common 0.65 -1 -1 -1 -1 -1 -1 -1 -1 -1 32 33 -1 -1 success v8.0.0-3321-g5c3070c45-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.4.0 on Linux-4.15.0-45-generic x86_64 2021-02-08T13:52:56 mkurc-PC /home/mkurc/Repos/google-vtr-verilog-to-routing 77184 33 32 161 193 1 65 97 34 34 1156 -1 32x32 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000337066 0.000266689 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 94c10f6b2ad..8061f5644db 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -29,6 +29,7 @@ regression_tests/vtr_reg_strong/strong_fix_pins_random regression_tests/vtr_reg_strong/strong_global_routing regression_tests/vtr_reg_strong/strong_manual_annealing regression_tests/vtr_reg_strong/strong_pack +regression_tests/vtr_reg_strong/strong_pack_modes regression_tests/vtr_reg_strong/strong_pack_and_place regression_tests/vtr_reg_strong/strong_fc_abs regression_tests/vtr_reg_strong/strong_multiclock