diff --git a/ODIN_II/SRC/odin_ii.cpp b/ODIN_II/SRC/odin_ii.cpp
index 62e89268a04..6cdfd7356c4 100644
--- a/ODIN_II/SRC/odin_ii.cpp
+++ b/ODIN_II/SRC/odin_ii.cpp
@@ -572,7 +572,7 @@ void get_options(int argc, char** argv) {
global_args.verilog_files.value().size() > 0 //have a verilog input list
})) {
parser.print_usage();
- error_message(PARSE_ARGS, unknown_location, "%s", "Must include only one of either:\n\ta config file(-c)\n\ta blif file(-b)\n\ta verilog file(-V)\n");
+ warning_message(PARSE_ARGS, unknown_location, "%s", "Must include only one of either:\n\ta config file(-c)\n\ta blif file(-b)\n\ta verilog file(-V)\nUnless is used for infrastructure directly\n");
}
//adjust thread count
diff --git a/ODIN_II/SRC/read_xml_config_file.cpp b/ODIN_II/SRC/read_xml_config_file.cpp
index d5a8c2740b0..bbbdf14cd46 100644
--- a/ODIN_II/SRC/read_xml_config_file.cpp
+++ b/ODIN_II/SRC/read_xml_config_file.cpp
@@ -44,6 +44,8 @@ void read_debug_switches(pugi::xml_node a_node, config_t* config, const pugiutil
void read_optimizations(pugi::xml_node a_node, config_t* config, const pugiutil::loc_data& loc_data);
void set_default_optimization_settings(config_t* config);
+extern HardSoftLogicMixer* mixer;
+
/*-------------------------------------------------------------------------
* (function: read_config_file)
* This reads an XML config file that specifies what we will do in the tool.
@@ -217,6 +219,27 @@ void read_optimizations(pugi::xml_node a_node, config_t* config, const pugiutil:
config->split_hard_multiplier = 1;
}
+ child = get_single_child(a_node, "mix_soft_hard_blocks", loc_data, OPTIONAL);
+ if (child != NULL) {
+ prop = get_attribute(child, "mults_ratio", loc_data, OPTIONAL).as_string(NULL);
+ if (prop != NULL) {
+ float ratio = atof(prop);
+ if (ratio >= 0.0 && ratio <= 1.0) {
+ delete mixer->_opts[MULTIPLY];
+ mixer->_opts[MULTIPLY] = new MultsOpt(ratio);
+ }
+ }
+
+ prop = get_attribute(child, "exact_mults", loc_data, OPTIONAL).as_string(NULL);
+ if (prop != NULL) {
+ int exact = atoi(prop);
+ if (exact >= 0) {
+ delete mixer->_opts[MULTIPLY];
+ mixer->_opts[MULTIPLY] = new MultsOpt(exact);
+ }
+ }
+ }
+
child = get_single_child(a_node, "memory", loc_data, OPTIONAL);
if (child != NULL) {
prop = get_attribute(child, "split_memory_width", loc_data, OPTIONAL).as_string(NULL);
diff --git a/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/config_file_half.xml b/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/config_file_half.xml
new file mode 100644
index 00000000000..2db003131d9
--- /dev/null
+++ b/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/config_file_half.xml
@@ -0,0 +1,15 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/simulation_result.json b/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/simulation_result.json
new file mode 100644
index 00000000000..799b7c15d74
--- /dev/null
+++ b/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/simulation_result.json
@@ -0,0 +1,368 @@
+{
+ "config_file_half/bm_base_multiply/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_base_multiply/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "blif": "bm_base_multiply.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 131.5,
+ "exec_time(ms)": 1187.5,
+ "simulation_time(ms)": 1051.4,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 47,
+ "Po": 78,
+ "logic element": 454,
+ "latch": 71,
+ "Multiplier": 1,
+ "generic logic size": 4,
+ "Longest Path": 25,
+ "Average Path": 5,
+ "Estimated LUTs": 454,
+ "Total Node": 527
+ },
+ "config_file_half/bm_base_multiply/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_base_multiply/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "blif": "bm_base_multiply.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 144.6,
+ "exec_time(ms)": 2065.9,
+ "simulation_time(ms)": 1986.3,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 47,
+ "Po": 78,
+ "logic element": 795,
+ "latch": 71,
+ "generic logic size": 6,
+ "Longest Path": 26,
+ "Average Path": 6,
+ "Estimated LUTs": 795,
+ "Total Node": 867
+ },
+ "config_file_half/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "blif": "bm_match1_str_arch.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 309.5,
+ "exec_time(ms)": 2995.4,
+ "simulation_time(ms)": 2725.4,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 88,
+ "Po": 144,
+ "logic element": 1775,
+ "latch": 72,
+ "Multiplier": 1,
+ "generic logic size": 4,
+ "Longest Path": 74,
+ "Average Path": 5,
+ "Estimated LUTs": 1775,
+ "Total Node": 1849
+ },
+ "config_file_half/bm_match1_str_arch/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_match1_str_arch/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "blif": "bm_match1_str_arch.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 612.7,
+ "exec_time(ms)": 4697.8,
+ "simulation_time(ms)": 4462.7,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 88,
+ "Po": 144,
+ "logic element": 3872,
+ "latch": 72,
+ "generic logic size": 6,
+ "Longest Path": 74,
+ "Average Path": 6,
+ "Estimated LUTs": 3872,
+ "Total Node": 3945
+ },
+ "config_file_half/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "blif": "bm_match2_str_arch.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 199.6,
+ "exec_time(ms)": 2072,
+ "simulation_time(ms)": 1833.1,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 54,
+ "Po": 99,
+ "logic element": 565,
+ "latch": 54,
+ "Adder": 173,
+ "Multiplier": 2,
+ "generic logic size": 4,
+ "Longest Path": 31,
+ "Average Path": 6,
+ "Estimated LUTs": 565,
+ "Total Node": 795
+ },
+ "config_file_half/bm_match2_str_arch/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_match2_str_arch/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "blif": "bm_match2_str_arch.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 489.8,
+ "exec_time(ms)": 3950.4,
+ "simulation_time(ms)": 3753.8,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 54,
+ "Po": 99,
+ "logic element": 3211,
+ "latch": 54,
+ "generic logic size": 6,
+ "Longest Path": 32,
+ "Average Path": 7,
+ "Estimated LUTs": 3211,
+ "Total Node": 3266
+ },
+ "config_file_half/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "blif": "bm_match3_str_arch.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 119.2,
+ "exec_time(ms)": 1043.6,
+ "simulation_time(ms)": 825.4,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 54,
+ "Po": 54,
+ "logic element": 287,
+ "latch": 54,
+ "Adder": 50,
+ "generic logic size": 4,
+ "Longest Path": 31,
+ "Average Path": 5,
+ "Estimated LUTs": 287,
+ "Total Node": 392
+ },
+ "config_file_half/bm_match3_str_arch/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_match3_str_arch/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "blif": "bm_match3_str_arch.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 91.3,
+ "exec_time(ms)": 833.6,
+ "simulation_time(ms)": 777.4,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 54,
+ "Po": 54,
+ "logic element": 375,
+ "latch": 54,
+ "generic logic size": 6,
+ "Longest Path": 58,
+ "Average Path": 5,
+ "Estimated LUTs": 375,
+ "Total Node": 430
+ },
+ "config_file_half/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "blif": "bm_match4_str_arch.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 192.9,
+ "exec_time(ms)": 2030.2,
+ "simulation_time(ms)": 1830.6,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 51,
+ "Po": 216,
+ "logic element": 604,
+ "latch": 108,
+ "Adder": 74,
+ "Multiplier": 1,
+ "generic logic size": 4,
+ "Longest Path": 48,
+ "Average Path": 5,
+ "Estimated LUTs": 604,
+ "Total Node": 788
+ },
+ "config_file_half/bm_match4_str_arch/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_match4_str_arch/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "blif": "bm_match4_str_arch.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 238.4,
+ "exec_time(ms)": 2740.3,
+ "simulation_time(ms)": 2620.9,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 51,
+ "Po": 216,
+ "logic element": 1367,
+ "latch": 108,
+ "generic logic size": 6,
+ "Longest Path": 49,
+ "Average Path": 5,
+ "Estimated LUTs": 1367,
+ "Total Node": 1476
+ },
+ "config_file_half/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "blif": "bm_match5_str_arch.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 209.4,
+ "exec_time(ms)": 2198.2,
+ "simulation_time(ms)": 1997.2,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 90,
+ "Po": 54,
+ "logic element": 753,
+ "latch": 54,
+ "Adder": 125,
+ "Multiplier": 3,
+ "generic logic size": 4,
+ "Longest Path": 32,
+ "Average Path": 5,
+ "Estimated LUTs": 753,
+ "Total Node": 936
+ },
+ "config_file_half/bm_match5_str_arch/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_match5_str_arch/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "blif": "bm_match5_str_arch.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 319.7,
+ "exec_time(ms)": 3413.6,
+ "simulation_time(ms)": 3220.1,
+ "test_coverage(%)": 100,
+ "Latch Drivers": 1,
+ "Pi": 90,
+ "Po": 54,
+ "logic element": 2147,
+ "latch": 54,
+ "generic logic size": 6,
+ "Longest Path": 34,
+ "Average Path": 6,
+ "Estimated LUTs": 2147,
+ "Total Node": 2202
+ },
+ "config_file_half/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "blif": "multiply_hard_block.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 59.9,
+ "exec_time(ms)": 118.1,
+ "simulation_time(ms)": 17.4,
+ "test_coverage(%)": 100,
+ "Pi": 8,
+ "Po": 8,
+ "logic element": 17,
+ "Multiplier": 1,
+ "generic logic size": 4,
+ "Longest Path": 7,
+ "Average Path": 4,
+ "Estimated LUTs": 17,
+ "Total Node": 18
+ },
+ "config_file_half/twobits_arithmetic_multiply/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/twobits_arithmetic_multiply/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "blif": "twobits_arithmetic_multiply.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 55.1,
+ "exec_time(ms)": 101.8,
+ "simulation_time(ms)": 5.6,
+ "test_coverage(%)": 92.5,
+ "Latch Drivers": 1,
+ "Pi": 5,
+ "Po": 5,
+ "logic element": 21,
+ "latch": 4,
+ "generic logic size": 4,
+ "Longest Path": 9,
+ "Average Path": 5,
+ "Estimated LUTs": 21,
+ "Total Node": 26
+ },
+ "config_file_half/twobits_arithmetic_multiply/k6_N10_40nm": {
+ "test_name": "config_file_half/twobits_arithmetic_multiply/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "blif": "twobits_arithmetic_multiply.blif",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 37.9,
+ "exec_time(ms)": 19.4,
+ "simulation_time(ms)": 5.7,
+ "test_coverage(%)": 92.5,
+ "Latch Drivers": 1,
+ "Pi": 5,
+ "Po": 5,
+ "logic element": 21,
+ "latch": 4,
+ "generic logic size": 6,
+ "Longest Path": 9,
+ "Average Path": 5,
+ "Estimated LUTs": 21,
+ "Total Node": 26
+ },
+ "DEFAULT": {
+ "test_name": "n/a",
+ "architecture": "n/a",
+ "blif": "n/a",
+ "exit": 0,
+ "leaks": 0,
+ "errors": [],
+ "warnings": [],
+ "expectation": [],
+ "max_rss(MiB)": -1,
+ "exec_time(ms)": -1,
+ "simulation_time(ms)": -1,
+ "test_coverage(%)": -1,
+ "Latch Drivers": 0,
+ "Pi": 0,
+ "Po": 0,
+ "logic element": 0,
+ "latch": 0,
+ "Adder": -1,
+ "Multiplier": -1,
+ "Memory": -1,
+ "Hard Ip": -1,
+ "generic logic size": -1,
+ "Longest Path": 0,
+ "Average Path": 0,
+ "Estimated LUTs": 0,
+ "Total Node": 0
+ }
+}
diff --git a/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/synthesis_result.json
new file mode 100644
index 00000000000..62d2d513368
--- /dev/null
+++ b/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/synthesis_result.json
@@ -0,0 +1,379 @@
+{
+ "config_file_half/bm_base_multiply/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_base_multiply/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "verilog": "bm_base_multiply.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 61.3,
+ "exec_time(ms)": 110.6,
+ "synthesis_time(ms)": 30.9,
+ "Latch Drivers": 1,
+ "Pi": 47,
+ "Po": 78,
+ "logic element": 376,
+ "latch": 71,
+ "Adder": 0,
+ "Multiplier": 1,
+ "Memory": 0,
+ "generic logic size": 4,
+ "Longest Path": 24,
+ "Average Path": 4,
+ "Estimated LUTs": 376,
+ "Total Node": 449
+ },
+ "config_file_half/bm_base_multiply/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_base_multiply/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "verilog": "bm_base_multiply.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 45.5,
+ "exec_time(ms)": 33,
+ "synthesis_time(ms)": 24.4,
+ "Latch Drivers": 1,
+ "Pi": 47,
+ "Po": 78,
+ "logic element": 717,
+ "latch": 71,
+ "generic logic size": 6,
+ "Longest Path": 25,
+ "Average Path": 5,
+ "Estimated LUTs": 717,
+ "Total Node": 789
+ },
+ "config_file_half/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "verilog": "bm_match1_str_arch.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 65.7,
+ "exec_time(ms)": 113.5,
+ "synthesis_time(ms)": 35.3,
+ "Latch Drivers": 1,
+ "Pi": 88,
+ "Po": 144,
+ "logic element": 1631,
+ "latch": 72,
+ "Adder": 0,
+ "Multiplier": 1,
+ "Memory": 0,
+ "generic logic size": 4,
+ "Longest Path": 73,
+ "Average Path": 4,
+ "Estimated LUTs": 1631,
+ "Total Node": 1705
+ },
+ "config_file_half/bm_match1_str_arch/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_match1_str_arch/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "verilog": "bm_match1_str_arch.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 57.9,
+ "exec_time(ms)": 85.5,
+ "synthesis_time(ms)": 76.8,
+ "Latch Drivers": 1,
+ "Pi": 88,
+ "Po": 144,
+ "logic element": 3728,
+ "latch": 72,
+ "generic logic size": 6,
+ "Longest Path": 73,
+ "Average Path": 5,
+ "Estimated LUTs": 3728,
+ "Total Node": 3801
+ },
+ "config_file_half/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "verilog": "bm_match2_str_arch.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 61.4,
+ "exec_time(ms)": 104.1,
+ "synthesis_time(ms)": 18.1,
+ "Latch Drivers": 1,
+ "Pi": 54,
+ "Po": 99,
+ "logic element": 466,
+ "latch": 54,
+ "Adder": 173,
+ "Multiplier": 2,
+ "Memory": 0,
+ "generic logic size": 4,
+ "Longest Path": 30,
+ "Average Path": 5,
+ "Estimated LUTs": 466,
+ "Total Node": 696
+ },
+ "config_file_half/bm_match2_str_arch/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_match2_str_arch/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "verilog": "bm_match2_str_arch.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 53.3,
+ "exec_time(ms)": 71.2,
+ "synthesis_time(ms)": 62.3,
+ "Latch Drivers": 1,
+ "Pi": 54,
+ "Po": 99,
+ "logic element": 3112,
+ "latch": 54,
+ "generic logic size": 6,
+ "Longest Path": 31,
+ "Average Path": 6,
+ "Estimated LUTs": 3112,
+ "Total Node": 3167
+ },
+ "config_file_half/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "verilog": "bm_match3_str_arch.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 59.3,
+ "exec_time(ms)": 87.1,
+ "synthesis_time(ms)": 10,
+ "Latch Drivers": 1,
+ "Pi": 54,
+ "Po": 54,
+ "logic element": 233,
+ "latch": 54,
+ "Adder": 50,
+ "Multiplier": 0,
+ "Memory": 0,
+ "generic logic size": 4,
+ "Longest Path": 30,
+ "Average Path": 4,
+ "Estimated LUTs": 233,
+ "Total Node": 338
+ },
+ "config_file_half/bm_match3_str_arch/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_match3_str_arch/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "verilog": "bm_match3_str_arch.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 41.8,
+ "exec_time(ms)": 21,
+ "synthesis_time(ms)": 12.7,
+ "Latch Drivers": 1,
+ "Pi": 54,
+ "Po": 54,
+ "logic element": 321,
+ "latch": 54,
+ "generic logic size": 6,
+ "Longest Path": 57,
+ "Average Path": 4,
+ "Estimated LUTs": 321,
+ "Total Node": 376
+ },
+ "config_file_half/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "verilog": "bm_match4_str_arch.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 62.2,
+ "exec_time(ms)": 111.1,
+ "synthesis_time(ms)": 23.6,
+ "Latch Drivers": 1,
+ "Pi": 51,
+ "Po": 216,
+ "logic element": 388,
+ "latch": 108,
+ "Adder": 74,
+ "Multiplier": 1,
+ "Memory": 0,
+ "generic logic size": 4,
+ "Longest Path": 47,
+ "Average Path": 4,
+ "Estimated LUTs": 388,
+ "Total Node": 572
+ },
+ "config_file_half/bm_match4_str_arch/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_match4_str_arch/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "verilog": "bm_match4_str_arch.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 47.6,
+ "exec_time(ms)": 42.2,
+ "synthesis_time(ms)": 34,
+ "Latch Drivers": 1,
+ "Pi": 51,
+ "Po": 216,
+ "logic element": 1151,
+ "latch": 108,
+ "generic logic size": 6,
+ "Longest Path": 48,
+ "Average Path": 4,
+ "Estimated LUTs": 1151,
+ "Total Node": 1260
+ },
+ "config_file_half/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "verilog": "bm_match5_str_arch.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 61.6,
+ "exec_time(ms)": 103,
+ "synthesis_time(ms)": 22.6,
+ "Latch Drivers": 1,
+ "Pi": 90,
+ "Po": 54,
+ "logic element": 699,
+ "latch": 54,
+ "Adder": 125,
+ "Multiplier": 3,
+ "Memory": 0,
+ "generic logic size": 4,
+ "Longest Path": 31,
+ "Average Path": 4,
+ "Estimated LUTs": 699,
+ "Total Node": 882
+ },
+ "config_file_half/bm_match5_str_arch/k6_N10_40nm": {
+ "test_name": "config_file_half/bm_match5_str_arch/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "verilog": "bm_match5_str_arch.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 48.5,
+ "exec_time(ms)": 47.4,
+ "synthesis_time(ms)": 39.1,
+ "Latch Drivers": 1,
+ "Pi": 90,
+ "Po": 54,
+ "logic element": 2093,
+ "latch": 54,
+ "generic logic size": 6,
+ "Longest Path": 33,
+ "Average Path": 5,
+ "Estimated LUTs": 2093,
+ "Total Node": 2148
+ },
+ "config_file_half/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "verilog": "multiply_hard_block.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:",
+ "multiply_hard_block.v:9:2 [AST] Attempting to convert this instance to a hard block (multiply) - unnamed port connections will be matched according to hard block specification and may produce unexpected results"
+ ],
+ "max_rss(MiB)": 55.8,
+ "exec_time(ms)": 57.1,
+ "synthesis_time(ms)": 1.7,
+ "Pi": 8,
+ "Po": 8,
+ "logic element": 9,
+ "Adder": 0,
+ "Multiplier": 1,
+ "Memory": 0,
+ "generic logic size": 4,
+ "Longest Path": 6,
+ "Average Path": 3,
+ "Estimated LUTs": 9,
+ "Total Node": 10
+ },
+ "config_file_half/multiply_hard_block/k6_N10_40nm": {
+ "test_name": "config_file_half/multiply_hard_block/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "verilog": "multiply_hard_block.v",
+ "exit": 134,
+ "errors": [
+ "multiply_hard_block.v:8:1 [AST] Can't find module name multiply"
+ ],
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ]
+ },
+ "config_file_half/twobits_arithmetic_multiply/k6_frac_N10_frac_chain_mem32K_40nm": {
+ "test_name": "config_file_half/twobits_arithmetic_multiply/k6_frac_N10_frac_chain_mem32K_40nm",
+ "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+ "verilog": "twobits_arithmetic_multiply.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 56.2,
+ "exec_time(ms)": 60.6,
+ "synthesis_time(ms)": 1.7,
+ "Latch Drivers": 1,
+ "Pi": 5,
+ "Po": 5,
+ "logic element": 16,
+ "latch": 4,
+ "Adder": 0,
+ "Multiplier": 0,
+ "Memory": 0,
+ "generic logic size": 4,
+ "Longest Path": 8,
+ "Average Path": 4,
+ "Estimated LUTs": 16,
+ "Total Node": 21
+ },
+ "config_file_half/twobits_arithmetic_multiply/k6_N10_40nm": {
+ "test_name": "config_file_half/twobits_arithmetic_multiply/k6_N10_40nm",
+ "architecture": "k6_N10_40nm.xml",
+ "verilog": "twobits_arithmetic_multiply.v",
+ "warnings": [
+ "[PARSE_ARGS] Must include only one of either:"
+ ],
+ "max_rss(MiB)": 38.8,
+ "exec_time(ms)": 10.8,
+ "synthesis_time(ms)": 2.6,
+ "Latch Drivers": 1,
+ "Pi": 5,
+ "Po": 5,
+ "logic element": 16,
+ "latch": 4,
+ "generic logic size": 6,
+ "Longest Path": 8,
+ "Average Path": 4,
+ "Estimated LUTs": 16,
+ "Total Node": 21
+ },
+ "DEFAULT": {
+ "test_name": "n/a",
+ "architecture": "n/a",
+ "verilog": "n/a",
+ "exit": 0,
+ "leaks": 0,
+ "errors": [],
+ "warnings": [],
+ "expectation": [],
+ "max_rss(MiB)": -1,
+ "exec_time(ms)": -1,
+ "synthesis_time(ms)": -1,
+ "Latch Drivers": 0,
+ "Pi": 0,
+ "Po": 0,
+ "logic element": 0,
+ "latch": 0,
+ "Adder": -1,
+ "Multiplier": -1,
+ "Memory": -1,
+ "Hard Ip": -1,
+ "generic logic size": -1,
+ "Longest Path": 0,
+ "Average Path": 0,
+ "Estimated LUTs": 0,
+ "Total Node": 0
+ }
+}
diff --git a/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/task.conf b/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/task.conf
new file mode 100644
index 00000000000..803b7a8df3b
--- /dev/null
+++ b/ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/task.conf
@@ -0,0 +1,33 @@
+##############################################
+# Configuration file for running experiments
+##############################################
+# Path to directory of circuits to use
+# setup the architecture
+archs_dir=../vtr_flow/arch/timing
+
+# hard adder and frac mul
+arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
+# frac mul
+arch_list_add=k6_frac_N10_mem32k_40nm.xml
+# mul
+arch_list_add=k6_N10_mem32k_40nm.xml
+# no hard block
+arch_list_add=k6_N10_40nm.xml
+
+# setup the circuits
+circuits_dir=regression_test/benchmark/verilog
+
+# unit test
+circuit_list_add=operators/twobits_arithmetic_multiply.v
+# simple wide multiplication
+circuit_list_add=micro/bm_base_multiply.v
+# harblock mul
+circuit_list_add=micro/multiply_hard_block.v
+# complex mutliplication
+circuit_list_add=micro/bm_match[012345]_str_arch.v
+
+synthesis_params= -c regression_test/benchmark/task/mixing_optimization/config_file_half/config_file_half.xml
+simulation_params= -c regression_test/benchmark/task/mixing_optimization/config_file_half/config_file_half.xml
+
+synthesis_parse_file=regression_test/parse_result/conf/synth.toml
+simulation_parse_file=regression_test/parse_result/conf/sim.toml
diff --git a/doc/src/odin/dev_guide/regression_test.md b/doc/src/odin/dev_guide/regression_test.md
index 0dd0bdb09d7..4372403285e 100644
--- a/doc/src/odin/dev_guide/regression_test.md
+++ b/doc/src/odin/dev_guide/regression_test.md
@@ -303,7 +303,7 @@ The micro regression tests targets hards blocks and pieces that can be easily in
### mixing_optimization
-The mixing optimization regression tests targets mixing implementations for operations implementable in hard blocks and their soft logic counterparts that can be can be easily instantiated in architectures.
+The mixing optimization regression tests targets mixing implementations for operations implementable in hard blocks and their soft logic counterparts that can be can be easily instantiated in architectures. The tests support extensive command line coverage, as well as provide infrastructure to enable the optimization from an .xml configuration file, require for using the optimization as a part of VTR synthesis flow.
### operators
@@ -433,6 +433,11 @@ benchmark
│ │ | ├── simulation_result.json
│ │ | |── synthesis_result.json
│ │ | └── task.conf
+ | | ├── config_file_half
+ │ │ | ├── config_file_half.xml
+ │ │ | ├── simulation_result.json
+ │ │ | |── synthesis_result.json
+ │ │ | └── task.conf
│ ├── operators
│ │ ├── simulation_result.json
│ │ ├── synthesis_result.json
diff --git a/doc/src/vtr/run_vtr_flow.rst b/doc/src/vtr/run_vtr_flow.rst
index 6ce79a8e0ca..24eff4020d5 100644
--- a/doc/src/vtr/run_vtr_flow.rst
+++ b/doc/src/vtr/run_vtr_flow.rst
@@ -173,3 +173,13 @@ Detailed Command-line Options
Tells ODIN II to connect the first cin in an adder/subtractor chain
to a global gnd/vdd net. Instead of creating a dummy adder to generate
the input signal of the first cin port of the chain.
+
+.. option:: -odin_xml
+
+ Tells VTR flow to use a custom ODIN II configuration value. The default
+ behavior is to use the vtr_flow/misc/basic_odin_config_split.xml.
+ Instead, an alternative config file might be supplied; compare the
+ default and vtr_flow/misc/custom_odin_config_no_mults.xml for usage
+ scenarios. This option is needed for running the entire VTR flow with
+ additional parameters for ODIN II that are provided from within the
+ .xml file.
diff --git a/vtr_flow/misc/custom_odin_config_no_mults.xml b/vtr_flow/misc/custom_odin_config_no_mults.xml
new file mode 100644
index 00000000000..f09b0426f6f
--- /dev/null
+++ b/vtr_flow/misc/custom_odin_config_no_mults.xml
@@ -0,0 +1,42 @@
+
+
+
+
+
+
+ XXX
+
+
+
+
+
+
+ +
+
+
+
+
+
+
+
+
+
+
+ .
+ 1
+ 1
+
+
diff --git a/vtr_flow/scripts/python_libs/vtr/flow.py b/vtr_flow/scripts/python_libs/vtr/flow.py
index 11f02827c9c..7182da742ac 100644
--- a/vtr_flow/scripts/python_libs/vtr/flow.py
+++ b/vtr_flow/scripts/python_libs/vtr/flow.py
@@ -43,6 +43,7 @@ def run(
vpr_args=None,
keep_intermediate_files=True,
keep_result_files=True,
+ odin_config=None,
min_hard_mult_size=3,
min_hard_adder_size=1,
check_equivalent=False,
@@ -182,6 +183,7 @@ def run(
command_runner=command_runner,
temp_dir=temp_dir,
odin_args=odin_args,
+ odin_config=odin_config,
min_hard_mult_size=min_hard_mult_size,
min_hard_adder_size=min_hard_adder_size,
)
diff --git a/vtr_flow/scripts/python_libs/vtr/odin/odin.py b/vtr_flow/scripts/python_libs/vtr/odin/odin.py
index 7698e5334f4..353e2efa7ed 100644
--- a/vtr_flow/scripts/python_libs/vtr/odin/odin.py
+++ b/vtr_flow/scripts/python_libs/vtr/odin/odin.py
@@ -82,34 +82,34 @@ def run(
if odin_config is None:
odin_base_config = str(paths.odin_cfg_path)
+ else:
+ odin_base_config = str(Path(odin_config).resolve())
+
+ # Copy the config file
+ odin_config = "odin_config.xml"
+ odin_config_full_path = str(temp_dir / odin_config)
+ shutil.copyfile(odin_base_config, odin_config_full_path)
+
+ # Update the config file
+ file_replace(
+ odin_config_full_path,
+ {
+ "XXX": circuit_file.name,
+ "YYY": architecture_file.name,
+ "ZZZ": output_netlist.name,
+ "PPP": determine_memory_addr_width(str(architecture_file)),
+ "MMM": min_hard_mult_size,
+ "AAA": min_hard_adder_size,
+ },
+ )
- # Copy the config file
- odin_config = "odin_config.xml"
- odin_config_full_path = str(temp_dir / odin_config)
- shutil.copyfile(odin_base_config, odin_config_full_path)
-
- # Update the config file
- file_replace(
- odin_config_full_path,
- {
- "XXX": circuit_file.name,
- "YYY": architecture_file.name,
- "ZZZ": output_netlist.name,
- "PPP": determine_memory_addr_width(str(architecture_file)),
- "MMM": min_hard_mult_size,
- "AAA": min_hard_adder_size,
- },
- )
- disable_odin_xml = False
- if "disable_odin_xml" in odin_args:
- disable_odin_xml = True
- del odin_args["disable_odin_xml"]
+ cmd = [odin_exec]
use_odin_simulation = False
+
if "use_odin_simulation" in odin_args:
use_odin_simulation = True
del odin_args["use_odin_simulation"]
- cmd = [odin_exec, "-c", odin_config]
for arg, value in odin_args.items():
if isinstance(value, bool) and value:
cmd += ["--" + arg]
@@ -117,8 +117,11 @@ def run(
cmd += ["--" + arg, str(value)]
else:
pass
+
cmd += ["-U0"]
- if disable_odin_xml:
+
+ if "disable_odin_xml" in odin_args:
+ del odin_args["disable_odin_xml"]
cmd += [
"-a",
architecture_file.name,
@@ -127,6 +130,8 @@ def run(
"-o",
output_netlist.name,
]
+ else:
+ cmd += ["-c", odin_config]
command_runner.run_system_command(
cmd, temp_dir=temp_dir, log_filename=log_filename, indent_depth=1
diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py
index f4361d4da5b..271e48eca97 100755
--- a/vtr_flow/scripts/run_vtr_flow.py
+++ b/vtr_flow/scripts/run_vtr_flow.py
@@ -314,6 +314,12 @@ def vtr_command_argparser(prog=None):
type=int,
help="Tells ODIN II the minimum adder size that should be implemented using hard adder.",
)
+ odin.add_argument(
+ "-odin_xml",
+ default=None,
+ dest="odin_config",
+ help="Supplies Odin with a custom config file for optimizations.",
+ )
#
# VPR arguments
#
@@ -421,6 +427,7 @@ def vtr_command_main(arg_list, prog=None):
keep_result_files=args.keep_result_files,
min_hard_mult_size=args.min_hard_mult_size,
min_hard_adder_size=args.min_hard_adder_size,
+ odin_config=args.odin_config,
check_equivalent=args.check_equivalent,
check_incremental_sta_consistency=args.check_incremental_sta_consistency,
use_old_abc_script=args.use_old_abc_script,
diff --git a/vtr_flow/scripts/run_vtr_task.py b/vtr_flow/scripts/run_vtr_task.py
index ef77d207e2b..ad67d8e445e 100755
--- a/vtr_flow/scripts/run_vtr_task.py
+++ b/vtr_flow/scripts/run_vtr_task.py
@@ -283,7 +283,8 @@ def run_tasks(
if args.parse:
print("\nParsing test results...")
- print("scripts/parse_vtr_task.py -l {}".format(args.list_file[0]))
+ if len(args.list_file) > 0:
+ print("scripts/parse_vtr_task.py -l {}".format(args.list_file[0]))
parse_tasks(configs, jobs)
if args.create_golden: