diff --git a/vpr/packing_pin_util.rpt b/vpr/packing_pin_util.rpt deleted file mode 100644 index 6c8ccb82430..00000000000 --- a/vpr/packing_pin_util.rpt +++ /dev/null @@ -1,65 +0,0 @@ -#Packing pin usage report -Type: io - Input Pin Usage: - Max: 1.00 (0.50) - Avg: 0.34 (0.17) - Min: 0.00 (0.00) - Histogram: - [ 0: 0.2) 41 ( 66.1%) |************************************************ - [ 0.2: 0.4) 0 ( 0.0%) | - [ 0.4: 0.6) 0 ( 0.0%) | - [ 0.6: 0.8) 0 ( 0.0%) | - [ 0.8: 1) 21 ( 33.9%) |************************* - [ 1: 1.2) 0 ( 0.0%) | - [ 1.2: 1.4) 0 ( 0.0%) | - [ 1.4: 1.6) 0 ( 0.0%) | - [ 1.6: 1.8) 0 ( 0.0%) | - [ 1.8: 2) 0 ( 0.0%) | - Output Pin Usage: - Max: 1.00 (1.00) - Avg: 0.66 (0.66) - Min: 0.00 (0.00) - Histogram: - [ 0: 0.1) 21 ( 33.9%) |************************* - [ 0.1: 0.2) 0 ( 0.0%) | - [ 0.2: 0.3) 0 ( 0.0%) | - [ 0.3: 0.4) 0 ( 0.0%) | - [ 0.4: 0.5) 0 ( 0.0%) | - [ 0.5: 0.6) 0 ( 0.0%) | - [ 0.6: 0.7) 0 ( 0.0%) | - [ 0.7: 0.8) 0 ( 0.0%) | - [ 0.8: 0.9) 0 ( 0.0%) | - [ 0.9: 1) 41 ( 66.1%) |************************************************ - -Type: clb - Input Pin Usage: - Max: 17.00 (0.40) - Avg: 11.60 (0.28) - Min: 4.00 (0.10) - Histogram: - [ 0: 4.2) 1 ( 20.0%) |************************* - [ 4.2: 8.4) 1 ( 20.0%) |************************* - [ 8.4: 13) 0 ( 0.0%) | - [ 13: 17) 1 ( 20.0%) |************************* - [ 17: 21) 2 ( 40.0%) |************************************************* - [ 21: 25) 0 ( 0.0%) | - [ 25: 29) 0 ( 0.0%) | - [ 29: 34) 0 ( 0.0%) | - [ 34: 38) 0 ( 0.0%) | - [ 38: 42) 0 ( 0.0%) | - Output Pin Usage: - Max: 9.00 (0.43) - Avg: 4.60 (0.22) - Min: 2.00 (0.10) - Histogram: - [ 0: 2.1) 3 ( 60.0%) |************************************************* - [ 2.1: 4.2) 0 ( 0.0%) | - [ 4.2: 6.3) 0 ( 0.0%) | - [ 6.3: 8.4) 1 ( 20.0%) |**************** - [ 8.4: 10) 1 ( 20.0%) |**************** - [ 10: 13) 0 ( 0.0%) | - [ 13: 15) 0 ( 0.0%) | - [ 15: 17) 0 ( 0.0%) | - [ 17: 19) 0 ( 0.0%) | - [ 19: 21) 0 ( 0.0%) | - diff --git a/vpr/pre_pack.report_timing.setup.rpt b/vpr/pre_pack.report_timing.setup.rpt deleted file mode 100644 index 0d250130ad5..00000000000 --- a/vpr/pre_pack.report_timing.setup.rpt +++ /dev/null @@ -1,617 +0,0 @@ -#Timing report of worst 21 path(s) -# Unit scale: 1e-09 seconds -# Output precision: 3 - -#Path 1 -Startpoint: b0.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:d1.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -b0.inpad[0] (.input) 0.000 0.000 -[22].in[0] (.names) 1.338 1.338 -[22].out[0] (.names) 0.261 1.599 -d1.in[4] (.names) 1.338 2.937 -d1.out[0] (.names) 0.261 3.198 -out:d1.outpad[0] (.output) 1.338 4.535 -data arrival time 4.535 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.535 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.535 - - -#Path 2 -Startpoint: b0.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:c1.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -b0.inpad[0] (.input) 0.000 0.000 -[22].in[0] (.names) 1.338 1.338 -[22].out[0] (.names) 0.261 1.599 -c1.in[4] (.names) 1.338 2.937 -c1.out[0] (.names) 0.261 3.198 -out:c1.outpad[0] (.output) 1.338 4.535 -data arrival time 4.535 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.535 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.535 - - -#Path 3 -Startpoint: i.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:i1.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -i.inpad[0] (.input) 0.000 0.000 -[247].in[0] (.names) 1.338 1.338 -[247].out[0] (.names) 0.261 1.599 -na1.in[5] (.names) 1.338 2.937 -na1.out[0] (.names) 0.261 3.198 -out:i1.outpad[0] (.output) 1.338 4.535 -data arrival time 4.535 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.535 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.535 - - -#Path 4 -Startpoint: i.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:a1.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -i.inpad[0] (.input) 0.000 0.000 -[247].in[0] (.names) 1.338 1.338 -[247].out[0] (.names) 0.261 1.599 -na1.in[5] (.names) 1.338 2.937 -na1.out[0] (.names) 0.261 3.198 -out:a1.outpad[0] (.output) 1.338 4.535 -data arrival time 4.535 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.535 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.535 - - -#Path 5 -Startpoint: i.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:h1.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -i.inpad[0] (.input) 0.000 0.000 -[247].in[0] (.names) 1.338 1.338 -[247].out[0] (.names) 0.261 1.599 -h1.in[5] (.names) 1.338 2.937 -h1.out[0] (.names) 0.261 3.198 -out:h1.outpad[0] (.output) 1.338 4.535 -data arrival time 4.535 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.535 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.535 - - -#Path 6 -Startpoint: i.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:j1.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -i.inpad[0] (.input) 0.000 0.000 -[259].in[0] (.names) 1.338 1.338 -[259].out[0] (.names) 0.261 1.599 -j1.in[4] (.names) 1.338 2.937 -j1.out[0] (.names) 0.235 3.172 -out:j1.outpad[0] (.output) 1.338 4.509 -data arrival time 4.509 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.509 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.509 - - -#Path 7 -Startpoint: c.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:r0.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -c.inpad[0] (.input) 0.000 0.000 -[238].in[0] (.names) 1.338 1.338 -[238].out[0] (.names) 0.235 1.573 -r0.in[5] (.names) 1.338 2.911 -r0.out[0] (.names) 0.261 3.172 -out:r0.outpad[0] (.output) 1.338 4.509 -data arrival time 4.509 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.509 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.509 - - -#Path 8 -Startpoint: o.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:w0.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -o.inpad[0] (.input) 0.000 0.000 -[41].in[0] (.names) 1.338 1.338 -[41].out[0] (.names) 0.235 1.573 -w0.in[5] (.names) 1.338 2.911 -w0.out[0] (.names) 0.261 3.172 -out:w0.outpad[0] (.output) 1.338 4.509 -data arrival time 4.509 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.509 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.509 - - -#Path 9 -Startpoint: k.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:p0.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -k.inpad[0] (.input) 0.000 0.000 -[76].in[0] (.names) 1.338 1.338 -[76].out[0] (.names) 0.235 1.573 -p0.in[3] (.names) 1.338 2.911 -p0.out[0] (.names) 0.235 3.146 -out:p0.outpad[0] (.output) 1.338 4.483 -data arrival time 4.483 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.483 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.483 - - -#Path 10 -Startpoint: k.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:b1.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -k.inpad[0] (.input) 0.000 0.000 -[76].in[0] (.names) 1.338 1.338 -[76].out[0] (.names) 0.235 1.573 -b1.in[4] (.names) 1.338 2.911 -b1.out[0] (.names) 0.235 3.146 -out:b1.outpad[0] (.output) 1.338 4.483 -data arrival time 4.483 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.483 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.483 - - -#Path 11 -Startpoint: b0.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:q0.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -b0.inpad[0] (.input) 0.000 0.000 -[29].in[0] (.names) 1.338 1.338 -[29].out[0] (.names) 0.261 1.599 -q0.in[1] (.names) 1.338 2.937 -q0.out[0] (.names) 0.195 3.132 -out:q0.outpad[0] (.output) 1.338 4.469 -data arrival time 4.469 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.469 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.469 - - -#Path 12 -Startpoint: b0.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:z0.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -b0.inpad[0] (.input) 0.000 0.000 -[23].in[0] (.names) 1.338 1.338 -[23].out[0] (.names) 0.195 1.533 -z0.in[1] (.names) 1.338 2.871 -z0.out[0] (.names) 0.261 3.132 -out:z0.outpad[0] (.output) 1.338 4.469 -data arrival time 4.469 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -4.469 --------------------------------------------------------------------------------- -slack (VIOLATED) -4.469 - - -#Path 13 -Startpoint: b0.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:t0.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -b0.inpad[0] (.input) 0.000 0.000 -t0.in[0] (.names) 1.338 1.338 -t0.out[0] (.names) 0.235 1.573 -out:t0.outpad[0] (.output) 1.338 2.911 -data arrival time 2.911 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -2.911 --------------------------------------------------------------------------------- -slack (VIOLATED) -2.911 - - -#Path 14 -Startpoint: b0.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:s0.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -b0.inpad[0] (.input) 0.000 0.000 -s0.in[0] (.names) 1.338 1.338 -s0.out[0] (.names) 0.235 1.573 -out:s0.outpad[0] (.output) 1.338 2.911 -data arrival time 2.911 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -2.911 --------------------------------------------------------------------------------- -slack (VIOLATED) -2.911 - - -#Path 15 -Startpoint: b.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:f1.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -b.inpad[0] (.input) 0.000 0.000 -f1.in[0] (.names) 1.338 1.338 -f1.out[0] (.names) 0.195 1.533 -out:f1.outpad[0] (.output) 1.338 2.871 -data arrival time 2.871 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -2.871 --------------------------------------------------------------------------------- -slack (VIOLATED) -2.871 - - -#Path 16 -Startpoint: n0.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:x0.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -n0.inpad[0] (.input) 0.000 0.000 -x0.in[0] (.names) 1.338 1.338 -x0.out[0] (.names) 0.195 1.533 -out:x0.outpad[0] (.output) 1.338 2.871 -data arrival time 2.871 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -2.871 --------------------------------------------------------------------------------- -slack (VIOLATED) -2.871 - - -#Path 17 -Startpoint: b0.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:v0.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -b0.inpad[0] (.input) 0.000 0.000 -v0.in[0] (.names) 1.338 1.338 -v0.out[0] (.names) 0.195 1.533 -out:v0.outpad[0] (.output) 1.338 2.871 -data arrival time 2.871 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -2.871 --------------------------------------------------------------------------------- -slack (VIOLATED) -2.871 - - -#Path 18 -Startpoint: b0.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:u0.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -b0.inpad[0] (.input) 0.000 0.000 -u0.in[0] (.names) 1.338 1.338 -u0.out[0] (.names) 0.195 1.533 -out:u0.outpad[0] (.output) 1.338 2.871 -data arrival time 2.871 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -2.871 --------------------------------------------------------------------------------- -slack (VIOLATED) -2.871 - - -#Path 19 -Startpoint: b.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:g1.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -b.inpad[0] (.input) 0.000 0.000 -g1.in[0] (.names) 1.338 1.338 -g1.out[0] (.names) 0.195 1.533 -out:g1.outpad[0] (.output) 1.338 2.871 -data arrival time 2.871 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -2.871 --------------------------------------------------------------------------------- -slack (VIOLATED) -2.871 - - -#Path 20 -Startpoint: m.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:e1.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -m.inpad[0] (.input) 0.000 0.000 -e1.in[0] (.names) 1.338 1.338 -e1.out[0] (.names) 0.195 1.533 -out:e1.outpad[0] (.output) 1.338 2.871 -data arrival time 2.871 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -2.871 --------------------------------------------------------------------------------- -slack (VIOLATED) -2.871 - - -#Path 21 -Startpoint: l.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:y0.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -l.inpad[0] (.input) 0.000 0.000 -y0.in[0] (.names) 1.338 1.338 -y0.out[0] (.names) 0.195 1.533 -out:y0.outpad[0] (.output) 1.338 2.871 -data arrival time 2.871 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -2.871 --------------------------------------------------------------------------------- -slack (VIOLATED) -2.871 - - -#End of timing report diff --git a/vpr/report_timing.hold.rpt b/vpr/report_timing.hold.rpt deleted file mode 100644 index 576c128751a..00000000000 --- a/vpr/report_timing.hold.rpt +++ /dev/null @@ -1,115 +0,0 @@ -#Timing report of worst 4 path(s) -# Unit scale: 1e-09 seconds -# Output precision: 3 - -#Path 1 -Startpoint: pc.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:pd.outpad[0] (.output clocked by virtual_io_clock) -Path Type : hold - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -pc.inpad[0] (.input) 0.000 0.000 -out:pd.outpad[0] (.output) 0.202 0.202 -data arrival time 0.202 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time -0.000 -data arrival time 0.202 --------------------------------------------------------------------------------- -slack (MET) 0.202 - - -#Path 2 -Startpoint: pc.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:pg.outpad[0] (.output clocked by virtual_io_clock) -Path Type : hold - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -pc.inpad[0] (.input) 0.000 0.000 -pg.in[0] (.names) 0.260 0.260 -pg.out[0] (.names) 0.174 0.434 -out:pg.outpad[0] (.output) 0.340 0.774 -data arrival time 0.774 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time -0.000 -data arrival time 0.774 --------------------------------------------------------------------------------- -slack (MET) 0.774 - - -#Path 3 -Startpoint: pa.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:pf.outpad[0] (.output clocked by virtual_io_clock) -Path Type : hold - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -pa.inpad[0] (.input) 0.000 0.000 -pf.in[0] (.names) 0.260 0.260 -pf.out[0] (.names) 0.174 0.434 -out:pf.outpad[0] (.output) 0.879 1.312 -data arrival time 1.312 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time -0.000 -data arrival time 1.312 --------------------------------------------------------------------------------- -slack (MET) 1.312 - - -#Path 4 -Startpoint: pa.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:pe.outpad[0] (.output clocked by virtual_io_clock) -Path Type : hold - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -pa.inpad[0] (.input) 0.000 0.000 -pe.in[0] (.names) 0.260 0.260 -pe.out[0] (.names) 0.174 0.434 -out:pe.outpad[0] (.output) 1.033 1.467 -data arrival time 1.467 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time -0.000 -data arrival time 1.467 --------------------------------------------------------------------------------- -slack (MET) 1.467 - - -#End of timing report diff --git a/vpr/report_timing.setup.rpt b/vpr/report_timing.setup.rpt deleted file mode 100644 index 9f3cb8bd220..00000000000 --- a/vpr/report_timing.setup.rpt +++ /dev/null @@ -1,115 +0,0 @@ -#Timing report of worst 4 path(s) -# Unit scale: 1e-09 seconds -# Output precision: 3 - -#Path 1 -Startpoint: pb.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:pe.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -pb.inpad[0] (.input) 0.000 0.000 -pe.in[1] (.names) 0.287 0.287 -pe.out[0] (.names) 0.235 0.522 -out:pe.outpad[0] (.output) 1.034 1.556 -data arrival time 1.556 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -1.556 --------------------------------------------------------------------------------- -slack (VIOLATED) -1.556 - - -#Path 2 -Startpoint: pb.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:pf.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -pb.inpad[0] (.input) 0.000 0.000 -pf.in[1] (.names) 0.287 0.287 -pf.out[0] (.names) 0.235 0.522 -out:pf.outpad[0] (.output) 0.880 1.402 -data arrival time 1.402 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -1.402 --------------------------------------------------------------------------------- -slack (VIOLATED) -1.402 - - -#Path 3 -Startpoint: pc.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:pg.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -pc.inpad[0] (.input) 0.000 0.000 -pg.in[0] (.names) 0.286 0.286 -pg.out[0] (.names) 0.235 0.521 -out:pg.outpad[0] (.output) 0.342 0.863 -data arrival time 0.863 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -0.863 --------------------------------------------------------------------------------- -slack (VIOLATED) -0.863 - - -#Path 4 -Startpoint: pc.inpad[0] (.input clocked by virtual_io_clock) -Endpoint : out:pd.outpad[0] (.output clocked by virtual_io_clock) -Path Type : setup - -Point Incr Path --------------------------------------------------------------------------------- -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -input external delay 0.000 0.000 -pc.inpad[0] (.input) 0.000 0.000 -out:pd.outpad[0] (.output) 0.206 0.206 -data arrival time 0.206 - -clock virtual_io_clock (rise edge) 0.000 0.000 -clock source latency 0.000 0.000 -clock uncertainty 0.000 0.000 -output external delay 0.000 0.000 -data required time 0.000 --------------------------------------------------------------------------------- -data required time 0.000 -data arrival time -0.206 --------------------------------------------------------------------------------- -slack (VIOLATED) -0.206 - - -#End of timing report diff --git a/vpr/report_unconstrained_timing.hold.rpt b/vpr/report_unconstrained_timing.hold.rpt deleted file mode 100644 index 114dbb93413..00000000000 --- a/vpr/report_unconstrained_timing.hold.rpt +++ /dev/null @@ -1,6 +0,0 @@ -#Unconstrained hold timing startpoint/endpoint - -timing_node_id node_type node_name --------------- --------- --------- - -#End of unconstrained hold startpoint/endpoint report diff --git a/vpr/report_unconstrained_timing.setup.rpt b/vpr/report_unconstrained_timing.setup.rpt deleted file mode 100644 index 241f5b5ba82..00000000000 --- a/vpr/report_unconstrained_timing.setup.rpt +++ /dev/null @@ -1,6 +0,0 @@ -#Unconstrained setup timing startpoint/endpoint - -timing_node_id node_type node_name --------------- --------- --------- - -#End of unconstrained setup startpoint/endpoint report diff --git a/vpr/src/route/check_rr_graph.cpp b/vpr/src/route/check_rr_graph.cpp index 28f8388d933..961bdd2177e 100644 --- a/vpr/src/route/check_rr_graph.cpp +++ b/vpr/src/route/check_rr_graph.cpp @@ -123,17 +123,23 @@ void check_rr_graph(const t_graph_type graph_type, t_rr_type to_rr_type = device_ctx.rr_nodes[to_node].type(); - //Only expect chan <-> chan connections to have multiple edges - if ((to_rr_type != CHANX && to_rr_type != CHANY) - || (rr_type != CHANX && rr_type != CHANY)) { + /* Only expect the following cases to have multiple edges + * - chan <-> chan connections + * - IPIN <-> chan connections (unique rr_node for IPIN nodes on multiple sides) + * - OPIN <-> chan connections (unique rr_node for OPIN nodes on multiple sides) + */ + if (((to_rr_type != CHANX && to_rr_type != CHANY && rr_type != IPIN) + || (rr_type != CHANX && rr_type != CHANY)) + && ((to_rr_type != CHANX && to_rr_type != CHANY) + || (rr_type != CHANX && rr_type != CHANY && rr_type != OPIN))) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d (%s) connects to node %d (%s) %zu times - multi-connections only expected for CHAN->CHAN.\n", inode, rr_node_typename[rr_type], to_node, rr_node_typename[to_rr_type], num_edges_to_node); } //Between two wire segments - VTR_ASSERT_MSG(to_rr_type == CHANX || to_rr_type == CHANY, "Expect channel type"); - VTR_ASSERT_MSG(rr_type == CHANX || rr_type == CHANY, "Expect channel type"); + VTR_ASSERT_MSG(to_rr_type == CHANX || to_rr_type == CHANY || to_rr_type == IPIN, "Expect channel type or input pin type"); + VTR_ASSERT_MSG(rr_type == CHANX || rr_type == CHANY || rr_type == OPIN, "Expect channel type or output pin type"); //While multiple connections between the same wires can be electrically legal, //they are redundant if they are of the same switch type. @@ -151,10 +157,16 @@ void check_rr_graph(const t_graph_type graph_type, for (auto kv : switch_counts) { if (kv.second <= 1) continue; - auto switch_type = device_ctx.rr_switch_inf[kv.first].type(); + /* Redundant edges are not allowed for chan <-> chan connections + * but allowed for input pin <-> chan or output pin <-> chan connections + */ + if ((to_rr_type == CHANX || to_rr_type == CHANY) + && (rr_type == CHANX || rr_type == CHANY)) { + auto switch_type = device_ctx.rr_switch_inf[kv.first].type(); - VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d has %d redundant connections to node %d of switch type %d (%s)", - inode, kv.second, to_node, kv.first, SWITCH_TYPE_STRINGS[size_t(switch_type)]); + VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d has %d redundant connections to node %d of switch type %d (%s)", + inode, kv.second, to_node, kv.first, SWITCH_TYPE_STRINGS[size_t(switch_type)]); + } } } diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 5ecba46ddfa..a98e3ecc2ae 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1455,10 +1455,10 @@ static void build_rr_sinks_sources(const int i, /* Connect IPINS to SINKS and initialize OPINS */ //We loop through all the pin locations on the block to initialize the IPINs/OPINs, //and hook-up the IPINs to sinks. - for (int width_offset = 0; width_offset < type->width; ++width_offset) { - for (int height_offset = 0; height_offset < type->height; ++height_offset) { - for (e_side side : {TOP, BOTTOM, LEFT, RIGHT}) { - for (int ipin = 0; ipin < num_pins; ++ipin) { + for (int ipin = 0; ipin < num_pins; ++ipin) { + for (e_side side : SIDES) { + for (int width_offset = 0; width_offset < type->width; ++width_offset) { + for (int height_offset = 0; height_offset < type->height; ++height_offset) { if (type->pinloc[width_offset][height_offset][side][ipin]) { int inode; int iclass = pin_class[ipin]; @@ -1467,40 +1467,50 @@ static void build_rr_sinks_sources(const int i, //Connect the input pin to the sink inode = get_rr_node_index(L_rr_node_indices, i + width_offset, j + height_offset, IPIN, ipin, side); - int to_node = get_rr_node_index(L_rr_node_indices, i, j, SINK, iclass); - - //Add info about the edge to be created - rr_edges_to_create.emplace_back(inode, to_node, delayless_switch); + /* Input pins are uniquified, we may not always find one */ + if (OPEN != inode) { + int to_node = get_rr_node_index(L_rr_node_indices, i, j, SINK, iclass); - VTR_ASSERT(inode >= 0); - L_rr_node[inode].set_cost_index(IPIN_COST_INDEX); - L_rr_node[inode].set_type(IPIN); + //Add info about the edge to be created + rr_edges_to_create.emplace_back(inode, to_node, delayless_switch); + VTR_ASSERT(inode >= 0); + L_rr_node[inode].set_cost_index(IPIN_COST_INDEX); + L_rr_node[inode].set_type(IPIN); + } } else { VTR_ASSERT(class_inf[iclass].type == DRIVER); //Initialize the output pin // Note that we leave it's out-going edges unconnected (they will be hooked up to global routing later) inode = get_rr_node_index(L_rr_node_indices, i + width_offset, j + height_offset, OPIN, ipin, side); - //Initially left unconnected - VTR_ASSERT(inode >= 0); - L_rr_node[inode].set_cost_index(OPIN_COST_INDEX); - L_rr_node[inode].set_type(OPIN); + /* Output pins may not exist on some sides, we may not always find one */ + if (OPEN != inode) { + //Initially left unconnected + VTR_ASSERT(inode >= 0); + L_rr_node[inode].set_cost_index(OPIN_COST_INDEX); + L_rr_node[inode].set_type(OPIN); + } } /* Common to both DRIVERs and RECEIVERs */ - L_rr_node[inode].set_capacity(1); - float R = 0.; - float C = 0.; - L_rr_node[inode].set_rc_index(find_create_rr_rc_data(R, C)); - L_rr_node[inode].set_ptc_num(ipin); - - //Note that we store the grid tile location and side where the pin is located, - //which greatly simplifies the drawing code - L_rr_node[inode].set_coordinates(i + width_offset, j + height_offset, i + width_offset, j + height_offset); - L_rr_node[inode].set_side(side); - - VTR_ASSERT(type->pinloc[width_offset][height_offset][L_rr_node[inode].side()][L_rr_node[inode].pin_num()]); + if (OPEN != inode) { + L_rr_node[inode].set_capacity(1); + float R = 0.; + float C = 0.; + L_rr_node[inode].set_rc_index(find_create_rr_rc_data(R, C)); + L_rr_node[inode].set_ptc_num(ipin); + + //Note that we store the grid tile location and side where the pin is located, + //which greatly simplifies the drawing code + //For those pins located on multiple sides, we save the rr node index + //for the pin on all sides at which it exists + //As such, multipler driver problem can be avoided. + L_rr_node[inode].set_coordinates(i + width_offset, j + height_offset, i + width_offset, j + height_offset); + L_rr_node[inode].set_side(side); + + VTR_ASSERT(type->pinloc[width_offset][height_offset][L_rr_node[inode].side()][L_rr_node[inode].pin_num()]); + } } } } @@ -2478,6 +2488,8 @@ std::string describe_rr_node(int inode) { } msg += vtr::string_fmt(" capacity: %d", rr_node.capacity()); + msg += vtr::string_fmt(" fan-in: %d", rr_node.fan_in()); + msg += vtr::string_fmt(" fan-out: %d", rr_node.num_edges()); return msg; } diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index c4955f72ae2..28516f69866 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1082,13 +1082,67 @@ static void load_block_rr_indices(const DeviceGrid& grid, VTR_ASSERT(indices[SOURCE][x][y][0].size() == type->class_inf.size()); VTR_ASSERT(indices[SINK][x][y][0].size() == type->class_inf.size()); + /* Limited sides for grids + * The wanted side depends on the location of the grid. + * In particular for perimeter grid, + * ------------------------------------------------------- + * Grid location | IPIN side + * ------------------------------------------------------- + * TOP | BOTTOM + * ------------------------------------------------------- + * RIGHT | LEFT + * ------------------------------------------------------- + * BOTTOM | TOP + * ------------------------------------------------------- + * LEFT | RIGHT + * ------------------------------------------------------- + * TOP-LEFT | BOTTOM & RIGHT + * ------------------------------------------------------- + * TOP-RIGHT | BOTTOM & LEFT + * ------------------------------------------------------- + * BOTTOM-LEFT | TOP & RIGHT + * ------------------------------------------------------- + * BOTTOM-RIGHT | TOP & LEFT + * ------------------------------------------------------- + * Other | First come first fit + * ------------------------------------------------------- + * + * Special for IPINs: + * If there are multiple wanted sides, first come first fit is applied + * This guarantee that there is only a unique rr_node + * for the same input pin on multiple sides, and thus avoid multiple driver problems + */ + std::vector wanted_sides; + if (grid.height() - 1 == y) { /* TOP side */ + wanted_sides.push_back(BOTTOM); + } + if (grid.width() - 1 == x) { /* RIGHT side */ + wanted_sides.push_back(LEFT); + } + if (0 == y) { /* BOTTOM side */ + wanted_sides.push_back(TOP); + } + if (0 == x) { /* LEFT side */ + wanted_sides.push_back(RIGHT); + } + + /* If wanted sides is empty still, this block does not have specific wanted sides, + * Deposit all the sides + */ + if (true == wanted_sides.empty()) { + for (e_side side : {TOP, BOTTOM, LEFT, RIGHT}) { + wanted_sides.push_back(side); + } + } + //Assign indices for IPINs and OPINs at all offsets from root for (int ipin = 0; ipin < type->num_pins; ++ipin) { - for (int width_offset = 0; width_offset < type->width; ++width_offset) { - int x_tile = x + width_offset; - for (int height_offset = 0; height_offset < type->height; ++height_offset) { - int y_tile = y + height_offset; - for (e_side side : SIDES) { + bool assigned_to_rr_node = false; + for (e_side side : wanted_sides) { + for (int width_offset = 0; width_offset < type->width; ++width_offset) { + int x_tile = x + width_offset; + for (int height_offset = 0; height_offset < type->height; ++height_offset) { + int y_tile = y + height_offset; if (type->pinloc[width_offset][height_offset][side][ipin]) { int iclass = type->pin_class[ipin]; auto class_type = type->class_inf[iclass].type; @@ -1096,12 +1150,13 @@ static void load_block_rr_indices(const DeviceGrid& grid, if (class_type == DRIVER) { indices[OPIN][x_tile][y_tile][side].push_back(*index); indices[IPIN][x_tile][y_tile][side].push_back(OPEN); + assigned_to_rr_node = true; } else { VTR_ASSERT(class_type == RECEIVER); - indices[IPIN][x_tile][y_tile][side].push_back(*index); indices[OPIN][x_tile][y_tile][side].push_back(OPEN); + indices[IPIN][x_tile][y_tile][side].push_back(*index); + assigned_to_rr_node = true; } - ++(*index); } else { indices[IPIN][x_tile][y_tile][side].push_back(OPEN); indices[OPIN][x_tile][y_tile][side].push_back(OPEN); @@ -1109,6 +1164,20 @@ static void load_block_rr_indices(const DeviceGrid& grid, } } } + /* A pin may locate on multiple sides of a tile. + * Instead of allocating multiple rr_nodes for the pin, + * we just create a rr_node and make it indexable on these sides + * As such, we can avoid redundant rr_node to be allocated + * and multiple nets to be mapped to the pin + * + * Considering that some pin could be just dangling, we do not need + * to create a void rr_node for it. + * As such, we only allocate a rr node when the pin is indeed located + * on at least one side + */ + if (assigned_to_rr_node) { + ++(*index); + } } //Sanity check @@ -1117,8 +1186,15 @@ static void load_block_rr_indices(const DeviceGrid& grid, for (int height_offset = 0; height_offset < type->height; ++height_offset) { int y_tile = y + height_offset; for (e_side side : SIDES) { - VTR_ASSERT(indices[IPIN][x_tile][y_tile][side].size() == size_t(type->num_pins)); - VTR_ASSERT(indices[OPIN][x_tile][y_tile][side].size() == size_t(type->num_pins)); + //Note that the fast look-up stores all the indices for the pins on each side + //It has a fixed size (either 0 or the number of pins) + //Case 0 pins: the side is skipped as no pins are located on it + //Case number of pins: there are pins on this side + //and data query can be applied any pin id on this side + VTR_ASSERT((indices[IPIN][x_tile][y_tile][side].size() == size_t(type->num_pins)) + || (0 == indices[IPIN][x_tile][y_tile][side].size())); + VTR_ASSERT((indices[OPIN][x_tile][y_tile][side].size() == size_t(type->num_pins)) + || (0 == indices[OPIN][x_tile][y_tile][side].size())); } } } @@ -1263,30 +1339,36 @@ bool verify_rr_node_indices(const DeviceGrid& grid, const t_rr_node_indices& rr_ } else { VTR_ASSERT(rr_node.type() == IPIN || rr_node.type() == OPIN); - if (rr_node.xlow() != x) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%d/%d): %s", - rr_node.xlow(), - x, - describe_rr_node(inode).c_str()); - } - - if (rr_node.ylow() != y) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node ylow does not match between rr_nodes and rr_node_indices (%d/%d): %s", - rr_node.ylow(), - y, - describe_rr_node(inode).c_str()); - } + /* As we allow a pin to be indexable on multiple sides, + * This check code should be invalid + * if (rr_node.xlow() != x) { + * VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%d/%d): %s", + * rr_node.xlow(), + * x, + * describe_rr_node(inode).c_str()); + * } + * + * if (rr_node.ylow() != y) { + * VPR_ERROR(VPR_ERROR_ROUTE, "RR node ylow does not match between rr_nodes and rr_node_indices (%d/%d): %s", + * rr_node.ylow(), + * y, + * describe_rr_node(inode).c_str()); + * } + */ } if (rr_type == IPIN || rr_type == OPIN) { - if (rr_node.side() != side) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%s/%s): %s", - SIDE_STRING[rr_node.side()], - SIDE_STRING[side], - describe_rr_node(inode).c_str()); - } else { - VTR_ASSERT(rr_node.side() == side); - } + /* As we allow a pin to be indexable on multiple sides, + * This check code should be invalid + * if (rr_node.side() != side) { + * VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%s/%s): %s", + * SIDE_STRING[rr_node.side()], + * SIDE_STRING[side], + * describe_rr_node(inode).c_str()); + * } else { + * VTR_ASSERT(rr_node.side() == side); + * } + */ } else { //Non-pin's don't have sides, and should only be in side 0 if (side != SIDES[0]) { VPR_ERROR(VPR_ERROR_ROUTE, "Non-Pin RR node in rr_node_indices found with non-default side %s: %s", @@ -1325,7 +1407,10 @@ bool verify_rr_node_indices(const DeviceGrid& grid, const t_rr_node_indices& rr_ count, describe_rr_node(inode).c_str()); } - } else { + /* As we allow a pin to be indexable on multiple sides, + * This check code should not be applied to input and output pins + */ + } else if ((OPIN != rr_node.type()) && (IPIN != rr_node.type())) { if (count != rr_node.length() + 1) { VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node length (%d) and count within rr_node_indices (%d, should be length + 1): %s", rr_node.length(), diff --git a/vtr_flow/arch/timing/k6_N10_mem32K_40nm_i_or_o.xml b/vtr_flow/arch/timing/k6_N10_mem32K_40nm_i_or_o.xml index cd8e7afc73b..29715f5b661 100644 --- a/vtr_flow/arch/timing/k6_N10_mem32K_40nm_i_or_o.xml +++ b/vtr_flow/arch/timing/k6_N10_mem32K_40nm_i_or_o.xml @@ -14,6 +14,17 @@ Based on flagship k6_frac_N10_mem32K_40nm.xml architecture. This architecture has no fracturable LUTs + Important Notes: + + - This architecture is designed to test + - the splitted I/O blocks (input and output blocks are individual blocks rather than an unified blocks) + - I/Os are located on two sides (top and bottom in this case) of a FPGA + - Fill tiles ('clb' in this case) are mixed with heterogeneous blocks ('DSP' and 'RAM' in this case) in the same columns + + - It carries architecture features which may be challenging for physical layouts. + For example, the mixed clb, DSP and RAM in one column is rarely seen in modern FPGA architectures. + Please consider this not as popular architecture choices when doing architecture evaluation. + Authors: Jason Luu, Jeff Goeders, Vaughn Betz --> @@ -154,20 +165,28 @@ + - - + + + + - + - - + + - + diff --git a/vtr_flow/arch/titan/stratixiv_arch.timing.xml b/vtr_flow/arch/titan/stratixiv_arch.timing.xml index 02d4db9dfe8..c3d2dcd4fe7 100644 --- a/vtr_flow/arch/titan/stratixiv_arch.timing.xml +++ b/vtr_flow/arch/titan/stratixiv_arch.timing.xml @@ -4471,7 +4471,16 @@ - + + @@ -6206,7 +6215,7 @@ - + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/golden_results.txt index cec30a582ff..b37515cf381 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/golden_results.txt @@ -11,7 +11,7 @@ k4_n4_v7_bidir.xml elliptic.blif common 25.60 -1 k4_n4_v7_bidir.xml ex1010.blif common 42.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 1500 10 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/run001/k4_n4_v7_bidir.xml/ex1010.blif/common 113436 10 10 4608 4618 0 3623 1520 41 41 1681 clb auto 0.60 45175 7.96 0.05 25.1226 -238.702 -25.1226 nan 0.00290815 0.00211423 0.329953 0.241901 28 67222 28 4.563e+07 4.5e+07 -1 -1 27.15 1.45555 1.13442 63915 21 25634 102060 7281409 688030 29.4535 nan -282.894 -29.4535 0 0 -1 -1 1.00 0.187372 0.159317 k4_n4_v7_bidir.xml ex5p.blif common 6.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/run001/k4_n4_v7_bidir.xml/ex5p.blif/common 69928 8 63 1072 1135 0 907 417 21 21 441 clb auto 0.14 11398 1.28 0.01 12.6763 -545.382 -12.6763 nan 0.000799243 0.000594782 0.084179 0.0641134 31 16883 28 1.083e+07 1.038e+07 -1 -1 3.26 0.316333 0.251429 15788 24 7482 25012 2075555 191623 15.6503 nan -702.867 -15.6503 0 0 -1 -1 0.24 0.0483952 0.0417931 k4_n4_v7_bidir.xml frisc.blif common 54.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 1046 20 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/run001/k4_n4_v7_bidir.xml/frisc.blif/common 104728 20 116 4445 4561 1 2328 1182 35 35 1225 clb auto 0.57 37817 5.69 0.03 21.94 -12224.3 -21.94 21.94 0.0027042 0.00211557 0.331313 0.25084 32 56262 47 3.267e+07 3.138e+07 -1 -1 42.88 1.44221 1.15046 58630 32 18405 81081 16516341 1651690 46.6193 46.6193 -21966 -46.6193 0 0 -1 -1 1.69 0.223085 0.188567 -k4_n4_v7_bidir.xml misex3.blif common 7.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 432 14 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/run001/k4_n4_v7_bidir.xml/misex3.blif/common 82556 14 14 1411 1425 0 1075 460 23 23 529 clb auto 0.20 13598 1.64 0.01 11.3211 -143.641 -11.3211 nan 0.000927313 0.000679702 0.0991134 0.074422 31 20214 32 1.323e+07 1.296e+07 -1 -1 3.36 0.374588 0.296214 19135 17 7394 26107 2102529 193873 13.8099 nan -178.659 -13.8099 0 0 -1 -1 0.25 0.0474358 0.0410493 +k4_n4_v7_bidir.xml misex3.blif common 7.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 432 14 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/run001/k4_n4_v7_bidir.xml/misex3.blif/common 82556 14 14 1411 1425 0 1075 460 23 23 529 clb auto 0.20 13598 1.64 0.01 11.3211 -143.641 -11.3211 nan 0.000927313 0.000679702 0.0991134 0.074422 31 20214 32 1.323e+07 1.296e+07 -1 -1 3.36 0.374588 0.296214 19135 17 7394 26107 2102529 193873 23.2052 nan -259.458 -23.2052 0 0 -1 -1 0.25 0.0474358 0.0410493 k4_n4_v7_bidir.xml pdc.blif common 53.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 1529 16 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/run001/k4_n4_v7_bidir.xml/pdc.blif/common 127464 16 40 4591 4631 0 3652 1585 42 42 1764 clb auto 0.83 69293 8.69 0.05 22.9735 -755.09 -22.9735 nan 0.00317526 0.00228021 0.378692 0.278853 47 98338 46 4.8e+07 4.587e+07 -1 -1 35.76 2.04688 1.61117 91883 20 23554 96391 10674416 835639 28.598 nan -950.895 -28.598 0 0 -1 -1 1.30 0.198719 0.170119 k4_n4_v7_bidir.xml s298.blif common 10.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 569 4 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/run001/k4_n4_v7_bidir.xml/s298.blif/common 80096 4 6 1942 1948 1 1189 579 26 26 676 clb auto 0.20 13884 2.01 0.01 21.1936 -164.918 -21.1936 21.1936 0.00130246 0.000974313 0.141335 0.107281 24 20030 24 1.728e+07 1.707e+07 -1 -1 5.55 0.559017 0.444955 19690 22 7663 39775 2741727 242872 25.5227 25.5227 -203.401 -25.5227 0 0 -1 -1 0.37 0.0774698 0.0666477 k4_n4_v7_bidir.xml s38417.blif common 38.66 -1 -1 -1 -1 -1 -1 -1 -1 -1 1735 29 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/run001/k4_n4_v7_bidir.xml/s38417.blif/common 152684 29 106 7534 7640 1 4766 1870 44 44 1936 clb auto 0.84 45643 10.47 0.06 17.3298 -10138 -17.3298 17.3298 0.00458617 0.00338354 0.52986 0.39436 24 61754 34 5.292e+07 5.205e+07 -1 -1 20.17 2.11685 1.6641 58517 21 28006 92995 6026656 607814 21.3055 21.3055 -13076.9 -21.3055 0 0 -1 -1 0.93 0.287494 0.244391 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt index 230b3258bab..a0336f50a4b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 130 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/run011/k6_frac_N10_40nm.xml/riscv_core_lut6.blif/common_--absorb_buffer_luts_on 35720 130 150 1169 1319 1 888 364 12 12 144 clb auto 0.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00185239 0.00152993 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 130 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/run011/k6_frac_N10_40nm.xml/riscv_core_lut6.blif/common_--absorb_buffer_luts_off 35512 130 150 1216 1366 1 925 369 12 12 144 clb auto 0.79 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00186601 0.00153509 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.28 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 130 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/run002/k6_frac_N10_40nm.xml/riscv_core_lut6.blif/common_--absorb_buffer_luts_on 53584 130 150 1169 1319 1 888 364 12 12 144 clb auto 0.91 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00209121 0.00181151 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 130 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/run002/k6_frac_N10_40nm.xml/riscv_core_lut6.blif/common_--absorb_buffer_luts_off 53404 130 150 1216 1366 1 925 369 12 12 144 clb auto 0.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00214106 0.0018429 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt index 1cf703179b4..ce125e04ca3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.25 0.05 9176 4 0.12 -1 -1 33076 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/run014/k6_N10_mem32K_40nm.xml/stereovision3.v/common 28876 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 411 0.09 0.00 2.21827 -167.491 -2.21827 2.12157 0.000337004 0.000269811 0.0361555 0.0278073 476 706 1762 86557 15062 1.07788e+06 1.02399e+06 207176. 4228.08 21 2.37477 2.25251 -178.461 -2.37477 0 0 0.06 0.0536857 0.0427473 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.41 0.05 9636 5 0.11 -1 -1 33320 -1 -1 14 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/run014/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 31048 11 30 313 321 2 117 55 7 7 49 clb auto 0.28 389 0.09 0.00 2.27833 -153.323 -2.27833 2.06764 0.000326252 0.000262622 0.0476506 0.0376635 524 235 443 11245 3448 1.07788e+06 754516 219490. 4479.39 8 2.4554 2.27846 -166.763 -2.4554 0 0 0.02 0.0630713 0.0518124 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.08 0.06 6948 4 0.16 -1 -1 32508 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common 42536 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 411 0.08 0.00 2.21827 -167.491 -2.21827 2.12157 0.000220069 0.00016842 0.0261455 0.0199267 466 779 2010 94407 16356 1.07788e+06 1.02399e+06 207176. 4228.08 26 2.37477 2.25251 -176.32 -2.37477 0 0 0.04 0.0456533 0.0368073 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.36 0.06 6944 5 0.14 -1 -1 30768 -1 -1 14 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/run002/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 40648 11 30 313 321 2 118 55 7 7 49 clb auto 0.30 413 0.10 0.00 2.27922 -157.154 -2.27922 2.04734 0.000265937 0.00020917 0.035247 0.0275825 564 231 414 13653 4088 1.07788e+06 754516 219490. 4479.39 9 2.64615 2.34528 -176.378 -2.64615 0 0 0.02 0.0522232 0.0434419 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt index d44d9647f42..8938fc997e8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.36 0.03 9096 3 0.22 -1 -1 37720 -1 -1 65 99 1 0 success v8.0.0-2110-gded231c238-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 9.3.0 on Linux-5.4.0-31-generic x86_64 2020-08-20T20:47:54 daniel-razer /home/zhaiyif1/Desktop/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/run001/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 30516 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 798 0.30 0.00 2.04518 -201.963 -2.04518 2.04518 0.000300324 0.000261792 0.00271246 0.00257694 50 1591 14 5.66058e+06 4.05111e+06 406292. 2821.48 0.97 0.10259 0.0931782 1509 10 538 681 81449 27794 2.45839 2.45839 -237.398 -2.45839 0 0 539112. 3743.83 0.03 0.0134249 0.012679 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.15 0.05 6712 3 0.31 -1 -1 31536 -1 -1 65 99 1 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/run002/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 37584 99 130 363 493 1 251 295 12 12 144 clb auto 0.11 1019 0.26 0.00 2.00621 -204.675 -2.00621 2.00621 0.000404203 0.000362763 0.00325482 0.00310504 50 2012 20 5.66058e+06 4.05111e+06 406292. 2821.48 1.27 0.171838 0.158701 1800 11 538 688 65774 22088 2.48711 2.48711 -239.345 -2.48711 0 0 520805. 3616.70 0.04 0.0208505 0.0197607 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index 1ea1bfdf5ad..b3a2c853ecc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_n4_v7_bidir.xml styr.blif common 1.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run006/k4_n4_v7_bidir.xml/styr.blif/common 61248 10 10 253 263 1 169 87 11 11 121 clb auto 0.03 1219 0.19 0.00 5.40419 -68.5058 -5.40419 5.40419 0.000217579 0.000166257 0.0223325 0.0173698 16 2070 47 2.43e+06 2.01e+06 -1 -1 0.60 0.0994811 0.0795096 1842 22 1327 4511 245200 28913 6.73981 6.73981 -88.7727 -6.73981 0 0 -1 -1 0.04 0.0115718 0.00977908 -k4_n4_v7_longline_bidir.xml styr.blif common 1.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run006/k4_n4_v7_longline_bidir.xml/styr.blif/common 61176 10 10 253 263 1 169 87 11 11 121 clb auto 0.03 1271 0.22 0.00 5.90336 -76.6383 -5.90336 5.90336 0.000217709 0.000166247 0.0235612 0.0182918 18 2616 37 2.43e+06 2.01e+06 -1 -1 0.44 0.0766402 0.0615427 2437 27 1697 5237 423570 48479 9.25941 9.25941 -113.19 -9.25941 0 0 -1 -1 0.05 0.0131935 0.0110878 -k4_n4_v7_l1_bidir.xml styr.blif common 1.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run006/k4_n4_v7_l1_bidir.xml/styr.blif/common 61416 10 10 253 263 1 169 87 11 11 121 clb auto 0.03 1235 0.22 0.00 6.82024 -77.4787 -6.82024 6.82024 0.000229449 0.000178317 0.0239951 0.018662 10 1482 34 2.43e+06 2.01e+06 -1 -1 1.11 0.0775563 0.0616187 1375 27 1335 4712 482365 103678 8.8584 8.8584 -107.817 -8.8584 0 0 -1 -1 0.07 0.0130463 0.0109667 -k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2670-g0b26ced43-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 10.2.0 on Linux-5.8.5-arch1-1 x86_64 2020-09-08T12:05:34 davidbaines-desktop /home/dbaines/Documents/research/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run006/k4_n4_v7_bidir_pass_gate.xml/styr.blif/common 61072 10 10 253 263 1 169 87 11 11 121 clb auto 0.03 1244 0.43 0.00 5.39221 -64.0616 -5.39221 5.39221 0.000221899 0.000171117 0.0262523 0.0203894 17 2190 29 2.43e+06 2.01e+06 -1 -1 0.46 0.0694995 0.0552789 2076 24 1477 5068 1218069 157053 20.8637 20.8637 -235.207 -20.8637 0 0 -1 -1 0.11 0.0120796 0.010179 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_n4_v7_bidir.xml styr.blif common 1.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_bidir.xml/styr.blif/common 23568 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1270 0.23 0.00 5.57595 -70.6881 -5.57595 5.57595 0.000181897 0.00014297 0.0196268 0.0159363 16 2004 29 2.43e+06 2.01e+06 -1 -1 0.40 0.07519 0.0633621 1902 24 1378 4371 246547 28194 7.23996 7.23996 -92.3987 -7.23996 0 0 -1 -1 0.05 0.0147415 0.0130549 +k4_n4_v7_longline_bidir.xml styr.blif common 1.93 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_longline_bidir.xml/styr.blif/common 21548 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1234 0.26 0.00 5.77027 -74.3866 -5.77027 5.77027 0.000190686 0.000150269 0.0199143 0.0162876 18 2361 37 2.43e+06 2.01e+06 -1 -1 0.54 0.0814192 0.0687497 2409 21 1514 4799 386424 43001 8.75717 8.75717 -109.461 -8.75717 0 0 -1 -1 0.06 0.0144257 0.0128624 +k4_n4_v7_l1_bidir.xml styr.blif common 1.88 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_l1_bidir.xml/styr.blif/common 21528 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1235 0.26 0.00 6.82024 -77.4787 -6.82024 6.82024 0.000179396 0.000141516 0.0197106 0.0159732 10 1513 47 2.43e+06 2.01e+06 -1 -1 0.91 0.0669803 0.0566492 1294 23 1248 4320 389587 82246 8.65232 8.65232 -101.426 -8.65232 0 0 -1 -1 0.10 0.0187415 0.0166916 +k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.37 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_bidir_pass_gate.xml/styr.blif/common 23280 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1244 0.54 0.00 5.39221 -64.0616 -5.39221 5.39221 0.000181231 0.000144846 0.0215371 0.0174077 16 2062 32 2.43e+06 2.01e+06 -1 -1 1.20 0.113886 0.0960411 2100 30 1484 4823 1048337 136252 11.9977 11.9977 -129.445 -11.9977 0 0 -1 -1 0.13 0.0186144 0.0165004 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt index 400056c259e..b76fd4c963a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.33 0.05 9464 4 0.14 -1 -1 33008 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/run011/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--verify_binary_search_off 29572 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 395 0.12 0.00 2.22041 -166.454 -2.22041 2.11404 0.000290214 0.000229793 0.0333367 0.0257718 22 602 35 1.07788e+06 1.02399e+06 54623.3 1114.76 0.13 0.0858249 0.0689766 598 29 933 2291 84683 24243 2.72583 2.49701 -190.532 -2.72583 0 0 69322.2 1414.74 0.04 0.0207673 0.0175407 -k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.46 0.03 9356 4 0.13 -1 -1 33124 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/run011/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--verify_binary_search_on 29508 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 395 0.11 0.00 2.22041 -166.454 -2.22041 2.11404 0.00028622 0.000226844 0.0320311 0.0245901 22 602 35 1.07788e+06 1.02399e+06 54623.3 1114.76 0.26 0.132887 0.106021 598 29 933 2291 84683 24243 2.72583 2.49701 -190.532 -2.72583 0 0 69322.2 1414.74 0.04 0.0205748 0.0173417 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.43 0.06 6948 4 0.14 -1 -1 31188 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--verify_binary_search_off 38456 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 395 0.12 0.00 2.22041 -166.454 -2.22041 2.11404 0.000221953 0.000168169 0.0249577 0.0189637 22 602 35 1.07788e+06 1.02399e+06 54623.3 1114.76 0.13 0.070836 0.0573522 598 29 933 2291 84600 24180 2.72583 2.49701 -190.532 -2.72583 0 0 69322.2 1414.74 0.04 0.0202667 0.0175377 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.70 0.10 6948 4 0.15 -1 -1 31188 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--verify_binary_search_on 42552 11 30 262 292 2 104 60 7 7 49 clb auto 0.13 395 0.12 0.00 2.22041 -166.454 -2.22041 2.11404 0.000227786 0.000174142 0.0247913 0.018903 22 602 35 1.07788e+06 1.02399e+06 54623.3 1114.76 0.26 0.116606 0.0944809 598 29 933 2291 84600 24180 2.72583 2.49701 -190.532 -2.72583 0 0 69322.2 1414.74 0.04 0.0203844 0.0176225 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt index 5cf59b02251..55b378c8bda 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml ch_intrinsics.v common 11.31 0.10 9044 3 0.41 -1 -1 39980 -1 -1 70 99 1 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common 71344 99 130 363 493 1 255 300 12 12 144 clb auto 0.23 655 3.49 0.02 2.18412 -208.426 -2.18412 2.18412 0.0168429 0.0156467 1.38585 1.22025 38 1213 28 5.66058e+06 4.32058e+06 306247. 2126.71 3.39 2.94623 2.47815 1113 18 739 1031 114104 39086 2.6714 2.6714 -228.621 -2.6714 0 0 388532. 2698.14 0.28 0.233271 0.0961667 -k6_N10_mem32K_40nm.xml diffeq1.v common 30.65 0.13 8656 15 0.62 -1 -1 38360 -1 -1 52 162 0 5 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm.xml/diffeq1.v/common 76816 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.64 5392 6.41 0.02 19.8556 -1716.78 -19.8556 19.8556 0.00777612 0.00755412 2.92766 2.74303 44 11950 42 1.21132e+07 4.78249e+06 665287. 2598.78 16.33 8.30359 7.63854 9499 24 4032 8541 2355345 561334 21.9068 21.9068 -1883.87 -21.9068 0 0 864808. 3378.16 1.16 0.279793 0.248573 -k6_N10_mem32K_40nm.xml single_wire.v common 1.22 0.03 5588 1 0.01 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm.xml/single_wire.v/common 62204 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.01 0.00 0.205011 -0.205011 -0.205011 nan 0.00203777 0.00175101 0.00363454 0.00267006 14 5 1 53894 0 3251.56 361.284 0.06 0.0202002 0.00525638 5 1 1 1 23 21 0.515002 nan -0.515002 -0.515002 0 0 4350.07 483.341 0.00 0.000284556 0.000229007 -k6_N10_mem32K_40nm.xml single_ff.v common 1.34 0.01 5556 1 0.01 -1 -1 33340 -1 -1 1 2 0 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm.xml/single_ff.v/common 62660 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.01 0.00 0.570641 -0.944653 -0.570641 0.570641 0.00123048 0.000945615 0.0049211 0.0038887 2 3 2 53894 53894 1165.58 129.509 0.04 0.0209083 0.0137863 3 2 4 4 86 48 0.577715 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 0.000519317 0.000337559 -k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 166.64 0.20 8972 3 0.42 -1 -1 39820 -1 -1 70 99 1 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm_i_or_o.xml/ch_intrinsics.v/common 68196 99 130 363 493 1 255 300 19 19 361 o auto 0.30 792 156.14 0.01 2.14848 -226.623 -2.14848 2.14848 0.00126129 0.00115112 0.827134 0.709591 32 1591 15 1.92828e+07 4.32058e+06 754825. 2090.93 4.59 2.01089 1.65332 1311 14 852 1223 127641 39958 2.48928 2.48928 -252.191 -2.48928 0 0 935064. 2590.20 0.13 0.0733341 0.0635439 -k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 41.18 0.13 8776 15 0.55 -1 -1 38532 -1 -1 52 162 0 5 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm_i_or_o.xml/diffeq1.v/common 84740 162 96 999 932 1 707 315 24 24 576 i auto 0.58 7164 12.84 0.02 20.2809 -1846.99 -20.2809 20.2809 0.0104701 0.0057697 2.88408 2.70228 40 11806 30 3.2214e+07 4.78249e+06 1.47109e+06 2553.97 18.85 7.79402 7.19715 10980 25 4173 9005 3355783 783837 22.0003 22.0003 -2005.62 -22.0003 0 0 1.84580e+06 3204.51 1.77 0.76645 0.692156 -k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 1.43 0.04 5584 1 0.01 -1 -1 33176 -1 -1 0 1 0 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm_i_or_o.xml/single_wire.v/common 63028 1 1 1 2 0 1 2 4 4 16 i auto 0.02 4 0.02 0.00 0.310441 -0.310441 -0.310441 nan 4.7286e-05 2.42e-05 0.000137975 7.4338e-05 4 5 1 323364 0 1970.29 123.143 0.13 0.00861919 0.00267743 6 1 1 1 32 25 0.484024 nan -0.484024 -0.484024 0 0 3039.08 189.942 0.00 0.000303122 0.000238994 -k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 1.44 0.02 5548 1 0.01 -1 -1 33176 -1 -1 1 2 0 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm_i_or_o.xml/single_ff.v/common 62508 2 1 3 4 1 3 4 4 4 16 i auto 0.00 6 0.12 0.00 0.59309 -1.03934 -0.59309 0.59309 2.5118e-05 1.1253e-05 0.0854558 0.0370764 8 5 2 323364 53894 4250.52 265.658 0.09 0.0933332 0.0443832 5 2 3 3 89 46 0.594048 0.594048 -1.06808 -0.594048 0 0 5124.99 320.312 0.00 0.00041458 0.000325376 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.38 0.05 6688 3 0.26 -1 -1 31536 -1 -1 70 99 1 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run002/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common 38912 99 130 363 493 1 255 300 12 12 144 clb auto 0.07 655 0.54 0.00 2.18412 -208.426 -2.18412 2.18412 0.000409987 0.000365712 0.0549996 0.0492099 38 1230 28 5.66058e+06 4.32058e+06 306247. 2126.71 0.51 0.165964 0.151832 1123 18 794 1106 118593 39868 2.6714 2.6714 -229.924 -2.6714 0 0 388532. 2698.14 0.04 0.0206528 0.019343 +k6_N10_mem32K_40nm.xml diffeq1.v common 8.61 0.04 6480 15 0.40 -1 -1 32796 -1 -1 52 162 0 5 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run002/k6_N10_mem32K_40nm.xml/diffeq1.v/common 57572 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.21 5392 1.12 0.00 19.8556 -1716.78 -19.8556 19.8556 0.00128516 0.00116434 0.172779 0.156661 46 10666 26 1.21132e+07 4.78249e+06 696785. 2721.82 4.75 0.796458 0.738658 9452 21 3686 7765 2162482 516249 21.7607 21.7607 -1889.07 -21.7607 0 0 894618. 3494.60 0.38 0.097738 0.0926606 +k6_N10_mem32K_40nm.xml single_wire.v common 0.36 0.03 3380 1 0.00 -1 -1 27604 -1 -1 0 1 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run002/k6_N10_mem32K_40nm.xml/single_wire.v/common 18148 1 1 1 2 0 1 2 3 3 9 -1 auto 0.02 2 0.01 0.00 0.205011 -0.205011 -0.205011 nan 6.979e-06 2.305e-06 4.0089e-05 2.0917e-05 14 5 1 53894 0 3251.56 361.284 0.01 0.000140196 8.387e-05 5 1 1 1 20 18 0.515002 nan -0.515002 -0.515002 0 0 4350.07 483.341 0.00 6.3237e-05 4.0785e-05 +k6_N10_mem32K_40nm.xml single_ff.v common 0.34 0.03 3380 1 0.01 -1 -1 27696 -1 -1 1 2 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run002/k6_N10_mem32K_40nm.xml/single_ff.v/common 22260 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.570641 -0.944653 -0.570641 0.570641 6.987e-06 3.4e-06 5.3082e-05 3.3742e-05 2 2 2 53894 53894 1165.58 129.509 0.00 0.000183404 0.000125493 2 2 3 3 67 41 0.576831 0.576831 -0.957916 -0.576831 0 0 1165.58 129.509 0.00 0.00010899 7.8635e-05 +k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 6.31 0.07 6696 3 0.23 -1 -1 31532 -1 -1 70 99 1 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run002/k6_N10_mem32K_40nm_i_or_o.xml/ch_intrinsics.v/common 40180 99 130 363 493 1 255 300 19 19 361 o auto 0.07 788 1.84 0.00 2.39119 -230.678 -2.39119 2.39119 0.000391358 0.000344539 0.0524755 0.0469608 36 1409 13 1.79173e+07 4.32058e+06 833707. 2309.44 2.20 0.180928 0.165672 1243 18 822 1177 152174 48894 2.67664 2.67664 -244.043 -2.67664 0 0 1.02328e+06 2834.56 0.06 0.026121 0.0243926 +k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 14.78 0.05 6488 15 0.41 -1 -1 33848 -1 -1 52 162 0 5 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run002/k6_N10_mem32K_40nm_i_or_o.xml/diffeq1.v/common 60280 162 96 999 932 1 707 315 24 24 576 i auto 0.22 6845 3.50 0.01 20.347 -1892.13 -20.347 20.347 0.00130511 0.00117968 0.195164 0.176609 42 12440 38 3.08128e+07 4.78249e+06 1.54255e+06 2678.04 7.29 0.868369 0.804547 11040 26 3897 7922 2279368 499710 22.3056 22.3056 -2031.34 -22.3056 0 0 1.92788e+06 3347.02 0.37 0.101116 0.0954675 +k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.40 0.03 3348 1 0.00 -1 -1 27612 -1 -1 0 1 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run002/k6_N10_mem32K_40nm_i_or_o.xml/single_wire.v/common 18148 1 1 1 2 0 1 2 4 4 16 i auto 0.01 4 0.01 0.00 0.285677 -0.285677 -0.285677 nan 5.661e-06 2.382e-06 3.9615e-05 2.2142e-05 4 5 1 215576 0 2092.17 130.760 0.01 0.000143843 9.1263e-05 5 1 1 1 24 18 0.401292 nan -0.401292 -0.401292 0 0 3281.68 205.105 0.00 0.000124726 7.8184e-05 +k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.45 0.01 3348 1 0.01 -1 -1 27692 -1 -1 1 2 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run002/k6_N10_mem32K_40nm_i_or_o.xml/single_ff.v/common 22260 2 1 3 4 1 3 4 4 4 16 i auto 0.01 6 0.01 0.00 0.629738 -1.0262 -0.629738 0.629738 1.2149e-05 5.53e-06 8.5786e-05 5.6432e-05 8 5 1 215576 53894 4601.64 287.602 0.01 0.000277421 0.000193523 5 1 2 2 53 32 0.664543 0.664543 -1.06388 -0.664543 0 0 5606.09 350.380 0.00 0.000155161 0.000110488 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt index 9bd589c3255..9699a7c692e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.28 0.05 9248 4 0.12 -1 -1 33124 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/run015/k6_N10_mem32K_40nm.xml/stereovision3.v/common 28704 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 395 0.03 0.00 -1 -1 -1 -1 0 0 0 0 20 695 50 1.07788e+06 1.02399e+06 49980.0 1020.00 0.16 0.0645011 0.0526037 571 26 1026 2494 78614 23220 2.58874 2.37064 -190.862 -2.58874 0 0 65453.8 1335.79 0.04 0.0204325 0.0174085 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.30 0.06 6948 4 0.14 -1 -1 31976 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common 42556 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 395 0.03 0.00 -1 -1 -1 -1 0 0 0 0 20 700 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.12 0.0422584 0.0354243 571 26 1026 2494 78441 23084 2.58874 2.37064 -190.862 -2.58874 0 0 65453.8 1335.79 0.03 0.0187379 0.0162504 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt index ae2d48a1500..df699ef8f16 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.05 0.05 9352 4 0.12 -1 -1 33140 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/run015/k6_N10_mem32K_40nm.xml/stereovision3.v/common 28652 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 402 0.09 0.00 2.23968 -167.49 -2.23968 2.12269 0.0003376 0.000271184 0.0410785 0.0318842 519 -1 -1 -1 -1 1.07788e+06 1.02399e+06 207176. 4228.08 9 2.603 2.54078 -189.078 -2.603 0 0 0.03 0.0448481 0.0353861 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.16 0.07 6944 4 0.16 -1 -1 31456 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common 38436 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 402 0.08 0.00 2.23968 -167.49 -2.23968 2.12269 0.000229487 0.000177458 0.0254047 0.0195965 521 -1 -1 -1 -1 1.07788e+06 1.02399e+06 207176. 4228.08 11 2.53215 2.38348 -182.279 -2.53215 0 0 0.05 0.0292999 0.0232822 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt index 70592e308f9..74ac257a0dd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -sub_tiles.xml sub_tiles.blif common_--check_route_full 1.80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run004/sub_tiles.xml/sub_tiles.blif/common_--check_route_full 46088 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 1.37 0.00 3.87729 -27.141 -3.87729 nan 3.5931e-05 2.6291e-05 0.000126829 9.2438e-05 6 19 4 14813.4 192574 -1 -1 0.04 0.000697701 0.000494867 19 2 32 34 5402 2849 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000609721 0.000425509 -sub_tiles.xml sub_tiles.blif common_--check_route_quick 1.80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run004/sub_tiles.xml/sub_tiles.blif/common_--check_route_quick 46144 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 1.40 0.00 3.87729 -27.141 -3.87729 nan 3.4256e-05 2.4869e-05 0.000122996 9.0043e-05 6 19 4 14813.4 192574 -1 -1 0.04 0.00060591 0.00042679 19 2 32 34 5402 2849 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00030006 0.000214753 -sub_tiles.xml sub_tiles.blif common_--check_route_off 1.75 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run004/sub_tiles.xml/sub_tiles.blif/common_--check_route_off 46172 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 1.37 0.00 3.87729 -27.141 -3.87729 nan 3.4104e-05 2.4533e-05 0.000123891 8.9864e-05 6 19 4 14813.4 192574 -1 -1 0.04 0.000640294 0.00044823 19 2 32 34 5402 2849 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000243534 0.000170302 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common_--check_route_full 4.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run002/sub_tiles.xml/sub_tiles.blif/common_--check_route_full 30072 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 3.70 0.00 3.87729 -27.141 -3.87729 nan 1.2388e-05 7.622e-06 7.447e-05 5.1285e-05 6 19 3 14813.4 192574 -1 -1 0.05 0.000328242 0.000238578 19 3 34 37 8289 3450 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000185505 0.000127799 +sub_tiles.xml sub_tiles.blif common_--check_route_quick 4.27 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run002/sub_tiles.xml/sub_tiles.blif/common_--check_route_quick 28660 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 3.70 0.00 3.87729 -27.141 -3.87729 nan 1.2391e-05 7.789e-06 7.4084e-05 5.0659e-05 6 19 3 14813.4 192574 -1 -1 0.05 0.000320558 0.000230222 19 3 34 37 8289 3450 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000212398 0.000156679 +sub_tiles.xml sub_tiles.blif common_--check_route_off 4.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run002/sub_tiles.xml/sub_tiles.blif/common_--check_route_off 29600 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 3.70 0.00 3.87729 -27.141 -3.87729 nan 1.2291e-05 7.807e-06 7.626e-05 5.2617e-05 6 19 3 14813.4 192574 -1 -1 0.05 0.000345502 0.000245196 19 3 34 37 8289 3450 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000287502 0.000210268 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index 21222b332bc..e47c6fc182b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.03 0.01 5816 1 0.02 -1 -1 29900 -1 -1 3 9 0 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/run015/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common 26016 9 8 71 66 1 37 20 5 5 25 clb auto 0.47 85 0.06 0.00 2.22275 -22.7102 -2.22275 2.22275 0.000143941 0.000119207 0.019139 0.0157608 26 199 19 151211 75605.7 37105.9 1484.24 0.04 0.0304893 0.0250386 166 14 147 195 5055 2690 3.84065 3.84065 -36.0874 -3.84065 0 0 45067.1 1802.68 0.01 0.00348874 0.00302937 14 16 16 6 0 0 -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 2.92 0.02 5952 1 0.02 -1 -1 30440 -1 -1 8 19 0 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/run015/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common 28404 19 18 299 240 1 150 45 6 6 36 clb auto 1.94 498 0.11 0.00 3.67246 -67.9518 -3.67246 3.67246 0.00027031 0.000219413 0.0391563 0.03287 52 1244 30 403230 201615 110337. 3064.92 0.27 0.118437 0.100608 980 19 973 1386 60799 23055 5.39047 5.39047 -120.052 -5.39047 0 0 143382. 3982.83 0.03 0.0163773 0.0147932 62 81 85 13 0 0 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.18 0.02 3344 1 0.01 -1 -1 27784 -1 -1 3 9 0 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/run002/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common 21664 9 8 71 66 1 37 20 5 5 25 clb auto 0.56 85 0.03 0.00 2.22275 -22.7102 -2.22275 2.22275 3.4614e-05 2.5764e-05 0.0050787 0.00393591 26 199 19 151211 75605.7 37105.9 1484.24 0.03 0.0123078 0.0100505 170 14 142 193 4705 2511 3.14757 3.14757 -34.7115 -3.14757 0 0 45067.1 1802.68 0.01 0.00385458 0.00354101 14 16 16 6 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 3.10 0.03 3604 1 0.02 -1 -1 28092 -1 -1 8 19 0 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/run002/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common 29308 19 18 299 240 1 150 45 6 6 36 clb auto 2.16 498 0.10 0.00 3.67246 -67.9518 -3.67246 3.67246 0.000143038 0.000108869 0.0220539 0.0178043 50 1334 44 403230 201615 107229. 2978.57 0.20 0.06972 0.058608 966 20 984 1535 63702 24337 6.03514 6.03514 -119.678 -6.03514 0 0 134937. 3748.26 0.03 0.0141196 0.0130567 62 81 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt index 6f371323b68..1974073f3b1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run009/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 19548 1 4 28 32 2 10 9 4 4 16 clb auto 0.01 20 0.03 0.00 2.18276 0 0 2.18276 6.7283e-05 5.2326e-05 0.00815367 0.00626288 8 20 5 215576 215576 5503.53 343.971 0.03 0.0157619 0.0120416 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.000982231 0.000821075 -timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run009/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 19656 1 4 28 32 2 10 9 4 4 16 clb auto 0.00 20 0.02 0.00 2.18276 0 0 2.18276 4.6786e-05 3.6598e-05 0.00472127 0.00352975 8 20 5 215576 215576 5503.53 343.971 0.02 0.00917158 0.00685601 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.00126981 0.00106383 -timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run009/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 19500 1 4 28 32 2 10 9 4 4 16 clb auto 0.01 20 0.02 0.00 2.18276 0 0 2.18276 6.3783e-05 4.9035e-05 0.00495275 0.00373809 8 20 5 215576 215576 5503.53 343.971 0.02 0.00973133 0.00733373 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.000838713 0.000702013 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run002/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 18400 1 4 28 32 2 10 9 4 4 16 clb auto 0.01 20 0.01 0.00 2.18276 0 0 2.18276 1.5917e-05 1.0257e-05 0.00172397 0.00112996 8 20 5 215576 215576 5503.53 343.971 0.01 0.004242 0.00310874 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.000703857 0.000634713 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run002/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 20444 1 4 28 32 2 10 9 4 4 16 clb auto 0.01 20 0.02 0.00 2.18276 0 0 2.18276 2.7053e-05 1.8727e-05 0.00283269 0.00196492 8 20 5 215576 215576 5503.53 343.971 0.02 0.00654403 0.00493255 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.000669596 0.000599337 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run002/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 18404 1 4 28 32 2 10 9 4 4 16 clb auto 0.01 20 0.02 0.00 2.18276 0 0 2.18276 1.6271e-05 1.0634e-05 0.00208481 0.00142279 8 20 5 215576 215576 5503.53 343.971 0.01 0.00437003 0.00321301 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.000680294 0.000610781 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt index b1454517013..f1ca684344e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-2368-g3c56542c2-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-111-generic x86_64 2020-08-07T14:08:33 goeders-ssh0 /home/shadtorrie/git/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/run116/timing/k6_N10_40nm.xml/clock_set_delay_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 8512 2 2 22 24 2 4 6 4 4 16 clb auto 0.01 4 0.01 0.00 1.293 0 0 1.293 1.181e-05 8.064e-06 0.000109995 9.1012e-05 6 20 2 215576 107788 3924.73 245.296 0.01 0.000804665 0.000648399 7 2 3 3 135 78 1.293 1.293 0 0 0 0 5503.53 343.971 0.00 0.000288477 0.000259906 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/run002/timing/k6_N10_40nm.xml/clock_set_delay_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 16276 2 2 22 24 2 4 6 4 4 16 clb auto 0.01 4 0.01 0.00 1.293 0 0 1.293 1.6288e-05 1.0388e-05 0.000159115 0.000129766 6 20 2 215576 107788 3924.73 245.296 0.01 0.000641511 0.000546125 7 2 3 3 135 78 1.293 1.293 0 0 0 0 5503.53 343.971 0.00 0.000405705 0.000357855 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt index 9acd474a6e5..81b31136d7c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets -timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.23 0.00 5132 1 0.01 -1 -1 29836 -1 -1 1 2 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 18736 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.571526 -0.946421 -0.571526 0.571526 1.7441e-05 1.149e-05 7.1145e-05 4.8641e-05 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.000254072 0.000169134 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.22 0.00 5088 1 0.00 -1 -1 29712 -1 -1 1 2 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 18828 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.00 0.526189 -0.94819 -0.526189 0.526189 2.6654e-05 1.7791e-05 0.000101225 7.076e-05 -1 5 2 53894 53894 14028.3 1558.70 0.00 0.000323996 0.00021954 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 3.22 0.25 52116 2 0.91 -1 -1 50852 -1 -1 155 5 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 26512 5 156 191 347 1 163 316 15 15 225 clb auto 0.04 22 0.16 0.00 1.10064 -11.4028 -1.10064 1.10064 0.00018189 0.000157805 0.0168641 0.0144931 -1 38 4 9.10809e+06 8.35357e+06 828754. 3683.35 0.00 0.0200693 0.0173657 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 3.20 0.32 52072 2 0.99 -1 -1 50968 -1 -1 155 5 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 26700 5 156 191 347 1 163 316 15 15 225 clb auto 0.05 25 0.11 0.00 1.08173 -11.7171 -1.08173 1.08173 0.000168376 0.000145799 0.0118848 0.0101721 -1 53 5 9.10809e+06 8.35357e+06 858153. 3814.01 0.01 0.0153738 0.0132187 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 -timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.29 0.02 5524 1 0.01 -1 -1 29668 -1 -1 1 2 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_mem32K_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 24540 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.571526 -0.946421 -0.571526 0.571526 2.2399e-05 1.4995e-05 0.000108559 7.325e-05 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.000326066 0.00021689 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.27 0.01 5604 1 0.01 -1 -1 29632 -1 -1 1 2 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_mem32K_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 24584 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.00 0.526189 -0.94819 -0.526189 0.526189 1.666e-05 1.0936e-05 6.8312e-05 4.7081e-05 -1 5 2 53894 53894 14028.3 1558.70 0.00 0.000220808 0.000149648 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 -timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 4.05 0.13 16332 2 0.08 -1 -1 33604 -1 -1 32 311 15 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_mem32K_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 52004 311 156 972 1128 1 953 514 28 28 784 memory auto 0.32 8018 1.16 0.01 3.83829 -4111.97 -3.83829 3.83829 0.00233626 0.00199214 0.349669 0.293018 -1 12414 17 4.25198e+07 9.94461e+06 2.96205e+06 3778.13 0.81 0.474833 0.406689 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 -timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 4.59 0.12 16324 2 0.09 -1 -1 33564 -1 -1 32 311 15 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_mem32K_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 52228 311 156 972 1128 1 953 514 28 28 784 memory auto 0.33 8012 1.39 0.01 4.15843 -3579.44 -4.15843 4.15843 0.00258934 0.00213737 0.40798 0.337577 -1 12768 17 4.25198e+07 9.94461e+06 3.02951e+06 3864.17 1.00 0.53661 0.454871 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.21 0.01 2836 1 0.00 -1 -1 27704 -1 -1 1 2 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run002/timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 18076 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.571526 -0.946421 -0.571526 0.571526 6.724e-06 3.208e-06 5.0488e-05 3.2064e-05 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.000178195 0.000119393 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.21 0.01 2828 1 0.00 -1 -1 27708 -1 -1 1 2 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run002/timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 16032 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.00 0.526189 -0.94819 -0.526189 0.526189 6.893e-06 3.289e-06 4.9135e-05 3.0638e-05 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.000163423 0.000108532 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 3.73 0.31 52032 2 1.09 -1 -1 45304 -1 -1 155 5 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run002/timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 30184 5 156 191 347 1 163 316 15 15 225 clb auto 0.04 22 0.11 0.00 1.10064 -11.4028 -1.10064 1.10064 0.000146031 0.000129005 0.00858668 0.00754068 -1 38 3 9.10809e+06 8.35357e+06 828754. 3683.35 0.00 0.0116239 0.0103636 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 3.82 0.31 52028 2 1.14 -1 -1 45108 -1 -1 155 5 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run002/timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 32232 5 156 191 347 1 163 316 15 15 225 clb auto 0.03 25 0.13 0.00 1.08173 -11.7171 -1.08173 1.08173 0.000145826 0.000128208 0.0109639 0.00962759 -1 42 3 9.10809e+06 8.35357e+06 858153. 3814.01 0.00 0.0138801 0.0123598 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.27 0.02 3384 1 0.01 -1 -1 27704 -1 -1 1 2 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run002/timing/k6_N10_mem32K_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 22268 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.571526 -0.946421 -0.571526 0.571526 6.73e-06 3.125e-06 5.2834e-05 3.3914e-05 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.000181272 0.000121852 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.24 0.02 3388 1 0.01 -1 -1 27712 -1 -1 1 2 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run002/timing/k6_N10_mem32K_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 20220 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.00 0.526189 -0.94819 -0.526189 0.526189 7.068e-06 3.464e-06 5.1777e-05 3.3184e-05 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.00017655 0.000119346 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 4.69 0.16 14224 2 0.10 -1 -1 34708 -1 -1 32 311 15 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run002/timing/k6_N10_mem32K_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 51148 311 156 972 1128 1 953 514 28 28 784 memory auto 0.39 7648 1.40 0.01 3.69723 -4053.17 -3.69723 3.69723 0.00289423 0.0025068 0.437359 0.374786 -1 12238 15 4.25198e+07 9.94461e+06 2.96205e+06 3778.13 0.89 0.573133 0.500593 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 4.63 0.15 14220 2 0.11 -1 -1 32664 -1 -1 32 311 15 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run002/timing/k6_N10_mem32K_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 53200 311 156 972 1128 1 953 514 28 28 784 memory auto 0.38 8057 1.41 0.01 4.09939 -3298.68 -4.09939 4.09939 0.00289764 0.00254174 0.436395 0.37645 -1 12870 15 4.25198e+07 9.94461e+06 3.02951e+06 3864.17 0.78 0.572073 0.502178 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt index d983f4b783d..d26b1ac7cff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.43 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/run004/k6_frac_N10_mem32K_40nm_clk_pll_valid.xml/multiclock_buf.blif/common 25580 8 4 25 28 5 19 19 6 6 36 clb auto 0.28 33 0.02 0.00 1.2518 -5.38119 -1.2518 0.545 3.9051e-05 2.9422e-05 0.00485776 0.00345104 88 18 18 1374 518 431152 215576 56755.0 1576.53 2 1.72803 0.545 -7.04473 -1.72803 -0.669015 -0.398071 0.00 0.00545285 0.00391538 -k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/run004/k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml/multiclock_buf.blif/common 17160 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/run002/k6_frac_N10_mem32K_40nm_clk_pll_valid.xml/multiclock_buf.blif/common 25136 8 4 25 28 5 19 19 6 6 36 clb auto 0.34 33 0.01 0.00 1.2518 -5.38119 -1.2518 0.545 1.5962e-05 1.0261e-05 0.00216054 0.00128125 88 21 21 1517 564 431152 215576 56755.0 1576.53 4 1.72803 0.545 -7.04473 -1.72803 -0.669015 -0.398071 0.00 0.00271492 0.00172899 +k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/run002/k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml/multiclock_buf.blif/common 8648 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt index 47a59b4a85f..07e0bac3ce6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/run015/k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common 25076 -1 2 2 4 0 2 4 4 4 16 clb auto 0.00 0 0.01 0.00 nan 0 0 nan 1.3744e-05 8.231e-06 6.572e-05 4.2352e-05 2 0 1 107788 107788 1342.00 83.8749 0.01 0.000188746 0.000121875 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.000109803 7.5671e-05 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/run002/k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common 22232 -1 2 2 4 0 2 4 4 4 16 clb auto 0.01 0 0.01 0.00 nan 0 0 nan 7.027e-06 2.715e-06 4.5667e-05 2.5174e-05 2 0 1 107788 107788 1342.00 83.8749 0.00 0.0001313 7.9905e-05 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 6.4143e-05 4.2229e-05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index b68393c4b96..74a21719e8c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -fixed_grid.xml raygentop.v common 32.14 0.34 30692 3 1.15 -1 -1 40444 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/fixed_grid.xml/raygentop.v/common 79440 214 305 2964 2870 1 1438 634 25 25 625 -1 25x25 2.14 12433 2.85 0.01 4.27896 -2529.83 -4.27896 4.27896 0.00310914 0.00268943 0.473982 0.4021 50 27096 39 3.19446e+07 8.93466e+06 2.03477e+06 3255.63 20.78 2.07927 1.82354 22100 20 7309 16834 4662790 1022693 4.87864 4.87864 -2997.81 -4.87864 0 0 2.70140e+06 4322.25 0.81 0.210053 0.19299 -column_io.xml raygentop.v common 16.28 0.31 30576 3 1.08 -1 -1 40404 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/column_io.xml/raygentop.v/common 73260 214 305 2964 2870 1 1438 634 25 25 625 io auto 2.11 11453 2.49 0.01 4.49554 -2526.95 -4.49554 4.49554 0.00304143 0.00264159 0.409192 0.34743 52 25238 32 2.82259e+07 8.93466e+06 1.94438e+06 3111.01 5.87 1.3259 1.16988 21443 16 5916 12766 3066686 667810 4.88861 4.88861 -3042.94 -4.88861 0 0 2.55773e+06 4092.38 0.53 0.178769 0.166464 -multiwidth_blocks.xml raygentop.v common 15.70 0.38 30632 3 1.26 -1 -1 40500 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/multiwidth_blocks.xml/raygentop.v/common 67544 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 2.19 10759 2.30 0.01 4.33368 -2452.19 -4.33368 4.33368 0.00304881 0.00265461 0.458839 0.391485 66 22580 50 1.65001e+07 8.93466e+06 1.25644e+06 3480.44 5.85 1.47914 1.30527 19187 14 5762 12949 4054788 991646 4.85255 4.85255 -2921.26 -4.85255 0 0 1.57029e+06 4349.83 0.70 0.175554 0.164092 -non_column.xml raygentop.v common 34.36 0.34 30864 3 1.04 -1 -1 40524 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/non_column.xml/raygentop.v/common 98700 214 305 2964 2870 1 1438 634 33 33 1089 io auto 2.12 13674 3.76 0.01 4.4409 -2597.8 -4.4409 4.4409 0.00286403 0.00250291 0.422186 0.358431 42 32841 48 5.44432e+07 8.93466e+06 2.65355e+06 2436.68 21.40 1.92776 1.68935 25196 24 8281 18643 4750391 1157127 5.14301 5.14301 -3217.38 -5.14301 0 0 3.33682e+06 3064.11 0.84 0.228471 0.210195 -non_column_tall_aspect_ratio.xml raygentop.v common 22.75 0.34 30836 3 1.14 -1 -1 40524 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/non_column_tall_aspect_ratio.xml/raygentop.v/common 99468 214 305 2964 2870 1 1438 634 23 46 1058 io auto 2.07 13161 3.74 0.01 4.53129 -2590.45 -4.53129 4.53129 0.00293991 0.00255505 0.426191 0.361146 48 28227 43 5.05849e+07 8.93466e+06 3.02110e+06 2855.48 9.68 1.52391 1.34245 22800 16 6240 14099 3206151 774400 5.24897 5.24897 -3134.25 -5.24897 0 0 3.85688e+06 3645.44 0.60 0.191899 0.177672 -non_column_wide_aspect_ratio.xml raygentop.v common 24.94 0.39 30912 3 1.10 -1 -1 40428 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/non_column_wide_aspect_ratio.xml/raygentop.v/common 94324 214 305 2964 2870 1 1438 634 43 22 946 io auto 2.32 13891 3.53 0.01 4.43985 -2787.05 -4.43985 4.43985 0.00311606 0.00270965 0.42392 0.359652 46 29178 37 4.55909e+07 8.93466e+06 2.54300e+06 2688.17 11.87 1.37639 1.20633 23948 19 6853 15830 3958847 942808 5.14016 5.14016 -3266.42 -5.14016 0 0 3.26968e+06 3456.32 0.77 0.204084 0.188245 -custom_sbloc.xml raygentop.v common 14.51 0.37 30684 3 1.14 -1 -1 40424 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/custom_sbloc.xml/raygentop.v/common 67116 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 2.09 10923 2.20 0.01 4.37821 -2527.54 -4.37821 4.37821 0.00299357 0.00255811 0.448137 0.379618 64 23396 48 1.65001e+07 8.93466e+06 1.19565e+06 3312.06 4.89 1.25479 1.09924 19687 17 5978 13180 3973491 953556 4.82034 4.82034 -3060.92 -4.82034 0 0 1.50465e+06 4168.01 0.64 0.1864 0.17368 -multiple_io_types.xml raygentop.v common 168.17 0.35 30676 3 1.03 -1 -1 40524 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/multiple_io_types.xml/raygentop.v/common 418024 214 305 2964 2870 1 1438 634 67 67 4489 io_left auto 2.64 38230 28.16 0.01 6.79184 -4560.73 -6.79184 6.79184 0.00289183 0.00248393 0.470717 0.396242 54 52339 48 2.48753e+08 8.93466e+06 1.32429e+07 2950.07 119.61 1.90407 1.67449 47802 13 6253 13980 6759458 1620836 7.06436 7.06436 -4977.72 -7.06436 0 0 1.71824e+07 3827.68 1.01 0.151637 0.141993 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_grid.xml raygentop.v common 28.04 0.53 28248 3 1.13 -1 -1 38196 -1 -1 111 214 0 8 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run002/fixed_grid.xml/raygentop.v/common 72648 214 305 2963 2869 1 1440 638 25 25 625 -1 25x25 2.74 11823 3.63 0.01 4.20109 -2559.97 -4.20109 4.20109 0.00372541 0.00335662 0.618281 0.55746 52 23939 30 3.19446e+07 9.15023e+06 2.10129e+06 3362.06 14.17 2.4261 2.2269 20984 16 5514 12476 3273512 731141 4.89303 4.89303 -3026.26 -4.89303 0 0 2.76576e+06 4425.22 0.79 0.269305 0.255823 +column_io.xml raygentop.v common 23.36 0.48 28244 3 1.13 -1 -1 38196 -1 -1 111 214 0 8 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run002/column_io.xml/raygentop.v/common 74684 214 305 2963 2869 1 1440 638 25 25 625 io auto 2.74 11086 3.17 0.01 4.46209 -2486.32 -4.46209 4.46209 0.00399585 0.0036143 0.526061 0.47501 52 25265 32 2.82259e+07 9.15023e+06 1.94438e+06 3111.01 8.65 1.73234 1.59072 20771 18 5648 12575 3186911 695900 4.99978 4.99978 -2922.86 -4.99978 0 0 2.55773e+06 4092.38 0.70 0.253707 0.239607 +multiwidth_blocks.xml raygentop.v common 17.75 0.42 28252 3 1.14 -1 -1 38168 -1 -1 111 214 0 8 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run002/multiwidth_blocks.xml/raygentop.v/common 76608 214 305 2963 2869 1 1440 638 19 19 361 io clb auto 2.81 10875 2.87 0.01 4.39313 -2533.87 -4.39313 4.39313 0.00397097 0.00357617 0.598998 0.54012 66 24088 48 1.65001e+07 9.15023e+06 1.25644e+06 3480.44 6.06 1.78052 1.63469 19905 19 6398 14695 3944021 996562 4.84807 4.84807 -2967.26 -4.84807 0 0 1.57029e+06 4349.83 0.81 0.265907 0.251574 +non_column.xml raygentop.v common 35.21 0.61 28476 3 1.12 -1 -1 38192 -1 -1 111 214 0 8 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run002/non_column.xml/raygentop.v/common 88352 214 305 2963 2869 1 1440 638 33 33 1089 io auto 2.84 12646 4.61 0.01 4.42704 -2538.33 -4.42704 4.42704 0.00390217 0.00353335 0.533727 0.482188 56 23560 22 5.44432e+07 9.15023e+06 3.43439e+06 3153.71 18.89 2.33968 2.14511 22257 19 5758 12773 3272277 827572 4.98687 4.98687 -2989.6 -4.98687 0 0 4.38776e+06 4029.17 0.75 0.260394 0.246336 +non_column_tall_aspect_ratio.xml raygentop.v common 38.90 0.65 28464 3 1.13 -1 -1 38192 -1 -1 111 214 0 8 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run002/non_column_tall_aspect_ratio.xml/raygentop.v/common 82848 214 305 2963 2869 1 1440 638 23 46 1058 io auto 3.02 12816 4.42 0.01 4.46426 -2744.27 -4.46426 4.46426 0.00386513 0.00348539 0.522543 0.472563 44 28795 45 5.05849e+07 9.15023e+06 2.72257e+06 2573.32 22.70 2.35276 2.15969 22546 19 6950 15806 3966981 947597 5.13526 5.13526 -3188.64 -5.13526 0 0 3.54171e+06 3347.55 0.88 0.262957 0.248732 +non_column_wide_aspect_ratio.xml raygentop.v common 30.15 0.53 28468 3 1.14 -1 -1 38196 -1 -1 111 214 0 8 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run002/non_column_wide_aspect_ratio.xml/raygentop.v/common 85796 214 305 2963 2869 1 1440 638 43 22 946 io auto 2.94 13910 4.14 0.01 4.56584 -2789.95 -4.56584 4.56584 0.00424477 0.00383225 0.574779 0.522799 48 27569 39 4.55909e+07 9.15023e+06 2.61331e+06 2762.48 14.71 2.25856 2.07391 22968 17 6755 15690 4318355 1047066 4.99019 4.99019 -3243.66 -4.99019 0 0 3.33573e+06 3526.14 1.00 0.270191 0.254942 +custom_sbloc.xml raygentop.v common 23.15 0.49 28248 3 1.28 -1 -1 38200 -1 -1 111 214 0 8 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run002/custom_sbloc.xml/raygentop.v/common 74672 214 305 2963 2869 1 1440 638 19 19 361 io clb auto 2.83 10997 2.72 0.01 4.46787 -2561.46 -4.46787 4.46787 0.00397924 0.00359094 0.57399 0.51933 70 21614 20 1.65001e+07 9.15023e+06 1.29772e+06 3594.79 11.43 2.2712 2.0852 19206 16 5435 12413 4031189 927241 4.84918 4.84918 -2941.08 -4.84918 0 0 1.63975e+06 4542.24 0.79 0.239109 0.227062 +multiple_io_types.xml raygentop.v common 188.00 0.47 28268 3 1.12 -1 -1 38196 -1 -1 111 214 0 8 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run002/multiple_io_types.xml/raygentop.v/common 403668 214 305 2963 2869 1 1440 638 67 67 4489 io_left auto 3.40 37050 32.41 0.01 5.38629 -4371.06 -5.38629 5.38629 0.00333214 0.00299604 0.46892 0.421885 46 53400 36 2.48753e+08 9.15023e+06 1.14498e+07 2550.63 132.02 2.3049 2.11157 47679 17 7366 16415 7588104 1735788 5.91175 5.91175 -4814.2 -5.91175 0 0 1.47872e+07 3294.09 1.29 0.213457 0.202147 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt index 3166a11066d..65b5b94e915 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 2.39 0.04 8916 3 0.27 -1 -1 36220 -1 -1 65 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/run015/k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common 36108 99 130 363 493 1 251 295 12 12 144 clb auto 0.12 633 0.48 0.00 2.00656 -201.062 -2.00656 2.00656 0.000405159 0.000350221 0.0537882 0.0463387 50 1406 15 5.66058e+06 4.05111e+06 423042. 2937.80 0.50 0.144363 0.127655 1316 10 578 760 65734 22502 2.47507 2.47507 -237.488 -2.47507 0 0 561550. 3899.65 0.04 0.0217154 0.0199903 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 2.76 0.07 6716 3 0.29 -1 -1 31536 -1 -1 65 99 1 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/run002/k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common 41684 99 130 363 493 1 251 295 12 12 144 clb auto 0.12 633 0.54 0.00 2.00656 -201.062 -2.00656 2.00656 0.000395525 0.000351497 0.0546874 0.048402 50 1412 15 5.66058e+06 4.05111e+06 418267. 2904.63 0.56 0.156865 0.143097 1318 12 596 762 50158 17266 2.45758 2.45758 -238.852 -2.45758 0 0 534684. 3713.08 0.03 0.0178395 0.0168983 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt index 33d40f9ef9b..009eeba038a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.28 0.04 8840 4 0.19 -1 -1 33940 -1 -1 75 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/run015/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/ch_intrinsics.v/common 36036 99 130 378 508 1 307 305 15 15 225 memory auto 0.04 805 0.38 0.00 1.48585 -153.891 -1.48585 1.48585 0.000417369 0.000361723 0.0624584 0.0535332 1265 695 1705 233724 60603 1.16234e+06 375248 2.18283e+06 9701.45 18 1.86698 1.86698 -178.287 -1.86698 -0.0308982 -0.0308982 0.05 0.0803599 0.0696521 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.75 0.10 6588 4 0.25 -1 -1 33588 -1 -1 75 99 1 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/run002/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/ch_intrinsics.v/common 37268 99 130 378 508 1 307 305 15 15 225 memory auto 0.05 805 0.38 0.00 1.48585 -153.891 -1.48585 1.48585 0.000412676 0.000360107 0.0530387 0.0472305 1267 697 1728 233122 60204 1.16234e+06 375248 2.18283e+06 9701.45 18 1.86698 1.86698 -178.211 -1.86698 -0.0308982 -0.0308982 0.06 0.0730797 0.0658141 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt index 50eef810267..32a40624aa4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets -timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 14.17 0.12 16360 2 0.10 -1 -1 34244 -1 -1 29 311 15 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run015/timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 71668 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.49 8249 2.68 0.01 4.06259 -3369.31 -4.06259 4.06259 0.00239796 0.002034 0.342229 0.283615 36 15880 24 4.25198e+07 9.78293e+06 1.97160e+06 2514.80 5.63 0.95166 0.824493 13986 16 3061 3486 4980323 2134077 4.66801 4.66801 -4358.27 -4.66801 -426.967 -1.41574 2.42825e+06 3097.26 1.74 0.113561 0.10334 15 950 -timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 13.97 0.09 16356 2 0.12 -1 -1 34376 -1 -1 29 311 15 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run015/timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 73024 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.49 8216 2.73 0.01 3.87435 -3448.99 -3.87435 3.87435 0.00259015 0.00209923 0.369649 0.306293 36 15614 20 4.25198e+07 9.78293e+06 2.00618e+06 2558.90 5.74 0.994123 0.859995 13962 15 3531 4036 3370681 961715 4.1019 4.1019 -4151.44 -4.1019 -238.207 -1.50963 2.47848e+06 3161.33 1.34 0.108281 0.0984048 15 950 -timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 14.52 0.09 16428 2 0.12 -1 -1 34384 -1 -1 29 311 15 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run015/timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 73400 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.56 8117 2.44 0.01 3.8524 -3651.42 -3.8524 3.8524 0.00221509 0.0018317 0.324477 0.268193 40 16634 25 4.25198e+07 9.78293e+06 2.15085e+06 2743.43 5.93 0.926307 0.801747 15345 15 2987 3412 5488063 2593602 5.42665 5.42665 -4393.57 -5.42665 -1602.53 -3.37364 2.68809e+06 3428.68 1.98 0.105948 0.0966677 15 950 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 25.25 0.20 14284 2 0.13 -1 -1 33068 -1 -1 29 311 15 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run002/timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 65424 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.60 8024 2.97 0.01 4.74102 -3573.4 -4.74102 4.74102 0.00285776 0.00247926 0.413962 0.355212 38 15347 25 4.25198e+07 9.78293e+06 2.06185e+06 2629.91 15.57 1.45756 1.30372 13771 16 3402 3768 3500790 1239035 4.40787 4.40787 -4272.15 -4.40787 -405.941 -1.4191 2.60823e+06 3326.82 1.73 0.149631 0.139358 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 21.00 0.19 14288 2 0.15 -1 -1 33596 -1 -1 29 311 15 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run002/timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 66316 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.59 8013 2.98 0.01 4.25398 -3574.27 -4.25398 4.25398 0.00281502 0.00241439 0.407377 0.348903 40 15288 17 4.25198e+07 9.78293e+06 2.19000e+06 2793.37 11.16 1.59462 1.42896 13839 13 2970 3363 2766087 788753 4.8363 4.8363 -4420.31 -4.8363 -240.167 -1.24248 2.74289e+06 3498.59 1.59 0.133172 0.124208 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 17.58 0.19 14276 2 0.12 -1 -1 32292 -1 -1 29 311 15 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run002/timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 60524 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.71 8117 3.02 0.01 3.8524 -3651.42 -3.8524 3.8524 0.00278215 0.00239609 0.414196 0.354608 40 16627 22 4.25198e+07 9.78293e+06 2.15085e+06 2743.43 7.10 1.23656 1.10174 15311 15 3109 3524 5490211 2581102 5.30904 5.30904 -4325.31 -5.30904 -1567.11 -3.23864 2.68809e+06 3428.68 2.40 0.148361 0.137911 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt index b331eaebf71..36b4daabac9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 7.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/run014/k4_N4_90nm_default_fc_pinloc.xml/diffeq.blif/common 52868 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.26 10194 1.93 0.01 6.5862 -1367.76 -6.5862 6.5862 0.0017261 0.00134038 0.240938 0.175852 24 12158 27 983127 929624 797780. 1508.09 3.02 0.561167 0.43501 11171 19 7079 24040 1692224 422101 6.8984 6.8984 -1482.36 -6.8984 0 0 1.04508e+06 1975.57 0.46 0.112933 0.095172 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 7.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/run002/k4_N4_90nm_default_fc_pinloc.xml/diffeq.blif/common 53848 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.32 10352 2.02 0.01 6.71108 -1302.88 -6.71108 6.71108 0.00238134 0.00200155 0.238486 0.205075 24 12471 21 983127 929624 797780. 1508.09 2.83 0.594347 0.514412 11271 20 6811 23023 1564433 387864 6.96084 6.96084 -1425.08 -6.96084 0 0 1.04508e+06 1975.57 0.47 0.132686 0.118181 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt index b7312a7c8bc..9354662f157 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 21.85 0.36 30924 4 1.78 -1 -1 39832 -1 -1 167 193 5 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/run015/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common 72028 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.43 10454 2.79 0.01 4.17962 -2464.62 -4.17962 4.17962 0.00387448 0.00316113 0.547803 0.442993 80 20576 38 2.07112e+07 1.17403e+07 2.10510e+06 5262.74 11.79 1.91781 1.6406 18693 16 5010 14283 1459244 324974 4.84767 4.84767 -2845.86 -4.84767 -12.6591 -0.360359 2.64606e+06 6615.15 0.35 0.182318 0.167841 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 22.29 0.37 28228 4 2.15 -1 -1 37000 -1 -1 167 193 5 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/run002/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common 74916 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.79 10767 3.51 0.02 4.38764 -2424.87 -4.38764 4.38764 0.0046601 0.00410848 0.694983 0.610102 76 21837 33 2.07112e+07 1.17403e+07 2.02110e+06 5052.76 9.78 2.36309 2.10955 19921 16 5464 15237 1677966 362561 4.80242 4.80242 -2886.51 -4.80242 -6.84129 -0.340786 2.51807e+06 6295.18 0.52 0.264674 0.247267 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt index 93b763f1be2..28ce7b2c03f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.24 0.05 8984 3 0.20 -1 -1 36332 -1 -1 65 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/run014/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 35616 99 130 363 493 1 251 295 12 12 144 clb auto 0.12 624 0.46 0.00 1.94344 -198.852 -1.94344 1.94344 0.000400353 0.00034645 0.0554696 0.0477651 50 1398 19 5.66058e+06 4.05111e+06 406292. 2821.48 0.49 0.148872 0.131874 1368 9 565 725 73444 24903 2.56877 2.56877 -239.947 -2.56877 0 0 539112. 3743.83 0.03 0.0133877 0.0124567 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.64 0.08 6712 3 0.24 -1 -1 31540 -1 -1 65 99 1 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/run002/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 39636 99 130 363 493 1 251 295 12 12 144 clb auto 0.13 624 0.53 0.00 1.94344 -198.852 -1.94344 1.94344 0.000404759 0.000360521 0.0527646 0.0471224 50 1399 11 5.66058e+06 4.05111e+06 406292. 2821.48 0.56 0.149737 0.136927 1316 9 572 748 52711 18395 2.42731 2.42731 -236.084 -2.42731 0 0 520805. 3616.70 0.03 0.0155824 0.0148396 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index 7f1f4a26028..31f12723ffb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml test_eblif.eblif common 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-2368-g3c56542c2-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-111-generic x86_64 2020-08-07T14:08:33 goeders-ssh0 /home/shadtorrie/git/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/run119/k6_frac_N10_40nm.xml/test_eblif.eblif/common 8832 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.00 0.544641 -0.918653 -0.544641 0.544641 4.815e-06 2.731e-06 3.8107e-05 2.655e-05 20 10 1 53894 53894 4880.82 542.314 0.00 0.000144243 0.000104436 14 2 4 4 76 62 1.21985 1.21985 -1.76449 -1.21985 0 0 6579.40 731.044 0.00 6.8754e-05 5.3143e-05 -k6_frac_N10_40nm.xml conn_order.eblif common 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-2368-g3c56542c2-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-111-generic x86_64 2020-08-07T14:08:33 goeders-ssh0 /home/shadtorrie/git/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/run119/k6_frac_N10_40nm.xml/conn_order.eblif/common 8752 2 1 4 5 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.709011 -1.25365 -0.709011 0.709011 4.339e-06 2.328e-06 3.3398e-05 2.2701e-05 20 11 1 53894 53894 4880.82 542.314 0.00 0.000128923 9.2203e-05 19 1 2 2 66 59 2.01453 2.01453 -2.56006 -2.01453 0 0 6579.40 731.044 0.00 5.915e-05 4.6654e-05 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml test_eblif.eblif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/run002/k6_frac_N10_40nm.xml/test_eblif.eblif/common 14632 3 1 5 6 1 4 5 3 3 9 -1 auto 0.01 6 0.00 0.00 0.544641 -0.918653 -0.544641 0.544641 7.911e-06 4.121e-06 6.193e-05 4.2296e-05 20 10 1 53894 53894 4880.82 542.314 0.00 0.000216662 0.000155656 14 2 4 4 67 53 1.21985 1.21985 -1.76449 -1.21985 0 0 6579.40 731.044 0.00 0.000126455 9.6311e-05 +k6_frac_N10_40nm.xml conn_order.eblif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/run002/k6_frac_N10_40nm.xml/conn_order.eblif/common 18712 2 1 4 5 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.709011 -1.25365 -0.709011 0.709011 7.205e-06 3.544e-06 6.2869e-05 4.344e-05 20 11 1 53894 53894 4880.82 542.314 0.01 0.000207737 0.000150612 19 1 2 2 63 56 2.01453 2.01453 -2.56006 -2.01453 0 0 6579.40 731.044 0.00 0.000110343 8.6347e-05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt index fe9e0078589..7417a16b499 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml eblif_write.eblif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/run014/arch.xml/eblif_write.eblif/common 18544 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 0.00 8 0.01 0.00 0.188362 -0.633245 -0.188362 0.188362 6.543e-05 5.807e-05 0.00141955 0.000897781 2 8 3 59253.6 29626.8 -1 -1 0.01 0.00285527 0.00183743 8 3 6 6 122 69 0.249819 0.249819 -0.756538 -0.249819 0 0 -1 -1 0.00 0.000215509 0.000140858 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml eblif_write.eblif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/run002/arch.xml/eblif_write.eblif/common 11236 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 0.00 8 0.01 0.00 0.188362 -0.633245 -0.188362 0.188362 8.219e-06 3.551e-06 0.000685279 0.000310962 2 8 3 59253.6 29626.8 -1 -1 0.01 0.00130788 0.000685564 8 3 6 6 111 62 0.249819 0.249819 -0.756538 -0.249819 0 0 -1 -1 0.00 0.000130831 9.2828e-05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt index 1e91e93e525..3cc9e0838f6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.13 0.05 9256 4 0.13 -1 -1 33092 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/run015/k6_N10_mem32K_40nm.xml/stereovision3.v/common 27508 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 393 0.13 0.00 2.23968 -171.108 -2.23968 2.13287 0.000286003 0.000229733 0.0321467 0.0249497 -1 476 25 1.07788e+06 1.02399e+06 90369.8 1844.28 0.03 0.0513387 0.04117 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.26 0.07 6948 4 0.15 -1 -1 31728 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common 42568 11 30 262 292 2 104 60 7 7 49 clb auto 0.11 393 0.13 0.00 2.23968 -171.108 -2.23968 2.13287 0.000227592 0.000175381 0.0259973 0.0199792 -1 476 25 1.07788e+06 1.02399e+06 90369.8 1844.28 0.03 0.0446604 0.0361737 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt index 7574a18e313..f57ae196b9e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -equivalent.xml equivalent.blif common 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/run011/equivalent.xml/equivalent.blif/common 18484 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 0.00 7 0.01 0.00 3.6909 -3.6909 -3.6909 nan 1.7662e-05 1.2102e-05 0.00129277 0.000882898 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00155496 0.00105635 3 1 3 3 50 17 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.000152151 9.921e-05 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +equivalent.xml equivalent.blif common 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/run002/equivalent.xml/equivalent.blif/common 11192 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 0.00 7 0.00 0.00 3.6909 -3.6909 -3.6909 nan 5.32e-06 2.053e-06 0.000381521 0.000153212 1 3 1 59253.6 29626.8 -1 -1 0.00 0.000500318 0.000222758 3 1 3 3 89 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 6.0765e-05 3.9105e-05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt index 927861bdd9e..69cc53255d3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.30 0.05 9176 4 0.12 -1 -1 33040 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/run014/k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common 30384 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 401 0.12 0.00 2.2283 -166.679 -2.2283 2.11876 0.000334435 0.000269344 0.0328891 0.0254814 16 574 25 1.07788e+06 1.02399e+06 88828.2 1812.82 0.14 0.0818614 0.0655978 502 28 978 2119 97696 25382 2.88672 2.66584 -203.092 -2.88672 0 0 104221. 2126.97 0.04 0.020146 0.0170636 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.51 0.06 6944 4 0.14 -1 -1 31448 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/run002/k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common 42528 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 394 0.12 0.00 2.2252 -165.622 -2.2252 2.11729 0.00021963 0.000168656 0.0225902 0.0173267 16 557 25 1.07788e+06 1.02399e+06 88828.2 1812.82 0.14 0.0640596 0.0519732 555 41 875 2024 95151 24083 2.87905 2.67344 -202.641 -2.87905 0 0 104221. 2126.97 0.04 0.0257455 0.0221405 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt index 51ab7473e23..87beae5bd10 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -fix_clusters_test_arch.xml apex2.blif common 7.84 -1 -1 -1 -1 -1 -1 -1 -1 -1 141 38 -1 -1 success v8.0.0-2202-g8f11883e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-07-27T19:24:47 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/run037/fix_clusters_test_arch.xml/apex2.blif/common 53244 38 3 1916 1919 0 1062 182 7 7 49 clb auto 2.08 5387 0.18 0.03 4.66816 -13.91 -4.66816 nan 0.00147967 0.0012157 0.0240095 0.0229321 164 7659 37 1.34735e+06 7.59905e+06 957298. 19536.7 4.36 0.824295 0.669083 6946 18 6057 24435 1152150 355904 5.7306 nan -16.8488 -5.7306 0 0 1.19720e+06 24432.6 0.25 0.119777 0.107901 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fix_clusters_test_arch.xml apex2.blif common 8.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 141 38 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/run002/fix_clusters_test_arch.xml/apex2.blif/common 35276 38 3 1916 1919 0 1062 182 7 7 49 clb auto 2.86 5387 0.25 0.03 4.66816 -13.91 -4.66816 nan 0.00187519 0.00162709 0.0313872 0.0302253 164 7581 33 1.34735e+06 7.59905e+06 957298. 19536.7 3.31 0.824572 0.717788 6888 18 6029 24392 1134785 345591 5.73451 nan -16.9018 -5.73451 0 0 1.19720e+06 24432.6 0.33 0.155212 0.142553 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt index 9a134895485..86cd6cfc781 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.42 0.05 9352 4 0.13 -1 -1 33132 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/run014/k6_N10_mem32K_40nm.xml/stereovision3.v/common 29336 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 478 0.14 0.00 2.23968 -173.325 -2.23968 2.1232 0.000376852 0.000231273 0.031811 0.02419 22 792 25 1.07788e+06 1.02399e+06 54623.3 1114.76 0.13 0.0808549 0.0645732 719 45 1163 2902 121680 33636 2.65665 2.40886 -195.159 -2.65665 0 0 69322.2 1414.74 0.06 0.0323268 0.0268877 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.51 0.07 6944 4 0.14 -1 -1 30924 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common 42532 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 478 0.18 0.00 2.23968 -173.325 -2.23968 2.1232 0.000249657 0.000181308 0.0323332 0.0248691 22 792 25 1.07788e+06 1.02399e+06 54623.3 1114.76 0.15 0.0844685 0.0688531 719 45 1163 2902 121530 33542 2.65665 2.40886 -195.159 -2.65665 0 0 69322.2 1414.74 0.05 0.0269099 0.0229606 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt index 6f85a06583d..c79d2fb07e4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -shorted_flyover_wires.xml raygentop.v common 16.33 0.28 30652 3 1.40 -1 -1 40476 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/run015/shorted_flyover_wires.xml/raygentop.v/common 66264 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 2.18 10856 2.36 0.01 4.39652 -2498.48 -4.39652 4.39652 0.00296434 0.00257976 0.462061 0.393261 66 27866 32 1.65001e+07 8.93466e+06 1.15238e+06 3192.19 5.76 1.36556 1.1895 22609 23 6564 15129 5362840 1300782 5.32517 5.32517 -2957.12 -5.32517 0 0 1.43513e+06 3975.42 1.02 0.265233 0.244978 -buffered_flyover_wires.xml raygentop.v common 15.93 0.30 30588 3 1.35 -1 -1 40448 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/run015/buffered_flyover_wires.xml/raygentop.v/common 66324 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 2.21 10890 2.30 0.01 4.35951 -2423.98 -4.35951 4.35951 0.00301783 0.00259087 0.467389 0.396939 68 26177 38 1.65001e+07 8.93466e+06 1.22105e+06 3382.40 5.50 1.41939 1.24455 21304 16 6126 14336 5421684 1304674 4.95972 4.95972 -3001.08 -4.95972 0 0 1.52022e+06 4211.15 0.84 0.181002 0.168567 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +shorted_flyover_wires.xml raygentop.v common 20.55 0.48 28244 3 1.23 -1 -1 38196 -1 -1 111 214 0 8 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/run002/shorted_flyover_wires.xml/raygentop.v/common 74720 214 305 2963 2869 1 1440 638 19 19 361 io clb auto 2.72 11244 2.73 0.01 4.44813 -2545.22 -4.44813 4.44813 0.00416179 0.00377296 0.57668 0.522707 64 27846 33 1.65001e+07 9.15023e+06 1.11360e+06 3084.77 8.12 2.03758 1.87439 23816 17 6829 16255 5284994 1305556 5.17649 5.17649 -3058.41 -5.17649 0 0 1.39747e+06 3871.11 1.09 0.254582 0.2411 +buffered_flyover_wires.xml raygentop.v common 21.56 0.47 28252 3 1.32 -1 -1 38196 -1 -1 111 214 0 8 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/run002/buffered_flyover_wires.xml/raygentop.v/common 74664 214 305 2963 2869 1 1440 638 19 19 361 io clb auto 2.73 10916 2.82 0.01 4.16668 -2495.77 -4.16668 4.16668 0.0038549 0.0034747 0.602541 0.544803 66 26969 49 1.65001e+07 9.15023e+06 1.19176e+06 3301.28 8.81 2.30752 2.12022 21886 20 6888 15553 5667581 1403211 4.98413 4.98413 -2937.21 -4.98413 0 0 1.48698e+06 4119.07 1.30 0.300038 0.283816 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt index 3447c779d7b..8ef7d683e9c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -hard_fpu_arch_timing.xml mm3.v common 2.21 0.02 6364 1 0.02 -1 -1 30536 -1 -1 0 193 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/run015/hard_fpu_arch_timing.xml/mm3.v/common 34840 193 32 545 422 1 289 227 21 21 441 io auto 0.97 3073 0.30 0.00 2.985 -793.195 -2.985 2.985 0.000763196 0.00068747 0.100217 0.0904177 4204 388 388 1639031 600440 809148 68766.3 979092. 2220.16 4 2.985 2.985 -803.223 -2.985 -21.8252 -0.0851 0.21 0.115939 0.10529 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +hard_fpu_arch_timing.xml mm3.v common 2.70 0.08 4044 1 0.02 -1 -1 28352 -1 -1 0 193 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/run002/hard_fpu_arch_timing.xml/mm3.v/common 28920 193 32 545 422 1 289 227 21 21 441 io auto 1.13 3075 0.34 0.00 2.985 -793.857 -2.985 2.985 0.000835041 0.000762044 0.105087 0.096525 4208 381 381 1557957 568832 809148 68766.3 979092. 2220.16 4 2.985 2.985 -803.774 -2.985 -21.7856 -0.0851 0.25 0.124568 0.115271 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt index 52371aa301c..e58efd657a3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 2.27 0.04 8984 3 0.24 -1 -1 36260 -1 -1 67 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/run015/k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common 36352 99 130 363 493 1 249 297 13 13 169 clb auto 0.39 558 0.22 0.00 36 1334 10 0 0 481804. 2850.91 0.46 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 2.71 0.06 6648 3 0.26 -1 -1 31544 -1 -1 67 99 1 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/run002/k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common 38140 99 130 363 493 1 249 297 13 13 169 clb auto 0.50 558 0.26 0.00 36 1348 11 0 0 481804. 2850.91 0.52 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt index 615a5a37d4d..4f3e6ea23aa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.02 0.05 9228 4 0.11 -1 -1 33080 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/run011/k6_N10_mem32K_40nm.xml/stereovision3.v/common 27716 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 393 0.08 0.00 2.23968 -171.108 -2.23968 2.13287 0.000286094 0.000228816 0.0332272 0.0258492 -1 476 25 1.07788e+06 1.02399e+06 90369.8 1844.28 0.04 0.0540432 0.0433436 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.09 0.08 6948 4 0.15 -1 -1 32504 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common 42548 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 393 0.07 0.00 2.23968 -171.108 -2.23968 2.13287 0.000222574 0.000170484 0.024891 0.0189955 -1 476 25 1.07788e+06 1.02399e+06 90369.8 1844.28 0.03 0.0435697 0.0352058 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt index 27ad7a55e6c..63bbb9a5597 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml const_true.blif common 0.26 -1 -1 0 0.00 -1 -1 29572 -1 -1 1 0 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run015/k6_frac_N10_40nm.xml/const_true.blif/common 19384 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 1.2237e-05 7.343e-06 4.9024e-05 3.1558e-05 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000143025 8.9268e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml const_false.blif common 0.22 -1 -1 0 0.01 -1 -1 29700 -1 -1 1 0 -1 -1 success v8.0.0-1877-g77d3b9ae4 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7611c909a58..72683a4fdb1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml const_true.blif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/const_true.blif/common 19160 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 1.2116e-05 7.148e-06 4.9436e-05 3.1401e-05 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000137672 8.6389e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml const_false.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/const_false.blif/common 19108 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 1.6666e-05 1.0142e-05 7.5238e-05 4.8097e-05 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000199786 0.000128102 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_true.blif common 0.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/always_true.blif/common 20012 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.00 0.736421 -0.736421 -0.736421 nan 2.2031e-05 1.5121e-05 9.6391e-05 7.1506e-05 -1 9 13 53894 53894 20487.3 2276.37 0.00 0.000645406 0.000461608 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_false.blif common 0.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/always_false.blif/common 20108 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.00 0.736421 -0.736421 -0.736421 nan 2.2199e-05 1.515e-05 0.000102961 7.5062e-05 -1 9 13 53894 53894 20487.3 2276.37 0.00 0.000582954 0.000398915 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/multiconnected_lut.blif/common 19164 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.00 0.736421 -0.736421 -0.736421 nan 2.403e-05 1.5916e-05 0.000108273 7.5908e-05 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.000338817 0.000242869 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/multiconnected_lut2.blif/common 19080 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.00 0.736421 -0.736421 -0.736421 nan 3.2406e-05 2.2919e-05 0.000149203 0.000107347 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00042548 0.000308476 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run002/k6_frac_N10_40nm.xml/const_true.blif/common 12528 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 6.624e-06 2.36e-06 4.3229e-05 2.3097e-05 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000119872 7.1961e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run002/k6_frac_N10_40nm.xml/const_false.blif/common 12524 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 6.409e-06 2.117e-06 4.3155e-05 2.2471e-05 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000119024 7.1923e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run002/k6_frac_N10_40nm.xml/always_true.blif/common 12584 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.00 0.736421 -0.736421 -0.736421 nan 1.0064e-05 5.535e-06 8.3491e-05 5.9363e-05 -1 8 11 53894 53894 20487.3 2276.37 0.00 0.000418989 0.000301014 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run002/k6_frac_N10_40nm.xml/always_false.blif/common 12588 6 1 7 8 0 7 8 3 3 9 -1 auto 0.01 14 0.00 0.00 0.736421 -0.736421 -0.736421 nan 8.013e-06 4.344e-06 7.3042e-05 5.2734e-05 -1 8 11 53894 53894 20487.3 2276.37 0.00 0.000344159 0.000246324 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run002/k6_frac_N10_40nm.xml/multiconnected_lut.blif/common 12580 5 1 6 7 0 6 7 3 3 9 -1 auto 0.01 12 0.00 0.00 0.736421 -0.736421 -0.736421 nan 8.06e-06 4.37e-06 6.9517e-05 4.9913e-05 -1 7 12 53894 53894 20487.3 2276.37 0.00 0.000345603 0.000246533 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run002/k6_frac_N10_40nm.xml/multiconnected_lut2.blif/common 12580 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.00 0.736421 -0.736421 -0.736421 nan 8.15e-06 4.413e-06 6.9625e-05 4.983e-05 -1 7 12 53894 53894 20487.3 2276.37 0.00 0.000326201 0.000229584 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index 64894c055ba..6f64eacfebf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -x_gaussian_y_uniform.xml stereovision3.v common 1.33 0.05 9276 4 0.11 -1 -1 33060 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_gaussian_y_uniform.xml/stereovision3.v/common 27700 11 30 262 292 2 110 54 7 7 49 clb auto 0.12 367 0.10 0.00 1.91988 -135.359 -1.91988 1.85222 0.000283933 0.000230209 0.0483647 0.0398743 12 301 4 1.07788e+06 700622 -1 -1 0.12 0.0955425 0.0802346 288 2 145 219 14754 5946 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.00863779 0.00815694 -x_uniform_y_gaussian.xml stereovision3.v common 1.34 0.05 9180 4 0.14 -1 -1 33096 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_uniform_y_gaussian.xml/stereovision3.v/common 28048 11 30 262 292 2 110 54 7 7 49 clb auto 0.10 344 0.08 0.00 1.91988 -135.359 -1.91988 1.85222 0.0004883 0.000403134 0.033427 0.0274684 10 314 19 1.07788e+06 700622 -1 -1 0.15 0.0756226 0.0632296 259 3 169 256 15612 6426 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.02 0.0147541 0.0138339 -x_gaussian_y_gaussian.xml stereovision3.v common 1.29 0.05 9328 4 0.10 -1 -1 33056 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_gaussian_y_gaussian.xml/stereovision3.v/common 27792 11 30 262 292 2 110 54 7 7 49 clb auto 0.10 349 0.09 0.00 1.91988 -135.359 -1.91988 1.85222 0.000489259 0.00040451 0.0384295 0.0316628 12 288 8 1.07788e+06 700622 -1 -1 0.16 0.0825146 0.0694766 272 3 159 237 14357 5895 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.00969215 0.00913209 -x_delta_y_uniform.xml stereovision3.v common 1.27 0.06 9324 4 0.11 -1 -1 33136 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_delta_y_uniform.xml/stereovision3.v/common 27940 11 30 262 292 2 110 54 7 7 49 clb auto 0.09 370 0.09 0.00 1.91988 -135.359 -1.91988 1.85222 0.000289699 0.000233697 0.0407541 0.0330296 48 299 3 1.07788e+06 700622 -1 -1 0.13 0.103302 0.0855557 300 2 154 228 16498 6675 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.02 0.0130216 0.0123026 -x_delta_y_delta.xml stereovision3.v common 1.55 0.05 9256 4 0.15 -1 -1 33080 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_delta_y_delta.xml/stereovision3.v/common 27756 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 365 0.14 0.00 1.91988 -135.359 -1.91988 1.85222 0.000479438 0.000397034 0.0652252 0.0543857 48 295 15 1.07788e+06 700622 -1 -1 0.22 0.162305 0.137058 283 11 204 319 22292 8966 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.03 0.0209343 0.0190146 -x_uniform_y_delta.xml stereovision3.v common 1.44 0.05 9256 4 0.12 -1 -1 33080 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_uniform_y_delta.xml/stereovision3.v/common 27928 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 365 0.09 0.00 1.91988 -135.359 -1.91988 1.85222 0.000285296 0.00023051 0.0411397 0.0336476 38 284 2 1.07788e+06 700622 -1 -1 0.19 0.126387 0.106109 287 15 174 293 17775 6988 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.03 0.0230303 0.0205393 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +x_gaussian_y_uniform.xml stereovision3.v common 1.38 0.06 6960 4 0.15 -1 -1 31192 -1 -1 13 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run002/x_gaussian_y_uniform.xml/stereovision3.v/common 41512 11 30 262 292 2 110 54 7 7 49 clb auto 0.11 367 0.08 0.00 1.91988 -135.359 -1.91988 1.85222 0.000217001 0.000167025 0.0281173 0.0222484 12 300 4 1.07788e+06 700622 -1 -1 0.10 0.0624432 0.052014 288 2 145 219 14686 5884 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.0124631 0.0119982 +x_uniform_y_gaussian.xml stereovision3.v common 1.46 0.07 6964 4 0.15 -1 -1 30928 -1 -1 13 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run002/x_uniform_y_gaussian.xml/stereovision3.v/common 43556 11 30 262 292 2 110 54 7 7 49 clb auto 0.11 344 0.07 0.00 1.91988 -135.359 -1.91988 1.85222 0.000222725 0.000172462 0.0249436 0.019778 10 314 19 1.07788e+06 700622 -1 -1 0.17 0.0675648 0.0566131 260 4 222 323 19432 7955 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.02 0.0109737 0.0104268 +x_gaussian_y_gaussian.xml stereovision3.v common 1.35 0.06 6960 4 0.14 -1 -1 32508 -1 -1 13 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run002/x_gaussian_y_gaussian.xml/stereovision3.v/common 41508 11 30 262 292 2 110 54 7 7 49 clb auto 0.11 349 0.07 0.00 1.91988 -135.359 -1.91988 1.85222 0.000218273 0.000168154 0.0271346 0.0214673 12 288 8 1.07788e+06 700622 -1 -1 0.16 0.0638091 0.0532172 272 3 159 237 14275 5820 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.0105418 0.0100526 +x_delta_y_uniform.xml stereovision3.v common 1.37 0.06 6956 4 0.15 -1 -1 30924 -1 -1 13 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run002/x_delta_y_uniform.xml/stereovision3.v/common 39468 11 30 262 292 2 110 54 7 7 49 clb auto 0.11 370 0.08 0.00 1.91988 -135.359 -1.91988 1.85222 0.000220631 0.000170345 0.0322724 0.0255601 48 299 3 1.07788e+06 700622 -1 -1 0.12 0.0897481 0.0745471 300 2 154 228 16368 6614 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.00984045 0.00945171 +x_delta_y_delta.xml stereovision3.v common 1.37 0.06 6956 4 0.15 -1 -1 31976 -1 -1 13 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run002/x_delta_y_delta.xml/stereovision3.v/common 41508 11 30 262 292 2 110 54 7 7 49 clb auto 0.11 365 0.08 0.00 1.91988 -135.359 -1.91988 1.85222 0.000221195 0.000171778 0.0317394 0.0251314 48 295 15 1.07788e+06 700622 -1 -1 0.14 0.0919654 0.0760096 283 11 204 319 22223 8922 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.02 0.0137832 0.0126854 +x_uniform_y_delta.xml stereovision3.v common 1.38 0.06 6960 4 0.15 -1 -1 31188 -1 -1 13 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run002/x_uniform_y_delta.xml/stereovision3.v/common 43564 11 30 262 292 2 110 54 7 7 49 clb auto 0.11 365 0.10 0.00 1.91988 -135.359 -1.91988 1.85222 0.000591414 0.000478467 0.038388 0.0307962 38 284 2 1.07788e+06 700622 -1 -1 0.14 0.0952558 0.0793471 287 15 174 293 17710 6940 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.02 0.0156215 0.0142455 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt index 324955d5572..55cb09a4ea7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 0.03 9256 4 0.12 -1 -1 33032 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run014/timing/k6_N10_mem32K_40nm.xml/stereovision3.v/common 27316 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 393 0.07 0.00 1.93141 -141.327 -1.93141 1.88461 0.000334722 0.000270475 0.0287483 0.0235286 10 332 24 1.07788e+06 1.02399e+06 -1 -1 0.20 0.0949287 0.0786353 322 23 620 1331 105337 41161 1.93141 1.88461 -141.327 -1.93141 0 0 -1 -1 0.07 0.028243 0.0242568 -nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.24 0.05 9324 4 0.13 -1 -1 33156 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run014/nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml/stereovision3.v/common 27144 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 397 0.07 0.00 1.93141 -141.327 -1.93141 1.88461 0.000284883 0.000230777 0.0279787 0.022886 14 351 23 1.07788e+06 1.02399e+06 -1 -1 0.11 0.0703105 0.0585028 324 23 680 1240 112202 45973 1.93141 1.88461 -141.327 -1.93141 0 0 -1 -1 0.04 0.0194268 0.0171311 -nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.38 0.06 9248 4 0.10 -1 -1 33032 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run014/nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml/stereovision3.v/common 27188 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 426 0.11 0.00 1.93141 -141.327 -1.93141 1.88461 0.000933193 0.000749405 0.0426975 0.0353334 14 354 48 1.07788e+06 1.02399e+06 -1 -1 0.27 0.140665 0.116929 353 22 633 1263 104916 43343 1.93141 1.88461 -141.327 -1.93141 0 0 -1 -1 0.04 0.0167794 0.0145753 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.37 0.06 6948 4 0.14 -1 -1 32968 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run002/timing/k6_N10_mem32K_40nm.xml/stereovision3.v/common 40828 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 393 0.07 0.00 1.93141 -141.327 -1.93141 1.88461 0.000227324 0.000175934 0.0225819 0.0178709 10 338 24 1.07788e+06 1.02399e+06 -1 -1 0.17 0.0736285 0.0616624 319 23 620 1329 104896 40975 1.93141 1.88461 -141.327 -1.93141 0 0 -1 -1 0.04 0.017436 0.0154366 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.36 0.06 6948 4 0.14 -1 -1 30920 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run002/nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml/stereovision3.v/common 40484 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 397 0.08 0.00 1.93141 -141.327 -1.93141 1.88461 0.000401132 0.000313592 0.0267576 0.0212839 14 351 23 1.07788e+06 1.02399e+06 -1 -1 0.14 0.0717478 0.0598962 324 23 680 1240 112082 45874 1.93141 1.88461 -141.327 -1.93141 0 0 -1 -1 0.04 0.017239 0.0152653 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.27 0.06 6948 4 0.15 -1 -1 31452 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run002/nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml/stereovision3.v/common 40492 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 426 0.07 0.00 1.93141 -141.327 -1.93141 1.88461 0.000226884 0.000175358 0.0216232 0.0172742 14 354 48 1.07788e+06 1.02399e+06 -1 -1 0.12 0.0726259 0.0603896 353 22 633 1263 104831 43261 1.93141 1.88461 -141.327 -1.93141 0 0 -1 -1 0.04 0.0167539 0.0147699 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt index 5611ffbb3f0..4eeaebb65f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 3.48 0.05 9180 4 0.11 -1 -1 33036 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/run004/k6_N10_mem32K_40nm.xml/stereovision3.v/common 49184 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 411 1.39 0.00 2.21827 -167.491 -2.21827 2.12157 0.000291008 0.000232527 0.0346588 0.0269316 -1 476 21 1.07788e+06 1.02399e+06 207176. 4228.08 0.61 0.0523586 0.0418939 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 4.29 0.06 6944 4 0.14 -1 -1 31712 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common 52824 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 411 1.70 0.00 2.21827 -167.491 -2.21827 2.12157 0.000219468 0.000168818 0.0258416 0.0196762 -1 466 26 1.07788e+06 1.02399e+06 207176. 4228.08 0.83 0.0453597 0.0366114 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt index f2e559d3624..e6739e5ef59 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml stereovision3.v common 1.30 0.06 8840 4 0.11 -1 -1 33040 -1 -1 13 11 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/run014/k6_frac_N10_40nm.xml/stereovision3.v/common 23524 11 30 262 292 2 110 54 6 6 36 clb auto 0.10 390 0.05 0.00 2.26562 -157.479 -2.26562 2.11716 0.000297036 0.000226766 0.0155239 0.0121872 36 724 21 862304 700622 64877.6 1802.15 0.20 0.089481 0.0723913 545 12 323 532 14269 5196 2.50329 2.28128 -182.979 -2.50329 0 0 80896.3 2247.12 0.02 0.0135541 0.0121761 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml stereovision3.v common 1.38 0.06 6496 4 0.17 -1 -1 30920 -1 -1 13 11 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/run002/k6_frac_N10_40nm.xml/stereovision3.v/common 34968 11 30 262 292 2 110 54 6 6 36 clb auto 0.11 392 0.06 0.00 2.26562 -158.103 -2.26562 2.11716 0.000226852 0.000166978 0.012395 0.0097655 34 783 26 862304 700622 62337.4 1731.59 0.15 0.0650342 0.053967 607 12 356 540 19697 7521 2.50175 2.29238 -190.241 -2.50175 0 0 76364.4 2121.23 0.02 0.0147038 0.0134774 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt index 2044f6c488d..82c1dfaa918 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_90nm.xml diffeq.blif common 7.56 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run015/k4_N4_90nm.xml/diffeq.blif/common 52456 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.38 10194 1.98 0.02 6.5862 -1367.76 -6.5862 6.5862 0.00278317 0.00219727 0.260315 0.199008 24 12158 27 983127 929624 797780. 1508.09 3.05 0.571302 0.450593 11171 19 7079 24040 1692224 422101 6.8984 6.8984 -1482.36 -6.8984 0 0 1.04508e+06 1975.57 0.39 0.0930463 0.0792965 -k4_N4_90nm.xml ex5p.blif common 17.66 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run015/k4_N4_90nm.xml/ex5p.blif/common 44252 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.20 11469 1.36 0.01 6.00224 -269.468 -6.00224 nan 0.00114423 0.000849497 0.129256 0.0972554 36 15772 36 804782 771343 957936. 2172.19 13.74 0.444201 0.346706 13567 23 9150 30844 4172449 1193561 6.73044 nan -286.327 -6.73044 0 0 1.20592e+06 2734.52 0.71 0.0707398 0.0601922 -k4_N4_90nm.xml s298.blif common 11.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run015/k4_N4_90nm.xml/s298.blif/common 57704 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.40 13020 2.39 0.01 11.1117 -88.2322 -11.1117 11.1117 0.0019518 0.00135616 0.262064 0.183421 26 18430 38 1.28409e+06 1.27294e+06 1.12979e+06 1671.28 5.48 0.616792 0.455222 17192 20 9138 46892 4593534 908726 11.2577 11.2577 -91.3533 -11.2577 0 0 1.43821e+06 2127.53 0.90 0.115793 0.0986491 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml diffeq.blif common 7.62 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run002/k4_N4_90nm.xml/diffeq.blif/common 53016 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.39 10352 1.96 0.01 6.71108 -1302.88 -6.71108 6.71108 0.0018259 0.00150667 0.216298 0.184358 24 12471 21 983127 929624 797780. 1508.09 2.75 0.569621 0.49259 11271 20 6811 23023 1564433 387864 6.96084 6.96084 -1425.08 -6.96084 0 0 1.04508e+06 1975.57 0.48 0.135612 0.121136 +k4_N4_90nm.xml ex5p.blif common 11.71 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run002/k4_N4_90nm.xml/ex5p.blif/common 33052 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.27 11587 1.56 0.01 6.252 -279.925 -6.252 nan 0.00124718 0.00106338 0.129201 0.110852 34 16040 37 804782 771343 910617. 2064.89 7.63 0.473933 0.409491 13415 19 8473 28229 3175081 812479 6.31444 nan -289.624 -6.31444 0 0 1.15594e+06 2621.17 0.65 0.0786925 0.0703992 +k4_N4_90nm.xml s298.blif common 39.55 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run002/k4_N4_90nm.xml/s298.blif/common 47864 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.33 14143 2.45 0.02 11.5848 -90.802 -11.5848 11.5848 0.00240663 0.00204641 0.251728 0.218074 24 18935 48 1.28409e+06 1.27294e+06 1.03625e+06 1532.92 33.56 1.06243 0.907664 16671 18 8451 42052 3765403 831311 11.5848 11.5848 -93.0296 -11.5848 0 0 1.35767e+06 2008.39 0.92 0.133222 0.118717 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt index 0c1086f138f..e9ff41352ff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.29 0.06 9444 5 0.14 -1 -1 33316 -1 -1 15 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/run014/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 31620 11 30 313 321 2 114 56 7 7 49 clb auto 0.23 382 0.09 0.00 4.29791 0 0 4.13033 0.00027049 0.0002255 0.0394027 0.0322835 587 171 321 11871 3447 1.07788e+06 808410 219490. 4479.39 6 4.57733 4.27235 0 0 -164.701 -1.707 0.06 0.0913421 0.0823425 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.51 0.07 6948 5 0.15 -1 -1 31500 -1 -1 14 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/run002/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 42704 11 30 313 321 2 119 55 7 7 49 clb auto 0.28 390 0.09 0.00 4.33528 0 0 4.07916 0.000191022 0.000150669 0.0286994 0.0228059 555 315 540 14562 4089 1.07788e+06 754516 219490. 4479.39 9 4.59421 4.26908 0 0 -165.109 -1.707 0.15 0.156426 0.14712 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt index ef3ea7e2c38..79405295418 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.74 0.04 9052 3 0.21 -1 -1 36248 -1 -1 64 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/run015/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common 36072 99 130 363 493 1 251 294 12 12 144 clb auto 0.12 631 0.22 0.00 40 1720 12 5.66058e+06 3.99722e+06 360333. 2502.31 0.38 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 2.21 0.08 6736 3 0.31 -1 -1 31532 -1 -1 64 99 1 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/run002/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common 40300 99 130 363 493 1 251 294 12 12 144 clb auto 0.15 631 0.29 0.00 40 1776 14 5.66058e+06 3.99722e+06 360333. 2502.31 0.42 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt index 3bcd8702b9b..854ffbd7a88 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.78 0.04 9352 4 0.11 -1 -1 33068 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/run014/k6_N10_mem32K_40nm.xml/stereovision3.v/common 27252 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000398583 0.000303303 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 0.98 0.07 6944 4 0.15 -1 -1 31452 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common 40492 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000570083 0.000433793 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt index 815f7cf0806..f62a3cdf30e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.98 0.05 9284 4 0.12 -1 -1 33040 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/run014/k6_N10_mem32K_40nm.xml/stereovision3.v/common 28084 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 395 0.12 0.00 2.22041 -166.454 -2.22041 2.11404 0.000341291 0.000270976 0.0326007 0.0252046 -1 -1 -1 -1 -1 -1 -1 -1 0.0330103 0.0255164 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.18 0.08 6948 4 0.21 -1 -1 32508 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common 38448 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 395 0.12 0.00 2.22041 -166.454 -2.22041 2.11404 0.000231519 0.000177609 0.0261495 0.0201634 -1 -1 -1 -1 -1 -1 -1 -1 0.0264977 0.020429 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt index 26e1a3ba7e2..a11b7702a92 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml mult_5x6.blif common 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-1769-gb0af4b978-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64 2020-05-21T12:42:01 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/run001/k6_frac_N10_40nm.xml/mult_5x6.blif/common 12024 11 11 59 70 0 48 26 4 4 16 clb auto 0.04 155 0.04 2.26753 -18.3823 -2.26753 30 250 46 215576 215576 18771.3 1173.21 0.12 215 14 228 489 11159 6264 2.8603 nan -23.4652 -2.8603 0 0 22855.5 1428.47 0.01 -k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1769-gb0af4b978-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64 2020-05-21T12:42:01 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/run001/k6_frac_N10_40nm_disable_packing.xml/mult_5x6.blif/common 10368 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml mult_5x6.blif common 0.33 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/run002/k6_frac_N10_40nm.xml/mult_5x6.blif/common 17348 11 11 59 70 0 48 26 4 4 16 clb auto 0.03 155 0.03 0.00 2.26753 -18.3823 -2.26753 nan 5.8955e-05 4.3892e-05 0.00716838 0.00567197 32 230 19 215576 215576 19628.8 1226.80 0.08 0.0261585 0.0217133 238 12 308 672 15144 7807 2.86052 nan -24.6091 -2.86052 0 0 23512.3 1469.52 0.01 0.00433274 0.00401076 +k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/run002/k6_frac_N10_40nm_disable_packing.xml/mult_5x6.blif/common 10528 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt index 4b4fbdbad73..e5dae8abc08 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 19.43 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 785600 10 10 168 178 1 62 30 11 8 88 io auto 0.33 338 1.50 0.00 6.42475 -70.0057 -6.42475 6.42475 0.000210069 0.000170001 0.0206966 0.016419 18 790 16 0 0 88905.3 1010.29 0.40 0.0538882 0.0445886 639 12 269 1020 106260 54300 6.98692 6.98692 -75.0776 -6.98692 0 0 114811. 1304.67 0.04 0.0125945 0.0115189 -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 20.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 785616 10 10 168 178 1 62 30 11 8 88 io auto 0.33 332 1.50 0.00 6.5579 -69.9738 -6.5579 6.5579 0.000295816 0.000220692 0.0229095 0.01789 16 871 17 0 0 80336.7 912.917 1.10 0.084033 0.0679953 718 14 322 1131 133881 69813 7.11693 7.11693 -77.5537 -7.11693 0 0 100211. 1138.76 0.04 0.0132427 0.0120206 -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 20.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 785404 10 10 168 178 1 62 30 11 8 88 io auto 0.33 347 1.97 0.00 6.26392 -68.7055 -6.26392 6.26392 0.000228263 0.000173269 0.0213126 0.0166803 16 889 21 0 0 80336.7 912.917 0.47 0.0574665 0.0469206 727 14 387 1575 164654 85947 6.94009 6.94009 -77.0502 -6.94009 0 0 100211. 1138.76 0.04 0.0132417 0.0119827 -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 20.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 788772 10 10 168 178 1 62 30 11 8 88 io auto 0.34 349 1.98 0.00 6.58215 -68.9146 -6.58215 6.58215 0.00020901 0.000173343 0.0206752 0.0164291 28 680 15 0 0 134307. 1526.22 0.74 0.0839271 0.0692388 555 12 233 818 105815 48725 6.96661 6.96661 -73.0028 -6.96661 0 0 173484. 1971.41 0.04 0.0123703 0.0113118 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 24.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 762792 10 10 168 178 1 62 30 11 8 88 io auto 0.41 357 1.87 0.00 6.46199 -69.3428 -6.46199 6.46199 0.000158342 0.000128688 0.0175169 0.0145286 20 843 17 0 0 100248. 1139.18 0.78 0.0705978 0.0607056 706 18 438 1928 165528 64657 6.74513 6.74513 -76.3567 -6.74513 0 0 125464. 1425.72 0.05 0.0160253 0.0149188 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 23.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 762480 10 10 168 178 1 62 30 11 8 88 io auto 0.43 371 1.91 0.00 6.62144 -70.0537 -6.62144 6.62144 0.000155484 0.000122094 0.0170311 0.0141243 18 903 20 0 0 88979.3 1011.13 0.76 0.0666961 0.0571499 705 14 337 1322 122145 48442 6.73463 6.73463 -75.7981 -6.73463 0 0 114778. 1304.29 0.04 0.0140833 0.0131341 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 23.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 763024 10 10 168 178 1 62 30 11 8 88 io auto 0.41 347 2.48 0.00 6.26392 -68.7055 -6.26392 6.26392 0.000162409 0.000127497 0.016791 0.0140011 18 925 43 0 0 88979.3 1011.13 0.79 0.0801616 0.0687532 766 18 471 1999 160101 65079 6.73453 6.73453 -76.2678 -6.73453 0 0 114778. 1304.29 0.05 0.0153474 0.0142117 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 22.68 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 763024 10 10 168 178 1 62 30 11 8 88 io auto 0.41 349 2.52 0.00 6.58215 -68.9146 -6.58215 6.58215 0.000151263 0.000122383 0.0157634 0.0131427 28 681 23 0 0 134428. 1527.59 0.29 0.0492842 0.0427051 556 12 237 872 90795 32982 6.96661 6.96661 -73.2429 -6.96661 0 0 173354. 1969.93 0.04 0.01342 0.0126286 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt index 286a94df90c..dd50a274a4a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 19.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta 786656 10 10 168 178 1 62 30 11 8 88 io auto 0.33 338 1.50 0.00 6.42475 -70.0057 -6.42475 6.42475 0.000213653 0.000172023 0.0208692 0.0165288 18 790 16 0 0 88905.3 1010.29 0.40 0.0546836 0.0452492 639 12 269 1020 106260 54300 6.98692 6.98692 -75.0776 -6.98692 0 0 114811. 1304.67 0.04 0.0124049 0.0113595 -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 20.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override 785496 10 10 168 178 1 62 30 11 8 88 io auto 0.33 332 1.51 0.00 6.5579 -69.9738 -6.5579 6.5579 0.000246646 0.000189851 0.0210186 0.0164993 16 871 17 0 0 80336.7 912.917 1.08 0.0817692 0.0662263 718 14 322 1131 133881 69813 7.11693 7.11693 -77.5537 -7.11693 0 0 100211. 1138.76 0.04 0.0130732 0.0118572 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 23.30 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta 762624 10 10 168 178 1 62 30 11 8 88 io auto 0.42 357 1.84 0.00 6.46199 -69.3428 -6.46199 6.46199 0.000153458 0.000123846 0.0176875 0.0146652 20 843 17 0 0 100248. 1139.18 0.76 0.0690009 0.0590992 706 18 438 1928 165528 64657 6.74513 6.74513 -76.3567 -6.74513 0 0 125464. 1425.72 0.05 0.0155815 0.0144562 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 22.58 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override 763016 10 10 168 178 1 62 30 11 8 88 io auto 0.40 371 1.88 0.00 6.62144 -70.0537 -6.62144 6.62144 0.000154766 0.000121243 0.0164106 0.0134944 18 903 20 0 0 88979.3 1011.13 0.77 0.0672959 0.0576555 705 14 337 1322 122145 48442 6.73463 6.73463 -75.7981 -6.73463 0 0 114778. 1304.29 0.04 0.0141376 0.0132042 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt index f7b6c3bc5c0..154599223bb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -EArch.xml ex5p.blif common_--place_effort_scaling_circuit 2.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run004/EArch.xml/ex5p.blif/common_--place_effort_scaling_circuit 40432 8 63 1072 1135 0 632 130 11 11 121 clb auto 1.09 5949 0.65 0.00 4.5988 -192.739 -4.5988 nan 0.00102661 0.000765209 0.134072 0.102888 -1 -1 -1 -1 -1 -1 -1 -1 0.13539 0.103905 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 2.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run004/EArch.xml/ex5p.blif/common_--place_effort_scaling_device_circuit 40308 8 63 1072 1135 0 632 130 11 11 121 clb auto 1.23 5986 0.69 0.00 4.55938 -193.607 -4.55938 nan 0.000997948 0.000748922 0.142982 0.109904 -1 -1 -1 -1 -1 -1 -1 -1 0.145309 0.111707 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 4.89 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run004/EArch.xml/ex5p.blif/common_--place_effort_scaling_circuit_--target_utilization_0.1 65408 8 63 1072 1135 0 632 130 27 27 729 -1 auto 1.11 6736 1.94 0.00 5.04695 -230.507 -5.04695 nan 0.000998492 0.000738891 0.141988 0.108922 -1 -1 -1 -1 -1 -1 -1 -1 0.14332 0.109944 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 5.44 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run004/EArch.xml/ex5p.blif/common_--place_effort_scaling_device_circuit_--target_utilization_0.1 65296 8 63 1072 1135 0 632 130 27 27 729 -1 auto 1.10 6023 2.55 0.01 4.57207 -199.792 -4.57207 nan 0.000994746 0.000736193 0.146404 0.112325 -1 -1 -1 -1 -1 -1 -1 -1 0.14773 0.113354 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml ex5p.blif common_--place_effort_scaling_circuit 2.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run002/EArch.xml/ex5p.blif/common_--place_effort_scaling_circuit 36188 8 63 1072 1135 0 632 130 11 11 121 clb auto 1.37 5950 0.76 0.00 4.5988 -192.739 -4.5988 nan 0.000999691 0.000785461 0.125668 0.107094 -1 -1 -1 -1 -1 -1 -1 -1 0.12705 0.108228 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 2.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run002/EArch.xml/ex5p.blif/common_--place_effort_scaling_device_circuit 34844 8 63 1072 1135 0 632 130 11 11 121 clb auto 1.37 5987 0.76 0.00 4.55938 -193.607 -4.55938 nan 0.000985093 0.000798708 0.12812 0.108984 -1 -1 -1 -1 -1 -1 -1 -1 0.129502 0.110124 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 5.93 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run002/EArch.xml/ex5p.blif/common_--place_effort_scaling_circuit_--target_utilization_0.1 57156 8 63 1072 1135 0 632 130 27 27 729 -1 auto 1.39 6738 2.37 0.00 5.04695 -230.507 -5.04695 nan 0.000986015 0.000790356 0.143695 0.121455 -1 -1 -1 -1 -1 -1 -1 -1 0.145219 0.122729 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 6.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run002/EArch.xml/ex5p.blif/common_--place_effort_scaling_device_circuit_--target_utilization_0.1 57156 8 63 1072 1135 0 632 130 27 27 729 -1 auto 1.40 6645 3.08 0.01 5.06465 -229.992 -5.06465 nan 0.000959655 0.000797151 0.153085 0.131034 -1 -1 -1 -1 -1 -1 -1 -1 0.154637 0.132347 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt index 5053a6f6894..8b4f83bf750 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 2.19 0.07 9296 4 0.16 -1 -1 32824 -1 -1 19 11 0 0 success v8.0.0-2579-g270d1efd9-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-09-04T06:15:46 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/run003/k6_N10_mem32K_40nm.xml/stereovision3.v/common 28964 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 453 0.24 0.13 2.18141 -165.789 -2.18141 2.0954 0.12497 0.10019 0.156789 0.124805 26 608 25 1.07788e+06 1.02399e+06 65453.8 1335.79 0.27 0.252669 0.202403 608 25 973 2367 87670 24993 2.53264 2.50992 -189.166 -2.53264 0 0 80140.9 1635.53 0.03 0.0187426 0.0157532 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.83 0.06 6952 4 0.14 -1 -1 31452 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common 40484 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 453 0.27 0.12 2.18141 -165.789 -2.18141 2.0954 0.118543 0.0899507 0.149616 0.113676 26 608 25 1.07788e+06 1.02399e+06 65453.8 1335.79 0.15 0.201739 0.157294 608 25 973 2367 87439 24801 2.53264 2.50992 -189.166 -2.53264 0 0 80140.9 1635.53 0.03 0.0180345 0.0157056 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index 5ace834bbc0..3f8492ca2a3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.03 0.04 9032 3 0.23 -1 -1 36184 -1 52324 65 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/run015/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 38012 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 649 0.50 0.00 1.83922 -196.437 -1.83922 1.83922 0.000405138 0.000348938 0.0569279 0.0489824 52 1344 14 5.66058e+06 4.05111e+06 419432. 2912.72 0.61 0.160688 0.142471 1268 10 547 697 50558 16348 2.26669 2.26669 -234.063 -2.26669 0 0 551878. 3832.49 0.03 0.0141372 0.013132 0.009993 0.2128 0.07602 0.7112 -k6_frac_N10_mem32K_40nm.xml diffeq1.v common 8.15 0.02 8788 15 0.30 -1 -1 34660 -1 54084 36 162 0 5 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/run015/k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common 48288 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.27 5309 1.03 0.00 19.796 -1786.28 -19.796 19.796 0.00136819 0.00121722 0.201032 0.176641 48 12568 47 1.21132e+07 3.92018e+06 756778. 2956.16 3.39 0.64297 0.577124 10180 19 3169 6154 2037599 497337 22.4129 22.4129 -2167.74 -22.4129 0 0 968034. 3781.38 0.30 0.0770259 0.0717386 0.007913 0.3536 0.01655 0.6298 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.21 0.05 6700 3 0.30 -1 -1 31552 -1 50336 65 99 1 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/run002/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 36268 99 130 363 493 1 251 295 12 12 144 clb auto 0.13 649 0.54 0.00 1.83922 -196.437 -1.83922 1.83922 0.000404898 0.000360541 0.0545123 0.0487133 52 1352 13 5.66058e+06 4.05111e+06 419432. 2912.72 0.57 0.154132 0.140978 1256 10 539 688 49047 15627 2.26669 2.26669 -234.162 -2.26669 0 0 551878. 3832.49 0.03 0.0164765 0.015642 0.00998 0.2118 0.07611 0.7121 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 10.16 0.05 6492 15 0.40 -1 -1 33584 -1 52176 36 162 0 5 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/run002/k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common 56364 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.36 5309 1.17 0.01 19.796 -1786.28 -19.796 19.796 0.00147734 0.00134517 0.203381 0.184991 48 12372 48 1.21132e+07 3.92018e+06 756778. 2956.16 3.88 0.723767 0.671618 10033 17 3073 5959 1987433 483546 22.4043 22.4043 -2076.56 -22.4043 0 0 968034. 3781.38 0.35 0.0874516 0.0832604 0.007892 0.3517 0.0166 0.6317 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt index f8aa36ac962..8677b6b61db 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.24 0.04 9252 4 0.13 -1 -1 33012 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/run014/k6_N10_mem32K_40nm.xml/stereovision3.v/common 28796 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 411 0.08 0.00 2.21827 -167.491 -2.21827 2.12157 0.000286099 0.000229625 0.0335546 0.0259543 476 706 1762 86557 15062 1.07788e+06 1.02399e+06 207176. 4228.08 21 2.37477 2.25251 -178.461 -2.37477 0 0 0.03 0.0516532 0.0413056 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.50 0.06 9556 5 0.10 -1 -1 33256 -1 -1 14 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/run014/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 31232 11 30 313 321 2 117 55 7 7 49 clb auto 0.27 389 0.11 0.00 2.27833 -153.323 -2.27833 2.06764 0.000549577 0.000448282 0.0538636 0.0429385 524 235 443 11245 3448 1.07788e+06 754516 219490. 4479.39 8 2.4554 2.27846 -166.763 -2.4554 0 0 0.03 0.0765967 0.0638709 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.11 0.06 6948 4 0.15 -1 -1 32508 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common 40480 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 411 0.08 0.00 2.21827 -167.491 -2.21827 2.12157 0.000221035 0.000169659 0.0263472 0.020151 466 779 2010 94407 16356 1.07788e+06 1.02399e+06 207176. 4228.08 26 2.37477 2.25251 -176.32 -2.37477 0 0 0.03 0.0454608 0.0366842 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.42 0.06 6952 5 0.19 -1 -1 31500 -1 -1 14 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/run002/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 44740 11 30 313 321 2 118 55 7 7 49 clb auto 0.28 413 0.09 0.00 2.27922 -157.154 -2.27922 2.04734 0.000236419 0.000181243 0.0332645 0.0257964 564 231 414 13653 4088 1.07788e+06 754516 219490. 4479.39 9 2.64615 2.34528 -176.378 -2.64615 0 0 0.02 0.0496336 0.0410878 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt index 2081e02fbbc..5166753f5a5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 20.02 0.26 30784 4 1.81 -1 -1 39784 -1 -1 167 193 5 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/run011/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common 71568 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.33 10454 2.60 0.01 4.17962 -2464.62 -4.17962 4.17962 0.00299973 0.00239168 0.46302 0.37433 80 20576 39 2.07112e+07 1.17403e+07 2.10510e+06 5262.74 10.51 1.74356 1.49433 18693 17 5010 14283 1459244 324974 4.84767 4.84767 -2845.86 -4.84767 -12.6591 -0.360359 2.64606e+06 6615.15 0.36 0.189262 0.17394 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 19.89 0.39 28228 4 2.01 -1 -1 36684 -1 -1 167 193 5 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/run002/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common 74904 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.64 10767 3.15 0.02 4.38764 -2424.87 -4.38764 4.38764 0.00381293 0.00327028 0.557327 0.480677 76 21837 34 2.07112e+07 1.17403e+07 2.02110e+06 5052.76 8.32 1.82698 1.6168 19921 17 5464 15237 1677966 362561 4.80242 4.80242 -2886.51 -4.80242 -6.84129 -0.340786 2.51807e+06 6295.18 0.45 0.234206 0.218846 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt index 44d1d2087d9..f6992df51b9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/run011/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_all_critical 38260 8 63 748 811 0 474 151 13 13 169 clb auto 0.28 4625 0.44 0.00 3.81146 -161.595 -3.81146 nan 0.00150047 0.00109178 0.127492 0.0990043 6362 3946 14540 677760 102374 6.63067e+06 4.31152e+06 714925. 4230.32 23 4.24514 nan -182.157 -4.24514 0 0 0.19 0.208624 0.170839 -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 1.32 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/run011/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_lookahead 38368 8 63 748 811 0 474 151 13 13 169 clb auto 0.29 4625 0.40 0.00 3.81146 -161.595 -3.81146 nan 0.000965051 0.000715673 0.110265 0.084314 6509 4453 16911 764005 114794 6.63067e+06 4.31152e+06 714925. 4230.32 32 4.15613 nan -185.233 -4.15613 0 0 0.22 0.20245 0.164438 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.53 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/run002/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_all_critical 32608 8 63 748 811 0 474 151 13 13 169 clb auto 0.35 4625 0.46 0.00 3.81146 -161.595 -3.81146 nan 0.000994355 0.000815233 0.109459 0.0932995 6362 3946 14540 676127 101157 6.63067e+06 4.31152e+06 714925. 4230.32 23 4.24514 nan -182.157 -4.24514 0 0 0.20 0.197652 0.173373 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 1.87 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/run002/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_lookahead 32612 8 63 748 811 0 474 151 13 13 169 clb auto 0.42 4625 0.57 0.00 3.81146 -161.595 -3.81146 nan 0.00102421 0.000838718 0.139258 0.119581 6431 3766 13932 632967 95374 6.63067e+06 4.31152e+06 714925. 4230.32 21 4.19023 nan -182.626 -4.19023 0 0 0.20 0.226537 0.199024 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt index 518fd3fcac8..8e6992bd869 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.37 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2584-g5f6578a34 release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.1 on Linux-4.15.0-101-generic x86_64 2020-09-06T19:44:18 acomodi /data/vtr-symbiflow/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run054/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_classic 40544 8 63 748 811 0 474 151 13 13 169 clb auto 0.31 4714 0.57 0.00 3.70871 -159.069 -3.70871 nan 0.000595846 0.000483397 0.093679 0.0767406 6802 4803 18126 1410663 241971 6.63067e+06 4.31152e+06 558096. 3302.35 31 4.15097 nan -183.347 -4.15097 0 0 0.25 0.133699 0.10838 -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2584-g5f6578a34 release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.1 on Linux-4.15.0-101-generic x86_64 2020-09-06T19:44:18 acomodi /data/vtr-symbiflow/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run054/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_map 40116 8 63 748 811 0 474 151 13 13 169 clb auto 0.30 4774 0.49 0.00 3.68749 -162.239 -3.68749 nan 0.000750225 0.000628302 0.0994842 0.0818529 6885 4550 17546 783482 128874 6.63067e+06 4.31152e+06 558096. 3302.35 25 4.28104 nan -189.84 -4.28104 0 0 0.18 0.142113 0.116707 -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 1.65 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2584-g5f6578a34 release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.1 on Linux-4.15.0-101-generic x86_64 2020-09-06T19:44:18 acomodi /data/vtr-symbiflow/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run054/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_extended_map 42564 8 63 748 811 0 474 151 13 13 169 clb auto 0.33 4756 0.52 0.01 3.96235 -167.937 -3.96235 nan 0.000771353 0.000639451 0.0941602 0.079945 6963 3821 13362 1508440 271241 6.63067e+06 4.31152e+06 558096. 3302.35 25 4.68054 nan -193.587 -4.68054 0 0 0.22 0.133333 0.110696 -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2584-g5f6578a34 release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.1 on Linux-4.15.0-101-generic x86_64 2020-09-06T19:44:18 acomodi /data/vtr-symbiflow/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run054/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 43940 8 63 748 811 0 474 151 13 13 169 clb auto 0.28 4756 0.45 0.00 3.96235 -167.937 -3.96235 nan 0.000597938 0.000489964 0.0821085 0.0685745 6963 3821 13362 1508440 271241 6.63067e+06 4.31152e+06 558096. 3302.35 25 4.68054 nan -193.587 -4.68054 0 0 0.22 0.118205 0.0971101 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run002/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_classic 30572 8 63 748 811 0 474 151 13 13 169 clb auto 0.33 4655 0.44 0.00 3.66026 -163.077 -3.66026 nan 0.000896008 0.00072685 0.104611 0.0890482 7091 4741 17915 1451349 247667 6.63067e+06 4.31152e+06 558096. 3302.35 27 4.21322 nan -188.639 -4.21322 0 0 0.28 0.199819 0.175242 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run002/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_map 30572 8 63 748 811 0 474 151 13 13 169 clb auto 0.33 4627 0.46 0.00 3.76868 -164.929 -3.76868 nan 0.00088964 0.000725078 0.108024 0.091072 6872 4846 19991 920633 146986 6.63067e+06 4.31152e+06 558096. 3302.35 25 4.26507 nan -196.263 -4.26507 0 0 0.25 0.201632 0.176194 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 2.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run002/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_extended_map 32616 8 63 748 811 0 474 151 13 13 169 clb auto 0.33 4660 0.48 0.00 3.92852 -163.895 -3.92852 nan 0.00104374 0.000853244 0.116401 0.100158 6742 4255 16069 1176183 201189 6.63067e+06 4.31152e+06 558096. 3302.35 29 4.44743 nan -186.692 -4.44743 0 0 0.29 0.219165 0.193032 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run002/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 32612 8 63 748 811 0 474 151 13 13 169 clb auto 0.33 4660 0.47 0.00 3.92852 -163.895 -3.92852 nan 0.0010746 0.000883505 0.115479 0.0993971 6742 4255 16069 1176183 201189 6.63067e+06 4.31152e+06 558097. 3302.35 29 4.44743 nan -186.692 -4.44743 0 0 0.31 0.221667 0.194809 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt index 3e4fba874e8..f6d244c3002 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/run011/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_off 38780 8 63 748 811 0 474 151 13 13 169 clb auto 0.26 4637 0.51 0.00 3.90481 -171.483 -3.90481 nan 0.000949892 0.000701354 0.141238 0.107461 6533 3905 14523 665599 104616 6.63067e+06 4.31152e+06 648366. 3836.48 22 4.19585 nan -190.835 -4.19585 0 0 0.18 0.214983 0.172742 -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 1.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/run011/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_on 38900 8 63 748 811 0 474 151 13 13 169 clb auto 0.29 4637 0.40 0.00 3.90481 -171.483 -3.90481 nan 0.000937804 0.00069632 0.107439 0.0822581 6549 3830 14383 660219 104384 6.63067e+06 4.31152e+06 648366. 3836.48 19 4.19585 nan -192.564 -4.19585 0 0 0.17 0.17892 0.145456 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 1.43 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/run002/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_off 30572 8 63 748 811 0 474 151 13 13 169 clb auto 0.33 4637 0.46 0.00 3.90481 -171.483 -3.90481 nan 0.00106029 0.000890373 0.106874 0.0910232 6498 3887 14520 663371 103751 6.63067e+06 4.31152e+06 648366. 3836.48 21 4.19585 nan -192.068 -4.19585 0 0 0.20 0.194126 0.170591 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 1.58 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/run002/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_on 32612 8 63 748 811 0 474 151 13 13 169 clb auto 0.33 4637 0.50 0.00 3.90481 -171.483 -3.90481 nan 0.00114265 0.000970416 0.130655 0.113711 6499 3909 14676 669926 104571 6.63067e+06 4.31152e+06 648366. 3836.48 21 4.19585 nan -192.068 -4.19585 0 0 0.21 0.221336 0.196441 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt index a6a943d254b..a3b6f18f7aa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -slicem.xml carry_chain.blif common 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/run014/slicem.xml/carry_chain.blif/common 19572 1 -1 48 34 1 32 5 4 4 16 BLK_IG-SLICEM auto 0.16 65 0.02 0.00 0.55434 -5.54475 -0.55434 0.55434 8.727e-05 7.1791e-05 0.0100323 0.00811205 27 213 21 59253.6 59253.6 -1 -1 0.09 0.0302786 0.02379 164 12 95 95 20812 11936 1.25215 1.25215 -10.6324 -1.25215 0 0 -1 -1 0.01 0.0022928 0.00191969 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +slicem.xml carry_chain.blif common 0.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/run002/slicem.xml/carry_chain.blif/common 22324 1 -1 48 34 1 32 5 4 4 16 BLK_IG-SLICEM auto 0.14 65 0.01 0.00 0.55434 -5.54475 -0.55434 0.55434 2.6566e-05 1.88e-05 0.00268519 0.00194624 29 222 49 59253.6 59253.6 -1 -1 0.08 0.0120957 0.00941838 171 16 83 83 18139 10393 1.35256 1.35256 -12.8703 -1.35256 0 0 -1 -1 0.01 0.00283714 0.00246924 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index 5ec06ab0857..18127f883b4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml ndff.blif common 0.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/run014/arch.xml/ndff.blif/common 18512 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 0.00 23 0.01 0.00 0.198362 -1.99999 -0.198362 0.198362 2.588e-05 1.7338e-05 0.00289752 0.00192378 4 25 13 59253.6 44440.2 -1 -1 0.02 0.00547603 0.00363759 26 2 15 20 897 403 0.260484 0.260484 -2.61426 -0.260484 0 0 -1 -1 0.00 0.000397896 0.000295969 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml ndff.blif common 0.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/run002/arch.xml/ndff.blif/common 13360 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 0.01 23 0.01 0.00 0.198362 -1.99999 -0.198362 0.198362 1.054e-05 5.72e-06 0.00128063 0.000678862 4 25 13 59253.6 44440.2 -1 -1 0.01 0.00252724 0.00152683 26 2 14 18 767 330 0.260484 0.260484 -2.61426 -0.260484 0 0 -1 -1 0.00 0.000204223 0.000164416 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt index a786cc3dac8..c2fd49d14ae 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.23 0.06 9472 5 0.10 -1 -1 33224 -1 -1 15 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/run014/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 30972 11 30 313 321 2 114 56 7 7 49 clb auto 0.23 382 0.09 0.00 4.29791 0 0 4.13033 0.000325202 0.000271371 0.0433681 0.0355896 581 172 326 11476 3370 1.07788e+06 808410 219490. 4479.39 6 4.57733 4.27235 0 0 -164.701 -1.707 0.02 0.0558825 0.0472557 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.32 0.07 6948 5 0.14 -1 -1 30972 -1 -1 14 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/run002/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 43144 11 30 313 321 2 119 55 7 7 49 clb auto 0.28 390 0.08 0.00 4.33528 0 0 4.07916 0.000188804 0.000149741 0.0283857 0.0226503 559 277 494 13732 3849 1.07788e+06 754516 219490. 4479.39 9 4.59421 4.26908 0 0 -165.109 -1.707 0.02 0.0430684 0.0364617 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index a5deaa77e2e..a5c0847151a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/A.sdc 25288 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.00 0.738757 -2.61951 -0.738757 0.571 3.4936e-05 2.4423e-05 0.00314375 0.00224221 8 24 8 107788 107788 4794.78 299.674 0.01 0.00370959 0.00264217 33 4 14 14 686 498 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.000422038 0.000330531 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/B.sdc 25336 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 19 0.01 0.00 0.571 0 0 0.571 3.1349e-05 2.1849e-05 0.000127889 9.4626e-05 8 29 7 107788 107788 4794.78 299.674 0.01 0.000630239 0.000451601 23 4 13 13 297 127 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.000307493 0.000226879 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/C.sdc 25280 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.03 0.00 0.569757 -1.88754 -0.569757 0.571 4.0079e-05 2.5518e-05 0.00606995 0.00392157 8 26 4 107788 107788 4794.78 299.674 0.01 0.00672637 0.00438372 19 8 26 26 674 363 0.717991 0.571 -2.35413 -0.717991 0 0 5401.54 337.596 0.00 0.000496463 0.000348304 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/D.sdc 25376 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.00 1.56976 -4.87541 -1.56976 0.571 2.958e-05 1.7961e-05 0.00414537 0.00265591 8 26 10 107788 107788 4794.78 299.674 0.01 0.00490451 0.00315553 17 4 11 11 265 121 1.57153 0.571 -4.90021 -1.57153 0 0 5401.54 337.596 0.00 0.000378573 0.000269939 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/E.sdc 25100 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.00 1.37313 -2.68253 -1.37313 0.571 2.8867e-05 1.8372e-05 0.00546779 0.00367434 6 24 28 107788 107788 3417.33 213.583 0.01 0.00696488 0.00471235 18 2 10 10 262 131 1.39454 0.571 -2.70748 -1.39454 0 0 4794.78 299.674 0.00 0.000298742 0.000219104 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/F.sdc 25468 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.00 0.0697572 0 0 0.571 2.5355e-05 1.8235e-05 0.00407125 0.00280983 8 23 3 107788 107788 4794.78 299.674 0.01 0.00451409 0.00313548 27 3 14 14 519 336 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.000401233 0.000319461 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run002/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/A.sdc 18324 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.01 0.00 0.738757 -2.61951 -0.738757 0.571 8.726e-06 4.613e-06 0.00104713 0.000568235 8 24 8 107788 107788 4794.78 299.674 0.01 0.00140089 0.000824851 33 4 14 14 674 491 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.000240336 0.000187557 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run002/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/B.sdc 16276 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 18 0.01 0.00 0.571 0 0 0.571 1.0505e-05 5.983e-06 8.9811e-05 6.5003e-05 8 22 5 107788 107788 4794.78 299.674 0.01 0.000377269 0.000281808 21 4 14 14 401 210 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.000203591 0.000158282 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run002/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/C.sdc 18336 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.00 0.569757 -1.88754 -0.569757 0.571 1.213e-05 5.524e-06 0.00174783 0.000835339 8 26 4 107788 107788 4794.78 299.674 0.01 0.00207447 0.00107184 19 8 26 26 644 354 0.717991 0.571 -2.35413 -0.717991 0 0 5401.54 337.596 0.00 0.000312758 0.000227237 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run002/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/D.sdc 16288 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.00 1.56976 -4.87541 -1.56976 0.571 1.4343e-05 6.598e-06 0.0021016 0.00104517 8 26 10 107788 107788 4794.78 299.674 0.01 0.00265992 0.00142144 17 4 11 11 256 116 1.57153 0.571 -4.90021 -1.57153 0 0 5401.54 337.596 0.00 0.000286736 0.000215081 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run002/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/E.sdc 18336 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.00 1.37313 -2.68253 -1.37313 0.571 1.3262e-05 6.572e-06 0.00186082 0.000984416 6 24 29 107788 107788 3417.33 213.583 0.01 0.00269024 0.0015477 18 2 11 11 260 129 1.39454 0.571 -2.70748 -1.39454 0 0 4794.78 299.674 0.00 0.00023294 0.000178247 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run002/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/F.sdc 16292 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.00 0.0697572 0 0 0.571 9.72e-06 5.627e-06 0.00162859 0.00090061 8 23 3 107788 107788 4794.78 299.674 0.01 0.00195504 0.00115006 27 3 14 14 507 328 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.000258336 0.000202665 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index d0b1d6e9f3a..984ec01adc1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ -+arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 0.83 0.01 5960 1 0.01 -1 -1 33540 -1 -1 3 9 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common 24292 9 8 75 70 1 34 20 5 5 25 clb auto 0.48 72 0.02 2.25879 -23.5139 -2.25879 20 195 16 151211 75605.7 29112.5 1164.50 0.02 169 10 90 101 5752 3198 2.41865 2.41865 -34.9802 -2.41865 0 0 37105.9 1484.24 0.00 13 16 19 7 0 0 -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.92 0.01 5952 1 0.00 -1 -1 33624 -1 -1 2 11 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common 24492 11 10 108 97 1 44 23 4 4 16 clb auto 4.58 94 0.02 2.96669 -32.8172 -2.96669 34 213 25 50403.8 50403.8 21558.4 1347.40 0.05 156 7 110 135 4945 3112 3.64419 3.64419 -46.6251 -3.64419 0 0 26343.3 1646.46 0.00 14 25 29 8 0 0 -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 3.60 0.01 6068 1 0.01 -1 -1 33888 -1 -1 6 13 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common 25360 13 12 149 129 1 72 31 5 5 25 clb auto 3.09 180 0.04 3.03389 -41.8702 -3.03389 60 324 25 151211 151211 73020.3 2920.81 0.14 254 12 247 302 11201 5196 3.38467 3.38467 -55.0874 -3.38467 0 0 90821.2 3632.85 0.01 25 36 42 9 0 0 -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.03 0.01 6152 1 0.01 -1 -1 33832 -1 -1 6 15 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common 25616 15 14 196 165 1 95 35 5 5 25 clb auto 1.49 287 0.05 3.1163 -51.6955 -3.1163 46 525 19 151211 151211 57775.2 2311.01 0.17 395 18 375 525 17847 7934 3.85568 3.85568 -71.6886 -3.85568 0 0 73020.3 2920.81 0.01 38 49 57 11 0 0 -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 2.24 0.01 6144 1 0.01 -1 -1 33504 -1 -1 6 17 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common 26020 17 16 251 206 1 116 39 5 5 25 clb auto 1.71 377 0.06 3.26291 -60.9398 -3.26291 52 611 28 151211 151211 63348.9 2533.96 0.12 505 16 515 759 25843 11622 5.22085 5.22085 -95.6248 -5.22085 0 0 82390.3 3295.61 0.01 51 64 75 13 0 0 -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 4.70 0.01 6236 1 0.02 -1 -1 34160 -1 -1 7 19 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common 26564 19 18 308 249 1 141 44 6 6 36 clb auto 4.06 461 0.07 3.86024 -71.5388 -3.86024 54 1031 48 403230 176413 113905. 3164.04 0.17 755 18 655 1081 41335 16174 5.26704 5.26704 -107.994 -5.26704 0 0 146644. 4073.44 0.02 58 81 93 14 0 0 \ No newline at end of file +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.22 0.03 3336 1 0.01 -1 -1 27792 -1 -1 3 9 0 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run002/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common 23768 9 8 75 70 1 34 20 5 5 25 clb auto 0.57 72 0.03 0.00 2.25879 -23.5139 -2.25879 2.25879 3.6324e-05 2.6965e-05 0.004824 0.00375273 20 195 16 151211 75605.7 29112.5 1164.50 0.08 0.0123736 0.01026 169 10 90 101 5659 3130 2.41865 2.41865 -34.9802 -2.41865 0 0 37105.9 1484.24 0.01 0.00358427 0.00332755 13 16 19 7 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 6.39 0.02 3384 1 0.01 -1 -1 27864 -1 -1 2 11 0 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run002/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common 24128 11 10 108 97 1 44 23 4 4 16 clb auto 5.69 94 0.05 0.00 2.96669 -32.8172 -2.96669 2.96669 7.7357e-05 5.8788e-05 0.0129377 0.0102084 36 189 12 50403.8 50403.8 22423.4 1401.47 0.12 0.0406748 0.033338 150 12 151 181 6248 3869 3.40719 3.40719 -45.6771 -3.40719 0 0 28178.5 1761.16 0.01 0.00521765 0.00485308 14 25 29 8 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 4.88 0.03 3432 1 0.01 -1 -1 27916 -1 -1 6 13 0 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run002/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common 26436 13 12 149 129 1 72 31 5 5 25 clb auto 4.10 180 0.06 0.00 3.03389 -41.8702 -3.03389 3.03389 7.5458e-05 5.9118e-05 0.0114694 0.00925858 60 328 32 151211 151211 73020.3 2920.81 0.18 0.0459305 0.0382348 248 9 242 294 10276 4755 3.38467 3.38467 -53.1914 -3.38467 0 0 90821.2 3632.85 0.01 0.00545238 0.00514382 25 36 42 9 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.79 0.02 3484 1 0.01 -1 -1 27924 -1 -1 6 15 0 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run002/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common 24588 15 14 196 165 1 95 35 5 5 25 clb auto 1.91 287 0.06 0.00 3.1163 -51.6955 -3.1163 3.1163 8.9382e-05 7.0646e-05 0.0135782 0.0110734 44 624 31 151211 151211 54748.7 2189.95 0.22 0.0577906 0.0484515 455 19 460 628 24127 11128 4.22416 4.22416 -79.0706 -4.22416 0 0 71025.7 2841.03 0.02 0.0113362 0.0104559 38 49 57 11 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 3.18 0.03 3544 1 0.02 -1 -1 27960 -1 -1 6 17 0 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run002/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common 26932 17 16 251 206 1 116 39 5 5 25 clb auto 2.25 377 0.07 0.00 3.26291 -60.9398 -3.26291 3.26291 0.000114975 9.1562e-05 0.0171202 0.0139848 48 773 44 151211 151211 59785.0 2391.40 0.22 0.0689768 0.0579642 504 18 527 815 26300 12109 4.97625 4.97625 -93.675 -4.97625 0 0 75076.4 3003.05 0.02 0.0142122 0.0131538 51 64 75 13 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 6.07 0.03 3616 1 0.02 -1 -1 28100 -1 -1 7 19 0 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run002/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common 31472 19 18 308 249 1 141 44 6 6 36 clb auto 5.00 461 0.09 0.00 3.86024 -71.5388 -3.86024 3.86024 0.000138457 0.000111065 0.0200789 0.0163865 58 892 44 403230 176413 123560. 3432.22 0.34 0.0914337 0.077307 732 13 520 831 30616 11966 4.83428 4.83428 -103.925 -4.83428 0 0 154963. 4304.53 0.02 0.012717 0.011995 58 81 93 14 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt index db7914c9efb..bd9c884e90c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -sub_tiles.xml sub_tiles.blif common 1.81 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/run004/sub_tiles.xml/sub_tiles.blif/common 46184 6 7 19 26 0 19 26 3 3 9 -1 auto 0.01 38 1.38 0.00 3.87729 -27.141 -3.87729 nan 3.7606e-05 2.7467e-05 0.00012843 9.409e-05 6 19 4 14813.4 192574 -1 -1 0.08 0.00121158 0.000839129 19 2 32 34 5402 2849 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000235428 0.000165429 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common 4.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/run002/sub_tiles.xml/sub_tiles.blif/common 28964 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 3.93 0.00 3.87729 -27.141 -3.87729 nan 1.4734e-05 9.271e-06 8.6628e-05 5.8971e-05 6 19 3 14813.4 192574 -1 -1 0.05 0.000352328 0.000243359 19 3 34 37 8289 3450 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000207719 0.000153625 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt index 45196067b96..059c1092607 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.59 0.04 8984 3 0.23 -1 -1 36160 -1 -1 14 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/run015/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common 30424 99 74 307 381 1 199 188 8 8 64 io memory auto 0.05 665 0.28 0.00 1.91417 -195.15 -1.91417 1.91417 0.000326354 0.000276592 0.0514491 0.0432667 42 1220 14 2.23746e+06 1.30252e+06 130676. 2041.82 0.35 0.146871 0.126644 1097 15 753 1100 113456 36999 2.1112 2.1112 -216.052 -2.1112 0 0 165046. 2578.84 0.03 0.0147062 0.0131667 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.67 0.05 6692 3 0.25 -1 -1 31536 -1 -1 14 99 1 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/run002/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common 32736 99 74 307 381 1 199 188 8 8 64 io memory auto 0.06 665 0.28 0.00 1.91417 -195.15 -1.91417 1.91417 0.000293302 0.000253334 0.0392637 0.034126 42 1206 19 2.23746e+06 1.30252e+06 130676. 2041.82 0.31 0.124024 0.111066 1095 20 742 1067 114685 37312 2.37414 2.37414 -219.35 -2.37414 0 0 165046. 2578.84 0.04 0.0175467 0.016258 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt index 935b2db1a4b..a2eed2675f5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -EArch.xml styr.blif common_--target_ext_pin_util_1 0.72 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_1 30508 10 10 168 178 1 74 31 6 6 36 clb auto 0.13 382 0.07 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000221005 0.000177753 0.0254642 0.0199756 38 800 17 646728 592834 65452.3 1818.12 0.18 0.0814708 0.0665146 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.0163916 0.0146049 -EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_0.7 30452 10 10 168 178 1 74 31 6 6 36 clb auto 0.21 382 0.08 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000253731 0.000204724 0.0290702 0.0227229 38 800 17 646728 592834 65452.3 1818.12 0.18 0.0849551 0.0690739 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.016151 0.0144691 -EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 2.30 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_0.1,0.5 36796 10 10 168 178 1 162 110 14 14 196 clb auto 0.58 1387 0.42 0.00 2.51884 -31.4654 -2.51884 2.51884 0.000236837 0.000178212 0.0236971 0.018329 26 2837 16 9.20055e+06 4.85046e+06 387483. 1976.95 0.40 0.062511 0.050505 2742 14 650 2789 168625 37686 3.58224 3.58224 -42.6087 -3.58224 0 0 467681. 2386.13 0.06 0.0190385 0.0168887 -EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.87 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_0.5,0.3 31864 10 10 168 178 1 73 33 7 7 49 clb auto 0.16 360 0.10 0.00 2.15444 -25.01 -2.15444 2.15444 0.00021268 0.000176334 0.0253541 0.0198352 28 1248 38 1.07788e+06 700622 79600.7 1624.51 0.18 0.0684005 0.055929 928 18 558 2136 96280 33898 2.79653 2.79653 -35.1311 -2.79653 0 0 95067.4 1940.15 0.05 0.0297294 0.0270798 -EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.30 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_0.0 37244 10 10 168 178 1 163 121 14 14 196 clb auto 0.52 1410 0.52 0.00 2.77278 -32.4085 -2.77278 2.77278 0.000238357 0.000182325 0.0268028 0.0208842 26 2807 12 9.20055e+06 5.44329e+06 387483. 1976.95 0.39 0.0597298 0.0481853 2754 17 663 2477 151760 33519 3.70229 3.70229 -44.61 -3.70229 0 0 467681. 2386.13 0.04 0.0120313 0.010564 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7 0.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.7 30320 10 10 168 178 1 74 31 6 6 36 clb auto 0.17 382 0.08 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000218217 0.000176576 0.0276365 0.0219964 38 800 17 646728 592834 65452.3 1818.12 0.18 0.0830532 0.06813 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.04 0.0250439 0.0221544 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7_0.8 0.71 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.7_0.8 30388 10 10 168 178 1 74 31 6 6 36 clb auto 0.13 382 0.07 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000217263 0.000174673 0.0254039 0.0198319 38 800 17 646728 592834 65452.3 1818.12 0.17 0.0796192 0.0647946 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.017595 0.0156692 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.1_0.8 2.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.1_0.8 36568 10 10 168 178 1 162 110 14 14 196 clb auto 0.48 1387 0.50 0.00 2.51884 -31.4654 -2.51884 2.51884 0.000234864 0.000177166 0.0261234 0.0204132 26 2837 16 9.20055e+06 4.85046e+06 387483. 1976.95 0.41 0.060792 0.0493305 2742 14 650 2789 168625 37686 3.58224 3.58224 -42.6087 -3.58224 0 0 467681. 2386.13 0.04 0.0118605 0.0105076 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 0.84 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 30416 10 10 168 178 1 74 31 6 6 36 clb auto 0.15 382 0.08 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000217183 0.00017539 0.0256727 0.0202203 38 800 17 646728 592834 65452.3 1818.12 0.19 0.0843206 0.0685009 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.05 0.0277123 0.0244696 -EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.11 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_-0.1 25760 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_1.1 25824 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 0.11 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 25672 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 25812 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml styr.blif common_--target_ext_pin_util_1 1.83 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_1 27828 10 10 168 178 1 74 31 6 6 36 clb auto 0.16 382 0.08 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000169747 0.000137832 0.0183226 0.0149528 38 800 17 646728 592834 65452.3 1818.12 0.17 0.0667476 0.0568883 688 20 456 1668 63127 22882 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.04 0.0214689 0.0198609 +EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.80 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_0.7 27816 10 10 168 178 1 74 31 6 6 36 clb auto 0.17 382 0.08 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000161079 0.000129265 0.0194566 0.0160534 38 800 17 646728 592834 65452.3 1818.12 0.21 0.0715893 0.0615464 688 20 456 1668 63127 22882 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.04 0.0207965 0.0192246 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 2.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_0.1,0.5 27948 10 10 168 178 1 162 110 14 14 196 clb auto 0.60 1346 0.51 0.00 2.68272 -31.6369 -2.68272 2.68272 0.00017729 0.000135124 0.0175035 0.0144795 26 2915 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.42 0.047778 0.0410166 2584 13 571 2397 136568 29368 3.39525 3.39525 -40.7806 -3.39525 0 0 467681. 2386.13 0.04 0.0116322 0.010756 +EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_0.5,0.3 27524 10 10 168 178 1 73 33 7 7 49 clb auto 0.19 360 0.10 0.00 2.15444 -25.01 -2.15444 2.15444 0.000149891 0.000121428 0.0182473 0.0149111 30 1106 26 1.07788e+06 700622 84241.2 1719.21 0.36 0.0792055 0.0672536 861 21 585 2138 88882 29754 2.57173 2.57173 -33.7672 -2.57173 0 0 103128. 2104.65 0.03 0.0170242 0.0157178 +EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.58 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 10 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_0.0 28192 10 10 168 178 1 163 121 14 14 196 clb auto 0.65 1421 0.52 0.00 2.55384 -31.4019 -2.55384 2.55384 0.000163583 0.000126047 0.0169345 0.0137413 26 2882 11 9.20055e+06 5.44329e+06 387483. 1976.95 0.44 0.0471301 0.0402971 2730 11 482 2165 129279 27276 3.58472 3.58472 -43.6609 -3.58472 0 0 467681. 2386.13 0.06 0.0179756 0.0166435 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7 0.76 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.7 27816 10 10 168 178 1 74 31 6 6 36 clb auto 0.16 382 0.08 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000155666 0.000124211 0.0189065 0.0154087 38 800 17 646728 592834 65452.3 1818.12 0.18 0.0683951 0.0583213 688 20 456 1668 63127 22882 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.0167047 0.0154258 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7_0.8 0.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.7_0.8 27816 10 10 168 178 1 74 31 6 6 36 clb auto 0.17 382 0.08 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000164807 0.00013342 0.0197112 0.0163172 38 800 17 646728 592834 65452.3 1818.12 0.18 0.0698276 0.0597118 688 20 456 1668 63127 22882 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.0189179 0.0175376 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.1_0.8 2.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.1_0.8 29628 10 10 168 178 1 162 110 14 14 196 clb auto 0.58 1346 0.49 0.00 2.68272 -31.6369 -2.68272 2.68272 0.000167746 0.000126069 0.0164362 0.0134493 26 2915 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.42 0.0456424 0.0390176 2584 13 571 2397 136568 29368 3.39525 3.39525 -40.7806 -3.39525 0 0 467681. 2386.13 0.04 0.0113637 0.0104439 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 0.81 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 27820 10 10 168 178 1 74 31 6 6 36 clb auto 0.16 382 0.08 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000159734 0.000122589 0.0188474 0.0154052 38 800 17 646728 592834 65452.3 1818.12 0.22 0.0787071 0.0676313 688 20 456 1668 63127 22882 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.016296 0.0150647 +EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_-0.1 15644 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_1.1 15644 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 15644 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run002/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 15644 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index 6345820010d..58b2ca81f9a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.40 0.05 8924 3 0.22 -1 -1 36244 -1 -1 65 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/run015/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 35428 99 130 363 493 1 251 295 12 12 144 clb auto 0.09 624 0.47 0.00 1.94344 -198.852 -1.94344 1.94344 0.000653392 0.000563955 0.0573088 0.0494635 50 1398 19 5.66058e+06 4.05111e+06 406292. 2821.48 0.59 0.168467 0.149351 1368 9 565 725 73444 24903 2.56877 2.56877 -239.947 -2.56877 0 0 539112. 3743.83 0.03 0.0132233 0.0122888 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.62 0.06 6700 3 0.25 -1 -1 31536 -1 -1 65 99 1 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/run002/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 39632 99 130 363 493 1 251 295 12 12 144 clb auto 0.19 624 0.53 0.00 1.94344 -198.852 -1.94344 1.94344 0.000395958 0.000352264 0.0530583 0.0474397 50 1399 11 5.66058e+06 4.05111e+06 406292. 2821.48 0.56 0.150791 0.138002 1316 9 572 748 52711 18395 2.42731 2.42731 -236.084 -2.42731 0 0 520805. 3616.70 0.03 0.0153375 0.0146041 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index 6118c31ad79..024f61556f3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.29 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run011/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_netlist 27132 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.00 0.545 -3.13055 -0.545 0.545 2.6504e-05 1.7223e-05 0.00364423 0.0024041 20 26 8 107788 107788 10441.3 652.579 0.01 0.00430123 0.00287257 20 1 7 7 139 86 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000569671 0.000433281 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run011/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_aggregated 27176 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.00 0.545 -3.13055 -0.545 0.545 2.635e-05 1.6953e-05 0.00367386 0.00239662 20 26 8 107788 107788 10441.3 652.579 0.01 0.00433019 0.00286887 20 1 7 7 139 86 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000263548 0.000200567 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run011/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_detailed 27184 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.00 0.545 -3.13055 -0.545 0.545 2.6258e-05 1.7131e-05 0.00392208 0.00261425 20 26 8 107788 107788 10441.3 652.579 0.01 0.00459771 0.00309595 20 1 7 7 139 86 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000377741 0.000291052 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.27 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run002/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_netlist 17808 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.00 0.545 -3.13055 -0.545 0.545 1.1932e-05 5.362e-06 0.00169392 0.000840347 20 26 8 107788 107788 10441.3 652.579 0.01 0.00217836 0.00120268 20 1 7 7 130 81 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000233334 0.000191734 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run002/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_aggregated 17808 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.00 0.545 -3.13055 -0.545 0.545 1.2225e-05 5.614e-06 0.00167347 0.000843545 20 26 8 107788 107788 10441.3 652.579 0.01 0.00211785 0.00117693 20 1 7 7 130 81 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000232106 0.000190811 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run002/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_detailed 17812 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.00 0.545 -3.13055 -0.545 0.545 1.7077e-05 9.588e-06 0.00182889 0.000941747 20 26 8 107788 107788 10441.3 652.579 0.01 0.002329 0.00131819 20 1 7 7 130 81 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000288775 0.000234838 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt index ad1f6cc64f1..18a01820253 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.37 0.06 10600 5 0.08 -1 -1 33012 -1 -1 14 11 0 0 success v8.0.0-2062-g497427a4c release IPO VTR_ASSERT_LEVEL=2 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-10T16:04:07 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/run016/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 34320 11 30 313 321 2 117 55 7 7 49 clb auto 0.28 389 0.18 0.00 2.27833 -153.323 -2.27833 2.06764 0.000746185 0.00060234 0.103989 0.0830486 -1 524 8 1.07788e+06 754516 219490. 4479.39 0.03 0.129028 0.105458 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.11 0.06 6948 5 0.13 -1 -1 32556 -1 -1 14 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/run002/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 42696 11 30 313 321 2 118 55 7 7 49 clb auto 0.28 413 0.09 0.00 2.27922 -157.154 -2.27922 2.04734 0.000240739 0.000184141 0.0334331 0.0259176 -1 564 9 1.07788e+06 754516 219490. 4479.39 0.02 0.0502572 0.0416276 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt index c252f9475c5..08126abe930 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 0.95 0.05 9252 4 0.14 -1 -1 33036 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run001/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_auto 28864 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 411 0.08 0.00 2.21827 -167.491 -2.21827 2.12157 0.000292249 0.000234575 0.0337405 0.02608 -1 476 21 1.07788e+06 1.02399e+06 207176. 4228.08 0.03 0.0509136 0.0405874 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 0.99 0.05 9348 4 0.14 -1 -1 33080 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run001/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_full 28948 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 411 0.08 0.00 2.21827 -167.491 -2.21827 2.12157 0.000286383 0.000229729 0.0339332 0.0262336 -1 476 21 1.07788e+06 1.02399e+06 207176. 4228.08 0.03 0.0511426 0.0408293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 0.88 0.05 9332 4 0.13 -1 -1 33064 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run001/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_incremental 28856 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 411 0.07 0.00 2.21827 -167.491 -2.21827 2.12157 3.6119e-05 2.0841e-05 0.0209833 0.0145752 -1 476 21 1.07788e+06 1.02399e+06 207176. 4228.08 0.02 0.0325579 0.0238664 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 0.89 0.03 9328 4 0.11 -1 -1 33028 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run001/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_incremental_--quench_recompute_divider_999999999 28992 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 411 0.07 0.00 2.21827 -167.491 -2.21827 2.12157 0.000766939 0.000184216 0.0219317 0.0149481 -1 476 21 1.07788e+06 1.02399e+06 207176. 4228.08 0.02 0.0335243 0.0242639 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.17 0.07 6948 4 0.15 -1 -1 31716 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_auto 40484 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 411 0.08 0.00 2.21827 -167.491 -2.21827 2.12157 0.000219408 0.000168621 0.0259571 0.0198282 -1 466 26 1.07788e+06 1.02399e+06 207176. 4228.08 0.06 0.0575775 0.0472058 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.11 0.07 6952 4 0.14 -1 -1 31712 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_full 42532 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 411 0.08 0.00 2.21827 -167.491 -2.21827 2.12157 0.000224317 0.000172446 0.026674 0.0203735 -1 466 26 1.07788e+06 1.02399e+06 207176. 4228.08 0.04 0.0464534 0.0375519 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.10 0.07 6948 4 0.14 -1 -1 31452 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_incremental 42556 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 411 0.07 0.00 2.21827 -167.491 -2.21827 2.12157 2.9916e-05 2.1655e-05 0.0221604 0.0172221 -1 466 26 1.07788e+06 1.02399e+06 207176. 4228.08 0.03 0.035334 0.0283027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.08 0.06 6948 4 0.15 -1 -1 32248 -1 -1 19 11 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_incremental_--quench_recompute_divider_999999999 42564 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 411 0.08 0.00 2.21827 -167.491 -2.21827 2.12157 0.000948548 0.000212324 0.0233727 0.0175782 -1 466 26 1.07788e+06 1.02399e+06 207176. 4228.08 0.03 0.0367921 0.0288843 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt index c028d04eb74..dadcaf7ef2a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 58.38 42 750 0 0 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/run015/stratixiv_arch.timing.xml/ucsb_152_tap_fir_stratixiv_arch_timing.blif/common 997336 13 29 26295 20086 1 12417 792 39 29 1131 LAB auto 9.81 77912 17.33 0.10 5.12079 -4876.18 -4.12079 2.74162 0.0139895 0.010985 2.50669 1.70375 82153 28190 37696 29527083 3283224 0 0 2.17765e+07 19254.2 14 5.31542 2.74311 -5419.85 -4.31542 0 0 2.78 3.37429 2.44936 +arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 66.58 42 750 0 0 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/run002/stratixiv_arch.timing.xml/ucsb_152_tap_fir_stratixiv_arch_timing.blif/common 952968 13 29 26295 20086 1 12417 792 39 29 1131 LAB auto 11.74 79208 23.21 0.16 5.24702 -4706.87 -4.24702 2.64152 0.0384028 0.0334282 3.55365 2.99526 83630 28133 39786 30086536 2115709 0 0 2.05958e+07 18210.3 17 5.37523 2.79425 -5324.48 -4.37523 0 0 3.65 4.99909 4.26316 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt index 6cace066b32..7a7c0ed86ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 16.50 0.03 8884 6 0.15 -1 -1 34056 -1 -1 15 66 0 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/run015/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common 51964 66 96 1000 687 1 576 192 18 18 324 mult_27 auto 1.09 4949 1.15 0.00 15.0088 -833.523 -15.0088 15.0088 0.0011633 0.00105857 0.172945 0.154747 60 12307 48 6.4517e+06 1.13409e+06 1.66893e+06 5151.03 11.70 0.84001 0.762799 10840 24 3207 7121 2485336 618188 17.4691 17.4691 -1077.83 -17.4691 0 0 2.06264e+06 6366.18 0.47 0.122432 0.114905 135 200 146 33 66 33 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 16.40 0.09 6568 6 0.17 -1 -1 33412 -1 -1 15 66 0 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/run002/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common 51236 66 96 1000 687 1 576 192 18 18 324 mult_27 auto 1.59 5019 1.40 0.00 15.4335 -843.481 -15.4335 15.4335 0.0010598 0.000962042 0.185053 0.168056 70 12253 31 6.4517e+06 1.13409e+06 1.91711e+06 5917.01 10.14 0.840116 0.781057 10615 17 3116 6691 2276940 579894 16.992 16.992 -1042.37 -16.992 0 0 2.37354e+06 7325.76 0.42 0.0819956 0.0784277 133 200 146 33 66 33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt index eb1eda4b91a..b2f0c92e20e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run014/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_20 25096 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.02 0.00 1.10382 -14.1235 -1.10382 1.10382 7.102e-05 5.5257e-05 0.00769392 0.0058538 59 132 190 6966 3181 323364 161682 20103.2 804.128 23 1.30883 1.30883 -16.0731 -1.30883 0 0 0.01 0.0115487 0.00901437 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run014/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_20_--analysis 25104 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.02 0.00 1.10382 -14.1235 -1.10382 1.10382 7.024e-05 5.4449e-05 0.00771493 0.00591894 59 132 190 6966 3181 323364 161682 20103.2 804.128 23 1.30883 1.30883 -16.0731 -1.30883 0 0 0.01 0.0115629 0.00905474 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run014/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_8 24948 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.02 0.00 1.10205 -14.0594 -1.10205 1.10205 7.086e-05 5.5008e-05 0.00806438 0.00621324 -1 791 1058 67582 46410 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.03 -1 -1 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run014/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_8_--analysis 24912 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.02 0.00 1.10205 -14.0594 -1.10205 1.10205 7.1272e-05 5.5589e-05 0.00799577 0.00615493 133 791 1058 67582 46410 323364 161682 9037.03 361.481 -1 1.58422 1.58422 -20.6732 -1.58422 0 0 0.03 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run002/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_20 28856 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.01 0.00 1.10382 -14.1235 -1.10382 1.10382 3.361e-05 2.471e-05 0.00382436 0.00284661 92 160 211 11567 6159 323364 161682 20103.2 804.128 27 1.40596 1.40596 -17.5205 -1.40596 0 0 0.01 0.00703962 0.00561362 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.30 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run002/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_20_--analysis 26808 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.02 0.00 1.10382 -14.1235 -1.10382 1.10382 3.3428e-05 2.4599e-05 0.00397767 0.00299102 92 160 211 11567 6159 323364 161682 20103.2 804.128 27 1.40596 1.40596 -17.5205 -1.40596 0 0 0.01 0.0072131 0.00578615 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run002/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_8 26812 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.01 0.00 1.10205 -14.0594 -1.10205 1.10205 3.3521e-05 2.4789e-05 0.00399717 0.00299062 -1 2316 3067 207211 143666 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.06 -1 -1 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run002/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_8_--analysis 28856 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.01 0.00 1.10205 -14.0594 -1.10205 1.10205 3.7641e-05 2.5356e-05 0.00401873 0.00300245 121 2316 3067 207211 143666 323364 161682 9037.03 361.481 -1 1.6143 1.6143 -19.9972 -1.6143 0 0 0.06 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt index 7bb27bd19a1..f1038656f85 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_90nm.xml stereovision3.v common 1.86 0.03 8768 6 0.12 -1 -1 33068 -1 -1 66 11 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/run014/k4_N4_90nm.xml/stereovision3.v/common 25664 11 30 336 366 2 186 107 11 11 121 clb auto 0.05 1075 0.13 0.00 3.34892 -239.501 -3.34892 3.03185 0.000358116 0.000274374 0.036725 0.0279494 1041 911 2575 182253 35690 180575 147135 597941. 4941.66 14 3.34892 3.06614 -250.482 -3.34892 -0.21991 -0.0734 0.04 0.050806 0.0400998 -k6_frac_N10_40nm.xml stereovision3.v common 1.43 0.05 8872 4 0.13 -1 -1 33040 -1 -1 13 11 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/run014/k6_frac_N10_40nm.xml/stereovision3.v/common 22672 11 30 262 292 2 110 54 6 6 36 clb auto 0.08 357 0.08 0.00 2.2451 -160.339 -2.2451 2.08659 0.000289048 0.000232304 0.0373107 0.0293951 483 216 348 12809 4438 862304 700622 161034. 4473.17 7 2.54203 2.24422 -180.244 -2.54203 0 0 0.02 0.0490499 0.0400724 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml stereovision3.v common 2.22 0.05 6472 6 0.16 -1 -1 31188 -1 -1 66 11 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/run002/k4_N4_90nm.xml/stereovision3.v/common 40244 11 30 336 366 2 186 107 11 11 121 clb auto 0.06 1075 0.15 0.00 3.34892 -239.501 -3.34892 3.03185 0.000277126 0.000205559 0.0299006 0.0230031 1047 918 2587 183070 35898 180575 147135 597941. 4941.66 14 3.34892 3.06614 -250.357 -3.34892 -0.21991 -0.0734 0.05 0.0448475 0.0362061 +k6_frac_N10_40nm.xml stereovision3.v common 1.50 0.05 6496 4 0.16 -1 -1 30920 -1 -1 13 11 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/run002/k6_frac_N10_40nm.xml/stereovision3.v/common 37040 11 30 262 292 2 110 54 6 6 36 clb auto 0.12 359 0.07 0.00 2.26563 -155.681 -2.26563 2.09611 0.000223454 0.000169839 0.0274451 0.021168 454 194 269 9589 3274 862304 700622 161034. 4473.17 14 2.61223 2.32878 -173.036 -2.61223 0 0 0.02 0.043127 0.0354491 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt index fa4adbd43a2..139d12e1140 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_90nm.xml stereovision3.v common 1.71 0.03 8784 6 0.18 -1 -1 33068 -1 -1 66 11 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/run011/k4_N4_90nm.xml/stereovision3.v/common 27416 11 30 336 366 2 186 107 11 11 121 clb auto 0.04 1075 0.13 0.00 3.34892 -239.501 -3.34892 3.03185 0.000354345 0.0002719 0.0362337 0.0276948 1041 911 2575 182253 35690 180575 147135 597941. 4941.66 14 3.34892 3.06614 -250.482 -3.34892 -0.21991 -0.0734 0.04 0.0529663 0.0421552 -k6_frac_N10_40nm.xml stereovision3.v common 1.47 0.04 8820 4 0.14 -1 -1 33116 -1 -1 13 11 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/run011/k6_frac_N10_40nm.xml/stereovision3.v/common 23336 11 30 262 292 2 110 54 6 6 36 clb auto 0.09 357 0.07 0.00 2.2451 -160.339 -2.2451 2.08659 0.000306875 0.00024976 0.034639 0.0269934 483 216 348 12809 4438 862304 700622 161034. 4473.17 7 2.54203 2.24422 -180.244 -2.54203 0 0 0.02 0.0464467 0.0377276 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml stereovision3.v common 1.87 0.05 6472 6 0.16 -1 -1 31984 -1 -1 66 11 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/run002/k4_N4_90nm.xml/stereovision3.v/common 40248 11 30 336 366 2 186 107 11 11 121 clb auto 0.05 1075 0.14 0.00 3.34892 -239.501 -3.34892 3.03185 0.000276429 0.000204871 0.0285963 0.0216581 1047 918 2587 183070 35898 180575 147135 597941. 4941.66 14 3.34892 3.06614 -250.357 -3.34892 -0.21991 -0.0734 0.04 0.0423936 0.0338173 +k6_frac_N10_40nm.xml stereovision3.v common 1.48 0.05 6504 4 0.15 -1 -1 32508 -1 -1 13 11 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/run002/k6_frac_N10_40nm.xml/stereovision3.v/common 34992 11 30 262 292 2 110 54 6 6 36 clb auto 0.11 359 0.12 0.00 2.26563 -155.681 -2.26563 2.09611 0.000422861 0.000327993 0.0470507 0.0367222 454 194 269 9589 3274 862304 700622 161034. 4473.17 14 2.61223 2.32878 -173.036 -2.61223 0 0 0.02 0.0626611 0.050902