From 21aeca5603543e786ea8ce608a256b7342e8c90f Mon Sep 17 00:00:00 2001 From: emacdo12 Date: Wed, 3 Jun 2020 17:24:21 -0300 Subject: [PATCH] ast_util.cpp: Fixed possible memory leak c_simple_print. When checking for octal number, it checks that there are enough characters first. Also, added a line to check for indexing case where the index is the same as start which prints the whole line the function (for some reason). --- ODIN_II/SRC/ast_util.cpp | 61 +-- .../task/test/simulation_result.json | 122 ++++++ .../benchmark/task/test/synthesis_result.json | 118 ++++++ .../benchmark/task/test/task.conf | 23 + .../verilog/FIR/ex1BT16_fir_20_input | 2 +- .../benchmark/verilog/ex1BT16_fir_20_input | 398 ------------------ .../benchmark/verilog/test/ifdef_undefined.v | 12 + .../verilog/test/ifdef_undefined_input | 3 + .../verilog/test/ifdef_undefined_output | 3 + 9 files changed, 319 insertions(+), 423 deletions(-) create mode 100644 ODIN_II/regression_test/benchmark/task/test/simulation_result.json create mode 100644 ODIN_II/regression_test/benchmark/task/test/synthesis_result.json create mode 100644 ODIN_II/regression_test/benchmark/task/test/task.conf delete mode 100644 ODIN_II/regression_test/benchmark/verilog/ex1BT16_fir_20_input create mode 100644 ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined.v create mode 100644 ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined_input create mode 100644 ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined_output diff --git a/ODIN_II/SRC/ast_util.cpp b/ODIN_II/SRC/ast_util.cpp index db678cf75c9..407136eb0c3 100644 --- a/ODIN_II/SRC/ast_util.cpp +++ b/ODIN_II/SRC/ast_util.cpp @@ -1338,39 +1338,52 @@ void assert_constant_positionnal_args(ast_node_t* node, long arg_count) { * a simple printf would not be able to do this since escaped characters are compile time */ void c_simple_print(std::string str) { + size_t str_size = str.size(); size_t start = 0; while (start != std::string::npos) { size_t format_char_index = str.find_first_of('\\', start); size_t next_char = format_char_index; - printf("%s", str.substr(start, format_char_index).c_str()); + if (start != format_char_index) { + printf("%s", str.substr(start, format_char_index).c_str()); + } // print the string if (format_char_index != std::string::npos) { - // try and see if its an octal number - char buffer[4] = { - str[format_char_index + 1], - str[format_char_index + 2], - str[format_char_index + 3], - 0}; - next_char = format_char_index + 4; - char* endptr = NULL; - char octal_value = (char)strtoul(buffer, &endptr, 8); - if (endptr == &buffer[3]) { - // if it is an octal number print the octal char - printf("%c", octal_value); - } else { - next_char = format_char_index + 2; - switch (str[format_char_index + 1]) { - case 'n': - printf("\n"); - break; - case 't': - printf("\t"); - break; - default: + next_char = format_char_index + 2; + switch (str[format_char_index + 1]) { + case 'n': + printf("\n"); + break; + case 't': + printf("\t"); + break; + default: + // can only be octal if there is 3+ chars following + if ((str_size - 3) >= format_char_index) { + // try and see if its an octal number + char buffer[4] = { + str[format_char_index + 1], + str[format_char_index + 2], + str[format_char_index + 3], + 0}; + next_char = format_char_index + 4; + char* endptr = NULL; + char octal_value = (char)strtoul(buffer, &endptr, 8); + if (endptr == &buffer[3]) { + // if it is an octal number print the octal char + printf("%c", octal_value); + } else { + // otherwise just print the character + next_char = format_char_index + 2; + printf("%c", str[format_char_index + 1]); + break; + } + + } else { // otherwise just print the character + next_char = format_char_index + 2; printf("%c", str[format_char_index + 1]); break; - } + } } } start = next_char; diff --git a/ODIN_II/regression_test/benchmark/task/test/simulation_result.json b/ODIN_II/regression_test/benchmark/task/test/simulation_result.json new file mode 100644 index 00000000000..3cd803c54a7 --- /dev/null +++ b/ODIN_II/regression_test/benchmark/task/test/simulation_result.json @@ -0,0 +1,122 @@ +{ + "test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm": { + "test_name": "test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm", + "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml", + "blif": "ifdef_undefined.blif", + "exit": 134, + "errors": [ + "OUTPUT_BLIF Vector files differ." + ], + "warnings": [ + "OUTPUT_BLIF Simulation produced fewer than 2 vectors." + ], + "max_rss(MiB)": -1, + "exec_time(ms)": -1, + "simulation_time(ms)": -1, + "test_coverage(%)": -1, + "Latch Drivers": -1, + "Pi": -1, + "Po": -1, + "logic element": -1, + "latch": -1, + "Adder": -1, + "Multiplier": -1, + "Memory": -1, + "Hard Ip": -1, + "generic logic size": 4, + "Longest Path": -1, + "Average Path": -1, + "Estimated LUTs": -1, + "Total Node": -1 + }, + "test/ifdef_undefined/k6_N10_40nm": { + "test_name": "test/ifdef_undefined/k6_N10_40nm", + "architecture": "k6_N10_40nm.xml", + "blif": "ifdef_undefined.blif", + "exit": 134, + "errors": [ + "OUTPUT_BLIF Vector files differ." + ], + "warnings": [ + "OUTPUT_BLIF Simulation produced fewer than 2 vectors." + ], + "max_rss(MiB)": -1, + "exec_time(ms)": -1, + "simulation_time(ms)": -1, + "test_coverage(%)": -1, + "Latch Drivers": -1, + "Pi": -1, + "Po": -1, + "logic element": -1, + "latch": -1, + "Adder": -1, + "Multiplier": -1, + "Memory": -1, + "Hard Ip": -1, + "generic logic size": 6, + "Longest Path": -1, + "Average Path": -1, + "Estimated LUTs": -1, + "Total Node": -1 + }, + "test/ifdef_undefined/k6_N10_mem32K_40nm": { + "test_name": "test/ifdef_undefined/k6_N10_mem32K_40nm", + "architecture": "k6_N10_mem32K_40nm.xml", + "blif": "ifdef_undefined.blif", + "exit": 134, + "errors": [ + "OUTPUT_BLIF Vector files differ." + ], + "warnings": [ + "OUTPUT_BLIF Simulation produced fewer than 2 vectors." + ], + "max_rss(MiB)": -1, + "exec_time(ms)": -1, + "simulation_time(ms)": -1, + "test_coverage(%)": -1, + "Latch Drivers": -1, + "Pi": -1, + "Po": -1, + "logic element": -1, + "latch": -1, + "Adder": -1, + "Multiplier": -1, + "Memory": -1, + "Hard Ip": -1, + "generic logic size": 6, + "Longest Path": -1, + "Average Path": -1, + "Estimated LUTs": -1, + "Total Node": -1 + }, + "test/ifdef_undefined/no_arch": { + "test_name": "test/ifdef_undefined/no_arch", + "architecture": "n/a", + "blif": "ifdef_undefined.blif", + "exit": 134, + "errors": [ + "OUTPUT_BLIF Vector files differ." + ], + "warnings": [ + "OUTPUT_BLIF Simulation produced fewer than 2 vectors." + ], + "max_rss(MiB)": -1, + "exec_time(ms)": -1, + "simulation_time(ms)": -1, + "test_coverage(%)": -1, + "Latch Drivers": -1, + "Pi": -1, + "Po": -1, + "logic element": -1, + "latch": -1, + "Adder": -1, + "Multiplier": -1, + "Memory": -1, + "Hard Ip": -1, + "generic logic size": -1, + "Longest Path": -1, + "Average Path": -1, + "Estimated LUTs": -1, + "Total Node": -1 + } +} diff --git a/ODIN_II/regression_test/benchmark/task/test/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/test/synthesis_result.json new file mode 100644 index 00000000000..e06c99b1c1d --- /dev/null +++ b/ODIN_II/regression_test/benchmark/task/test/synthesis_result.json @@ -0,0 +1,118 @@ +{ + "test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm": { + "test_name": "test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm", + "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml", + "verilog": "ifdef_undefined.v", + "exit": 0, + "errors": [], + "warnings": [ + "OUTPUT_BLIF want to see if this will print json", + "NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed", + "NETLIST Net simple_op^out driving node simple_op^out is itself undriven." + ], + "max_rss(MiB)": 32.8, + "exec_time(ms)": 71.3, + "synthesis_time(ms)": 0.7, + "Latch Drivers": 0, + "Pi": 0, + "Po": 1, + "logic element": 0, + "latch": 0, + "Adder": 0, + "Multiplier": 0, + "Memory": 0, + "Hard Ip": -1, + "generic logic size": 4, + "Longest Path": 1, + "Average Path": 1, + "Estimated LUTs": 0, + "Total Node": 0 + }, + "test/ifdef_undefined/k6_N10_40nm": { + "test_name": "test/ifdef_undefined/k6_N10_40nm", + "architecture": "k6_N10_40nm.xml", + "verilog": "ifdef_undefined.v", + "exit": 0, + "errors": [], + "warnings": [ + "OUTPUT_BLIF want to see if this will print json", + "NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed", + "NETLIST Net simple_op^out driving node simple_op^out is itself undriven." + ], + "max_rss(MiB)": 15.1, + "exec_time(ms)": 11, + "synthesis_time(ms)": 0.9, + "Latch Drivers": 0, + "Pi": 0, + "Po": 1, + "logic element": 0, + "latch": 0, + "Adder": -1, + "Multiplier": -1, + "Memory": -1, + "Hard Ip": -1, + "generic logic size": 6, + "Longest Path": 1, + "Average Path": 1, + "Estimated LUTs": 0, + "Total Node": 0 + }, + "test/ifdef_undefined/k6_N10_mem32K_40nm": { + "test_name": "test/ifdef_undefined/k6_N10_mem32K_40nm", + "architecture": "k6_N10_mem32K_40nm.xml", + "verilog": "ifdef_undefined.v", + "exit": 0, + "errors": [], + "warnings": [ + "OUTPUT_BLIF want to see if this will print json", + "NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed", + "NETLIST Net simple_op^out driving node simple_op^out is itself undriven." + ], + "max_rss(MiB)": 32.2, + "exec_time(ms)": 51.1, + "synthesis_time(ms)": 0.5, + "Latch Drivers": 0, + "Pi": 0, + "Po": 1, + "logic element": 0, + "latch": 0, + "Adder": -1, + "Multiplier": 0, + "Memory": 0, + "Hard Ip": -1, + "generic logic size": 6, + "Longest Path": 1, + "Average Path": 1, + "Estimated LUTs": 0, + "Total Node": 0 + }, + "test/ifdef_undefined/no_arch": { + "test_name": "test/ifdef_undefined/no_arch", + "architecture": "n/a", + "verilog": "ifdef_undefined.v", + "exit": 0, + "errors": [], + "warnings": [ + "OUTPUT_BLIF want to see if this will print json", + "NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed", + "NETLIST Net simple_op^out driving node simple_op^out is itself undriven." + ], + "max_rss(MiB)": 11.1, + "exec_time(ms)": 4.6, + "synthesis_time(ms)": 1.8, + "Latch Drivers": 0, + "Pi": 0, + "Po": 1, + "logic element": 0, + "latch": 0, + "Adder": -1, + "Multiplier": -1, + "Memory": -1, + "Hard Ip": -1, + "generic logic size": -1, + "Longest Path": 1, + "Average Path": 1, + "Estimated LUTs": 0, + "Total Node": 0 + } +} diff --git a/ODIN_II/regression_test/benchmark/task/test/task.conf b/ODIN_II/regression_test/benchmark/task/test/task.conf new file mode 100644 index 00000000000..079d21ca23a --- /dev/null +++ b/ODIN_II/regression_test/benchmark/task/test/task.conf @@ -0,0 +1,23 @@ +######################## +# operators benchmarks config +######################## + +regression_params=--include_default_arch +script_synthesis_params=--time_limit 3600s +script_simulation_params=--time_limit 3600s +simulation_params= -L reset rst -H we + +# setup the architecture +archs_dir=../vtr_flow/arch/timing + +arch_list_add=k6_N10_40nm.xml +arch_list_add=k6_N10_mem32K_40nm.xml +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# setup the circuits +circuits_dir=regression_test/benchmark/verilog/ + +circuit_list_add=test/*.v + +synthesis_parse_file=regression_test/parse_result/conf/synth.toml +simulation_parse_file=regression_test/parse_result/conf/sim.toml \ No newline at end of file diff --git a/ODIN_II/regression_test/benchmark/verilog/FIR/ex1BT16_fir_20_input b/ODIN_II/regression_test/benchmark/verilog/FIR/ex1BT16_fir_20_input index 32450f91503..ec36273f6b3 100644 --- a/ODIN_II/regression_test/benchmark/verilog/FIR/ex1BT16_fir_20_input +++ b/ODIN_II/regression_test/benchmark/verilog/FIR/ex1BT16_fir_20_input @@ -395,4 +395,4 @@ GLOBAL_SIM_BASE_CLK clk In_X 0 1 0X227 1 0 0X826 0 0 0X255 -1 1 0X114 \ No newline at end of file +1 1 0X114 diff --git a/ODIN_II/regression_test/benchmark/verilog/ex1BT16_fir_20_input b/ODIN_II/regression_test/benchmark/verilog/ex1BT16_fir_20_input deleted file mode 100644 index ec36273f6b3..00000000000 --- a/ODIN_II/regression_test/benchmark/verilog/ex1BT16_fir_20_input +++ /dev/null @@ -1,398 +0,0 @@ -GLOBAL_SIM_BASE_CLK clk In_X -1 1 0Xacf -0 1 0X8d0 -1 0 0Xd71 -0 0 0X952 -1 1 0Xeae -0 1 0X14a -1 0 0X10b -0 0 0X171 -1 1 0Xfae -0 1 0X6b7 -1 0 0Xa8e -0 0 0X51e -1 1 0X9f4 -0 1 0X3eb -1 0 0X072 -0 0 0Xaa7 -1 1 0X713 -0 1 0Xd0c -1 0 0X082 -0 0 0Xe60 -1 1 0X779 -0 1 0X600 -1 0 0Xa31 -0 0 0X6df -1 1 0X0a0 -0 1 0X08b -1 0 0X9c9 -0 0 0X9bd -1 1 0X088 -0 1 0X91d -1 0 0X9f6 -0 0 0X88d -1 1 0Xa78 -0 1 0X6d7 -1 0 0X9e7 -0 0 0X931 -1 1 0X86b -0 1 0X801 -1 0 0X8f5 -0 0 0X6da -1 1 0X7c8 -0 1 0Xd7d -1 0 0X9e4 -0 0 0X873 -1 1 0X1fb -0 1 0X831 -1 0 0X78e -0 0 0X6e1 -1 1 0X455 -0 1 0Xb9a -1 0 0X7e8 -0 0 0Xc34 -1 1 0Xd9b -0 1 0X26d -1 0 0X48c -0 0 0X953 -1 1 0X642 -0 1 0X5f8 -1 0 0X04f -0 0 0Xc3a -1 1 0Xfa7 -0 1 0Xb8b -1 0 0X8ba -0 0 0X6da -1 1 0X653 -0 1 0X682 -1 0 0X6a6 -0 0 0Xf74 -1 1 0Xd31 -0 1 0Xa39 -1 0 0Xa68 -0 0 0Xf5a -1 1 0Xb04 -0 1 0X5d9 -1 0 0X7f2 -0 0 0X38a -1 1 0Xc50 -0 1 0Xaf6 -1 0 0X63d -0 0 0X45d -1 1 0Xf57 -0 1 0X49b -1 0 0Xedc -0 0 0Xd63 -1 1 0X614 -0 1 0X34e -1 0 0X43b -0 0 0X7bd -1 1 0Xb6e -0 1 0Xae1 -1 0 0X5fb -0 0 0X9e5 -1 1 0Xea7 -0 1 0X541 -1 0 0Xf5c -0 0 0X9f7 -1 1 0X81d -0 1 0X3b1 -1 0 0X6ab -0 0 0Xe48 -1 1 0Xd09 -0 1 0Xdd0 -1 0 0Xc98 -0 0 0X579 -1 1 0Xbef -0 1 0X077 -1 0 0X8d4 -0 0 0X615 -1 1 0X95e -0 1 0Xb5e -1 0 0X1c7 -0 0 0Xceb -1 1 0X14c -0 1 0X28a -1 0 0Xc29 -0 0 0Xd2f -1 1 0Xd41 -0 1 0X19c -1 0 0Xfbe -0 0 0X7aa -1 1 0Xd19 -0 1 0X9d6 -1 0 0X571 -0 0 0X3ad -1 1 0X359 -0 1 0Xc23 -1 0 0X83e -0 0 0X6d8 -1 1 0X0e6 -0 1 0X056 -1 0 0X86b -0 0 0X459 -1 1 0X4c3 -0 1 0X49f -1 0 0X0ce -0 0 0X0c7 -1 1 0X408 -0 1 0Xc07 -1 0 0X641 -0 0 0Xdb1 -1 1 0Xf80 -0 1 0Xaec -1 0 0Xacc -0 0 0X629 -1 1 0X61b -0 1 0X998 -1 0 0X927 -0 0 0X750 -1 1 0Xd9c -0 1 0X310 -1 0 0X816 -0 0 0X87c -1 1 0X49d -0 1 0Xfc4 -1 0 0X76c -0 0 0X5f2 -1 1 0X6b0 -0 1 0X8e6 -1 0 0X589 -0 0 0Xf06 -1 1 0X36c -0 1 0Xe94 -1 0 0X304 -0 0 0X53f -1 1 0X821 -0 1 0Xd8e -1 0 0X201 -0 0 0X28f -1 1 0Xbb1 -0 1 0X28f -1 0 0X8ea -0 0 0X0c7 -1 1 0X42a -0 1 0Xd63 -1 0 0Xfc7 -0 0 0X567 -1 1 0X1ea -0 1 0X1f3 -1 0 0X734 -0 0 0X871 -1 1 0X805 -0 1 0X1c1 -1 0 0Xb69 -0 0 0Xe24 -1 1 0X2bf -0 1 0X005 -1 0 0X83f -0 0 0X423 -1 1 0X0ae -0 1 0X6d3 -1 0 0X062 -0 0 0X0c3 -1 1 0X402 -0 1 0Xf35 -1 0 0Xfc2 -0 0 0X787 -1 1 0X3b4 -0 1 0X449 -1 0 0Xa32 -0 0 0X92a -1 1 0Xb03 -0 1 0Xa2d -1 0 0X207 -0 0 0X045 -1 1 0X4d8 -0 1 0X996 -1 0 0Xd3f -0 0 0Xaa2 -1 1 0Xfce -0 1 0X662 -1 0 0Xd6b -0 0 0X4e2 -1 1 0X335 -0 1 0X639 -1 0 0X80c -0 0 0X029 -1 1 0Xdb4 -0 1 0Xfd2 -1 0 0X18b -0 0 0Xe34 -1 1 0X523 -0 1 0Xfe0 -1 0 0X19c -0 0 0X564 -1 1 0Xec9 -0 1 0X5db -1 0 0X0c8 -0 0 0X771 -1 1 0Xc49 -0 1 0X35f -1 0 0X9fe -0 0 0X174 -1 1 0X316 -0 1 0Xa37 -1 0 0X3eb -0 0 0X6ea -1 1 0Xef5 -0 1 0X8ef -1 0 0Xeed -0 0 0Xd54 -1 1 0X476 -0 1 0X7a3 -1 0 0X6a2 -0 0 0X997 -1 1 0X099 -0 1 0X615 -1 0 0Xd13 -0 0 0X321 -1 1 0Xe5a -0 1 0Xf80 -1 0 0X73d -0 0 0X9a1 -1 1 0Xd9a -0 1 0X8b1 -1 0 0Xac4 -0 0 0X03a -1 1 0X005 -0 1 0X0a2 -1 0 0X07a -0 0 0X26f -1 1 0X690 -0 1 0X8ba -1 0 0X413 -0 0 0Xf1a -1 1 0X534 -0 1 0X5ae -1 0 0Xd11 -0 0 0X8ab -1 1 0Xb7d -0 1 0X39e -1 0 0Xb1d -0 0 0Xfe2 -1 1 0Xfe1 -0 1 0Xf10 -1 0 0Xeda -0 0 0Xc92 -1 1 0Xf74 -0 1 0X9bd -1 0 0Xfcc -0 0 0X74c -1 1 0Xcf1 -0 1 0Xb3e -1 0 0Xdc9 -0 0 0X799 -1 1 0Xe9b -0 1 0X8d3 -1 0 0X48a -0 0 0X881 -1 1 0X9a6 -0 1 0X1fd -1 0 0X0bd -0 0 0Xb8b -1 1 0X277 -0 1 0Xad4 -1 0 0Xfdc -0 0 0Xfa0 -1 1 0Xd7b -0 1 0Xe40 -1 0 0X1c3 -0 0 0Xb21 -1 1 0Xe11 -0 1 0X07e -1 0 0X025 -0 0 0X354 -1 1 0X4b8 -0 1 0X85f -1 0 0Xf59 -0 0 0Xb38 -1 1 0Xa13 -0 1 0X3e6 -1 0 0Xf7c -0 0 0Xe4c -1 1 0X13b -0 1 0Xb44 -1 0 0X37c -0 0 0X8f2 -1 1 0X1c2 -0 1 0Xdce -1 0 0Xc04 -0 0 0Xb60 -1 1 0Xdf8 -0 1 0Xfd9 -1 0 0Xac2 -0 0 0Xd77 -1 1 0X9b2 -0 1 0Xe15 -1 0 0X386 -0 0 0X6e8 -1 1 0Xa87 -0 1 0X9d6 -1 0 0X3eb -0 0 0X57d -1 1 0Xaae -0 1 0X18b -1 0 0X986 -0 0 0Xa42 -1 1 0X895 -0 1 0Xd4a -1 0 0Xf17 -0 0 0X3b9 -1 1 0X5ea -0 1 0Xa38 -1 0 0X8f4 -0 0 0Xfc6 -1 1 0Xf16 -0 1 0X569 -1 0 0Xa31 -0 0 0Xdd1 -1 1 0X25b -0 1 0Xf37 -1 0 0Xf3a -0 0 0X16b -1 1 0Xaeb -0 1 0Xa51 -1 0 0X639 -0 0 0Xde1 -1 1 0Xb50 -0 1 0X54d -1 0 0X310 -0 0 0X80c -1 1 0X7a2 -0 1 0X6bb -1 0 0X0b6 -0 0 0X2b8 -1 1 0X2cf -0 1 0Xf1e -1 0 0X6b8 -0 0 0X1aa -1 1 0Xb76 -0 1 0Xc19 -1 0 0Xa84 -0 0 0X6ac -1 1 0X2f9 -0 1 0X929 -1 0 0X633 -0 0 0Xc2a -1 1 0X4b8 -0 1 0Xa6d -1 0 0X0ba -0 0 0X968 -1 1 0X42a -0 1 0Xa32 -1 0 0X909 -0 0 0X4b9 -1 1 0X708 -0 1 0X66c -1 0 0Xc0d -0 0 0X056 -1 1 0Xe45 -0 1 0X4a2 -1 0 0X4e8 -0 0 0X603 -1 1 0X632 -0 1 0X227 -1 0 0X826 -0 0 0X255 -1 1 0X114 diff --git a/ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined.v b/ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined.v new file mode 100644 index 00000000000..8d722baeb07 --- /dev/null +++ b/ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined.v @@ -0,0 +1,12 @@ + +module simple_op(in,out); + $display("Warning::OUTPUT_BLIF want to see if this will print json \n"); + input in; + output out; + + `define firsts + + `ifdef first + assign out = in; + `endif +endmodule \ No newline at end of file diff --git a/ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined_input b/ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined_input new file mode 100644 index 00000000000..52108c0b085 --- /dev/null +++ b/ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined_input @@ -0,0 +1,3 @@ +GLOBAL_SIM_BASE_CLK in +0 0 +0 1 \ No newline at end of file diff --git a/ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined_output b/ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined_output new file mode 100644 index 00000000000..388de28236b --- /dev/null +++ b/ODIN_II/regression_test/benchmark/verilog/test/ifdef_undefined_output @@ -0,0 +1,3 @@ +out +x +x \ No newline at end of file