diff --git a/doc/src/arch/reference.rst b/doc/src/arch/reference.rst index aa9475721e8..7b5c4a40362 100644 --- a/doc/src/arch/reference.rst +++ b/doc/src/arch/reference.rst @@ -805,6 +805,34 @@ Tile **Attributes:** + :req_param name: The name of this tile. + + The name must be unique with respect to any other sibling ```` tag. + + :opt_param width: The width of the block type in grid tiles + + **Default:** ``1`` + + :opt_param height: The height of the block type in grid tiles + + **Default:** ``1`` + + :opt_param area: The logic area (in :term:`MWTA`) of the block type + + **Default:** from the ```` tag + +The following tags are common to all ```` tags: + + +.. arch:tag:: + + .. seealso:: For a tutorial on describing the usage of sub tiles for ``heterogeneous tiles`` (tiles which support multiple instances of the same or different :ref:`arch_complex_blocks`) definition see :ref:`heterogeneous_tiles_tutorial`. + + Describes one or many sub tiles corresponding to the physical tile. + Each sub tile is identifies a set of one or more stack location on a specific x, y grid location. + + **Attributes:** + :req_param name: The name of this tile. The name must be unique with respect to any other sibling ```` tag. @@ -817,250 +845,280 @@ Tile .. code-block:: xml - + ... - + specifies there are two instances of the block type ``IO`` at each of its grid locations. - :opt_param width: The width of the block type in grid tiles + .. note:: It is mandatory to have at least one sub tile definition for each physical tile. - **Default:** ``1`` + .. arch:tag:: - :opt_param height: The height of the block type in grid tiles + Defines an input port. + Multple input ports are described using multiple ```` tags. - **Default:** ``1`` + :req_param name: Name of the input port. + :req_param num_pins: Number of pins the input port has. - :opt_param area: The logic area (in :term:`MWTA`) of the block type + :opt_param equivalent: - **Default:** from the ```` tag + Describes if the pins of the port are logically equivalent. + Input logical equivalence means that the pin order can be swapped without changing functionality. + For example, an AND gate has logically equivalent inputs because you can swap the order of the inputs and it’s still correct; an adder, on the otherhand, is not logically equivalent because if you swap the MSB with the LSB, the results are completely wrong. + LUTs are also considered logically equivalent since the logic function (LUT mask) can be rotated to account for pin swapping. -The following tags are common to all ```` tags: + * ``none``: No input pins are logically equivalent. -.. arch:tag:: + Input pins can not be swapped by the router. (Generates a unique SINK rr-node for each block input port pin.) - Defines an input port. - Multple input ports are described using multiple ```` tags. + * ``full``: All input pins are considered logically equivalent (e.g. due to logical equivalance or a full-crossbar within the cluster). - :req_param name: Name of the input port. - :req_param num_pins: Number of pins the input port has. + All input pins can be swapped without limitation by the router. (Generates a single SINK rr-node shared by each input port pin.) - :opt_param equivalent: + **default:** ``none`` - Describes if the pins of the port are logically equivalent. - Input logical equivalence means that the pin order can be swapped without changing functionality. - For example, an AND gate has logically equivalent inputs because you can swap the order of the inputs and it’s still correct; an adder, on the otherhand, is not logically equivalent because if you swap the MSB with the LSB, the results are completely wrong. - LUTs are also considered logically equivalent since the logic function (LUT mask) can be rotated to account for pin swapping. + :opt_param is_non_clock_global: - * ``none``: No input pins are logically equivalent. + .. note:: Applies only to top-level pb_type. - Input pins can not be swapped by the router. (Generates a unique SINK rr-node for each block input port pin.) + Describes if this input pin is a global signal that is not a clock. + Very useful for signals such as FPGA-wide asynchronous resets. + These signals have their own dedicated routing channels and so should not use the general interconnect fabric on the FPGA. - * ``full``: All input pins are considered logically equivalent (e.g. due to logical equivalance or a full-crossbar within the cluster). - All input pins can be swapped without limitation by the router. (Generates a single SINK rr-node shared by each input port pin.) + .. arch:tag:: - **default:** ``none`` + Defines an output port. + Multple output ports are described using multiple ```` tags - :opt_param is_non_clock_global: + :req_param name: Name of the output port. + :req_param num_pins: Number of pins the output port has. - .. note:: Applies only to top-level pb_type. + :opt_param equivalent: - Describes if this input pin is a global signal that is not a clock. - Very useful for signals such as FPGA-wide asynchronous resets. - These signals have their own dedicated routing channels and so should not use the general interconnect fabric on the FPGA. + Describes if the pins of the output port are logically equivalent: + * ``none``: No output pins are logically equivalent. -.. arch:tag:: + Output pins can not be swapped by the router. (Generates a unique SRC rr-node for each block output port pin.) - Defines an output port. - Multple output ports are described using multiple ```` tags + * ``full``: All output pins are considered logically equivalent. - :req_param name: Name of the output port. - :req_param num_pins: Number of pins the output port has. + All output pins can be swapped without limitation by the router. For example, this option would be appropriate to model an output port which has a full crossbar between it and the logic within the block that drives it. (Generates a single SRC rr-node shared by each output port pin.) - :opt_param equivalent: + * ``instance``: Models that sub-instances within a block (e.g. LUTs/BLEs) can be swapped to achieve a limited form of output pin logical equivalence. - Describes if the pins of the output port are logically equivalent: + Like ``full``, this generates a single SRC rr-node shared by each output port pin. However, each net originating from this source can use only one output pin from the equivalence group. This can be useful in modeling more complex forms of equivalence in which you can swap which BLE implements which function to gain access to different inputs. - * ``none``: No output pins are logically equivalent. + .. warning:: When using ``instance`` equivalence you must be careful to ensure output swapping would not make the cluster internal routing (previously computed by the clusterer) illegal; the tool does not update the cluster internal routing due to output pin swapping. - Output pins can not be swapped by the router. (Generates a unique SRC rr-node for each block output port pin.) + **Default:** ``none`` - * ``full``: All output pins are considered logically equivalent. - All output pins can be swapped without limitation by the router. For example, this option would be appropriate to model an output port which has a full crossbar between it and the logic within the block that drives it. (Generates a single SRC rr-node shared by each output port pin.) + .. arch:tag:: - * ``instance``: Models that sub-instances within a block (e.g. LUTs/BLEs) can be swapped to achieve a limited form of output pin logical equivalence. + Describes a clock port. + Multple clock ports are described using multiple ```` tags. + *See above descriptions on inputs* - Like ``full``, this generates a single SRC rr-node shared by each output port pin. However, each net originating from this source can use only one output pin from the equivalence group. This can be useful in modeling more complex forms of equivalence in which you can swap which BLE implements which function to gain access to different inputs. + .. arch:tag:: - .. warning:: When using ``instance`` equivalence you must be careful to ensure output swapping would not make the cluster internal routing (previously computed by the clusterer) illegal; the tool does not update the cluster internal routing due to output pin swapping. + .. seealso:: For a step-by-step walkthrough on describing equivalent sites see :ref:`equivalent_sites_tutorial`. - **Default:** ``none`` + Describes the Complex Blocks that can be placed within a tile. + Each physical tile can comprehend a number from 1 to N of possible Complex Blocks, or ``sites``. + A ``site`` corresponds to a top-level Complex Block that must be placeable in at least 1 physical tile locations. + .. arch:tag:: -.. arch:tag:: + :req_param pb_type: Name of the corresponding pb_type. - Describes a clock port. - Multple clock ports are described using multiple ```` tags. - *See above descriptions on inputs* + :opt_param pin_mapping: Specifies whether the pin mapping between physical tile and logical pb_type: -.. _arch_fc: + * ``direct``: the pin mapping does not need to be specified as the tile pin definition is equal to the corresponding pb_type one; + * ``custom``: the pin mapping is user-defined. -.. arch:tag:: - :req_param in_type: - Indicates how the :math:`F_c` values for input pins should be interpreted. + **Default:** ``direct`` - ``frac``: The fraction of tracks of each wire/segment type. + **Example: Equivalent Sites** - ``abs``: The absolute number of tracks of each wire/segment type. + .. code-block:: xml - :req_param in_val: - Fraction or absolute number of tracks to which each input pin is connected. + + + - :req_param out_type: - Indicates how the :math:`F_c` values for output pins should be interpreted. + .. arch:tag:: - ``frac``: The fraction of tracks of each wire/segment type. + Desctibes the mapping of a physical tile's port on the logical block's (pb_type) port. + ``direct`` is an option sub-tag of ``site``. - ``abs``: The absolute number of tracks of each wire/segment type. + .. note:: This tag is need only if the pin_mapping of the ``site`` is defined as ``custom`` - :req_param out_val: - Fraction or absolute number of wires/segments to which each output pin connects. + Attributes: + - ``from`` is relative to the physical tile pins + - ``to`` is relative to the logical block pins + .. code-block:: xml - Sets the number of tracks/wires to which each logic block pin connects in each channel bordering the pin. + - The :math:`F_c` value :cite:`brown_fpgas` is interpreted as applying to each wire/segment type *individually* (see example). - When generating the FPGA routing architecture VPR will try to make 'good' choices about how pins and wires interconnect; for more details on the criteria and methods used see :cite:`betz_automatic_generation_of_fpga_routing`. + .. arch:tag:: + :req_param in_type: + Indicates how the :math:`F_c` values for input pins should be interpreted. - .. note:: If ```` is not specified for a complex block, the architecture's ```` is used. + ``frac``: The fraction of tracks of each wire/segment type. - .. note:: For unidirection routing architectures absolute :math:`F_c` values must be a multiple of 2. + ``abs``: The absolute number of tracks of each wire/segment type. - **Example:** + :req_param in_val: + Fraction or absolute number of tracks to which each input pin is connected. - Consider a routing architecture with 200 length 4 (L4) wires and 50 length 16 (L16) wires per channel, and the following Fc specification: + :req_param out_type: + Indicates how the :math:`F_c` values for output pins should be interpreted. - .. code-block:: xml + ``frac``: The fraction of tracks of each wire/segment type. - + ``abs``: The absolute number of tracks of each wire/segment type. - The above specifies that each: + :req_param out_val: + Fraction or absolute number of wires/segments to which each output pin connects. - * input pin connects to 20 L4 tracks (10% of the 200 L4s) and 5 L16 tracks (10% of the 50 L16s), and - * output pin connects to 25 L4 tracks and 25 L16 tracks. + Sets the number of tracks/wires to which each logic block pin connects in each channel bordering the pin. + The :math:`F_c` value :cite:`brown_fpgas` is interpreted as applying to each wire/segment type *individually* (see example). + When generating the FPGA routing architecture VPR will try to make 'good' choices about how pins and wires interconnect; for more details on the criteria and methods used see :cite:`betz_automatic_generation_of_fpga_routing`. - **Overriding Values:** - .. arch:tag:: + .. note:: If ```` is not specified for a complex block, the architecture's ```` is used. - Allows :math:`F_c` values to be overriden on a port or wire/segment type basis. + .. note:: For unidirection routing architectures absolute :math:`F_c` values must be a multiple of 2. - :req_param fc_type: - Indicates how the override :math:`F_c` value should be interpreted. + **Example:** - ``frac``: The fraction of tracks of each wire/segment type. + Consider a routing architecture with 200 length 4 (L4) wires and 50 length 16 (L16) wires per channel, and the following Fc specification: - ``abs``: The absolute number of tracks of each wire/segment type. + .. code-block:: xml - :req_param fc_val: - Fraction or absolute number of tracks in a channel. + - :opt_param port_name: - The name of the port to which this override applies. - If left unspecified this override applies to all ports. + The above specifies that each: - :opt_param segment_name: - The name of the segment (defined under ````) to which this override applies. - If left unspecified this override applies to all segments. + * input pin connects to 20 L4 tracks (10% of the 200 L4s) and 5 L16 tracks (10% of the 50 L16s), and - .. note:: At least one of ``port_name`` or ``segment_name`` must be specified. + * output pin connects to 25 L4 tracks and 25 L16 tracks. - **Port Override Example: Carry Chains** - If you have complex block pins that do not connect to general interconnect (eg. carry chains), you would use the ```` tag, within the ```` tag, to specify them: + **Overriding Values:** - .. code-block:: xml + .. arch:tag:: - - + Allows :math:`F_c` values to be overriden on a port or wire/segment type basis. - Where the attribute ``port_name`` is the name of the pin (``cin`` and ``cout`` in this example). + :req_param fc_type: + Indicates how the override :math:`F_c` value should be interpreted. + ``frac``: The fraction of tracks of each wire/segment type. - **Segment Override Example:** + ``abs``: The absolute number of tracks of each wire/segment type. - It is also possible to specify per ```` (i.e. routing wire) overrides: + :req_param fc_val: + Fraction or absolute number of tracks in a channel. - .. code-block:: xml + :opt_param port_name: + The name of the port to which this override applies. + If left unspecified this override applies to all ports. - + :opt_param segment_name: + The name of the segment (defined under ````) to which this override applies. + If left unspecified this override applies to all segments. - Where the above would cause all pins (both inputs and outputs) to use a fractional :math:`F_c` of ``0.1`` when connecting to segments of type ``L4``. + .. note:: At least one of ``port_name`` or ``segment_name`` must be specified. - **Combined Port and Segment Override Example:** - The ``port_name`` and ``segment_name`` attributes can be used together. - For example: + **Port Override Example: Carry Chains** - .. code-block:: xml + If you have complex block pins that do not connect to general interconnect (eg. carry chains), you would use the ```` tag, within the ```` tag, to specify them: - - + .. code-block:: xml - specifies that port ``my_input`` use a fractional :math:`F_c` of ``0.1`` when connecting to segments of type ``L4``, while the port ``my_output`` uses a fractional :math:`F_c` of ``0.2`` when connecting to segments of type ``L4``. - All other port/segment combinations would use the default :math:`F_c` values. + + -.. arch:tag:: + Where the attribute ``port_name`` is the name of the pin (``cin`` and ``cout`` in this example). - :req_param pattern: - * ``spread`` denotes that the pins are to be spread evenly on all sides of the complex block. - .. note:: *Includes* internal sides of blocks with width > 1 and/or height > 1. + **Segment Override Example:** - * ``perimeter`` denotes that the pins are to be spread evenly on perimeter sides of the complex block. + It is also possible to specify per ```` (i.e. routing wire) overrides: - .. note:: *Excludes* the internal sides of blocks with width > 1 and/or height > 1. + .. code-block:: xml - * ``spread_inputs_perimeter_outputs`` denotes that inputs pins are to be spread on all sides of the complex block, but output pins are to be spread only on perimeter sides of the block. + - .. note:: This is useful for ensuring outputs do not connect to wires which fly-over a width > 1 and height > 1 block (e.g. if using ``short`` or ``buffer`` connections instead of a fully configurable switch block within the block). + Where the above would cause all pins (both inputs and outputs) to use a fractional :math:`F_c` of ``0.1`` when connecting to segments of type ``L4``. - * ``custom`` allows the architect to specify specifically where the pins are to be placed using ```` tags. + **Combined Port and Segment Override Example:** - Describes the locations where the input, output, and clock pins are distributed in a complex logic block. + The ``port_name`` and ``segment_name`` attributes can be used together. + For example: - .. arch:tag:: name_of_complex_logic_block.port_name[int:int] ... + .. code-block:: xml - .. note:: ``...`` represents repeat as needed. Do not put ``...`` in the architecture file. + + - :req_param side: Specifies which of the four sides of a grid location the pins in the contents are located. + specifies that port ``my_input`` use a fractional :math:`F_c` of ``0.1`` when connecting to segments of type ``L4``, while the port ``my_output`` uses a fractional :math:`F_c` of ``0.2`` when connecting to segments of type ``L4``. + All other port/segment combinations would use the default :math:`F_c` values. - :opt_param xoffset: - Specifies the horizontal offset (in grid units) from block origin (bottom left corner). - The offset value must be less than the width of the block. + .. arch:tag:: - **Default:** ``0`` + :req_param pattern: + * ``spread`` denotes that the pins are to be spread evenly on all sides of the complex block. - :opt_param yoffset: - Specifies the vertical offset (in grid units) from block origin (bottom left corner). - The offset value must be less than the height of the block. + .. note:: *Includes* internal sides of blocks with width > 1 and/or height > 1. - **Default:** ``0`` + * ``perimeter`` denotes that the pins are to be spread evenly on perimeter sides of the complex block. + + .. note:: *Excludes* the internal sides of blocks with width > 1 and/or height > 1. + + * ``spread_inputs_perimeter_outputs`` denotes that inputs pins are to be spread on all sides of the complex block, but output pins are to be spread only on perimeter sides of the block. + + .. note:: This is useful for ensuring outputs do not connect to wires which fly-over a width > 1 and height > 1 block (e.g. if using ``short`` or ``buffer`` connections instead of a fully configurable switch block within the block). + + * ``custom`` allows the architect to specify specifically where the pins are to be placed using ```` tags. + + Describes the locations where the input, output, and clock pins are distributed in a complex logic block. + + .. arch:tag:: name_of_complex_logic_block.port_name[int:int] ... + + .. note:: ``...`` represents repeat as needed. Do not put ``...`` in the architecture file. - Physical equivalence for a pin is specified by listing a pin more than once for different locations. - For example, a LUT whose output can exit from the top and bottom of a block will have its output pin specified twice: once for the top and once for the bottom. + :req_param side: Specifies which of the four sides of a grid location the pins in the contents are located. - .. note:: If the ```` tag is missing, a ``spread`` pattern is assumed. + :opt_param xoffset: + Specifies the horizontal offset (in grid units) from block origin (bottom left corner). + The offset value must be less than the width of the block. + + **Default:** ``0`` + + :opt_param yoffset: + Specifies the vertical offset (in grid units) from block origin (bottom left corner). + The offset value must be less than the height of the block. + + **Default:** ``0`` + + Physical equivalence for a pin is specified by listing a pin more than once for different locations. + For example, a LUT whose output can exit from the top and bottom of a block will have its output pin specified twice: once for the top and once for the bottom. + + .. note:: If the ```` tag is missing, a ``spread`` pattern is assumed. .. arch:tag:: @@ -1177,49 +1235,6 @@ The following tags are common to all ```` tags: -.. arch:tag:: - - .. seealso:: For a step-by-step walkthrough on describing equivalent sites see :ref:`equivalent_sites_tutorial`. - - Describes the Complex Blocks that can be placed within a tile. - Each physical tile can comprehend a number from 1 to N of possible Complex Blocks, or ``sites``. - A ``site`` corresponds to a top-level Complex Block that must be placeable in at least 1 physical tile locations. - - .. arch:tag:: - - :req_param pb_type: Name of the corresponding pb_type. - - :opt_param pin_mapping: Specifies whether the pin mapping between physical tile and logical pb_type: - - * ``direct``: the pin mapping does not need to be specified as the tile pin definition is equal to the corresponding pb_type one; - * ``custom``: the pin mapping is user-defined. - - - **Default:** ``direct`` - - **Example: Equivalent Sites** - - .. code-block:: xml - - - - - - .. arch:tag:: - - Desctibes the mapping of a physical tile's port on the logical block's (pb_type) port. - ``direct`` is an option sub-tag of ``site``. - - .. note:: This tag is need only if the pin_mapping of the ``site`` is defined as ``custom`` - - Attributes: - - ``from`` is relative to the physical tile pins - - ``to`` is relative to the logical block pins - - .. code-block:: xml - - - .. _arch_complex_blocks: Complex Blocks diff --git a/doc/src/tutorials/arch/clock_tile_figure.png b/doc/src/tutorials/arch/clock_tile_figure.png new file mode 100644 index 00000000000..0df381e7d75 Binary files /dev/null and b/doc/src/tutorials/arch/clock_tile_figure.png differ diff --git a/doc/src/tutorials/arch/equivalent_sites.rst b/doc/src/tutorials/arch/equivalent_sites.rst index 6c505773fda..e70a7daaefa 100644 --- a/doc/src/tutorials/arch/equivalent_sites.rst +++ b/doc/src/tutorials/arch/equivalent_sites.rst @@ -34,8 +34,8 @@ Below the user can find the implementation of this situation starting from an ex - - + + @@ -54,8 +54,8 @@ Below the user can find the implementation of this situation starting from an ex - - + + @@ -71,8 +71,8 @@ Below the user can find the implementation of this situation starting from an ex - - ... + + / @@ -85,8 +85,8 @@ Below the user can find the implementation of this situation starting from an ex - - ... + + / @@ -123,8 +123,8 @@ To have the possibility to make VPR choose a ``SLICEM`` location when placing a - - + + With the above description of the ``SLICEM`` tile, the user can now have the ``SLICEL`` sites to be placed in ``SLICEM`` physical locations. @@ -147,7 +147,7 @@ Below the user can find the implementation of this situation starting from an ex - + LEFT_IOPAD_TILE.INPUT LEFT_IOPAD_TILE.OUTPUT @@ -161,7 +161,7 @@ Below the user can find the implementation of this situation starting from an ex - + RIGHT_IOPAD_TILE.INPUT RIGHT_IOPAD_TILE.OUTPUT @@ -173,14 +173,14 @@ Below the user can find the implementation of this situation starting from an ex - - ... + + / - - ... + + / @@ -197,7 +197,7 @@ To avoid duplicating the complex logic blocks in ``LEFT`` and ``RIGHT IOPADS``, - + LEFT_IOPAD_TILE.INPUT LEFT_IOPAD_TILE.OUTPUT @@ -211,7 +211,7 @@ To avoid duplicating the complex logic blocks in ``LEFT`` and ``RIGHT IOPADS``, - + RIGHT_IOPAD_TILE.INPUT RIGHT_IOPAD_TILE.OUTPUT @@ -223,8 +223,9 @@ To avoid duplicating the complex logic blocks in ``LEFT`` and ``RIGHT IOPADS``, - - ... + + ... + diff --git a/doc/src/tutorials/arch/hclk_ioi.png b/doc/src/tutorials/arch/hclk_ioi.png new file mode 100644 index 00000000000..edd90256008 Binary files /dev/null and b/doc/src/tutorials/arch/hclk_ioi.png differ diff --git a/doc/src/tutorials/arch/heterogeneous_tiles.rst b/doc/src/tutorials/arch/heterogeneous_tiles.rst new file mode 100644 index 00000000000..bb6ad9be400 --- /dev/null +++ b/doc/src/tutorials/arch/heterogeneous_tiles.rst @@ -0,0 +1,189 @@ +.. _heterogeneous_tiles_tutorial: + +Heterogeneous tiles tutorial +============================ + +This tutorial aims at providing information to the user on how to model sub tiles to enable *heterogeneous tiles* in VPR. + +An *heterogeneous tile* is a tile that includes two or more site types that may differ in the following aspects: + +- *Block types* (pb_type) +- *Fc* definition +- *Pin locations* definition +- *IO ports* definition + +As a result, an *heterogeneous tile* has the possibility of having multiple block types at the same (*x*, *y*) location in the grid. +This comes with the introduction of a third spatial coordinate (sub-block) that identifies the placement of the block type within the x and y grid coordinate. + +Moreover, the placer can choose and assign different locations for each block type within the same coordinates as well. + +.. figure:: sub_tiles_grid.png + + Device grid, with (x, y, sub-block) coordinates. Each block can be moved by the placer in all the three spatial dimensions. + +To correctly model an architecture, each :ref:`arch_tiles` requires at least one sub tile definition. This represents a default +homogeneous architecture, composed of one or many instances of the sub tile within the physical tile (the number of such sub-tiles is referred to as the *capacity*). + +To enhance the expressivity of VPR architecture, additional sub tiles can be inserted alongside with the default sub tile. +This enables the definition of the *heterogeneous tiles*. + +With this new capability, the device grid of a given architecture does include a new sub-block coordinate that identifies the type of sub tile used and its actual location, in case the capacity is greater than 1. + +Heterogeneous tiles examples +---------------------------- + +Following, there are two examples to illustrate some potential use cases of the *heterogeneous tiles*, that might be of interest to the reader. + +.. note:: The examples below are a simplified versions of the real architectural specification. + +Sub-tiles with different pin locations +###################################### + +The Xilinx Series 7 Clock tile is composed of 16 BUFGCTRL sites (pg. 36 of the `7 Series FPGAs +Clocking Resources `_ guide). Even though they are equivalent regarding the ports and Fc definition, some of the sites differ in terms of pin locations, as depicted by the simplified representation of the Clock tile in :numref:`clock_tile`. + +.. _clock_tile: +.. figure:: clock_tile_figure.png + + Simplified view of the Clock tile of the Xilinx Series 7 fabric. + +Heterogeneous tiles come in hand to model this kind of tiles and an example is the following: + +.. code-block:: XML + + + + + + + + + + + + + + + + BUFG_SUB_TILE_0.I1 BUFG_SUB_TILE_0.I0 BUFG_SUB_TILE_0.CE0 BUFG_SUB_TILE_0.S0 BUFG_SUB_TILE_0.IGNORE1 BUFG_SUB_TILE_0.CE1 BUFG_SUB_TILE_0.IGNORE0 BUFG_SUB_TILE_0.S1 + BUFG_SUB_TILE_0.I1 BUFG_SUB_TILE_0.I0 BUFG_SUB_TILE_0.O + + + + + + + + + + + + + + + + + + BUFG_SUB_TILE_1.S1 BUFG_SUB_TILE_1.I0 BUFG_SUB_TILE_1.CE1 BUFG_SUB_TILE_1.I1 BUFG_SUB_TILE_1.IGNORE1 BUFG_SUB_TILE_1.IGNORE0 BUFG_SUB_TILE_1.CE0 BUFG_SUB_TILE_1.S0 + BUFG_SUB_TILE_1.I0 BUFG_SUB_TILE_1.I1 BUFG_SUB_TILE_1.O + + + + + + + + + + + + + + + + + + BUFG_SUB_TILE_2.S1 BUFG_SUB_TILE_2.I0 BUFG_SUB_TILE_2.CE1 BUFG_SUB_TILE_2.I1 BUFG_SUB_TILE_2.IGNORE1 BUFG_SUB_TILE_2.IGNORE0 BUFG_SUB_TILE_2.CE0 BUFG_SUB_TILE_2.S0 + BUFG_SUB_TILE_2.I0 BUFG_SUB_TILE_2.I1 BUFG_SUB_TILE_2.O + + + + + + + + + + + + + + + + + + + + + + +The above ``BUFG_TILE`` contains three types of sub-tiles (``BUFG_SUB_TILE_0``, ``BUFG_SUB_TILE_1`` and ``BUFG_SUB_TILE_2``). + +While each sub-tile type contains the same pb_type (equivalent_sites of ``BUFGCTRL``), they differ in two ways: + +1. Each sub-tile has different pin locations. For example ``BUFG_SUB_TILE_0`` has the ``I1`` pins on the top side of the tile, while ``BUFG_SUB_TILE_1`` and ``BUFG_SUB_TILE_2`` have them on the right and left sides respectively. +2. Each sub-tile has a different 'capacity' (i.e. a different number of sites). ``BUFG_SUB_TILE_1`` and ``BUFG_SUB_TILE_2`` have capacity 1, while ``BUFG_SUB_TILE_1`` has capacity 14. As a result the ``BUFG_TILE`` can implement a total of 16 ``BUFGCTRL`` blocks. + +Sub-tiles containing different block types +########################################## + +As another example taken from the Xilinx Series 7 fabric, the HCLK_IOI tile is composed of three different block types, namely BUFIO, BUFR and IDELAYCTRL. + +.. figure:: hclk_ioi.png + + Simplified view of the HCLK_IOI tile in the Xilinx Series 7 fabric. + +The reader might think that it is possible to model this situation using the :ref:`arch_complex_blocks` to model this situation, with a ```` containing the various blocks. + +Indeed, this could be done, but, for some architectures, the placement location of a sub block is particularly relevant, hence the need of leaving this choice to the placement algorithm instead of the packer one. + +Each one of these site types has different IO pins as well as pin locations. + +.. code-block:: XML + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Each ``HCLK_IOI`` tile contains three sub-tiles, each containing a different type of pb_type: + +- the ``BUFIO`` sub-tile supports 4 instances (capacity = 4) of pb_type ``BUFIO_SITE`` +- the ``BUFR`` sub-tile supports 4 instances of ``BUFR_SITE`` pb_types +- the ``IDELAYCTRL`` sub-tile supports 1 instances of the ``IDELAYCTRL_SITE`` diff --git a/doc/src/tutorials/arch/index.rst b/doc/src/tutorials/arch/index.rst index 8a3a8d22482..ee074b7105e 100644 --- a/doc/src/tutorials/arch/index.rst +++ b/doc/src/tutorials/arch/index.rst @@ -31,6 +31,7 @@ Multiple examples of how this language can be used to describe different types o configurable_memory xilinx_virtex_6_like equivalent_sites + heterogeneous_tiles **Modeling Guides:** diff --git a/doc/src/tutorials/arch/sub_tiles_grid.png b/doc/src/tutorials/arch/sub_tiles_grid.png new file mode 100644 index 00000000000..6aa468ef542 Binary files /dev/null and b/doc/src/tutorials/arch/sub_tiles_grid.png differ diff --git a/libs/libarchfpga/arch/mult_luts_arch.xml b/libs/libarchfpga/arch/mult_luts_arch.xml index e1e4d7a3573..9941d3a796c 100644 --- a/libs/libarchfpga/arch/mult_luts_arch.xml +++ b/libs/libarchfpga/arch/mult_luts_arch.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/libs/libarchfpga/arch/sample_arch.xml b/libs/libarchfpga/arch/sample_arch.xml index 345b346dd28..f2f3e7173b3 100755 --- a/libs/libarchfpga/arch/sample_arch.xml +++ b/libs/libarchfpga/arch/sample_arch.xml @@ -133,54 +133,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 34df538e769..2ddabadd0b5 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -222,38 +222,12 @@ void free_type_descriptors(std::vector& type_descriptors) continue; } - for (int width = 0; width < type.width; ++width) { - for (int height = 0; height < type.height; ++height) { - for (int side = 0; side < 4; ++side) { - for (int pin = 0; pin < type.num_pin_loc_assignments[width][height][side]; ++pin) { - if (type.pin_loc_assignments[width][height][side][pin]) - vtr::free(type.pin_loc_assignments[width][height][side][pin]); - } - vtr::free(type.pinloc[width][height][side]); - vtr::free(type.pin_loc_assignments[width][height][side]); - } - vtr::free(type.pinloc[width][height]); - vtr::free(type.pin_loc_assignments[width][height]); - vtr::free(type.num_pin_loc_assignments[width][height]); - } - vtr::free(type.pinloc[width]); - vtr::free(type.pin_loc_assignments[width]); - vtr::free(type.num_pin_loc_assignments[width]); - } - vtr::free(type.pinloc); - vtr::free(type.pin_loc_assignments); - vtr::free(type.num_pin_loc_assignments); + for (auto& sub_tile : type.sub_tiles) { + vtr::free(sub_tile.name); - for (int j = 0; j < type.num_class; ++j) { - vtr::free(type.class_inf[j].pinlist); - } - vtr::free(type.class_inf); - vtr::free(type.is_ignored_pin); - vtr::free(type.is_pin_global); - vtr::free(type.pin_class); - - for (auto port : type.ports) { - vtr::free(port.name); + for (auto port : sub_tile.ports) { + vtr::free(port.name); + } } } type_descriptors.clear(); @@ -547,11 +521,6 @@ t_physical_tile_type SetupEmptyPhysicalType() { type.capacity = 0; type.num_drivers = 0; type.num_receivers = 0; - type.pinloc = nullptr; - type.num_class = 0; - type.class_inf = nullptr; - type.pin_class = nullptr; - type.is_ignored_pin = nullptr; type.area = UNDEFINED; type.switchblock_locations = vtr::Matrix({{size_t(type.width), size_t(type.height)}}, e_sb_type::FULL); type.switchblock_switch_overrides = vtr::Matrix({{size_t(type.width), size_t(type.height)}}, DEFAULT_SWITCH); @@ -569,6 +538,18 @@ t_logical_block_type SetupEmptyLogicalType() { return type; } +std::unordered_set get_equivalent_sites_set(t_physical_tile_type_ptr type) { + std::unordered_set equivalent_sites; + + for (auto& sub_tile : type->sub_tiles) { + for (auto& logical_block : sub_tile.equivalent_sites) { + equivalent_sites.insert(logical_block); + } + } + + return equivalent_sites; +} + void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, char* new_name, t_pb_type* copy) { diff --git a/libs/libarchfpga/src/arch_util.h b/libs/libarchfpga/src/arch_util.h index 54ebde163c1..ccc36f89912 100644 --- a/libs/libarchfpga/src/arch_util.h +++ b/libs/libarchfpga/src/arch_util.h @@ -2,6 +2,7 @@ #define ARCH_UTIL_H #include +#include #include "physical_types.h" class InstPort { @@ -48,6 +49,8 @@ t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, in t_physical_tile_type SetupEmptyPhysicalType(); t_logical_block_type SetupEmptyLogicalType(); +std::unordered_set get_equivalent_sites_set(t_physical_tile_type_ptr type); + void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, char* new_name, t_pb_type* copy); diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index 8d1ea79971a..3943f6e6a94 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -1,9 +1,11 @@ #include #include #include +#include #include "echo_arch.h" #include "arch_types.h" +#include "arch_util.h" #include "vtr_list.h" #include "vtr_util.h" #include "vtr_memory.h" @@ -103,7 +105,9 @@ void EchoArch(const char* EchoFile, int index = Type.index; fprintf(Echo, "\tindex: %d\n", index); - for (auto LogicalBlock : Type.equivalent_sites) { + auto equivalent_sites = get_equivalent_sites_set(&Type); + + for (auto LogicalBlock : equivalent_sites) { fprintf(Echo, "\nEquivalent Site: %s\n", LogicalBlock->name); } fprintf(Echo, "\n"); @@ -314,7 +318,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { arch->Directs[i].to_pin); fprintf(Echo, "\t\t\t\t x_offset %d y_offset %d z_offset %d\n", arch->Directs[i].x_offset, arch->Directs[i].y_offset, - arch->Directs[i].z_offset); + arch->Directs[i].sub_tile_offset); } fprintf(Echo, "*************************************************\n\n"); diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index f604e291657..fb65e7a4983 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -104,33 +104,29 @@ static e_directionality switch_type_directionaity(SwitchType type) { * t_physical_tile_type */ std::vector t_physical_tile_type::get_clock_pins_indices() const { - std::vector indices; // function return vector - - // Temporary variables - int clock_pins_start_idx = 0; - int clock_pins_stop_idx = 0; - - for (int capacity_num = 0; capacity_num < this->capacity; capacity_num++) { - // Ranges are picked on the basis that pins are ordered: inputs, outputs, then clock pins - // This is because ProcessPb_type assigns pb_type port indices in that order and - // SetupPinLocationsAndPinClasses assigns t_logical_block_type_ptr pin indices in the order of port indices - // TODO: This pin ordering assumption is also used functions such as load_external_nets_and_cb - // either remove this assumption all togther and create a better mapping or make use of - // the same functions throughout the code that return the pin ranges. - clock_pins_start_idx = this->num_input_pins + this->num_output_pins + clock_pins_stop_idx; - clock_pins_stop_idx = clock_pins_start_idx + this->num_clock_pins; - - for (int pin_idx = clock_pins_start_idx; pin_idx < clock_pins_stop_idx; pin_idx++) { - indices.push_back(pin_idx); - } + for (auto pin_index : this->clock_pin_indices) { + VTR_ASSERT(pin_index < this->num_pins); } - // assert that indices are not out of bounds by checking the last index inserted - if (!indices.empty()) { - VTR_ASSERT(indices.back() < this->num_pins); + return this->clock_pin_indices; +} + +int t_physical_tile_type::get_sub_tile_loc_from_pin(int pin_num) const { + VTR_ASSERT(pin_num < this->num_pins); + + for (auto sub_tile : this->sub_tiles) { + auto max_inst_pins = sub_tile.num_phy_pins / sub_tile.capacity.total(); + + for (int pin = 0; pin < sub_tile.num_phy_pins; pin++) { + if (sub_tile.sub_tile_to_tile_pin_indices[pin] == pin_num) { + //If the physical tile pin matches pin_num, return the + //corresponding absolute capacity location of the sub_tile + return pin / max_inst_pins + sub_tile.capacity.low; + } + } } - return indices; + return OPEN; } /** diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 1d750a138d6..c959683bcf1 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -58,6 +58,7 @@ struct t_physical_tile_port; struct t_equivalent_site; struct t_physical_tile_type; typedef const t_physical_tile_type* t_physical_tile_type_ptr; +struct t_sub_tile; struct t_logical_block_type; typedef const t_logical_block_type* t_logical_block_type_ptr; struct t_logical_pin; @@ -442,7 +443,13 @@ struct t_class { enum e_pin_type type; PortEquivalence equivalence; int num_pins; - int* pinlist; /* [0..num_pins - 1] */ + std::vector pinlist; /* [0..num_pins - 1] */ +}; + +/* Struct to hold the class ranges for specific sub tiles */ +struct t_class_range { + int low = 0; + int high = 0; }; enum e_power_wire_type { @@ -573,30 +580,27 @@ constexpr int DEFAULT_SWITCH = -2; struct t_physical_tile_type { char* name = nullptr; int num_pins = 0; + int num_inst_pins = 0; int num_input_pins = 0; int num_output_pins = 0; int num_clock_pins = 0; + std::vector clock_pin_indices; + int capacity = 0; int width = 0; int height = 0; - bool**** pinloc = nullptr; /* [0..width-1][0..height-1][0..3][0..num_pins-1] */ - - enum e_pin_location_distr pin_location_distribution = E_SPREAD_PIN_DISTR; - int*** num_pin_loc_assignments = nullptr; /* [0..width-1][0..height-1][0..3] */ - char***** pin_loc_assignments = nullptr; /* [0..width-1][0..height-1][0..3][0..num_tokens-1][0..string_name] */ + vtr::NdMatrix, 3> pinloc; /* [0..width-1][0..height-1][0..3][0..num_pins-1] */ - int num_class = 0; - t_class* class_inf = nullptr; /* [0..num_class-1] */ + std::vector class_inf; /* [0..num_class-1] */ - std::vector ports; - std::vector pin_width_offset; //[0..num_pins-1] - std::vector pin_height_offset; //[0..num_pins-1] - int* pin_class = nullptr; /* [0..num_pins-1] */ - bool* is_ignored_pin = nullptr; /* [0..num_pins-1] */ - bool* is_pin_global = nullptr; /* [0..num_pins -1] */ + std::vector pin_width_offset; // [0..num_pins-1] + std::vector pin_height_offset; // [0..num_pins-1] + std::vector pin_class; // [0..num_pins-1] + std::vector is_ignored_pin; // [0..num_pins-1] + std::vector is_pin_global; // [0..num_pins-1] std::vector fc_specs; @@ -611,7 +615,7 @@ struct t_physical_tile_type { int index = -1; /* index of type descriptor in array (allows for index referencing) */ - std::vector equivalent_sites; + std::vector sub_tiles; /* Unordered map indexed by the logical block index. * tile_block_pin_directs_map[logical block index][logical block pin] -> physical tile pin */ @@ -620,6 +624,8 @@ struct t_physical_tile_type { /* Returns the indices of pins that contain a clock for this physical logic block */ std::vector get_clock_pins_indices() const; + int get_sub_tile_loc_from_pin(int pin_num) const; + // TODO: Remove is_input_type / is_output_type as part of // https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193 @@ -630,15 +636,65 @@ struct t_physical_tile_type { bool is_output_type; }; +/* Holds the capacity range of a certain sub_tile block within the parent physical tile type. + * E.g. TILE_X has the following sub tiles: + * - SUB_TILE_A: capacity_range --> 0 to 4 + * - SUB_TILE_B: capacity_range --> 5 to 11 + * - SUB_TILE_C: capacity_range --> 12 to 16 + * + * Totale TILE_X capacity is 17 + */ +struct t_capacity_range { + int low = 0; + int high = 0; + + void set(int low_cap, int high_cap) { + low = low_cap; + high = high_cap; + } + + bool is_in_range(int cap) const { + return cap >= low and cap <= high; + } + + int total() const { + return high - low + 1; + } +}; + +/** Describes the possible placeable blocks within a physical tile type. + * A sub tile adds flexibility in the tile composition description. + */ +struct t_sub_tile { + char* name = nullptr; + + // Mapping between the sub tile's pins and the physical pins corresponding + // to the physical tile type. + std::vector sub_tile_to_tile_pin_indices; + + std::vector ports; + + std::vector equivalent_sites; + + t_capacity_range capacity; + t_class_range class_range; + + int num_phy_pins = 0; + + int index = -1; +}; + /** A logical pin defines the pin index of a logical block type (i.e. a top level PB type) * This structure wraps the int value of the logical pin to allow its storage in the * vtr::bimap container. */ struct t_logical_pin { int pin = -1; + int sub_tile_index = -1; - t_logical_pin(int value) { + t_logical_pin(int index, int value) { pin = value; + sub_tile_index = index; } bool operator==(const t_logical_pin o) const { @@ -1493,7 +1549,7 @@ struct t_direct_inf { char* to_pin; int x_offset; int y_offset; - int z_offset; + int sub_tile_offset; int switch_type; e_side from_side; e_side to_side; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index ab39a9b1ac7..c6bd70aec07 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -72,18 +72,49 @@ struct t_fc_override { float fc_value; }; +struct t_pin_counts { + int input = 0; + int output = 0; + int clock = 0; + + int total() { + return input + output + clock; + } +}; + +struct t_pin_locs { + private: + // Distribution must be set once for each physical tile type + // and must be equal for each sub tile within a physical tile. + bool distribution_set = false; + + public: + enum e_pin_location_distr distribution = E_SPREAD_PIN_DISTR; + + /* [0..num_sub_tiles-1][0..width-1][0..height-1][0..3][0..num_tokens-1] */ + vtr::NdMatrix, 4> assignments; + + bool is_distribution_set() { + return distribution_set; + } + + void set_distribution() { + VTR_ASSERT(distribution_set == false); + distribution_set = true; + } +}; + /* This gives access to the architecture file name to * all architecture-parser functions */ static const char* arch_file_name = nullptr; /* Function prototypes */ /* Populate data */ -static void SetupPinLocationsAndPinClasses(pugi::xml_node Locations, - t_physical_tile_type* PhysicalTileType, - const pugiutil::loc_data& loc_data); +static void SetupPinClasses(t_physical_tile_type* PhysicalTileType); static void LoadPinLoc(pugi::xml_node Locations, t_physical_tile_type* type, + t_pin_locs* pin_locs, const pugiutil::loc_data& loc_data); template static std::pair ProcessPinString(pugi::xml_node Locations, @@ -91,7 +122,7 @@ static std::pair ProcessPinString(pugi::xml_node Locations, const char* pin_loc_string, const pugiutil::loc_data& loc_data); -/* Process XML hierarchy */ +/* Process XML hierarchy */ static void ProcessTiles(pugi::xml_node Node, std::vector& PhysicalTileTypes, std::vector& LogicalBlockTypes, @@ -105,25 +136,40 @@ static void MarkIoTypes(std::vector& PhysicalTileTypes); static void ProcessTileProps(pugi::xml_node Node, t_physical_tile_type* PhysicalTileType, const pugiutil::loc_data& loc_data); -static void ProcessTilePorts(pugi::xml_node Parent, - t_physical_tile_type* PhysicalTileType, - const pugiutil::loc_data& loc_data); +static t_pin_counts ProcessSubTilePorts(pugi::xml_node Parent, + t_sub_tile* SubTile, + std::unordered_map& tile_port_names, + const pugiutil::loc_data& loc_data); static void ProcessTilePort(pugi::xml_node Node, t_physical_tile_port* port, const pugiutil::loc_data& loc_data); static void ProcessTileEquivalentSites(pugi::xml_node Parent, + t_sub_tile* SubTile, t_physical_tile_type* PhysicalTileType, std::vector& LogicalBlockTypes, const pugiutil::loc_data& loc_data); static void ProcessEquivalentSiteDirectConnection(pugi::xml_node Parent, + t_sub_tile* SubTile, t_physical_tile_type* PhysicalTileType, t_logical_block_type* LogicalBlockType, const pugiutil::loc_data& loc_data); static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, + t_sub_tile* SubTile, t_physical_tile_type* PhysicalTileType, t_logical_block_type* LogicalBlockType, std::string site_name, const pugiutil::loc_data& loc_data); +static void ProcessPinLocations(pugi::xml_node Locations, + t_physical_tile_type* PhysicalTileType, + t_sub_tile* SubTile, + t_pin_locs* pin_locs, + const pugiutil::loc_data& loc_data); +static void ProcessSubTiles(pugi::xml_node Node, + t_physical_tile_type* PhysicalTileType, + std::vector& LogicalBlockTypes, + std::vector& segments, + const t_default_fc_spec& arch_def_fc, + const pugiutil::loc_data& loc_data); static void ProcessPb_Type(vtr::string_internment* strings, pugi::xml_node Parent, t_pb_type* pb_type, @@ -146,6 +192,8 @@ static t_metadata_dict ProcessMetadata(vtr::string_internment* strings, pugi::xm static void Process_Fc_Values(pugi::xml_node Node, t_default_fc_spec& spec, const pugiutil::loc_data& loc_data); static void Process_Fc(pugi::xml_node Node, t_physical_tile_type* PhysicalTileType, + t_sub_tile* SubTile, + t_pin_counts pin_counts, std::vector& segments, const t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data); @@ -228,10 +276,10 @@ static void link_physical_logical_types(std::vector& Physi static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block); -static const t_physical_tile_port* get_port_by_name(t_physical_tile_type_ptr type, const char* port_name); +static const t_physical_tile_port* get_port_by_name(t_sub_tile* sub_tile, const char* port_name); static const t_port* get_port_by_name(t_logical_block_type_ptr type, const char* port_name); -static const t_physical_tile_port* get_port_by_pin(t_physical_tile_type_ptr type, int pin); +static const t_physical_tile_port* get_port_by_pin(const t_sub_tile* sub_tile, int pin); static const t_port* get_port_by_pin(t_logical_block_type_ptr type, int pin); template @@ -417,285 +465,114 @@ void XmlReadArch(const char* ArchFile, * */ -/* Sets up the pinloc map and pin classes for the type. - * Pins and pin classes must already be setup by SetupPinClasses */ -static void SetupPinLocationsAndPinClasses(pugi::xml_node Locations, - t_physical_tile_type* PhysicalTileType, - const pugiutil::loc_data& loc_data) { - int i, k, Count; - int capacity, pin_count; +/* Sets up the pin classes for the type. */ +static void SetupPinClasses(t_physical_tile_type* PhysicalTileType) { + int i, k; + int pin_count; int num_class; - const char* Prop; pugi::xml_node Cur; - capacity = PhysicalTileType->capacity; - if (!Locations) { - PhysicalTileType->pin_location_distribution = E_SPREAD_PIN_DISTR; - } else { - expect_only_attributes(Locations, {"pattern"}, loc_data); - - Prop = get_attribute(Locations, "pattern", loc_data).value(); - if (strcmp(Prop, "spread") == 0) { - PhysicalTileType->pin_location_distribution = E_SPREAD_PIN_DISTR; - } else if (strcmp(Prop, "perimeter") == 0) { - PhysicalTileType->pin_location_distribution = E_PERIMETER_PIN_DISTR; - } else if (strcmp(Prop, "spread_inputs_perimeter_outputs") == 0) { - PhysicalTileType->pin_location_distribution = E_SPREAD_INPUTS_PERIMETER_OUTPUTS_PIN_DISTR; - } else if (strcmp(Prop, "custom") == 0) { - PhysicalTileType->pin_location_distribution = E_CUSTOM_PIN_DISTR; - } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), - "%s is an invalid pin location pattern.\n", Prop); - } - } - - /* Alloc and clear pin locations */ - PhysicalTileType->pinloc = (bool****)vtr::malloc(PhysicalTileType->width * sizeof(int***)); - for (int width = 0; width < PhysicalTileType->width; ++width) { - PhysicalTileType->pinloc[width] = (bool***)vtr::malloc(PhysicalTileType->height * sizeof(int**)); - for (int height = 0; height < PhysicalTileType->height; ++height) { - PhysicalTileType->pinloc[width][height] = (bool**)vtr::malloc(4 * sizeof(int*)); - for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) { - PhysicalTileType->pinloc[width][height][side] = (bool*)vtr::malloc(PhysicalTileType->num_pins * sizeof(int)); - for (int pin = 0; pin < PhysicalTileType->num_pins; ++pin) { - PhysicalTileType->pinloc[width][height][side][pin] = false; - } - } - } - } - - PhysicalTileType->pin_loc_assignments = (char*****)vtr::malloc(PhysicalTileType->width * sizeof(char****)); - PhysicalTileType->num_pin_loc_assignments = (int***)vtr::malloc(PhysicalTileType->width * sizeof(int**)); - for (int width = 0; width < PhysicalTileType->width; ++width) { - PhysicalTileType->pin_loc_assignments[width] = (char****)vtr::calloc(PhysicalTileType->height, sizeof(char***)); - PhysicalTileType->num_pin_loc_assignments[width] = (int**)vtr::calloc(PhysicalTileType->height, sizeof(int*)); - for (int height = 0; height < PhysicalTileType->height; ++height) { - PhysicalTileType->pin_loc_assignments[width][height] = (char***)vtr::calloc(4, sizeof(char**)); - PhysicalTileType->num_pin_loc_assignments[width][height] = (int*)vtr::calloc(4, sizeof(int)); - } + for (i = 0; i < PhysicalTileType->num_pins; i++) { + PhysicalTileType->pin_class.push_back(OPEN); + PhysicalTileType->is_ignored_pin.push_back(true); + PhysicalTileType->is_pin_global.push_back(true); } - /* Load the pin locations */ - if (PhysicalTileType->pin_location_distribution == E_CUSTOM_PIN_DISTR) { - expect_only_children(Locations, {"loc"}, loc_data); - Cur = Locations.first_child(); - std::set> seen_sides; - while (Cur) { - check_node(Cur, "loc", loc_data); - - expect_only_attributes(Cur, {"side", "xoffset", "yoffset"}, loc_data); - - /* Get offset (ie. height) */ - int x_offset = get_attribute(Cur, "xoffset", loc_data, ReqOpt::OPTIONAL).as_int(0); - int y_offset = get_attribute(Cur, "yoffset", loc_data, ReqOpt::OPTIONAL).as_int(0); - - /* Get side */ - e_side side = TOP; - Prop = get_attribute(Cur, "side", loc_data).value(); - if (0 == strcmp(Prop, "left")) { - side = LEFT; - } else if (0 == strcmp(Prop, "top")) { - side = TOP; - } else if (0 == strcmp(Prop, "right")) { - side = RIGHT; - } else if (0 == strcmp(Prop, "bottom")) { - side = BOTTOM; - } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), - "'%s' is not a valid side.\n", Prop); - } - - if ((x_offset < 0) || (x_offset >= PhysicalTileType->width)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), - "'%d' is an invalid horizontal offset for type '%s' (must be within [0, %d]).\n", - x_offset, PhysicalTileType->name, PhysicalTileType->width - 1); - } - if ((y_offset < 0) || (y_offset >= PhysicalTileType->height)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), - "'%d' is an invalid vertical offset for type '%s' (must be within [0, %d]).\n", - y_offset, PhysicalTileType->name, PhysicalTileType->height - 1); - } - - //Check for duplicate side specifications, since the code below silently overwrites if there are duplicates - auto side_offset = std::make_tuple(side, x_offset, y_offset); - if (seen_sides.count(side_offset)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), - "Duplicate pin location side/offset specification." - " Only a single per side/xoffset/yoffset is permitted.\n"); - } - seen_sides.insert(side_offset); - - /* Go through lists of pins */ - const std::vector Tokens = vtr::split(Cur.child_value()); - Count = Tokens.size(); - PhysicalTileType->num_pin_loc_assignments[x_offset][y_offset][side] = Count; - if (Count > 0) { - PhysicalTileType->pin_loc_assignments[x_offset][y_offset][side] = (char**)vtr::calloc(Count, sizeof(char*)); - for (int pin = 0; pin < Count; ++pin) { - /* Store location assignment */ - PhysicalTileType->pin_loc_assignments[x_offset][y_offset][side][pin] = vtr::strdup(Tokens[pin].c_str()); - - /* Advance through list of pins in this location */ - } - } - Cur = Cur.next_sibling(Cur.name()); - } - - //Verify that all top-level pins have had thier locations specified + pin_count = 0; - //Record all the specified pins - std::map> port_pins_with_specified_locations; - for (int w = 0; w < PhysicalTileType->width; ++w) { - for (int h = 0; h < PhysicalTileType->height; ++h) { - for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) { - for (int itoken = 0; itoken < PhysicalTileType->num_pin_loc_assignments[w][h][side]; ++itoken) { - const char* pin_spec = PhysicalTileType->pin_loc_assignments[w][h][side][itoken]; - InstPort inst_port(PhysicalTileType->pin_loc_assignments[w][h][side][itoken]); + t_class_range class_range; - //A pin specification should contain only the block name, and not any instace count information - if (inst_port.instance_low_index() != InstPort::UNSPECIFIED || inst_port.instance_high_index() != InstPort::UNSPECIFIED) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), - "Pin location specification '%s' should not contain an instance range (should only be the block name)", - pin_spec); - } + /* Equivalent pins share the same class, non-equivalent pins belong to different pin classes */ + for (auto& sub_tile : PhysicalTileType->sub_tiles) { + int capacity = sub_tile.capacity.total(); + class_range.low = PhysicalTileType->class_inf.size(); + class_range.high = class_range.low - 1; + for (i = 0; i < capacity; ++i) { + for (const auto& port : sub_tile.ports) { + if (port.equivalent != PortEquivalence::NONE) { + t_class class_inf; + num_class = (int)PhysicalTileType->class_inf.size(); + class_inf.num_pins = port.num_pins; + class_inf.equivalence = port.equivalent; + + if (port.type == IN_PORT) { + class_inf.type = RECEIVER; + } else { + VTR_ASSERT(port.type == OUT_PORT); + class_inf.type = DRIVER; + } - //Check that the block name matches - if (inst_port.instance_name() != PhysicalTileType->name) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), - "Mismatched block name in pin location specification (expected '%s' was '%s')", - PhysicalTileType->name, inst_port.instance_name().c_str()); + for (k = 0; k < port.num_pins; ++k) { + class_inf.pinlist.push_back(pin_count); + PhysicalTileType->pin_class[pin_count] = num_class; + // clock pins and other specified global ports are initially specified + // as ignored pins (i.e. connections are not created in the rr_graph and + // nets connected to the port are ignored as well). + PhysicalTileType->is_ignored_pin[pin_count] = port.is_clock || port.is_non_clock_global; + // clock pins and other specified global ports are flaged as global + PhysicalTileType->is_pin_global[pin_count] = port.is_clock || port.is_non_clock_global; + + if (port.is_clock) { + PhysicalTileType->clock_pin_indices.push_back(pin_count); } - int pin_low_idx = inst_port.port_low_index(); - int pin_high_idx = inst_port.port_high_index(); + pin_count++; + } - if (pin_low_idx == InstPort::UNSPECIFIED && pin_high_idx == InstPort::UNSPECIFIED) { - //Empty range, so full port + PhysicalTileType->class_inf.push_back(class_inf); + class_range.high++; + } else if (port.equivalent == PortEquivalence::NONE) { + for (k = 0; k < port.num_pins; ++k) { + t_class class_inf; + num_class = (int)PhysicalTileType->class_inf.size(); + class_inf.num_pins = 1; + class_inf.pinlist.push_back(pin_count); + class_inf.equivalence = port.equivalent; + + if (port.type == IN_PORT) { + class_inf.type = RECEIVER; + } else { + VTR_ASSERT(port.type == OUT_PORT); + class_inf.type = DRIVER; + } - //Find the matching pb type to get the total number of pins - const t_physical_tile_port* port = nullptr; - for (const auto& tmp_port : PhysicalTileType->ports) { - if (tmp_port.name == inst_port.port_name()) { - port = &tmp_port; - break; - } - } + PhysicalTileType->pin_class[pin_count] = num_class; + // clock pins and other specified global ports are initially specified + // as ignored pins (i.e. connections are not created in the rr_graph and + // nets connected to the port are ignored as well). + PhysicalTileType->is_ignored_pin[pin_count] = port.is_clock || port.is_non_clock_global; + // clock pins and other specified global ports are flaged as global + PhysicalTileType->is_pin_global[pin_count] = port.is_clock || port.is_non_clock_global; - if (port) { - pin_low_idx = 0; - pin_high_idx = port->num_pins - 1; - } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), - "Failed to find port named '%s' on block '%s'", - inst_port.port_name().c_str(), PhysicalTileType->name); - } + if (port.is_clock) { + PhysicalTileType->clock_pin_indices.push_back(pin_count); } - VTR_ASSERT(pin_low_idx >= 0); - VTR_ASSERT(pin_high_idx >= 0); - for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) { - //Record that the pin has it's location specified - port_pins_with_specified_locations[inst_port.port_name()].insert(ipin); - } + pin_count++; + + PhysicalTileType->class_inf.push_back(class_inf); + class_range.high++; } } } } - //Check for any pins missing location specs - for (const auto& port : PhysicalTileType->ports) { - for (int ipin = 0; ipin < port.num_pins; ++ipin) { - if (!port_pins_with_specified_locations[port.name].count(ipin)) { - //Missing - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), - "Pin '%s.%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")", - PhysicalTileType->name, port.name, ipin); - } - } - } - } else if (Locations) { - //Non-custom pin locations. There should be no child tags - expect_child_node_count(Locations, 0, loc_data); + PhysicalTileType->sub_tiles[sub_tile.index].class_range = class_range; } - /* Setup pin classes */ - num_class = 0; - for (const auto& port : PhysicalTileType->ports) { - if (port.equivalent != PortEquivalence::NONE) { - num_class += capacity; - } else { - num_class += capacity * port.num_pins; - } - } - PhysicalTileType->class_inf = (t_class*)vtr::calloc(num_class, sizeof(t_class)); - PhysicalTileType->num_class = num_class; - PhysicalTileType->pin_class = (int*)vtr::malloc(PhysicalTileType->num_pins * sizeof(int) * capacity); - PhysicalTileType->is_ignored_pin = (bool*)vtr::malloc(PhysicalTileType->num_pins * sizeof(bool) * capacity); - PhysicalTileType->is_pin_global = (bool*)vtr::malloc(PhysicalTileType->num_pins * sizeof(bool) * capacity); - for (i = 0; i < PhysicalTileType->num_pins * capacity; i++) { - PhysicalTileType->pin_class[i] = OPEN; - PhysicalTileType->is_ignored_pin[i] = true; - PhysicalTileType->is_pin_global[i] = true; - } - - pin_count = 0; - - /* Equivalent pins share the same class, non-equivalent pins belong to different pin classes */ - num_class = 0; - for (i = 0; i < capacity; ++i) { - for (const auto& port : PhysicalTileType->ports) { - if (port.equivalent != PortEquivalence::NONE) { - PhysicalTileType->class_inf[num_class].num_pins = port.num_pins; - PhysicalTileType->class_inf[num_class].pinlist = (int*)vtr::malloc(sizeof(int) * port.num_pins); - PhysicalTileType->class_inf[num_class].equivalence = port.equivalent; - } - - for (k = 0; k < port.num_pins; ++k) { - if (port.equivalent == PortEquivalence::NONE) { - PhysicalTileType->class_inf[num_class].num_pins = 1; - PhysicalTileType->class_inf[num_class].pinlist = (int*)vtr::malloc(sizeof(int) * 1); - PhysicalTileType->class_inf[num_class].pinlist[0] = pin_count; - } else { - PhysicalTileType->class_inf[num_class].pinlist[k] = pin_count; - } - - if (port.type == IN_PORT) { - PhysicalTileType->class_inf[num_class].type = RECEIVER; - } else { - VTR_ASSERT(port.type == OUT_PORT); - PhysicalTileType->class_inf[num_class].type = DRIVER; - } - PhysicalTileType->pin_class[pin_count] = num_class; - // clock pins and other specified global ports are initially specified - // as ignored pins (i.e. connections are not created in the rr_graph and - // nets connected to the port are ignored as well). - PhysicalTileType->is_ignored_pin[pin_count] = port.is_clock || port.is_non_clock_global; - // clock pins and other specified global ports are flaged as global - PhysicalTileType->is_pin_global[pin_count] = port.is_clock || port.is_non_clock_global; - pin_count++; - - if (port.equivalent == PortEquivalence::NONE) { - num_class++; - } - } - if (port.equivalent != PortEquivalence::NONE) { - num_class++; - } - } - } - VTR_ASSERT(num_class == PhysicalTileType->num_class); VTR_ASSERT(pin_count == PhysicalTileType->num_pins); } static void LoadPinLoc(pugi::xml_node Locations, t_physical_tile_type* type, + t_pin_locs* pin_locs, const pugiutil::loc_data& loc_data) { type->pin_width_offset.resize(type->num_pins, 0); type->pin_height_offset.resize(type->num_pins, 0); std::vector physical_pin_counts(type->num_pins, 0); - if (type->pin_location_distribution == E_SPREAD_PIN_DISTR) { + if (pin_locs->distribution == E_SPREAD_PIN_DISTR) { /* evenly distribute pins starting at bottom left corner */ int num_sides = 4 * (type->width * type->height); @@ -720,7 +597,7 @@ static void LoadPinLoc(pugi::xml_node Locations, } VTR_ASSERT(side_index == num_sides); VTR_ASSERT(count == type->num_pins); - } else if (type->pin_location_distribution == E_PERIMETER_PIN_DISTR) { + } else if (pin_locs->distribution == E_PERIMETER_PIN_DISTR) { //Add one pin at-a-time to perimeter sides in round-robin order int ipin = 0; while (ipin < type->num_pins) { @@ -746,7 +623,7 @@ static void LoadPinLoc(pugi::xml_node Locations, } VTR_ASSERT(ipin == type->num_pins); - } else if (type->pin_location_distribution == E_SPREAD_INPUTS_PERIMETER_OUTPUTS_PIN_DISTR) { + } else if (pin_locs->distribution == E_SPREAD_INPUTS_PERIMETER_OUTPUTS_PIN_DISTR) { //Collect the sets of block input/output pins std::vector input_pins; std::vector output_pins; @@ -813,23 +690,30 @@ static void LoadPinLoc(pugi::xml_node Locations, VTR_ASSERT(ipin == output_pins.size()); } else { - VTR_ASSERT(type->pin_location_distribution == E_CUSTOM_PIN_DISTR); - for (int width = 0; width < type->width; ++width) { - for (int height = 0; height < type->height; ++height) { - for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) { - for (int pin = 0; pin < type->num_pin_loc_assignments[width][height][side]; ++pin) { - auto pin_range = ProcessPinString(Locations, - type, - type->pin_loc_assignments[width][height][side][pin], - loc_data); - - for (int pin_num = pin_range.first; pin_num < pin_range.second; ++pin_num) { - VTR_ASSERT(pin_num < type->num_pins / type->capacity); - for (int capacity = 0; capacity < type->capacity; ++capacity) { - type->pinloc[width][height][side][pin_num + capacity * type->num_pins / type->capacity] = true; - type->pin_width_offset[pin_num + capacity * type->num_pins / type->capacity] += width; - type->pin_height_offset[pin_num + capacity * type->num_pins / type->capacity] += height; - physical_pin_counts[pin_num + capacity * type->num_pins / type->capacity] += 1; + VTR_ASSERT(pin_locs->distribution == E_CUSTOM_PIN_DISTR); + for (auto& sub_tile : type->sub_tiles) { + int sub_tile_index = sub_tile.index; + int sub_tile_capacity = sub_tile.capacity.total(); + + for (int width = 0; width < type->width; ++width) { + for (int height = 0; height < type->height; ++height) { + for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) { + for (auto token : pin_locs->assignments[sub_tile_index][width][height][side]) { + auto pin_range = ProcessPinString(Locations, + &sub_tile, + token.c_str(), + loc_data); + + for (int pin_num = pin_range.first; pin_num < pin_range.second; ++pin_num) { + VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); + for (int capacity = 0; capacity < sub_tile_capacity; ++capacity) { + int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; + int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; + type->pinloc[width][height][side][physical_pin_index] = true; + type->pin_width_offset[physical_pin_index] += width; + type->pin_height_offset[physical_pin_index] += height; + physical_pin_counts[physical_pin_index] += 1; + } } } } @@ -2043,6 +1927,8 @@ static void Process_Fc_Values(pugi::xml_node Node, t_default_fc_spec& spec, cons * the appropriate fields of type. */ static void Process_Fc(pugi::xml_node Node, t_physical_tile_type* PhysicalTileType, + t_sub_tile* SubTile, + t_pin_counts pin_counts, std::vector& segments, const t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data) { @@ -2060,21 +1946,20 @@ static void Process_Fc(pugi::xml_node Node, /* Use the default value, if available */ if (!arch_def_fc.specified) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), - " is missing child , and no specified in architecture\n"); + " is missing child , and no specified in architecture\n"); } def_fc_spec = arch_def_fc; } /* Go through all the port/segment combinations and create the (potentially * overriden) pin/seg Fc specifications */ - int pins_per_capacity_instance = PhysicalTileType->num_pins / PhysicalTileType->capacity; for (size_t iseg = 0; iseg < segments.size(); ++iseg) { - for (int icapacity = 0; icapacity < PhysicalTileType->capacity; ++icapacity) { + for (int icapacity = 0; icapacity < SubTile->capacity.total(); ++icapacity) { //If capacity > 0, we need t offset the block index by the number of pins per instance //this ensures that all pins have an Fc specification - int iblk_pin = icapacity * pins_per_capacity_instance; + int iblk_pin = icapacity * pin_counts.total(); - for (const auto& port : PhysicalTileType->ports) { + for (const auto& port : SubTile->ports) { t_fc_specification fc_spec; fc_spec.seg_index = iseg; @@ -2137,7 +2022,8 @@ static void Process_Fc(pugi::xml_node Node, for (int iport_pin = 0; iport_pin < port.num_pins; ++iport_pin) { //XXX: this assumes that iterating through the tile ports // in order yields the block pin order - fc_spec.pins.push_back(iblk_pin); + int true_physical_blk_pin = SubTile->sub_tile_to_tile_pin_indices[iblk_pin]; + fc_spec.pins.push_back(true_physical_blk_pin); ++iblk_pin; } @@ -3002,23 +2888,6 @@ static void ProcessTiles(pugi::xml_node Node, "Duplicate tile descriptor name: '%s'.\n", PhysicalTileType.name); } - /* Process tile port definitions */ - ProcessTilePorts(CurTileType, &PhysicalTileType, loc_data); - - PhysicalTileType.num_pins = PhysicalTileType.capacity - * (PhysicalTileType.num_input_pins - + PhysicalTileType.num_output_pins - + PhysicalTileType.num_clock_pins); - PhysicalTileType.num_receivers = PhysicalTileType.capacity * PhysicalTileType.num_input_pins; - PhysicalTileType.num_drivers = PhysicalTileType.capacity * PhysicalTileType.num_output_pins; - - /* Assign Fc, Pin locations ans Switch Block locations to the Physical Tile Type */ - - /* Load pin names and classes and locations */ - Cur = get_single_child(CurTileType, "pinlocations", loc_data, ReqOpt::OPTIONAL); - SetupPinLocationsAndPinClasses(Cur, &PhysicalTileType, loc_data); - LoadPinLoc(Cur, &PhysicalTileType, loc_data); - //Warn that gridlocations is no longer supported //TODO: eventually remove try { @@ -3030,17 +2899,11 @@ static void ProcessTiles(pugi::xml_node Node, archfpga_throw(e.filename().c_str(), e.line(), msg.c_str()); } - /* Load Fc */ - Cur = get_single_child(CurTileType, "fc", loc_data, ReqOpt::OPTIONAL); - Process_Fc(Cur, &PhysicalTileType, arch.Segments, arch_def_fc, loc_data); - //Load switchblock type and location overrides Cur = get_single_child(CurTileType, "switchblock_locations", loc_data, ReqOpt::OPTIONAL); ProcessSwitchblockLocations(Cur, &PhysicalTileType, arch, loc_data); - //Load equivalent sites infromation - Cur = get_single_child(CurTileType, "equivalent_sites", loc_data, ReqOpt::REQUIRED); - ProcessTileEquivalentSites(Cur, &PhysicalTileType, LogicalBlockTypes, loc_data); + ProcessSubTiles(CurTileType, &PhysicalTileType, LogicalBlockTypes, arch.Segments, arch_def_fc, loc_data); /* Type fully read */ ++index; @@ -3059,14 +2922,16 @@ static void MarkIoTypes(std::vector& PhysicalTileTypes) { type.is_input_type = false; type.is_output_type = false; - for (const auto& equivalent_site : type.equivalent_sites) { + auto equivalent_sites = get_equivalent_sites_set(&type); + + for (const auto& equivalent_site : equivalent_sites) { if (block_type_contains_blif_model(equivalent_site, MODEL_INPUT)) { type.is_input_type = true; break; } } - for (const auto& equivalent_site : type.equivalent_sites) { + for (const auto& equivalent_site : equivalent_sites) { if (block_type_contains_blif_model(equivalent_site, MODEL_OUTPUT)) { type.is_output_type = true; break; @@ -3078,14 +2943,13 @@ static void MarkIoTypes(std::vector& PhysicalTileTypes) { static void ProcessTileProps(pugi::xml_node Node, t_physical_tile_type* PhysicalTileType, const pugiutil::loc_data& loc_data) { - expect_only_attributes(Node, {"name", "capacity", "width", "height", "area"}, loc_data); + expect_only_attributes(Node, {"name", "width", "height", "area"}, loc_data); /* Load type name */ auto Prop = get_attribute(Node, "name", loc_data).value(); PhysicalTileType->name = vtr::strdup(Prop); /* Load properties */ - PhysicalTileType->capacity = get_attribute(Node, "capacity", loc_data, ReqOpt::OPTIONAL).as_uint(1); PhysicalTileType->width = get_attribute(Node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1); PhysicalTileType->height = get_attribute(Node, "height", loc_data, ReqOpt::OPTIONAL).as_uint(1); PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED); @@ -3096,12 +2960,13 @@ static void ProcessTileProps(pugi::xml_node Node, } } -static void ProcessTilePorts(pugi::xml_node Parent, - t_physical_tile_type* PhysicalTileType, - const pugiutil::loc_data& loc_data) { +static t_pin_counts ProcessSubTilePorts(pugi::xml_node Parent, + t_sub_tile* SubTile, + std::unordered_map& tile_port_names, + const pugiutil::loc_data& loc_data) { pugi::xml_node Cur; - std::map tile_port_names; + std::map sub_tile_port_names; int num_ports, num_in_ports, num_out_ports, num_clock_ports; @@ -3111,62 +2976,70 @@ static void ProcessTilePorts(pugi::xml_node Parent, num_clock_ports = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); num_ports = num_in_ports + num_out_ports + num_clock_ports; - int iport = 0; - int k; + int port_index_by_type; + int port_index = 0; int absolute_first_pin_index = 0; - for (int itype = 0; itype < 3; itype++) { - if (itype == 0) { - k = 0; - Cur = get_first_child(Parent, "input", loc_data, ReqOpt::OPTIONAL); - } else if (itype == 1) { - k = 0; - Cur = get_first_child(Parent, "output", loc_data, ReqOpt::OPTIONAL); - } else { - k = 0; - Cur = get_first_child(Parent, "clock", loc_data, ReqOpt::OPTIONAL); - } + std::vector port_types = {"input", "output", "clock"}; + for (auto port_type : port_types) { + port_index_by_type = 0; + Cur = get_first_child(Parent, port_type, loc_data, ReqOpt::OPTIONAL); while (Cur) { t_physical_tile_port port; - port.index = iport; + port.index = port_index; port.absolute_first_pin_index = absolute_first_pin_index; - port.port_index_by_type = k; + port.port_index_by_type = port_index_by_type; ProcessTilePort(Cur, &port, loc_data); - absolute_first_pin_index += port.num_pins; - //Check port name duplicates - auto result = tile_port_names.insert(std::pair(port.name, 0)); - if (!result.second) { + auto sub_tile_port_result = sub_tile_port_names.insert(std::pair(port.name, 0)); + if (!sub_tile_port_result.second) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), "Duplicate port names in tile '%s': port '%s'\n", - PhysicalTileType->name, port.name); + SubTile->name, port.name); + } + + //Check port name duplicates + auto tile_port_result = tile_port_names.insert(std::pair(port.name, port)); + if (!tile_port_result.second) { + if (tile_port_result.first->second.num_pins != port.num_pins || tile_port_result.first->second.equivalent != port.equivalent) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + "Another port found with the same name in other sub tiles " + "that did not match the current port settings. '%s': port '%s'\n", + SubTile->name, port.name); + } } //Push port - PhysicalTileType->ports.push_back(port); + SubTile->ports.push_back(port); /* get next iteration */ - iport++; - k++; + port_index++; + port_index_by_type++; + absolute_first_pin_index += port.num_pins; + Cur = Cur.next_sibling(Cur.name()); } } - VTR_ASSERT(iport == num_ports); + VTR_ASSERT(port_index == num_ports); + + t_pin_counts pin_counts; /* Count stats on the number of each type of pin */ - for (const auto& port : PhysicalTileType->ports) { + for (const auto& port : SubTile->ports) { if (port.type == IN_PORT && port.is_clock == false) { - PhysicalTileType->num_input_pins += port.num_pins; + pin_counts.input += port.num_pins; } else if (port.type == OUT_PORT) { - PhysicalTileType->num_output_pins += port.num_pins; + pin_counts.output += port.num_pins; } else { VTR_ASSERT(port.is_clock && port.type == IN_PORT); - PhysicalTileType->num_clock_pins += port.num_pins; + pin_counts.clock += port.num_pins; } } + + return pin_counts; } static void ProcessTilePort(pugi::xml_node Node, @@ -3237,6 +3110,7 @@ static void ProcessTilePort(pugi::xml_node Node, } static void ProcessTileEquivalentSites(pugi::xml_node Parent, + t_sub_tile* SubTile, t_physical_tile_type* PhysicalTileType, std::vector& LogicalBlockTypes, const pugiutil::loc_data& loc_data) { @@ -3246,7 +3120,7 @@ static void ProcessTileEquivalentSites(pugi::xml_node Parent, if (count_children(Parent, "site", loc_data) < 1) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), - "There are no sites corresponding to this tile: %s.\n", PhysicalTileType->name); + "There are no sites corresponding to this tile: %s.\n", SubTile->name); } CurSite = Parent.first_child(); @@ -3263,13 +3137,13 @@ static void ProcessTileEquivalentSites(pugi::xml_node Parent, if (0 == strcmp(pin_mapping, "custom")) { // Pin mapping between Tile and Pb Type is user-defined - ProcessEquivalentSiteCustomConnection(CurSite, PhysicalTileType, LogicalBlockType, Prop, loc_data); + ProcessEquivalentSiteCustomConnection(CurSite, SubTile, PhysicalTileType, LogicalBlockType, Prop, loc_data); } else if (0 == strcmp(pin_mapping, "direct")) { - ProcessEquivalentSiteDirectConnection(CurSite, PhysicalTileType, LogicalBlockType, loc_data); + ProcessEquivalentSiteDirectConnection(CurSite, SubTile, PhysicalTileType, LogicalBlockType, loc_data); } if (0 == strcmp(LogicalBlockType->pb_type->name, Prop.c_str())) { - PhysicalTileType->equivalent_sites.push_back(LogicalBlockType); + SubTile->equivalent_sites.push_back(LogicalBlockType); check_port_direct_mappings(PhysicalTileType, LogicalBlockType); } @@ -3279,21 +3153,22 @@ static void ProcessTileEquivalentSites(pugi::xml_node Parent, } static void ProcessEquivalentSiteDirectConnection(pugi::xml_node Parent, + t_sub_tile* SubTile, t_physical_tile_type* PhysicalTileType, t_logical_block_type* LogicalBlockType, const pugiutil::loc_data& loc_data) { - int num_pins = PhysicalTileType->num_pins / PhysicalTileType->capacity; + int num_pins = (int)SubTile->sub_tile_to_tile_pin_indices.size() / SubTile->capacity.total(); if (num_pins != LogicalBlockType->pb_type->num_pins) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), - "Pin definition differ between site %s and tile %s. User-defined pin mapping is required.\n", LogicalBlockType->pb_type->name, PhysicalTileType->name); + "Pin definition differ between site %s and tile %s. User-defined pin mapping is required.\n", LogicalBlockType->pb_type->name, SubTile->name); } vtr::bimap directs_map; for (int npin = 0; npin < num_pins; npin++) { t_physical_pin physical_pin(npin); - t_logical_pin logical_pin(npin); + t_logical_pin logical_pin(SubTile->index, npin); directs_map.insert(logical_pin, physical_pin); } @@ -3302,6 +3177,7 @@ static void ProcessEquivalentSiteDirectConnection(pugi::xml_node Parent, } static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, + t_sub_tile* SubTile, t_physical_tile_type* PhysicalTileType, t_logical_block_type* LogicalBlockType, std::string site_name, @@ -3312,7 +3188,7 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, if (count_children(Parent, "direct", loc_data) < 1) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), - "There are no direct pin mappings between site %s and tile %s.\n", site_name.c_str(), PhysicalTileType->name); + "There are no direct pin mappings between site %s and tile %s.\n", site_name.c_str(), SubTile->name); } vtr::bimap directs_map; @@ -3330,7 +3206,7 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, // `to` attribute is relative to the logical block pins to = std::string(get_attribute(CurDirect, "to", loc_data).value()); - auto from_pins = ProcessPinString(CurDirect, PhysicalTileType, from.c_str(), loc_data); + auto from_pins = ProcessPinString(CurDirect, SubTile, from.c_str(), loc_data); auto to_pins = ProcessPinString(CurDirect, LogicalBlockType, to.c_str(), loc_data); // Checking that the number of pins is exactly the same @@ -3338,20 +3214,20 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), "The number of pins specified in the direct pin mapping is " "not equivalent for Physical Tile %s and Logical Block %s.\n", - PhysicalTileType->name, LogicalBlockType->name); + SubTile->name, LogicalBlockType->name); } int num_pins = from_pins.second - from_pins.first; for (int i = 0; i < num_pins; i++) { t_physical_pin physical_pin(from_pins.first + i); - t_logical_pin logical_pin(to_pins.first + i); + t_logical_pin logical_pin(SubTile->index, to_pins.first + i); auto result = directs_map.insert(logical_pin, physical_pin); if (!result.second) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), "Duplicate logical pin (%d) to physical pin (%d) mappings found for " "Physical Tile %s and Logical Block %s.\n", - logical_pin.pin, physical_pin.pin, PhysicalTileType->name, LogicalBlockType->name); + logical_pin.pin, physical_pin.pin, SubTile->name, LogicalBlockType->name); } } @@ -3361,6 +3237,295 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, PhysicalTileType->tile_block_pin_directs_map[LogicalBlockType->index] = directs_map; } +static void ProcessPinLocations(pugi::xml_node Locations, + t_physical_tile_type* PhysicalTileType, + t_sub_tile* SubTile, + t_pin_locs* pin_locs, + const pugiutil::loc_data& loc_data) { + pugi::xml_node Cur; + const char* Prop; + enum e_pin_location_distr distribution; + + if (Locations) { + expect_only_attributes(Locations, {"pattern"}, loc_data); + + Prop = get_attribute(Locations, "pattern", loc_data).value(); + if (strcmp(Prop, "spread") == 0) { + distribution = E_SPREAD_PIN_DISTR; + } else if (strcmp(Prop, "perimeter") == 0) { + distribution = E_PERIMETER_PIN_DISTR; + } else if (strcmp(Prop, "spread_inputs_perimeter_outputs") == 0) { + distribution = E_SPREAD_INPUTS_PERIMETER_OUTPUTS_PIN_DISTR; + } else if (strcmp(Prop, "custom") == 0) { + distribution = E_CUSTOM_PIN_DISTR; + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "%s is an invalid pin location pattern.\n", Prop); + } + } else { + distribution = E_SPREAD_PIN_DISTR; + Prop = "spread"; + } + + if (pin_locs->is_distribution_set()) { + if (pin_locs->distribution != distribution) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Sub Tile %s has a different pin location pattern (%s) with respect " + "to the sibling sub tiles", + SubTile->name, Prop); + } + } else { + pin_locs->distribution = distribution; + pin_locs->set_distribution(); + } + + int sub_tile_index = SubTile->index; + + /* Load the pin locations */ + if (distribution == E_CUSTOM_PIN_DISTR) { + expect_only_children(Locations, {"loc"}, loc_data); + Cur = Locations.first_child(); + std::set> seen_sides; + while (Cur) { + check_node(Cur, "loc", loc_data); + + expect_only_attributes(Cur, {"side", "xoffset", "yoffset"}, loc_data); + + /* Get offset (ie. height) */ + int x_offset = get_attribute(Cur, "xoffset", loc_data, ReqOpt::OPTIONAL).as_int(0); + int y_offset = get_attribute(Cur, "yoffset", loc_data, ReqOpt::OPTIONAL).as_int(0); + + /* Get side */ + e_side side = TOP; + Prop = get_attribute(Cur, "side", loc_data).value(); + if (0 == strcmp(Prop, "left")) { + side = LEFT; + } else if (0 == strcmp(Prop, "top")) { + side = TOP; + } else if (0 == strcmp(Prop, "right")) { + side = RIGHT; + } else if (0 == strcmp(Prop, "bottom")) { + side = BOTTOM; + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + "'%s' is not a valid side.\n", Prop); + } + + if ((x_offset < 0) || (x_offset >= PhysicalTileType->width)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + "'%d' is an invalid horizontal offset for type '%s' (must be within [0, %d]).\n", + x_offset, PhysicalTileType->name, PhysicalTileType->width - 1); + } + if ((y_offset < 0) || (y_offset >= PhysicalTileType->height)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + "'%d' is an invalid vertical offset for type '%s' (must be within [0, %d]).\n", + y_offset, PhysicalTileType->name, PhysicalTileType->height - 1); + } + + //Check for duplicate side specifications, since the code below silently overwrites if there are duplicates + auto side_offset = std::make_tuple(side, x_offset, y_offset); + if (seen_sides.count(side_offset)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + "Duplicate pin location side/offset specification." + " Only a single per side/xoffset/yoffset is permitted.\n"); + } + seen_sides.insert(side_offset); + + /* Go through lists of pins */ + const std::vector Tokens = vtr::split(Cur.child_value()); + int Count = (int)Tokens.size(); + if (Count > 0) { + for (int pin = 0; pin < Count; ++pin) { + /* Store location assignment */ + pin_locs->assignments[sub_tile_index][x_offset][y_offset][side].push_back(std::string(Tokens[pin].c_str())); + + /* Advance through list of pins in this location */ + } + } + Cur = Cur.next_sibling(Cur.name()); + } + + //Verify that all top-level pins have had their locations specified + + //Record all the specified pins + std::map> port_pins_with_specified_locations; + for (int w = 0; w < PhysicalTileType->width; ++w) { + for (int h = 0; h < PhysicalTileType->height; ++h) { + for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) { + for (auto token : pin_locs->assignments[sub_tile_index][w][h][side]) { + InstPort inst_port(token.c_str()); + + //A pin specification should contain only the block name, and not any instace count information + if (inst_port.instance_low_index() != InstPort::UNSPECIFIED || inst_port.instance_high_index() != InstPort::UNSPECIFIED) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Pin location specification '%s' should not contain an instance range (should only be the block name)", + token.c_str()); + } + + //Check that the block name matches + if (inst_port.instance_name() != SubTile->name) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Mismatched sub tile name in pin location specification (expected '%s' was '%s')", + SubTile->name, inst_port.instance_name().c_str()); + } + + int pin_low_idx = inst_port.port_low_index(); + int pin_high_idx = inst_port.port_high_index(); + + if (pin_low_idx == InstPort::UNSPECIFIED && pin_high_idx == InstPort::UNSPECIFIED) { + //Empty range, so full port + + //Find the matching pb type to get the total number of pins + const t_physical_tile_port* port = nullptr; + for (const auto& tmp_port : SubTile->ports) { + if (tmp_port.name == inst_port.port_name()) { + port = &tmp_port; + break; + } + } + + if (port) { + pin_low_idx = 0; + pin_high_idx = port->num_pins - 1; + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Failed to find port named '%s' on block '%s'", + inst_port.port_name().c_str(), SubTile->name); + } + } + VTR_ASSERT(pin_low_idx >= 0); + VTR_ASSERT(pin_high_idx >= 0); + + for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) { + //Record that the pin has it's location specified + port_pins_with_specified_locations[inst_port.port_name()].insert(ipin); + } + } + } + } + } + + //Check for any pins missing location specs + for (const auto& port : SubTile->ports) { + for (int ipin = 0; ipin < port.num_pins; ++ipin) { + if (!port_pins_with_specified_locations[port.name].count(ipin)) { + //Missing + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Pin '%s.%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")", + SubTile->name, port.name, ipin); + } + } + } + } else if (Locations) { + //Non-custom pin locations. There should be no child tags + expect_child_node_count(Locations, 0, loc_data); + } +} + +static void ProcessSubTiles(pugi::xml_node Node, + t_physical_tile_type* PhysicalTileType, + std::vector& LogicalBlockTypes, + std::vector& segments, + const t_default_fc_spec& arch_def_fc, + const pugiutil::loc_data& loc_data) { + pugi::xml_node CurSubTile; + pugi::xml_node Cur; + int index = 0; + + unsigned long int num_sub_tiles = count_children(Node, "sub_tile", loc_data); + unsigned long int width = PhysicalTileType->width; + unsigned long int height = PhysicalTileType->height; + unsigned long int num_sides = 4; + + std::map sub_tile_names; + + t_pin_locs pin_locs; + pin_locs.assignments.resize({num_sub_tiles, width, height, num_sides}); + + if (num_sub_tiles == 0) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "No sub tile found for the Physical Tile %s.\n" + "At least one sub tile is needed to correctly describe the Physical Tile.\n", + PhysicalTileType->name); + } + + CurSubTile = get_first_child(Node, "sub_tile", loc_data); + + while (CurSubTile) { + t_sub_tile SubTile; + + SubTile.index = index; + + expect_only_attributes(CurSubTile, {"name", "capacity"}, loc_data); + + /* Load type name */ + auto name = vtr::strdup(get_attribute(CurSubTile, "name", loc_data).value()); + + //Check Sub Tile name duplicates + auto result = sub_tile_names.insert(std::pair(std::string(name), 0)); + if (!result.second) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + "Duplicate Sub Tile names in tile '%s': Sub Tile'%s'\n", + PhysicalTileType->name, name); + } + + SubTile.name = name; + + /* Load properties */ + int capacity = get_attribute(CurSubTile, "capacity", loc_data, ReqOpt::OPTIONAL).as_int(1); + SubTile.capacity.set(PhysicalTileType->capacity, PhysicalTileType->capacity + capacity - 1); + PhysicalTileType->capacity += capacity; + + /* Process sub tile port definitions */ + std::unordered_map tile_port_names; + auto pin_counts = ProcessSubTilePorts(CurSubTile, &SubTile, tile_port_names, loc_data); + + /* Map Sub Tile physical pins with the Physical Tile Type physical pins. + * This takes into account the capacity of each sub tiles to add the correct offset. + */ + for (int ipin = 0; ipin < capacity * pin_counts.total(); ipin++) { + SubTile.sub_tile_to_tile_pin_indices.push_back(PhysicalTileType->num_pins + ipin); + } + + SubTile.num_phy_pins = pin_counts.total() * capacity; + + /* Assign pin counts to the Physical Tile Type */ + PhysicalTileType->num_input_pins += pin_counts.input; + PhysicalTileType->num_output_pins += pin_counts.output; + PhysicalTileType->num_clock_pins += pin_counts.clock; + PhysicalTileType->num_pins += capacity * pin_counts.total(); + PhysicalTileType->num_inst_pins += pin_counts.total(); + + /* Assign drivers and receivers count to Physical Tile Type */ + PhysicalTileType->num_receivers += capacity * pin_counts.input; + PhysicalTileType->num_drivers += capacity * pin_counts.output; + + Cur = get_single_child(CurSubTile, "pinlocations", loc_data, ReqOpt::OPTIONAL); + ProcessPinLocations(Cur, PhysicalTileType, &SubTile, &pin_locs, loc_data); + + /* Load Fc */ + Cur = get_single_child(CurSubTile, "fc", loc_data, ReqOpt::OPTIONAL); + Process_Fc(Cur, PhysicalTileType, &SubTile, pin_counts, segments, arch_def_fc, loc_data); + + //Load equivalent sites infromation + Cur = get_single_child(CurSubTile, "equivalent_sites", loc_data, ReqOpt::REQUIRED); + ProcessTileEquivalentSites(Cur, &SubTile, PhysicalTileType, LogicalBlockTypes, loc_data); + + PhysicalTileType->sub_tiles.push_back(SubTile); + + index++; + + CurSubTile = CurSubTile.next_sibling(CurSubTile.name()); + } + + // Initialize pinloc data structure. + int num_pins = PhysicalTileType->num_pins; + PhysicalTileType->pinloc.resize({width, height, num_sides}, std::vector(num_pins, false)); + + SetupPinClasses(PhysicalTileType); + LoadPinLoc(Cur, PhysicalTileType, &pin_locs, loc_data); +} + /* Takes in node pointing to and loads all the * child type objects. */ static void ProcessComplexBlocks(vtr::string_internment* strings, pugi::xml_node Node, std::vector& LogicalBlockTypes, t_arch& arch, const bool timing_enabled, const pugiutil::loc_data& loc_data) { @@ -3981,7 +4146,7 @@ static void ProcessDirects(pugi::xml_node Parent, t_direct_inf** Directs, int* N (*Directs)[i].x_offset = get_attribute(Node, "x_offset", loc_data).as_int(0); (*Directs)[i].y_offset = get_attribute(Node, "y_offset", loc_data).as_int(0); - (*Directs)[i].z_offset = get_attribute(Node, "z_offset", loc_data).as_int(0); + (*Directs)[i].sub_tile_offset = get_attribute(Node, "z_offset", loc_data).as_int(0); std::string from_side_str = get_attribute(Node, "from_side", loc_data, ReqOpt::OPTIONAL).value(); (*Directs)[i].from_side = string_to_side(from_side_str); @@ -4840,16 +5005,17 @@ static void link_physical_logical_types(std::vector& Physi for (auto& physical_tile : PhysicalTileTypes) { if (physical_tile.index == EMPTY_TYPE_INDEX) continue; - auto& equivalent_sites = physical_tile.equivalent_sites; + auto eq_sites_set = get_equivalent_sites_set(&physical_tile); + auto equivalent_sites = std::vector(eq_sites_set.begin(), eq_sites_set.end()); auto criteria = [&physical_tile](const t_logical_block_type* lhs, const t_logical_block_type* rhs) { - int num_physical_pins = physical_tile.num_pins / physical_tile.capacity; + int num_pins = physical_tile.num_inst_pins; int lhs_num_logical_pins = lhs->pb_type->num_pins; int rhs_num_logical_pins = rhs->pb_type->num_pins; - int lhs_diff_num_pins = num_physical_pins - lhs_num_logical_pins; - int rhs_diff_num_pins = num_physical_pins - rhs_num_logical_pins; + int lhs_diff_num_pins = num_pins - lhs_num_logical_pins; + int rhs_diff_num_pins = num_pins - rhs_num_logical_pins; return lhs_diff_num_pins < rhs_diff_num_pins; }; @@ -4860,7 +5026,6 @@ static void link_physical_logical_types(std::vector& Physi for (auto site : equivalent_sites) { if (0 == strcmp(logical_block.name, site->pb_type->name)) { logical_block.equivalent_tiles.push_back(&physical_tile); - break; } } @@ -4883,11 +5048,11 @@ static void link_physical_logical_types(std::vector& Physi auto criteria = [&logical_block](const t_physical_tile_type* lhs, const t_physical_tile_type* rhs) { int num_logical_pins = logical_block.pb_type->num_pins; - int lhs_num_physical_pins = lhs->num_pins / lhs->capacity; - int rhs_num_physical_pins = rhs->num_pins / rhs->capacity; + int lhs_num_pins = lhs->num_inst_pins; + int rhs_num_pins = rhs->num_inst_pins; - int lhs_diff_num_pins = lhs_num_physical_pins - num_logical_pins; - int rhs_diff_num_pins = rhs_num_physical_pins - num_logical_pins; + int lhs_diff_num_pins = lhs_num_pins - num_logical_pins; + int rhs_diff_num_pins = rhs_num_pins - num_logical_pins; return lhs_diff_num_pins < rhs_diff_num_pins; }; @@ -4897,32 +5062,34 @@ static void link_physical_logical_types(std::vector& Physi for (int pin = 0; pin < logical_block.pb_type->num_pins; pin++) { for (auto& tile : logical_block.equivalent_tiles) { auto direct_map = tile->tile_block_pin_directs_map.at(logical_block.index); - auto result = direct_map.find(t_logical_pin(pin)); - if (result == direct_map.end()) { - archfpga_throw(__FILE__, __LINE__, - "Logical pin %d not present in pin mapping between Tile %s and Block %s.\n", - pin, tile->name, logical_block.name); - } + for (auto& sub_tile : tile->sub_tiles) { + auto result = direct_map.find(t_logical_pin(sub_tile.index, pin)); + if (result == direct_map.end()) { + archfpga_throw(__FILE__, __LINE__, + "Logical pin %d not present in pin mapping between Tile %s and Block %s.\n", + pin, tile->name, logical_block.name); + } - int phy_index = result->second.pin; + int phy_index = result->second.pin; - bool is_ignored = tile->is_ignored_pin[phy_index]; - bool is_global = tile->is_pin_global[phy_index]; + bool is_ignored = tile->is_ignored_pin[phy_index]; + bool is_global = tile->is_pin_global[phy_index]; - auto ignored_result = ignored_pins_check_map.insert(std::pair(pin, is_ignored)); - if (!ignored_result.second && ignored_result.first->second != is_ignored) { - archfpga_throw(__FILE__, __LINE__, - "Physical Tile %s has a different value for the ignored pin (physical pin: %d, logical pin: %d) " - "different from the corresponding pins of the other equivalent sites\n.", - tile->name, phy_index, pin); - } + auto ignored_result = ignored_pins_check_map.insert(std::pair(pin, is_ignored)); + if (!ignored_result.second && ignored_result.first->second != is_ignored) { + archfpga_throw(__FILE__, __LINE__, + "Physical Tile %s has a different value for the ignored pin (physical pin: %d, logical pin: %d) " + "different from the corresponding pins of the other equivalent sites\n.", + tile->name, phy_index, pin); + } - auto global_result = global_pins_check_map.insert(std::pair(pin, is_global)); - if (!global_result.second && global_result.first->second != is_global) { - archfpga_throw(__FILE__, __LINE__, - "Physical Tile %s has a different value for the global pin (physical pin: %d, logical pin: %d) " - "different from the corresponding pins of the other equivalent sites\n.", - tile->name, phy_index, pin); + auto global_result = global_pins_check_map.insert(std::pair(pin, is_global)); + if (!global_result.second && global_result.first->second != is_global) { + archfpga_throw(__FILE__, __LINE__, + "Physical Tile %s has a different value for the global pin (physical pin: %d, logical pin: %d) " + "different from the corresponding pins of the other equivalent sites\n.", + tile->name, phy_index, pin); + } } } } @@ -4948,25 +5115,28 @@ static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t for (auto pin_map : pin_direct_mapping) { auto block_port = get_port_by_pin(logical_block, pin_map.first.pin); - auto tile_port = get_port_by_pin(physical_tile, pin_map.second.pin); - VTR_ASSERT(block_port != nullptr); - VTR_ASSERT(tile_port != nullptr); + for (auto& sub_tile : physical_tile->sub_tiles) { + auto sub_tile_port = get_port_by_pin(&sub_tile, pin_map.second.pin); - if (tile_port->type != block_port->type - || tile_port->num_pins != block_port->num_pins - || tile_port->equivalent != block_port->equivalent) { - archfpga_throw(__FILE__, __LINE__, - "Logical block (%s) and Physical tile (%s) do not have equivalent port specifications.\n", - logical_block->name, physical_tile->name); + VTR_ASSERT(block_port != nullptr); + VTR_ASSERT(sub_tile_port != nullptr); + + if (sub_tile_port->type != block_port->type + || sub_tile_port->num_pins != block_port->num_pins + || sub_tile_port->equivalent != block_port->equivalent) { + archfpga_throw(__FILE__, __LINE__, + "Logical block (%s) and Physical tile (%s) do not have equivalent port specifications.\n", + logical_block->name, sub_tile.name); + } } } } -static const t_physical_tile_port* get_port_by_name(t_physical_tile_type_ptr type, const char* port_name) { - for (auto port : type->ports) { +static const t_physical_tile_port* get_port_by_name(t_sub_tile* sub_tile, const char* port_name) { + for (auto port : sub_tile->ports) { if (0 == strcmp(port.name, port_name)) { - return &type->ports[port.index]; + return &sub_tile->ports[port.index]; } } @@ -4986,10 +5156,10 @@ static const t_port* get_port_by_name(t_logical_block_type_ptr type, const char* return nullptr; } -static const t_physical_tile_port* get_port_by_pin(t_physical_tile_type_ptr type, int pin) { - for (auto port : type->ports) { +static const t_physical_tile_port* get_port_by_pin(const t_sub_tile* sub_tile, int pin) { + for (auto port : sub_tile->ports) { if (pin >= port.absolute_first_pin_index && pin < port.absolute_first_pin_index + port.num_pins) { - return &type->ports[port.index]; + return &sub_tile->ports[port.index]; } } diff --git a/utils/fasm/src/fasm.cpp b/utils/fasm/src/fasm.cpp index 8ea5776c091..4b94fc2bd58 100644 --- a/utils/fasm/src/fasm.cpp +++ b/utils/fasm/src/fasm.cpp @@ -57,7 +57,7 @@ void FasmWriterVisitor::visit_clb_impl(ClusterBlockId blk_id, const t_pb* clb) { int x = place_ctx.block_locs[blk_id].loc.x; int y = place_ctx.block_locs[blk_id].loc.y; - int z = place_ctx.block_locs[blk_id].loc.z; + int sub_tile = place_ctx.block_locs[blk_id].loc.sub_tile; auto &grid_loc = device_ctx.grid[x][y]; physical_tile_ = grid_loc.type; logical_block_ = cluster_ctx.clb_nlist.block_type(blk_id); @@ -106,7 +106,7 @@ void FasmWriterVisitor::visit_clb_impl(ClusterBlockId blk_id, const t_pb* clb) { "number of fasm_prefix (%s) options (%d) for block (%s) must match capacity(%d)", prefix_unsplit.c_str(), fasm_prefixes.size(), physical_tile_->name, physical_tile_->capacity); } - grid_prefix = fasm_prefixes[z]; + grid_prefix = fasm_prefixes[sub_tile]; blk_prefix_ = grid_prefix + "."; } else { diff --git a/utils/fasm/test/test_fasm_arch.xml b/utils/fasm/test/test_fasm_arch.xml index 14bbe144e43..c24ff0492c2 100644 --- a/utils/fasm/test/test_fasm_arch.xml +++ b/utils/fasm/test/test_fasm_arch.xml @@ -1,30 +1,34 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + @@ -35,124 +39,163 @@ - - + + LOC=X1Y1 LR=L SING=_SING - CLB + + CLB + - + + LOC=X1Y2 LR=R SING=NULL - CLB + + CLB + - + + LOC=X1Y3 LR=L SING=NULL - CLB + + CLB + - + + LOC=X1Y4 LR=R SING=NULL - CLB + + CLB + - - + + LOC=X2Y1 LR=L SING=_SING - PLB + + PLB + - + + LOC=X2Y2 LR=R SING=NULL - PLB + + PLB + - + + LOC=X2Y3 LR=L SING=NULL - PLB + + PLB + - + + LOC=X2Y4 LR=R SING=NULL - PLB + + PLB + - - + + LOC=X3Y1 LR=L SING=_SING - + + - + + LOC=X3Y2 LR=R SING=NULL - + + - + + LOC=X3Y3 LR=L SING=NULL - + + - + + LOC=X3Y4 LR=R SING=NULL - + + - - + + LOC=X4Y1 LR=L SING=_SING - SLICE + + SLICE + - + + LOC=X4Y2 LR=R SING=NULL - SLICE + + SLICE + - + + LOC=X4Y3 LR=L SING=NULL - SLICE + + SLICE + - + + LOC=X4Y4 LR=R SING=NULL - SLICE + + SLICE + - - diff --git a/vpr/src/base/clock_modeling.cpp b/vpr/src/base/clock_modeling.cpp index 623eb3d7d6c..3873aca4310 100644 --- a/vpr/src/base/clock_modeling.cpp +++ b/vpr/src/base/clock_modeling.cpp @@ -5,7 +5,7 @@ void ClockModeling::treat_clock_pins_as_non_globals() { auto& device_ctx = g_vpr_ctx.mutable_device(); - for (const auto& type : device_ctx.physical_tile_types) { + for (auto& type : device_ctx.physical_tile_types) { if (!is_empty_type(&type)) { for (auto clock_pin_idx : type.get_clock_pins_indices()) { // clock pins should be originally considered as global when reading the architecture diff --git a/vpr/src/base/read_place.cpp b/vpr/src/base/read_place.cpp index dc83c90b48e..ac106058d57 100644 --- a/vpr/src/base/read_place.cpp +++ b/vpr/src/base/read_place.cpp @@ -114,7 +114,7 @@ void read_place(const char* net_file, std::string block_name = tokens[0]; int block_x = vtr::atoi(tokens[1]); int block_y = vtr::atoi(tokens[2]); - int block_z = vtr::atoi(tokens[3]); + int sub_tile_index = vtr::atoi(tokens[3]); ClusterBlockId blk_id = cluster_ctx.clb_nlist.find_block(block_name); @@ -126,7 +126,7 @@ void read_place(const char* net_file, //Set the location place_ctx.block_locs[blk_id].loc.x = block_x; place_ctx.block_locs[blk_id].loc.y = block_y; - place_ctx.block_locs[blk_id].loc.z = block_z; + place_ctx.block_locs[blk_id].loc.sub_tile = sub_tile_index; } else { //Unrecognized @@ -245,12 +245,12 @@ void read_user_pad_loc(const char* pad_loc_file) { place_ctx.block_locs[bnum].loc.x = i; /* Will be reloaded by initial_placement anyway. */ place_ctx.block_locs[bnum].loc.y = j; /* We need to set .x only as a done flag. */ - place_ctx.block_locs[bnum].loc.z = k; + place_ctx.block_locs[bnum].loc.sub_tile = k; place_ctx.block_locs[bnum].is_fixed = true; auto physical_tile = device_ctx.grid[i][j].type; auto logical_block = cluster_ctx.clb_nlist.block_type(bnum); - if (!is_tile_compatible(physical_tile, logical_block)) { + if (!is_sub_tile_compatible(physical_tile, logical_block, place_ctx.block_locs[bnum].loc.sub_tile)) { VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, 0, "Attempt to place block %s at illegal location (%d, %d).\n", bname, i, j); } @@ -313,7 +313,7 @@ void print_place(const char* net_file, if (strlen(cluster_ctx.clb_nlist.block_name(blk_id).c_str()) < 8) fprintf(fp, "\t"); - fprintf(fp, "%d\t%d\t%d", place_ctx.block_locs[blk_id].loc.x, place_ctx.block_locs[blk_id].loc.y, place_ctx.block_locs[blk_id].loc.z); + fprintf(fp, "%d\t%d\t%d", place_ctx.block_locs[blk_id].loc.x, place_ctx.block_locs[blk_id].loc.y, place_ctx.block_locs[blk_id].loc.sub_tile); fprintf(fp, "\t#%zu\n", size_t(blk_id)); } } diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index eecb06bede8..5ab679bdfd2 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -444,7 +444,10 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { if (device_ctx.grid.num_instances(&type) != 0) { float util = 0.; VTR_LOG("\tPhysical Tile %s:\n", type.name); - for (auto logical_block : type.equivalent_sites) { + + auto equivalent_sites = get_equivalent_sites_set(&type); + + for (auto logical_block : equivalent_sites) { util = float(num_type_instances[logical_block]) / device_ctx.grid.num_instances(&type); VTR_LOG("\tBlock Utilization: %.2f Logical Block: %s\n", util, logical_block->name); } diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 9b1422a7a98..528003aab71 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -493,26 +493,26 @@ struct t_bb { // z: z-offset struct t_pl_offset { t_pl_offset() = default; - t_pl_offset(int xoffset, int yoffset, int zoffset) + t_pl_offset(int xoffset, int yoffset, int sub_tile_offset) : x(xoffset) , y(yoffset) - , z(zoffset) {} + , sub_tile(sub_tile_offset) {} int x = 0; int y = 0; - int z = 0; + int sub_tile = 0; t_pl_offset& operator+=(const t_pl_offset& rhs) { x += rhs.x; y += rhs.y; - z += rhs.z; + sub_tile += rhs.sub_tile; return *this; } t_pl_offset& operator-=(const t_pl_offset& rhs) { x -= rhs.x; y -= rhs.y; - z -= rhs.z; + sub_tile -= rhs.sub_tile; return *this; } @@ -527,18 +527,18 @@ struct t_pl_offset { } friend t_pl_offset operator-(const t_pl_offset& other) { - return t_pl_offset(-other.x, -other.y, -other.z); + return t_pl_offset(-other.x, -other.y, -other.sub_tile); } friend t_pl_offset operator+(const t_pl_offset& other) { - return t_pl_offset(+other.x, +other.y, +other.z); + return t_pl_offset(+other.x, +other.y, +other.sub_tile); } friend bool operator<(const t_pl_offset& lhs, const t_pl_offset& rhs) { - return std::tie(lhs.x, lhs.y, lhs.z) < std::tie(rhs.x, rhs.y, rhs.z); + return std::tie(lhs.x, lhs.y, lhs.sub_tile) < std::tie(rhs.x, rhs.y, rhs.sub_tile); } friend bool operator==(const t_pl_offset& lhs, const t_pl_offset& rhs) { - return std::tie(lhs.x, lhs.y, lhs.z) == std::tie(rhs.x, rhs.y, rhs.z); + return std::tie(lhs.x, lhs.y, lhs.sub_tile) == std::tie(rhs.x, rhs.y, rhs.sub_tile); } friend bool operator!=(const t_pl_offset& lhs, const t_pl_offset& rhs) { @@ -552,7 +552,7 @@ struct hash { std::size_t operator()(const t_pl_offset& v) const noexcept { std::size_t seed = std::hash{}(v.x); vtr::hash_combine(seed, v.y); - vtr::hash_combine(seed, v.z); + vtr::hash_combine(seed, v.sub_tile); return seed; } }; @@ -568,26 +568,26 @@ struct hash { //offset between t_pl_loc. struct t_pl_loc { t_pl_loc() = default; - t_pl_loc(int xloc, int yloc, int zloc) + t_pl_loc(int xloc, int yloc, int sub_tile_loc) : x(xloc) , y(yloc) - , z(zloc) {} + , sub_tile(sub_tile_loc) {} int x = OPEN; int y = OPEN; - int z = OPEN; + int sub_tile = OPEN; t_pl_loc& operator+=(const t_pl_offset& rhs) { x += rhs.x; y += rhs.y; - z += rhs.z; + sub_tile += rhs.sub_tile; return *this; } t_pl_loc& operator-=(const t_pl_offset& rhs) { x -= rhs.x; y -= rhs.y; - z -= rhs.z; + sub_tile -= rhs.sub_tile; return *this; } @@ -608,15 +608,15 @@ struct t_pl_loc { } friend t_pl_offset operator-(const t_pl_loc& lhs, const t_pl_loc& rhs) { - return t_pl_offset(lhs.x - rhs.x, lhs.y - rhs.y, lhs.z - rhs.z); + return t_pl_offset(lhs.x - rhs.x, lhs.y - rhs.y, lhs.sub_tile - rhs.sub_tile); } friend bool operator<(const t_pl_loc& lhs, const t_pl_loc& rhs) { - return std::tie(lhs.x, lhs.y, lhs.z) < std::tie(rhs.x, rhs.y, rhs.z); + return std::tie(lhs.x, lhs.y, lhs.sub_tile) < std::tie(rhs.x, rhs.y, rhs.sub_tile); } friend bool operator==(const t_pl_loc& lhs, const t_pl_loc& rhs) { - return std::tie(lhs.x, lhs.y, lhs.z) == std::tie(rhs.x, rhs.y, rhs.z); + return std::tie(lhs.x, lhs.y, lhs.sub_tile) == std::tie(rhs.x, rhs.y, rhs.sub_tile); } friend bool operator!=(const t_pl_loc& lhs, const t_pl_loc& rhs) { @@ -630,7 +630,7 @@ struct hash { std::size_t operator()(const t_pl_loc& v) const noexcept { std::size_t seed = std::hash{}(v.x); vtr::hash_combine(seed, v.y); - vtr::hash_combine(seed, v.z); + vtr::hash_combine(seed, v.sub_tile); return seed; } }; diff --git a/vpr/src/draw/draw_types.cpp b/vpr/src/draw/draw_types.cpp index fdb0755b689..5105f6c8bb8 100644 --- a/vpr/src/draw/draw_types.cpp +++ b/vpr/src/draw/draw_types.cpp @@ -78,7 +78,7 @@ float t_draw_coords::get_tile_height() { ezgl::rectangle t_draw_coords::get_pb_bbox(ClusterBlockId clb_index, const t_pb_graph_node& pb_gnode) { auto& place_ctx = g_vpr_ctx.placement(); auto& cluster_ctx = g_vpr_ctx.clustering(); - return get_pb_bbox(place_ctx.block_locs[clb_index].loc.x, place_ctx.block_locs[clb_index].loc.y, place_ctx.block_locs[clb_index].loc.z, cluster_ctx.clb_nlist.block_type(clb_index), pb_gnode); + return get_pb_bbox(place_ctx.block_locs[clb_index].loc.x, place_ctx.block_locs[clb_index].loc.y, place_ctx.block_locs[clb_index].loc.sub_tile, cluster_ctx.clb_nlist.block_type(clb_index), pb_gnode); } ezgl::rectangle t_draw_coords::get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr logical_block_type, const t_pb_graph_node& pb_gnode) { @@ -136,7 +136,7 @@ ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(const ClusterBlockId clb_in auto& place_ctx = g_vpr_ctx.placement(); t_pl_loc loc = place_ctx.block_locs[clb_index].loc; - return get_pb_bbox(loc.x, loc.y, loc.z, block_type); + return get_pb_bbox(loc.x, loc.y, loc.sub_tile, block_type); } ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index) { diff --git a/vpr/src/place/compressed_grid.cpp b/vpr/src/place/compressed_grid.cpp index 9f3a6219eb4..eb8000383b8 100644 --- a/vpr/src/place/compressed_grid.cpp +++ b/vpr/src/place/compressed_grid.cpp @@ -1,4 +1,5 @@ #include "compressed_grid.h" +#include "arch_util.h" #include "globals.h" std::vector create_compressed_block_grids() { @@ -11,7 +12,9 @@ std::vector create_compressed_block_grids() { for (size_t y = 0; y < grid.height(); ++y) { const t_grid_tile& tile = grid[x][y]; if (tile.width_offset == 0 && tile.height_offset == 0) { - for (auto& block : tile.type->equivalent_sites) { + auto equivalent_sites = get_equivalent_sites_set(tile.type); + + for (auto& block : equivalent_sites) { //Only record at block root location block_locations[block->index].emplace_back(x, y); } @@ -20,8 +23,30 @@ std::vector create_compressed_block_grids() { } std::vector compressed_type_grids(device_ctx.logical_block_types.size()); - for (const auto& type : device_ctx.logical_block_types) { - compressed_type_grids[type.index] = create_compressed_block_grid(block_locations[type.index]); + for (const auto& logical_block : device_ctx.logical_block_types) { + auto compressed_block_grid = create_compressed_block_grid(block_locations[logical_block.index]); + + for (const auto& physical_tile : logical_block.equivalent_tiles) { + std::vector compatible_sub_tiles; + + // Build a vector to store all the sub tile indices that are compatible with the + // (physical_tile, logical_block) pair. + // + // Given that a logical block can potentially be compatible with only a subset of the + // sub tiles of a physical tile, we need to ensure which sub tile locations are part of + // this subset. + for (int isub_tile = 0; isub_tile < physical_tile->capacity; isub_tile++) { + if (is_sub_tile_compatible(physical_tile, &logical_block, isub_tile)) { + compatible_sub_tiles.push_back(isub_tile); + } + } + + // For each of physical tiles compatible with the current logical block, create add an entry + // to the compatible sub tiles map with the physical tile index and the above generated vector. + compressed_block_grid.compatible_sub_tiles_for_tile.insert({physical_tile->index, compatible_sub_tiles}); + } + + compressed_type_grids[logical_block.index] = compressed_block_grid; } return compressed_type_grids; diff --git a/vpr/src/place/compressed_grid.h b/vpr/src/place/compressed_grid.h index 64d99b9f24a..aed5a1a1680 100644 --- a/vpr/src/place/compressed_grid.h +++ b/vpr/src/place/compressed_grid.h @@ -32,6 +32,12 @@ struct t_compressed_block_grid { //stored sparsely, since we may not have full columns of blocks. //This makes it easy to check whether there exist std::vector> grid; + + //The sub type compatibility for a given physical tile and a compressed block grid + //corresponding to the possible placement location for a given logical block + // - key: physical tile index + // - value: vector of compatible sub tiles for the physical tile/logical block pair + std::unordered_map> compatible_sub_tiles_for_tile; }; //Compressed grid space for each block type diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 7060f629e5f..84ae58803b1 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -74,7 +74,7 @@ static void load_legal_placement_locations() { int itype = device_ctx.grid[i][j].type->index; legal_pos[itype][index[itype]].x = i; legal_pos[itype][index[itype]].y = j; - legal_pos[itype][index[itype]].z = k; + legal_pos[itype][index[itype]].sub_tile = k; index[itype]++; } } @@ -110,7 +110,7 @@ static int check_macro_can_be_placed(t_pl_macro pl_macro, int itype, t_pl_loc he // still within the chip's dimemsion and the member_z is allowed at that location on the grid if (member_pos.x < int(device_ctx.grid.width()) && member_pos.y < int(device_ctx.grid.height()) && device_ctx.grid[member_pos.x][member_pos.y].type->index == itype - && place_ctx.grid_blocks[member_pos.x][member_pos.y].blocks[member_pos.z] == EMPTY_BLOCK_ID) { + && place_ctx.grid_blocks[member_pos.x][member_pos.y].blocks[member_pos.sub_tile] == EMPTY_BLOCK_ID) { // Can still accommodate blocks here, check the next position continue; } else { @@ -132,7 +132,7 @@ static int try_place_macro(int itype, int ipos, t_pl_macro pl_macro) { t_pl_loc head_pos = legal_pos[itype][ipos]; // If that location is occupied, do nothing. - if (place_ctx.grid_blocks[head_pos.x][head_pos.y].blocks[head_pos.z] != EMPTY_BLOCK_ID) { + if (place_ctx.grid_blocks[head_pos.x][head_pos.y].blocks[head_pos.sub_tile] != EMPTY_BLOCK_ID) { return (macro_placed); } @@ -147,7 +147,7 @@ static int try_place_macro(int itype, int ipos, t_pl_macro pl_macro) { ClusterBlockId iblk = pl_macro.members[imember].blk_index; place_ctx.block_locs[iblk].loc = member_pos; - place_ctx.grid_blocks[member_pos.x][member_pos.y].blocks[member_pos.z] = pl_macro.members[imember].blk_index; + place_ctx.grid_blocks[member_pos.x][member_pos.y].blocks[member_pos.sub_tile] = pl_macro.members[imember].blk_index; place_ctx.grid_blocks[member_pos.x][member_pos.y].usage++; // Could not ensure that the randomiser would not pick this location again @@ -304,9 +304,9 @@ static void initial_placement_blocks(int* free_locations, enum e_pad_loc_type pa initial_placement_location(free_locations, ipos, itype, to); // Make sure that the position is EMPTY_BLOCK before placing the block down - VTR_ASSERT(place_ctx.grid_blocks[to.x][to.y].blocks[to.z] == EMPTY_BLOCK_ID); + VTR_ASSERT(place_ctx.grid_blocks[to.x][to.y].blocks[to.sub_tile] == EMPTY_BLOCK_ID); - place_ctx.grid_blocks[to.x][to.y].blocks[to.z] = blk_id; + place_ctx.grid_blocks[to.x][to.y].blocks[to.sub_tile] = blk_id; place_ctx.grid_blocks[to.x][to.y].usage++; place_ctx.block_locs[blk_id].loc = to; @@ -405,7 +405,7 @@ void initial_placement(enum e_pad_loc_type pad_loc_type, t_pl_loc pos = legal_pos[itype][ipos]; // Check if that location is occupied. If it is, remove from legal_pos - if (place_ctx.grid_blocks[pos.x][pos.y].blocks[pos.z] != EMPTY_BLOCK_ID && place_ctx.grid_blocks[pos.x][pos.y].blocks[pos.z] != INVALID_BLOCK_ID) { + if (place_ctx.grid_blocks[pos.x][pos.y].blocks[pos.sub_tile] != EMPTY_BLOCK_ID && place_ctx.grid_blocks[pos.x][pos.y].blocks[pos.sub_tile] != INVALID_BLOCK_ID) { legal_pos[itype][ipos] = legal_pos[itype][free_locations[itype] - 1]; free_locations[itype]--; diff --git a/vpr/src/place/move_transactions.cpp b/vpr/src/place/move_transactions.cpp index 5e8900d19a6..8cbd2ac4ca7 100644 --- a/vpr/src/place/move_transactions.cpp +++ b/vpr/src/place/move_transactions.cpp @@ -21,7 +21,7 @@ e_block_move_result record_block_move(t_pl_blocks_to_be_moved& blocks_affected, return e_block_move_result::ABORT; } - VTR_ASSERT_SAFE(to.z < int(place_ctx.grid_blocks[to.x][to.y].blocks.size())); + VTR_ASSERT_SAFE(to.sub_tile < int(place_ctx.grid_blocks[to.x][to.y].blocks.size())); // Sets up the blocks moved int imoved_blk = blocks_affected.num_moved_blocks; @@ -60,19 +60,19 @@ void commit_move_blocks(const t_pl_blocks_to_be_moved& blocks_affected) { t_pl_loc from = blocks_affected.moved_blocks[iblk].old_loc; //Remove from old location only if it hasn't already been updated by a previous block update - if (place_ctx.grid_blocks[from.x][from.y].blocks[from.z] == blk) { + if (place_ctx.grid_blocks[from.x][from.y].blocks[from.sub_tile] == blk) { ; - place_ctx.grid_blocks[from.x][from.y].blocks[from.z] = EMPTY_BLOCK_ID; + place_ctx.grid_blocks[from.x][from.y].blocks[from.sub_tile] = EMPTY_BLOCK_ID; --place_ctx.grid_blocks[from.x][from.y].usage; } //Add to new location - if (place_ctx.grid_blocks[to.x][to.y].blocks[to.z] == EMPTY_BLOCK_ID) { + if (place_ctx.grid_blocks[to.x][to.y].blocks[to.sub_tile] == EMPTY_BLOCK_ID) { ; //Only need to increase usage if previously unused ++place_ctx.grid_blocks[to.x][to.y].usage; } - place_ctx.grid_blocks[to.x][to.y].blocks[to.z] = blk; + place_ctx.grid_blocks[to.x][to.y].blocks[to.sub_tile] = blk; } // Finish updating clb for all blocks } @@ -89,7 +89,7 @@ void revert_move_blocks(t_pl_blocks_to_be_moved& blocks_affected) { place_ctx.block_locs[blk].loc = old; - VTR_ASSERT_SAFE_MSG(place_ctx.grid_blocks[old.x][old.y].blocks[old.z] = blk, "Grid blocks should only have been updated if swap commited (not reverted)"); + VTR_ASSERT_SAFE_MSG(place_ctx.grid_blocks[old.x][old.y].blocks[old.sub_tile] = blk, "Grid blocks should only have been updated if swap commited (not reverted)"); } } diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 1425b47226b..393ef210b3c 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -27,7 +27,7 @@ e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlock //Try inverting the swap direction auto& place_ctx = g_vpr_ctx.placement(); - ClusterBlockId b_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.z]; + ClusterBlockId b_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.sub_tile]; if (!b_to) { log_move_abort("inverted move no to block"); @@ -80,7 +80,7 @@ e_block_move_result find_affected_blocks(t_pl_blocks_to_be_moved& blocks_affecte VTR_ASSERT_SAFE(outcome != e_block_move_result::VALID || imember_from == int(pl_macros[imacro_from].members.size())); } else { - ClusterBlockId b_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.z]; + ClusterBlockId b_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.sub_tile]; int imacro_to = -1; get_imacro_from_iblk(&imacro_to, b_to, pl_macros); @@ -108,9 +108,9 @@ e_block_move_result record_single_block_swap(t_pl_blocks_to_be_moved& blocks_aff auto& place_ctx = g_vpr_ctx.mutable_placement(); - VTR_ASSERT_SAFE(to.z < int(place_ctx.grid_blocks[to.x][to.y].blocks.size())); + VTR_ASSERT_SAFE(to.sub_tile < int(place_ctx.grid_blocks[to.x][to.y].blocks.size())); - ClusterBlockId b_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.z]; + ClusterBlockId b_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.sub_tile]; t_pl_loc curr_from = place_ctx.block_locs[b_from].loc; @@ -173,7 +173,7 @@ e_block_move_result record_macro_swaps(t_pl_blocks_to_be_moved& blocks_affected, log_move_abort("macro_from swap to location illegal"); outcome = e_block_move_result::ABORT; } else { - ClusterBlockId b_to = place_ctx.grid_blocks[curr_to.x][curr_to.y].blocks[curr_to.z]; + ClusterBlockId b_to = place_ctx.grid_blocks[curr_to.x][curr_to.y].blocks[curr_to.sub_tile]; int imacro_to = -1; get_imacro_from_iblk(&imacro_to, b_to, pl_macros); @@ -317,7 +317,7 @@ e_block_move_result record_macro_move(t_pl_blocks_to_be_moved& blocks_affected, return e_block_move_result::ABORT; } - ClusterBlockId blk_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.z]; + ClusterBlockId blk_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.sub_tile]; record_block_move(blocks_affected, member.blk_index, to); @@ -348,7 +348,7 @@ e_block_move_result identify_macro_self_swap_affected_macros(std::vector& m return e_block_move_result::ABORT; } - ClusterBlockId blk_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.z]; + ClusterBlockId blk_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.sub_tile]; int imacro_to = -1; get_imacro_from_iblk(&imacro_to, blk_to, place_ctx.pl_macros); @@ -437,14 +437,19 @@ bool is_legal_swap_to_location(ClusterBlockId blk, t_pl_loc to) { auto& place_ctx = g_vpr_ctx.placement(); if (to.x < 0 || to.x >= int(device_ctx.grid.width()) - || to.y < 0 || to.y >= int(device_ctx.grid.height()) - || to.z < 0 || to.z >= device_ctx.grid[to.x][to.y].type->capacity - || !is_tile_compatible(device_ctx.grid[to.x][to.y].type, cluster_ctx.clb_nlist.block_type(blk))) { + || to.y < 0 || to.y >= int(device_ctx.grid.height())) { return false; } + auto physical_tile = device_ctx.grid[to.x][to.y].type; + auto logical_block = cluster_ctx.clb_nlist.block_type(blk); + + if (to.sub_tile < 0 || to.sub_tile >= physical_tile->capacity + || !is_sub_tile_compatible(physical_tile, logical_block, to.sub_tile)) { + return false; + } // If the destination block is user constrained, abort this swap - auto b_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.z]; + auto b_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.sub_tile]; if (b_to != INVALID_BLOCK_ID && b_to != EMPTY_BLOCK_ID) { if (place_ctx.block_locs[b_to].is_fixed) { return false; @@ -632,9 +637,10 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, auto to_type = grid[to.x][to.y].type; - //Each x/y location contains only a single type, so we can pick a random - //z (capcity) location - to.z = vtr::irand(to_type->capacity - 1); + //Each x/y location possibly contains multiple sub tiles, so we need to pick + //a z location within a compatible sub tile. + auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tiles_for_tile.at(to_type->index); + to.sub_tile = compatible_sub_tiles[vtr::irand((int)compatible_sub_tiles.size() - 1)]; VTR_ASSERT_MSG(is_tile_compatible(to_type, type), "Type must be compatible"); VTR_ASSERT_MSG(grid[to.x][to.y].width_offset == 0, "Should be at block base location"); diff --git a/vpr/src/place/place.cpp b/vpr/src/place/place.cpp index 733bbbf4070..68fd87254fb 100644 --- a/vpr/src/place/place.cpp +++ b/vpr/src/place/place.cpp @@ -207,7 +207,7 @@ std::unique_ptr f_move_stats_file(nullptr, vtr::fc ClusterBlockId b_from = affected_blocks.moved_blocks[0].block_num; \ \ t_pl_loc to = affected_blocks.moved_blocks[0].new_loc; \ - ClusterBlockId b_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.z]; \ + ClusterBlockId b_to = place_ctx.grid_blocks[to.x][to.y].blocks[to.sub_tile]; \ \ t_logical_block_type_ptr from_type = cluster_ctx.clb_nlist.block_type(b_from); \ t_logical_block_type_ptr to_type = nullptr; \ @@ -1752,9 +1752,6 @@ static void free_placement_structs(const t_placer_opts& placer_opts) { } free_placement_macros_structs(); - - /* Frees up all the data structure used in vpr_utils. */ - free_blk_pin_from_port_pin(); } /* Allocates the major structures needed only by the placer, primarily for * @@ -2458,14 +2455,19 @@ static int check_block_placement_consistency() { if (EMPTY_BLOCK_ID == bnum || INVALID_BLOCK_ID == bnum) continue; - if (physical_tile_type(bnum) != device_ctx.grid[i][j].type) { + auto logical_block = cluster_ctx.clb_nlist.block_type(bnum); + auto physical_tile = device_ctx.grid[i][j].type; + + if (physical_tile_type(bnum) != physical_tile) { VTR_LOG_ERROR("Block %zu type (%s) does not match grid location (%zu,%zu) type (%s).\n", - size_t(bnum), cluster_ctx.clb_nlist.block_type(bnum)->name, i, j, device_ctx.grid[i][j].type->name); + size_t(bnum), logical_block->name, i, j, physical_tile->name); error++; } - if ((place_ctx.block_locs[bnum].loc.x != int(i)) || (place_ctx.block_locs[bnum].loc.y != int(j))) { + + auto& loc = place_ctx.block_locs[bnum].loc; + if (loc.x != int(i) || loc.y != int(j) || !is_sub_tile_compatible(physical_tile, logical_block, loc.sub_tile)) { VTR_LOG_ERROR("Block %zu's location is (%d,%d,%d) but found in grid at (%zu,%zu,%d).\n", - size_t(bnum), place_ctx.block_locs[bnum].loc.x, place_ctx.block_locs[bnum].loc.y, place_ctx.block_locs[bnum].loc.z, + size_t(bnum), loc.x, loc.y, loc.sub_tile, i, j, k); error++; } @@ -2514,7 +2516,7 @@ int check_macro_placement_consistency() { } // Then check the place_ctx.grid data structure - if (place_ctx.grid_blocks[member_pos.x][member_pos.y].blocks[member_pos.z] != member_iblk) { + if (place_ctx.grid_blocks[member_pos.x][member_pos.y].blocks[member_pos.sub_tile] != member_iblk) { VTR_LOG_ERROR("Block %zu in pl_macro #%zu is not placed in the proper orientation.\n", size_t(member_iblk), imacro); error++; @@ -2536,7 +2538,7 @@ static void print_clb_placement(const char* fname) { fprintf(fp, "Block #\tName\t(X, Y, Z).\n"); for (auto i : cluster_ctx.clb_nlist.blocks()) { - fprintf(fp, "#%d\t%s\t(%d, %d, %d).\n", i, cluster_ctx.clb_nlist.block_name(i), place_ctx.block_locs[i].x, place_ctx.block_locs[i].y, place_ctx.block_locs[i].z); + fprintf(fp, "#%d\t%s\t(%d, %d, %d).\n", i, cluster_ctx.clb_nlist.block_name(i), place_ctx.block_locs[i].x, place_ctx.block_locs[i].y, place_ctx.block_locs[i].sub_tile); } fclose(fp); diff --git a/vpr/src/place/place_macro.cpp b/vpr/src/place/place_macro.cpp index 5411e3223f8..e7d3fac1800 100644 --- a/vpr/src/place/place_macro.cpp +++ b/vpr/src/place/place_macro.cpp @@ -355,7 +355,7 @@ std::vector alloc_and_load_placement_macros(t_direct_inf* directs, i for (size_t imember = 0; imember < macros[imacro].members.size(); imember++) { macros[imacro].members[imember].offset.x = imember * directs[pl_macro_idirect[imacro]].x_offset; macros[imacro].members[imember].offset.y = imember * directs[pl_macro_idirect[imacro]].y_offset; - macros[imacro].members[imember].offset.z = directs[pl_macro_idirect[imacro]].z_offset; + macros[imacro].members[imember].offset.sub_tile = directs[pl_macro_idirect[imacro]].sub_tile_offset; macros[imacro].members[imember].blk_index = pl_macro_member_blk_num[imacro][imember]; } } @@ -450,7 +450,7 @@ static void write_place_macros(std::string filename, const std::vectorblk_index).c_str(), macro_memb->offset.x, macro_memb->offset.y, - macro_memb->offset.z); + macro_memb->offset.sub_tile); } fprintf(f, "\n"); } diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp index 4ec3d1ce0d8..431d8b9f434 100644 --- a/vpr/src/place/timing_place_lookup.cpp +++ b/vpr/src/place/timing_place_lookup.cpp @@ -234,7 +234,7 @@ std::vector get_best_classes(enum e_pin_type pintype, t_physical_tile_type_ } //Collect all classes of matching type which connect to general routing - for (int i = 0; i < type->num_class; i++) { + for (int i = 0; i < (int)type->class_inf.size(); i++) { if (type->class_inf[i].type == pintype) { //Check whether all pins in this class are ignored or have zero fc bool any_pins_connect_to_general_routing = false; @@ -772,8 +772,8 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct, //Search the grid for an instance of from/to blocks which satisfy this direct connect offsets, //and which has the appropriate pins - int from_x = 0, from_y = 0, from_z = 0; - int to_x = 0, to_y = 0, to_z = 0; + int from_x = 0, from_y = 0, from_sub_tile = 0; + int to_x = 0, to_y = 0, to_sub_tile = 0; bool found = false; for (from_x = 0; from_x < (int)grid.width(); ++from_x) { to_x = from_x + direct->x_offset; @@ -813,10 +813,10 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct, } if (!to_pin_found) continue; - for (from_z = 0; from_z < from_type->capacity; ++from_z) { - to_z = from_z + direct->z_offset; + for (from_sub_tile = 0; from_sub_tile < from_type->capacity; ++from_sub_tile) { + to_sub_tile = from_sub_tile + direct->sub_tile_offset; - if (to_z < 0 || to_z >= to_type->capacity) continue; + if (to_sub_tile < 0 || to_sub_tile >= to_type->capacity) continue; found = true; break; @@ -832,14 +832,14 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct, //Now have a legal instance of this direct connect VTR_ASSERT(grid[from_x][from_y].type == from_type); - VTR_ASSERT(from_z < from_type->capacity); + VTR_ASSERT(from_sub_tile < from_type->capacity); VTR_ASSERT(grid[to_x][to_y].type == to_type); - VTR_ASSERT(to_z < to_type->capacity); + VTR_ASSERT(to_sub_tile < to_type->capacity); VTR_ASSERT(from_x + direct->x_offset == to_x); VTR_ASSERT(from_y + direct->y_offset == to_y); - VTR_ASSERT(from_z + direct->z_offset == to_z); + VTR_ASSERT(from_sub_tile + direct->sub_tile_offset == to_sub_tile); // //Find a source/sink RR node associated with the pins of the direct diff --git a/vpr/src/place/uniform_move_generator.cpp b/vpr/src/place/uniform_move_generator.cpp index 6d39f3f3eaf..b46b232aef4 100644 --- a/vpr/src/place/uniform_move_generator.cpp +++ b/vpr/src/place/uniform_move_generator.cpp @@ -25,8 +25,8 @@ e_create_move UniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks #if 0 auto& grid = g_vpr_ctx.device().grid; VTR_LOG( "swap [%d][%d][%d] %s block %zu \"%s\" <=> [%d][%d][%d] %s block ", - from.x, from.y, from.z, grid[from.x][from.y].type->name, size_t(b_from), (b_from ? cluster_ctx.clb_nlist.block_name(b_from).c_str() : ""), - to.x, to.y, to.z, grid[to.x][to.y].type->name); + from.x, from.y, from.sub_tile, grid[from.x][from.y].type->name, size_t(b_from), (b_from ? cluster_ctx.clb_nlist.block_name(b_from).c_str() : ""), + to.x, to.y, to.sub_tile, grid[to.x][to.y].type->name); if (b_to) { VTR_LOG("%zu \"%s\"", size_t(b_to), cluster_ctx.clb_nlist.block_name(b_to).c_str()); } else { diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index 72d3bf52235..4e3a46c3815 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -555,7 +555,7 @@ void recompute_occupancy_from_scratch() { * (CLB outputs used up by being directly wired to subblocks used only * * locally). */ for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { - for (iclass = 0; iclass < physical_tile_type(blk_id)->num_class; iclass++) { + for (iclass = 0; iclass < (int)physical_tile_type(blk_id)->class_inf.size(); iclass++) { num_local_opins = route_ctx.clb_opins_used_locally[blk_id][iclass].size(); /* Will always be 0 for pads or SINK classes. */ for (ipin = 0; ipin < num_local_opins; ipin++) { @@ -579,7 +579,7 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_ auto& device_ctx = g_vpr_ctx.device(); for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { - for (iclass = 0; iclass < physical_tile_type(blk_id)->num_class; iclass++) { + for (iclass = 0; iclass < (int)physical_tile_type(blk_id)->class_inf.size(); iclass++) { num_local_opins = clb_opins_used_locally[blk_id][iclass].size(); /* Always 0 for pads and for SINK classes */ diff --git a/vpr/src/route/check_rr_graph.cpp b/vpr/src/route/check_rr_graph.cpp index 200a893ca68..b4660817fd0 100644 --- a/vpr/src/route/check_rr_graph.cpp +++ b/vpr/src/route/check_rr_graph.cpp @@ -357,7 +357,7 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext& switch (rr_type) { case SOURCE: - if (ptc_num >= type->num_class + if (ptc_num >= (int)type->class_inf.size() || type->class_inf[ptc_num].type != DRIVER) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); @@ -369,7 +369,7 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext& break; case SINK: - if (ptc_num >= type->num_class + if (ptc_num >= (int)type->class_inf.size() || type->class_inf[ptc_num].type != RECEIVER) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/clock_connection_builders.cpp index ec3be21f784..a97fd4b5042 100644 --- a/vpr/src/route/clock_connection_builders.cpp +++ b/vpr/src/route/clock_connection_builders.cpp @@ -1,6 +1,7 @@ #include "clock_connection_builders.h" #include "globals.h" +#include "arch_util.h" #include "rr_graph2.h" #include "vtr_assert.h" @@ -264,7 +265,8 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra // Ignore grid locations that do not have blocks bool has_pb_type = false; - for (auto logical_block : type->equivalent_sites) { + auto equivalent_sites = get_equivalent_sites_set(type); + for (auto logical_block : equivalent_sites) { if (logical_block->pb_type) { has_pb_type = true; break; diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 1d37b362956..9b691550a7e 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -838,7 +838,7 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() { * specifies that this is necessary). */ t_clb_opins_used clb_opins_used_locally; - int clb_pin, iclass, class_low, class_high; + int clb_pin, iclass; auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -846,9 +846,11 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() { for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { auto type = physical_tile_type(blk_id); + auto sub_tile = type->sub_tiles[get_sub_tile_index(blk_id)]; - get_class_range_for_block(blk_id, &class_low, &class_high); - clb_opins_used_locally[blk_id].resize(type->num_class); + auto class_range = get_class_range_for_block(blk_id); + + clb_opins_used_locally[blk_id].resize((int)type->class_inf.size()); if (is_io_type(type)) continue; @@ -870,7 +872,7 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() { VTR_ASSERT(type->class_inf[iclass].type == DRIVER); /* Check to make sure class is in same range as that assigned to block */ - VTR_ASSERT(iclass >= class_low && iclass <= class_high); + VTR_ASSERT(iclass >= class_range.low && iclass <= class_range.high); //We push back OPEN to reserve space to store the exact pin which //will be reserved (determined later) @@ -1016,7 +1018,6 @@ static vtr::vector> load_rr_clb_sources(const t vtr::vector> rr_blk_source; int i, j, iclass, inode; - int class_low, class_high; t_rr_type rr_type; auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -1026,10 +1027,13 @@ static vtr::vector> load_rr_clb_sources(const t for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { auto type = physical_tile_type(blk_id); - get_class_range_for_block(blk_id, &class_low, &class_high); - rr_blk_source[blk_id].resize(type->num_class); - for (iclass = 0; iclass < type->num_class; iclass++) { - if (iclass >= class_low && iclass <= class_high) { + auto sub_tile = type->sub_tiles[get_sub_tile_index(blk_id)]; + + auto class_range = get_class_range_for_block(blk_id); + + rr_blk_source[blk_id].resize((int)type->class_inf.size()); + for (iclass = 0; iclass < (int)type->class_inf.size(); iclass++) { + if (iclass >= class_range.low && iclass <= class_range.high) { i = place_ctx.block_locs[blk_id].loc.x; j = place_ctx.block_locs[blk_id].loc.y; @@ -1272,11 +1276,14 @@ void print_route(FILE* fp, const vtr::vector& traceba fprintf(fp, "%d ", device_ctx.rr_nodes[inode].ptc_num()); - if (!is_io_type(device_ctx.grid[ilow][jlow].type) && (rr_type == IPIN || rr_type == OPIN)) { + auto physical_tile = device_ctx.grid[ilow][jlow].type; + if (!is_io_type(physical_tile) && (rr_type == IPIN || rr_type == OPIN)) { int pin_num = device_ctx.rr_nodes[inode].ptc_num(); int xoffset = device_ctx.grid[ilow][jlow].width_offset; int yoffset = device_ctx.grid[ilow][jlow].height_offset; - ClusterBlockId iblock = place_ctx.grid_blocks[ilow - xoffset][jlow - yoffset].blocks[0]; + int sub_tile_offset = physical_tile->get_sub_tile_loc_from_pin(pin_num); + + ClusterBlockId iblock = place_ctx.grid_blocks[ilow - xoffset][jlow - yoffset].blocks[sub_tile_offset]; VTR_ASSERT(iblock); t_pb_graph_pin* pb_pin = get_pb_graph_node_pin_from_block_pin(iblock, pin_num); t_pb_type* pb_type = pb_pin->parent_node->pb_type; @@ -1372,7 +1379,7 @@ void reserve_locally_used_opins(HeapInterface* heap, float pres_fac, float acc_f if (rip_up_local_opins) { for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { type = physical_tile_type(blk_id); - for (iclass = 0; iclass < type->num_class; iclass++) { + for (iclass = 0; iclass < (int)type->class_inf.size(); iclass++) { num_local_opin = route_ctx.clb_opins_used_locally[blk_id][iclass].size(); if (num_local_opin == 0) continue; @@ -1393,7 +1400,7 @@ void reserve_locally_used_opins(HeapInterface* heap, float pres_fac, float acc_f for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { type = physical_tile_type(blk_id); - for (iclass = 0; iclass < type->num_class; iclass++) { + for (iclass = 0; iclass < (int)type->class_inf.size(); iclass++) { num_local_opin = route_ctx.clb_opins_used_locally[blk_id][iclass].size(); if (num_local_opin == 0) continue; diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 97dc1f3a66a..7734b2a06f2 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1396,10 +1396,10 @@ static void build_rr_sinks_sources(const int i, return; auto type = grid[i][j].type; - int num_class = type->num_class; - t_class* class_inf = type->class_inf; + int num_class = (int)type->class_inf.size(); + const std::vector& class_inf = type->class_inf; int num_pins = type->num_pins; - int* pin_class = type->pin_class; + const std::vector& pin_class = type->pin_class; /* SINK and SOURCE-to-OPIN edges */ for (int iclass = 0; iclass < num_class; ++iclass) { @@ -2612,18 +2612,7 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in clb_to_clb_directs[i].from_clb_type = physical_tile; - bool port_found = false; - for (const auto& port : physical_tile->ports) { - if (0 == strcmp(port.name, port_name)) { - tile_port = port; - port_found = true; - break; - } - } - - if (!port_found) { - VPR_THROW(VPR_ERROR_ARCH, "Unable to find port %s (on block %s).\n", port_name, tile_name); - } + tile_port = find_tile_port_by_name(physical_tile, port_name); if (start_pin_index == OPEN) { VTR_ASSERT(start_pin_index == end_pin_index); @@ -2654,18 +2643,7 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in clb_to_clb_directs[i].to_clb_type = physical_tile; - port_found = false; - for (const auto& port : physical_tile->ports) { - if (0 == strcmp(port.name, port_name)) { - tile_port = port; - port_found = true; - break; - } - } - - if (!port_found) { - VPR_THROW(VPR_ERROR_ARCH, "Unable to find port %s (on block %s).\n", port_name, tile_name); - } + tile_port = find_tile_port_by_name(physical_tile, port_name); if (start_pin_index == OPEN) { VTR_ASSERT(start_pin_index == end_pin_index); @@ -2693,15 +2671,8 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in } free(tile_name); free(port_name); - - //We must be careful to clean-up anything that we may have incidentally allocated. - //Specifically, we can be called while generating the dummy architecture - //for placer delay estimation. Since the delay estimation occurs on a - //'different' architecture it is almost certain that the f_blk_pin_from_port_pin allocated - //by calling get_blk_pin_from_port_pin() will later be invalid. - //We therefore must free it now. - free_blk_pin_from_port_pin(); } + return clb_to_clb_directs; } @@ -2752,8 +2723,8 @@ static int get_opin_direct_connecions(int x, //Only add connections if the target clb type matches the type in the direct specification t_physical_tile_type_ptr target_type = device_ctx.grid[x + directs[i].x_offset][y + directs[i].y_offset].type; if (clb_to_clb_directs[i].to_clb_type == target_type - && z + directs[i].z_offset < int(target_type->capacity) - && z + directs[i].z_offset >= 0) { + && z + directs[i].sub_tile_offset < int(target_type->capacity) + && z + directs[i].sub_tile_offset >= 0) { /* Compute index of opin with regards to given pins */ int max_index = OPEN, min_index = OPEN; bool swap = false; @@ -2790,7 +2761,7 @@ static int get_opin_direct_connecions(int x, //If this block has capacity > 1 then the pins of z position > 0 are offset //by the number of pins per capacity instance - int ipin = logical_ipin + (target_type->num_pins / target_type->capacity) * (z + directs[i].z_offset); + int ipin = logical_ipin + (target_type->num_pins / target_type->capacity) * (z + directs[i].sub_tile_offset); //if (ipin > target_type->num_pins) continue; //Invalid z-offset diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index c5061ac840e..c4955f72ae2 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1067,8 +1067,8 @@ static void load_block_rr_indices(const DeviceGrid& grid, //Assign indices for SINKs and SOURCEs // Note that SINKS/SOURCES have no side, so we always use side 0 - for (int iclass = 0; iclass < type->num_class; ++iclass) { - auto class_type = type->class_inf[iclass].type; + for (const auto& class_inf : type->class_inf) { + auto class_type = class_inf.type; if (class_type == DRIVER) { indices[SOURCE][x][y][0].push_back(*index); indices[SINK][x][y][0].push_back(OPEN); @@ -1079,8 +1079,8 @@ static void load_block_rr_indices(const DeviceGrid& grid, } ++(*index); } - VTR_ASSERT(indices[SOURCE][x][y][0].size() == size_t(type->num_class)); - VTR_ASSERT(indices[SINK][x][y][0].size() == size_t(type->num_class)); + VTR_ASSERT(indices[SOURCE][x][y][0].size() == type->class_inf.size()); + VTR_ASSERT(indices[SINK][x][y][0].size() == type->class_inf.size()); //Assign indices for IPINs and OPINs at all offsets from root for (int ipin = 0; ipin < type->num_pins; ++ipin) { @@ -1454,7 +1454,7 @@ int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices, * and ptc gives the number of this resource. ptc is the class number, * pin number or track number, depending on what type of resource this * is. All ptcs start at 0 and go up to pins_per_clb-1 or the equivalent. - * There are type->num_class SOURCEs + SINKs, type->num_pins IPINs + OPINs, + * There are class_inf size SOURCEs + SINKs, type->num_pins IPINs + OPINs, * and max_chan_width CHANX and CHANY (each). * * Note that for segments (CHANX and CHANY) of length > 1, the segment is @@ -1497,12 +1497,12 @@ int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices, switch (rr_type) { case SOURCE: - VTR_ASSERT(ptc < type->num_class); + VTR_ASSERT(ptc < (int)type->class_inf.size()); VTR_ASSERT(type->class_inf[ptc].type == DRIVER); break; case SINK: - VTR_ASSERT(ptc < type->num_class); + VTR_ASSERT(ptc < (int)type->class_inf.size()); VTR_ASSERT(type->class_inf[ptc].type == RECEIVER); break; diff --git a/vpr/src/route/rr_graph_uxsdcxx_serializer.h b/vpr/src/route/rr_graph_uxsdcxx_serializer.h index 3c1a286aeac..b4c09cff670 100644 --- a/vpr/src/route/rr_graph_uxsdcxx_serializer.h +++ b/vpr/src/route/rr_graph_uxsdcxx_serializer.h @@ -1215,7 +1215,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { return tile->width; } inline size_t num_block_type_pin_class(const t_physical_tile_type*& tile) final { - return tile->num_class; + return (int)tile->class_inf.size(); } inline const std::pair get_block_type_pin_class(int n, const t_physical_tile_type*& tile) final { return std::make_pair(tile, &tile->class_inf[n]); @@ -1271,7 +1271,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { } inline void preallocate_block_type_pin_class(std::pair& context, size_t size) final { const t_physical_tile_type* tile = context.first; - if (tile->num_class != (ssize_t)size) { + if ((int)tile->class_inf.size() != (ssize_t)size) { report_error("Architecture file does not match block type"); } } @@ -1281,7 +1281,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { int& num_classes = context.second; // Count number of pin classes - if (num_classes >= tile->num_class) { + if (num_classes >= (int)tile->class_inf.size()) { report_error("Architecture file does not match block type"); } const t_class* class_inf = &context.first->class_inf[num_classes++]; @@ -1296,7 +1296,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { inline void finish_block_types_block_type(std::pair& context) final { const t_physical_tile_type* tile = context.first; int num_classes = context.second; - if (tile->num_class != num_classes) { + if ((int)tile->class_inf.size() != num_classes) { report_error("Architecture file does not match block type"); } } diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 5eb38f7622a..bbad95682c3 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -36,8 +36,8 @@ /* f_port_pin_to_block_pin array allows us to quickly find what block * * pin a port pin corresponds to. * - * [0...device_ctx.physical_tile_types.size()-1][0...num_ports-1][0...num_port_pins-1] */ -static int*** f_blk_pin_from_port_pin = nullptr; + * [0...device_ctx.physical_tile_types.size()-1][0..num_sub_tiles][0...num_ports-1][0...num_port_pins-1] */ +static std::vector>>> f_blk_pin_from_port_pin; //Regular expressions used to determine register and logic primitives //TODO: Make this set-able from command-line? @@ -46,8 +46,7 @@ const std::regex LOGIC_MODEL_REGEX("(.subckt\\s+)?.*(lut|names|lcell).*", std::r /******************** Subroutine declarations ********************************/ -/* Allocates and loads blk_pin_from_port_pin array. * - * The arrays are freed in free_placement_structs() */ +/* Allocates and loads blk_pin_from_port_pin array. */ static void alloc_and_load_blk_pin_from_port_pin(); /* Go through all the ports in all the blocks to find the port that has the same * @@ -57,10 +56,11 @@ static void alloc_and_load_blk_pin_from_port_pin(); * Otherwise, mark down all the pins in that port. */ static void mark_direct_of_ports(int idirect, int direct_type, char* pb_type_name, char* port_name, int end_pin_index, int start_pin_index, char* src_string, int line, int** idirect_from_blk_pin, int** direct_type_from_blk_pin); +static void get_blk_pin_from_port_pin(int blk_type_index, int sub_tile, int port, int port_pin, int* blk_pin); /* Mark the pin entry in idirect_from_blk_pin with idirect and the pin entry in * * direct_type_from_blk_pin with direct_type from start_pin_index to * * end_pin_index. */ -static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, int iport, int** idirect_from_blk_pin, int idirect, int** direct_type_from_blk_pin, int direct_type, int line, char* src_string); +static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, int isub_tile, int iport, int** idirect_from_blk_pin, int idirect, int** direct_type_from_blk_pin, int direct_type, int line, char* src_string); static void load_pb_graph_pin_lookup_from_index_rec(t_pb_graph_pin** pb_graph_pin_lookup_from_index, t_pb_graph_node* pb_graph_node); @@ -76,10 +76,12 @@ static t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_ static void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type); struct t_pin_inst_port { - int capacity_instance; //within capacity - int port_index; //Port index - int pin_index_in_port; //Pin's index within the port + int sub_tile_index; // Sub Tile index + int capacity_instance; // within capacity + int port_index; // Port index + int pin_index_in_port; // Pin's index within the port }; +static std::tuple get_pin_index_for_inst(t_physical_tile_type_ptr type, int pin_index); static t_pin_inst_port block_type_pin_index_to_pin_inst(t_physical_tile_type_ptr type, int pin_index); /******************** Subroutine definitions *********************************/ @@ -151,7 +153,7 @@ void sync_grid_to_blocks() { for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { int blk_x = place_ctx.block_locs[blk_id].loc.x; int blk_y = place_ctx.block_locs[blk_id].loc.y; - int blk_z = place_ctx.block_locs[blk_id].loc.z; + int blk_z = place_ctx.block_locs[blk_id].loc.sub_tile; auto type = physical_tile_type(blk_id); @@ -196,17 +198,39 @@ void sync_grid_to_blocks() { } } +static std::tuple get_pin_index_for_inst(t_physical_tile_type_ptr type, int pin_index) { + VTR_ASSERT(pin_index < type->num_pins); + + int total_pin_counts = 0; + int pin_offset = 0; + for (auto& sub_tile : type->sub_tiles) { + total_pin_counts += sub_tile.num_phy_pins; + + if (pin_index < total_pin_counts) { + int pins_per_inst = sub_tile.num_phy_pins / sub_tile.capacity.total(); + int inst_num = (pin_index - pin_offset) / pins_per_inst; + int inst_index = (pin_index - pin_offset) % pins_per_inst; + + return std::make_tuple(inst_index, inst_num, sub_tile.index); + } + + pin_offset += sub_tile.num_phy_pins; + } + + VPR_THROW(VPR_ERROR_ARCH, "Could not infer the correct pin instance index for %s (pin index: %d)", type->name, pin_index); +} + static t_pin_inst_port block_type_pin_index_to_pin_inst(t_physical_tile_type_ptr type, int pin_index) { - int pins_per_inst = type->num_pins / type->capacity; - int inst_num = pin_index / pins_per_inst; - pin_index %= pins_per_inst; + int sub_tile_index, inst_num; + std::tie(pin_index, inst_num, sub_tile_index) = get_pin_index_for_inst(type, pin_index); t_pin_inst_port pin_inst_port; + pin_inst_port.sub_tile_index = sub_tile_index; pin_inst_port.capacity_instance = inst_num; pin_inst_port.port_index = OPEN; pin_inst_port.pin_index_in_port = OPEN; - for (auto const& port : type->ports) { + for (auto const& port : type->sub_tiles[sub_tile_index].ports) { if (pin_index >= port.absolute_first_pin_index && pin_index < port.absolute_first_pin_index + port.num_pins) { pin_inst_port.port_index = port.index; pin_inst_port.pin_index_in_port = pin_index - port.absolute_first_pin_index; @@ -221,17 +245,16 @@ std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_ std::string pin_name = type->name; - if (type->capacity > 1) { - int pins_per_inst = type->num_pins / type->capacity; - int inst_num = pin_index / pins_per_inst; - pin_index %= pins_per_inst; + int sub_tile_index, inst_num; + std::tie(pin_index, inst_num, sub_tile_index) = get_pin_index_for_inst(type, pin_index); + if (type->sub_tiles[sub_tile_index].capacity.total() > 1) { pin_name += "[" + std::to_string(inst_num) + "]"; } pin_name += "."; - for (auto const& port : type->ports) { + for (auto const& port : type->sub_tiles[sub_tile_index].ports) { if (pin_index >= port.absolute_first_pin_index && pin_index < port.absolute_first_pin_index + port.num_pins) { //This port contains the desired pin index int index_in_port = pin_index - port.absolute_first_pin_index; @@ -245,13 +268,9 @@ std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_ } std::vector block_type_class_index_to_pin_names(t_physical_tile_type_ptr type, int class_index) { - VTR_ASSERT(class_index < type->num_class); - - //TODO: unsure if classes are modulo capacity or not... so this may be unnessesary - int classes_per_inst = type->num_class / type->capacity; - class_index %= classes_per_inst; + VTR_ASSERT(class_index < (int)type->class_inf.size()); - t_class& class_inf = type->class_inf[class_index]; + auto class_inf = type->class_inf[class_index]; std::vector pin_info; for (int ipin = 0; ipin < class_inf.num_pins; ++ipin) { @@ -268,9 +287,9 @@ std::vector block_type_class_index_to_pin_names(t_physical_tile_typ std::sort(pin_info.begin(), pin_info.end(), cmp); //Determine ranges for each capacity instance and port pair - std::map, std::pair> pin_ranges; + std::map, std::pair> pin_ranges; for (const auto& pin_inf : pin_info) { - auto key = std::make_pair(pin_inf.capacity_instance, pin_inf.port_index); + auto key = std::make_tuple(pin_inf.sub_tile_index, pin_inf.capacity_instance, pin_inf.port_index); if (!pin_ranges.count(key)) { pin_ranges[key].first = pin_inf.pin_index_in_port; pin_ranges[key].second = pin_inf.pin_index_in_port; @@ -286,23 +305,26 @@ std::vector block_type_class_index_to_pin_names(t_physical_tile_typ auto type_port = kv.first; auto pins = kv.second; - int icapacity = type_port.first; - int iport = type_port.second; + int isub_tile, icapacity, iport; + std::tie(isub_tile, icapacity, iport) = type_port; + int ipin_start = pins.first; int ipin_end = pins.second; + auto& sub_tile = type->sub_tiles[isub_tile]; + std::string pin_name; if (ipin_start == ipin_end) { pin_name = vtr::string_fmt("%s[%d].%s[%d]", type->name, icapacity, - type->ports[iport].name, + sub_tile.ports[iport].name, ipin_start); } else { pin_name = vtr::string_fmt("%s[%d].%s[%d:%d]", type->name, icapacity, - type->ports[iport].name, + sub_tile.ports[iport].name, ipin_start, ipin_end); } @@ -656,6 +678,25 @@ t_physical_tile_type_ptr physical_tile_type(ClusterBlockId blk) { return device_ctx.grid[loc.x][loc.y].type; } +int get_sub_tile_index(ClusterBlockId blk) { + auto& place_ctx = g_vpr_ctx.placement(); + auto& device_ctx = g_vpr_ctx.device(); + + auto block_loc = place_ctx.block_locs[blk]; + auto loc = block_loc.loc; + int sub_tile_coordinate = loc.sub_tile; + + auto type = device_ctx.grid[loc.x][loc.y].type; + + for (const auto& sub_tile : type->sub_tiles) { + if (sub_tile.capacity.is_in_range(sub_tile_coordinate)) { + return sub_tile.index; + } + } + + VPR_THROW(VPR_ERROR_PLACE, "The Block Id %d has been placed in an impossible sub tile location.\n", blk); +} + /* Each node in the pb_graph for a top-level pb_type can be uniquely identified * by its pins. Since the pins in a cluster of a certain type are densely indexed, * this function will find the pin index (int pin_count_in_cluster) of the first @@ -685,16 +726,24 @@ int get_unique_pb_graph_node_id(const t_pb_graph_node* pb_graph_node) { } } -void get_class_range_for_block(const ClusterBlockId blk_id, - int* class_low, - int* class_high) { +t_class_range get_class_range_for_block(const ClusterBlockId blk_id) { /* Assumes that the placement has been done so each block has a set of pins allocated to it */ auto& place_ctx = g_vpr_ctx.placement(); auto type = physical_tile_type(blk_id); - VTR_ASSERT(type->num_class % type->capacity == 0); - *class_low = place_ctx.block_locs[blk_id].loc.z * (type->num_class / type->capacity); - *class_high = (place_ctx.block_locs[blk_id].loc.z + 1) * (type->num_class / type->capacity) - 1; + auto sub_tile = type->sub_tiles[get_sub_tile_index(blk_id)]; + int sub_tile_capacity = sub_tile.capacity.total(); + auto class_range = sub_tile.class_range; + int class_range_total = class_range.high - class_range.low + 1; + + VTR_ASSERT((class_range_total) % sub_tile_capacity == 0); + int rel_capacity = place_ctx.block_locs[blk_id].loc.sub_tile - sub_tile.capacity.low; + + t_class_range abs_class_range; + abs_class_range.low = rel_capacity * (class_range_total / sub_tile_capacity) + class_range.low; + abs_class_range.high = (rel_capacity + 1) * (class_range_total / sub_tile_capacity) - 1 + class_range.low; + + return abs_class_range; } void get_pin_range_for_block(const ClusterBlockId blk_id, @@ -704,9 +753,16 @@ void get_pin_range_for_block(const ClusterBlockId blk_id, auto& place_ctx = g_vpr_ctx.placement(); auto type = physical_tile_type(blk_id); - VTR_ASSERT(type->num_pins % type->capacity == 0); - *pin_low = place_ctx.block_locs[blk_id].loc.z * (type->num_pins / type->capacity); - *pin_high = (place_ctx.block_locs[blk_id].loc.z + 1) * (type->num_pins / type->capacity) - 1; + auto sub_tile = type->sub_tiles[get_sub_tile_index(blk_id)]; + int sub_tile_capacity = sub_tile.capacity.total(); + + VTR_ASSERT(sub_tile.num_phy_pins % sub_tile_capacity == 0); + int rel_capacity = place_ctx.block_locs[blk_id].loc.sub_tile - sub_tile.capacity.low; + int rel_pin_low = rel_capacity * (sub_tile.num_phy_pins / sub_tile_capacity); + int rel_pin_high = (rel_capacity + 1) * (sub_tile.num_phy_pins / sub_tile_capacity) - 1; + + *pin_low = sub_tile.sub_tile_to_tile_pin_indices[rel_pin_low]; + *pin_high = sub_tile.sub_tile_to_tile_pin_indices[rel_pin_high]; } t_physical_tile_type_ptr find_tile_type_by_name(std::string name, const std::vector& types) { @@ -817,13 +873,7 @@ InstPort parse_inst_port(std::string str) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find block type named %s", inst_port.instance_name().c_str()); } - int num_pins = OPEN; - for (auto physical_port : blk_type->ports) { - if (0 == strcmp(inst_port.port_name().c_str(), physical_port.name)) { - num_pins = physical_port.num_pins; - break; - } - } + int num_pins = find_tile_port_by_name(blk_type, inst_port.port_name().c_str()).num_pins; if (num_pins == OPEN) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find port %s on block type %s", inst_port.port_name().c_str(), inst_port.instance_name().c_str()); @@ -868,12 +918,23 @@ int find_pin(t_physical_tile_type_ptr type, std::string port_name, int pin_index int port_base_ipin = 0; int num_pins = OPEN; - for (auto port : type->ports) { - if (port.name == port_name) { - num_pins = port.num_pins; + bool port_found = false; + for (const auto& sub_tile : type->sub_tiles) { + for (const auto& port : sub_tile.ports) { + if (0 == strcmp(port.name, port_name.c_str())) { + port_found = true; + num_pins = port.num_pins; + break; + } + + port_base_ipin += port.num_pins; + } + + if (port_found) { break; } - port_base_ipin += port.num_pins; + + port_base_ipin = 0; } if (num_pins != OPEN) { @@ -1566,7 +1627,7 @@ void free_pb_stats(t_pb* pb) { * * ***************************************************************************************/ -void get_blk_pin_from_port_pin(int blk_type_index, int port, int port_pin, int* blk_pin) { +static void get_blk_pin_from_port_pin(int blk_type_index, int sub_tile, int port, int port_pin, int* blk_pin) { /* This mapping is needed since there are two different netlist * * conventions - in the cluster level, ports and port pins are used * * while in the post-pack level, block pins are used. The reason block * @@ -1577,86 +1638,40 @@ void get_blk_pin_from_port_pin(int blk_type_index, int port, int port_pin, int* * [0...device_ctx.logical_block_types.size()-1][0...num_ports-1][0...num_port_pins-1] */ /* If the array is not allocated and loaded, allocate it. */ - if (f_blk_pin_from_port_pin == nullptr) { + if (f_blk_pin_from_port_pin.empty()) { alloc_and_load_blk_pin_from_port_pin(); } /* Return the port and port_pin for the pin. */ - *blk_pin = f_blk_pin_from_port_pin[blk_type_index][port][port_pin]; -} - -void free_blk_pin_from_port_pin() { - /* Frees the f_blk_pin_from_port_pin array. * - * * - * This function is called when the arrays are freed in * - * free_placement_structs() */ - - int iport, num_ports; - auto& device_ctx = g_vpr_ctx.device(); - - if (f_blk_pin_from_port_pin != nullptr) { - for (const auto& type : device_ctx.physical_tile_types) { - int itype = type.index; - - // Avoid EMPTY_PHYSICAL_TILE_TYPE - if (itype == 0) { - continue; - } - - num_ports = type.ports.size(); - for (iport = 0; iport < num_ports; iport++) { - free(f_blk_pin_from_port_pin[itype][iport]); - } - free(f_blk_pin_from_port_pin[itype]); - } - free(f_blk_pin_from_port_pin); - - f_blk_pin_from_port_pin = nullptr; - } + *blk_pin = f_blk_pin_from_port_pin[blk_type_index][sub_tile][port][port_pin]; } static void alloc_and_load_blk_pin_from_port_pin() { - /* Allocates and loads blk_pin_from_port_pin array. * - * * - * The arrays are freed in free_placement_structs() */ - - int*** temp_blk_pin_from_port_pin = nullptr; - unsigned int itype; - int iport, iport_pin; - int blk_pin_count, num_port_pins, num_ports; - auto& device_ctx = g_vpr_ctx.device(); - - /* Allocate and initialize the values to OPEN (-1). */ - temp_blk_pin_from_port_pin = (int***)vtr::malloc(device_ctx.physical_tile_types.size() * sizeof(int**)); - for (itype = 1; itype < device_ctx.physical_tile_types.size(); itype++) { - num_ports = device_ctx.physical_tile_types[itype].ports.size(); - temp_blk_pin_from_port_pin[itype] = (int**)vtr::malloc(num_ports * sizeof(int*)); - for (iport = 0; iport < num_ports; iport++) { - num_port_pins = device_ctx.physical_tile_types[itype].ports[iport].num_pins; - temp_blk_pin_from_port_pin[itype][iport] = (int*)vtr::malloc(num_port_pins * sizeof(int)); - - for (iport_pin = 0; iport_pin < num_port_pins; iport_pin++) { - temp_blk_pin_from_port_pin[itype][iport][iport_pin] = OPEN; - } - } - } + /* Allocates and loads blk_pin_from_port_pin array. */ - /* Load the values */ - /* itype starts from 1 since device_ctx.block_types[0] is the EMPTY_PHYSICAL_TILE_TYPE. */ - for (itype = 1; itype < device_ctx.physical_tile_types.size(); itype++) { - blk_pin_count = 0; - num_ports = device_ctx.physical_tile_types[itype].ports.size(); - for (iport = 0; iport < num_ports; iport++) { - num_port_pins = device_ctx.physical_tile_types[itype].ports[iport].num_pins; - for (iport_pin = 0; iport_pin < num_port_pins; iport_pin++) { - temp_blk_pin_from_port_pin[itype][iport][iport_pin] = blk_pin_count; - blk_pin_count++; + auto& device_ctx = g_vpr_ctx.device(); + auto& types = device_ctx.physical_tile_types; + + /* Resize and initialize the values to OPEN (-1). */ + int num_types = types.size(); + f_blk_pin_from_port_pin.resize(num_types); + for (int itype = 1; itype < num_types; itype++) { + int blk_pin_count = 0; + auto& type = types[itype]; + int num_sub_tiles = type.sub_tiles.size(); + f_blk_pin_from_port_pin[itype].resize(num_sub_tiles); + for (int isub_tile = 0; isub_tile < num_sub_tiles; isub_tile++) { + int num_ports = type.sub_tiles[isub_tile].ports.size(); + f_blk_pin_from_port_pin[itype][isub_tile].resize(num_ports); + for (int iport = 0; iport < num_ports; iport++) { + int num_pins = type.sub_tiles[isub_tile].ports[iport].num_pins; + for (int ipin = 0; ipin < num_pins; ipin++) { + f_blk_pin_from_port_pin[itype][isub_tile][iport].push_back(blk_pin_count); + blk_pin_count++; + } } } } - - /* Sets the file_scope variables to point at the arrays. */ - f_blk_pin_from_port_pin = temp_blk_pin_from_port_pin; } /*************************************************************************************** @@ -1755,7 +1770,7 @@ void parse_direct_pin_name(char* src_string, int line, int* start_pin_index, int } } -static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, int iport, int** idirect_from_blk_pin, int idirect, int** direct_type_from_blk_pin, int direct_type, int line, char* src_string) { +static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, int isub_tile, int iport, int** idirect_from_blk_pin, int idirect, int** direct_type_from_blk_pin, int direct_type, int line, char* src_string) { /* Mark the pin entry in idirect_from_blk_pin with idirect and the pin entry in * * direct_type_from_blk_pin with direct_type from start_pin_index to * * end_pin_index. */ @@ -1765,7 +1780,7 @@ static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int ityp // Mark pins with indices from start_pin_index to end_pin_index, inclusive for (iport_pin = start_pin_index; iport_pin <= end_pin_index; iport_pin++) { - get_blk_pin_from_port_pin(itype, iport, iport_pin, &iblk_pin); + get_blk_pin_from_port_pin(itype, isub_tile, iport, iport_pin, &iblk_pin); //iterate through all segment connections and check if all Fc's are 0 bool all_fcs_0 = true; @@ -1802,46 +1817,47 @@ static void mark_direct_of_ports(int idirect, int direct_type, char* pb_type_nam * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * * Otherwise, mark down all the pins in that port. */ - int num_ports, num_port_pins; - unsigned int itype; - int iport; auto& device_ctx = g_vpr_ctx.device(); // Go through all the block types - for (itype = 1; itype < device_ctx.physical_tile_types.size(); itype++) { + for (int itype = 1; itype < (int)device_ctx.physical_tile_types.size(); itype++) { auto& physical_tile = device_ctx.physical_tile_types[itype]; // Find blocks with the same pb_type_name if (strcmp(physical_tile.name, pb_type_name) == 0) { - num_ports = physical_tile.ports.size(); - for (iport = 0; iport < num_ports; iport++) { - // Find ports with the same port_name - if (strcmp(physical_tile.ports[iport].name, port_name) == 0) { - num_port_pins = physical_tile.ports[iport].num_pins; - - // Check whether the end_pin_index is valid - if (end_pin_index > num_port_pins) { - VTR_LOG_ERROR( - "[LINE %d] Invalid pin - %s, the end_pin_index in " - "[end_pin_index:start_pin_index] should " - "be less than the num_port_pins %d.\n", - line, src_string, num_port_pins); - exit(1); - } + int num_sub_tiles = physical_tile.sub_tiles.size(); + for (int isub_tile = 0; isub_tile < num_sub_tiles; isub_tile++) { + auto& ports = physical_tile.sub_tiles[isub_tile].ports; + int num_ports = ports.size(); + for (int iport = 0; iport < num_ports; iport++) { + // Find ports with the same port_name + if (strcmp(ports[iport].name, port_name) == 0) { + int num_port_pins = ports[iport].num_pins; + + // Check whether the end_pin_index is valid + if (end_pin_index > num_port_pins) { + VTR_LOG_ERROR( + "[LINE %d] Invalid pin - %s, the end_pin_index in " + "[end_pin_index:start_pin_index] should " + "be less than the num_port_pins %d.\n", + line, src_string, num_port_pins); + exit(1); + } - // Check whether the pin indices are specified - if (start_pin_index >= 0 || end_pin_index >= 0) { - mark_direct_of_pins(start_pin_index, end_pin_index, itype, - iport, idirect_from_blk_pin, idirect, - direct_type_from_blk_pin, direct_type, line, src_string); - } else { - mark_direct_of_pins(0, num_port_pins - 1, itype, - iport, idirect_from_blk_pin, idirect, - direct_type_from_blk_pin, direct_type, line, src_string); - } - } // Do nothing if port_name does not match - } // Finish going through all the ports - } // Do nothing if pb_type_name does not match - } // Finish going through all the blocks + // Check whether the pin indices are specified + if (start_pin_index >= 0 || end_pin_index >= 0) { + mark_direct_of_pins(start_pin_index, end_pin_index, itype, + isub_tile, iport, idirect_from_blk_pin, idirect, + direct_type_from_blk_pin, direct_type, line, src_string); + } else { + mark_direct_of_pins(0, num_port_pins - 1, itype, + isub_tile, iport, idirect_from_blk_pin, idirect, + direct_type_from_blk_pin, direct_type, line, src_string); + } + } // Do nothing if port_name does not match + } // Finish going through all the ports + } // Finish going through all the subtiles + } // Do nothing if pb_type_name does not match + } // Finish going through all the blocks } void alloc_and_load_idirect_from_blk_pin(t_direct_inf* directs, int num_directs, int*** idirect_from_blk_pin, int*** direct_type_from_blk_pin) { @@ -2095,15 +2111,21 @@ void place_sync_external_block_connections(ClusterBlockId iblk) { auto physical_tile = physical_tile_type(iblk); auto logical_block = clb_nlist.block_type(iblk); - VTR_ASSERT(physical_tile->num_pins % physical_tile->capacity == 0); - int max_num_block_pins = physical_tile->num_pins / physical_tile->capacity; + int sub_tile_index = get_sub_tile_index(iblk); + auto sub_tile = physical_tile->sub_tiles[sub_tile_index]; + + VTR_ASSERT(sub_tile.num_phy_pins % sub_tile.capacity.total() == 0); + + int max_num_block_pins = sub_tile.num_phy_pins / sub_tile.capacity.total(); /* Logical location and physical location is offset by z * max_num_block_pins */ + int rel_capacity = place_ctx.block_locs[iblk].loc.sub_tile - sub_tile.capacity.low; + for (auto pin : clb_nlist.block_pins(iblk)) { int logical_pin_index = clb_nlist.pin_logical_index(pin); - int physical_pin_index = get_physical_pin(physical_tile, logical_block, logical_pin_index); + int physical_pin_index = get_sub_tile_physical_pin(sub_tile_index, physical_tile, logical_block, logical_pin_index); - int new_physical_pin_index = physical_pin_index + place_ctx.block_locs[iblk].loc.z * max_num_block_pins; + int new_physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[physical_pin_index + rel_capacity * max_num_block_pins]; auto result = place_ctx.physical_pins.find(pin); if (result != place_ctx.physical_pins.end()) { @@ -2140,6 +2162,18 @@ bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_ return std::find(equivalent_tiles.begin(), equivalent_tiles.end(), physical_tile) != equivalent_tiles.end(); } +bool is_sub_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int sub_tile_loc) { + bool capacity_compatible = false; + for (auto& sub_tile : physical_tile->sub_tiles) { + if (sub_tile.capacity.is_in_range(sub_tile_loc)) { + capacity_compatible = true; + break; + } + } + + return capacity_compatible && is_tile_compatible(physical_tile, logical_block); +} + /** * This function returns the most common physical tile type given a logical block */ @@ -2148,7 +2182,7 @@ t_physical_tile_type_ptr pick_best_physical_type(t_logical_block_type_ptr logica } t_logical_block_type_ptr pick_best_logical_type(t_physical_tile_type_ptr physical_tile) { - return physical_tile->equivalent_sites[0]; + return physical_tile->sub_tiles[0].equivalent_sites[0]; } t_physical_tile_type_ptr get_physical_tile_type(const ClusterBlockId blk) { @@ -2184,10 +2218,11 @@ int get_logical_pin(t_physical_tile_type_ptr physical_tile, return result->second.pin; } -int get_physical_pin(t_physical_tile_type_ptr physical_tile, - t_logical_block_type_ptr logical_block, - int pin) { - t_logical_pin logical_pin(pin); +int get_sub_tile_physical_pin(int sub_tile_index, + t_physical_tile_type_ptr physical_tile, + t_logical_block_type_ptr logical_block, + int pin) { + t_logical_pin logical_pin(sub_tile_index, pin); const auto& direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index); auto result = direct_map.find(logical_pin); @@ -2203,6 +2238,23 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile, return result->second.pin; } +int get_physical_pin(t_physical_tile_type_ptr physical_tile, + t_logical_block_type_ptr logical_block, + int pin) { + int sub_tile_index = OPEN; + for (const auto& sub_tile : physical_tile->sub_tiles) { + auto eq_sites = sub_tile.equivalent_sites; + auto it = std::find(eq_sites.begin(), eq_sites.end(), logical_block); + if (it != eq_sites.end()) { + sub_tile_index = sub_tile.index; + } + } + + VTR_ASSERT(sub_tile_index != OPEN); + + return get_sub_tile_physical_pin(sub_tile_index, physical_tile, logical_block, pin); +} + int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index) { auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -2218,6 +2270,19 @@ int tile_pin_index(const ClusterPinId pin) { return place_ctx.physical_pins[pin]; } +t_physical_tile_port find_tile_port_by_name(t_physical_tile_type_ptr type, const char* port_name) { + for (const auto& sub_tile : type->sub_tiles) { + for (const auto& port : sub_tile.ports) { + if (0 == strcmp(port.name, port_name)) { + return port; + } + } + } + + // Port has not been found, throw an error. + VPR_THROW(VPR_ERROR_ARCH, "Unable to find port %s (on block %s).\n", port_name, type->name); +} + void pretty_print_uint(const char* prefix, size_t value, int num_digits, int scientific_precision) { //Print as integer if it will fit in the width, other wise scientific if (value <= std::pow(10, num_digits) - 1) { diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index aa40b1e0116..3a9f865bee1 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -30,10 +30,17 @@ bool is_empty_type(t_logical_block_type_ptr type); //Returns the corresponding physical type given the logical type as parameter t_physical_tile_type_ptr physical_tile_type(ClusterBlockId blk); +//Returns the sub tile corresponding to the logical block location within a physical type +int get_sub_tile_index(ClusterBlockId blk); + int get_unique_pb_graph_node_id(const t_pb_graph_node* pb_graph_node); -void get_class_range_for_block(const ClusterBlockId blk_id, int* class_low, int* class_high); +//Returns the physical class range relative to a block id. This must be called after placement +//as the block id is used to retrieve the information of the used physical tile. +t_class_range get_class_range_for_block(const ClusterBlockId blk_id); +//Returns the physical pin range relative to a block id. This must be called after placement +//as the block id is used to retrieve the information of the used physical tile. void get_pin_range_for_block(const ClusterBlockId blk_id, int* pin_low, int* pin_high); @@ -125,9 +132,6 @@ void free_pin_id_to_pb_mapping(vtr::vector& pin_id_to_pb float compute_primitive_base_cost(const t_pb_graph_node* primitive); int num_ext_inputs_atom_block(AtomBlockId blk_id); -void get_blk_pin_from_port_pin(int blk_type_index, int port, int port_pin, int* blk_pin); -void free_blk_pin_from_port_pin(); - void alloc_and_load_idirect_from_blk_pin(t_direct_inf* directs, int num_directs, int*** idirect_from_blk_pin, int*** direct_type_from_blk_pin); void parse_direct_pin_name(char* src_string, int line, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); @@ -144,8 +148,12 @@ AtomBlockId find_memory_sibling(const t_pb* pb); void place_sync_external_block_connections(ClusterBlockId iblk); int get_max_num_pins(t_logical_block_type_ptr logical_block); +//Verifies whether a given logical block is compatible with a given physical tile bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block); +//Verifies whether a logical block and a relative placement location is compatible with a given physical tile +bool is_sub_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int sub_tile_loc); + //Returns the physical tile type which 'best' matches logical_block t_physical_tile_type_ptr pick_best_physical_type(t_logical_block_type_ptr logical_block); @@ -162,6 +170,10 @@ int get_logical_pin(t_physical_tile_type_ptr physical_tile, int get_physical_pin(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int pin); +int get_sub_tile_physical_pin(int sub_tile_index, + t_physical_tile_type_ptr physical_tile, + t_logical_block_type_ptr logical_block, + int pin); //Returns the physical pin of the tile, related to the given ClusterNedId, and the net pin index int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index); @@ -169,6 +181,11 @@ int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index); //Returns the physical pin of the tile, related to the given ClusterPinId int tile_pin_index(const ClusterPinId pin); +// Returns one of the physical ports of a tile corresponding to the port_name. +// Given that each sub_tile's port that has exactly the same name has to be equivalent +// one to the other, it is indifferent which port is returned. +t_physical_tile_port find_tile_port_by_name(t_physical_tile_type_ptr type, const char* port_name); + int max_pins_per_grid_tile(); void pretty_print_uint(const char* prefix, size_t value, int num_digits, int scientific_precision); diff --git a/vpr/test/test_read_arch_metadata.xml b/vpr/test/test_read_arch_metadata.xml index 1068b139531..c3f2e0afd83 100644 --- a/vpr/test/test_read_arch_metadata.xml +++ b/vpr/test/test_read_arch_metadata.xml @@ -1,30 +1,34 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/bidir/k4_n4_v7_bidir.xml b/vtr_flow/arch/bidir/k4_n4_v7_bidir.xml index 009fef90cf6..33f9679c3ec 100644 --- a/vtr_flow/arch/bidir/k4_n4_v7_bidir.xml +++ b/vtr_flow/arch/bidir/k4_n4_v7_bidir.xml @@ -24,30 +24,34 @@ Architecture based off Stratix IV - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/bidir/k4_n4_v7_bidir_pass_gate.xml b/vtr_flow/arch/bidir/k4_n4_v7_bidir_pass_gate.xml index e6d3fb6eca3..f3bbb2fdf9f 100644 --- a/vtr_flow/arch/bidir/k4_n4_v7_bidir_pass_gate.xml +++ b/vtr_flow/arch/bidir/k4_n4_v7_bidir_pass_gate.xml @@ -24,30 +24,34 @@ Architecture based off Stratix IV - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/bidir/k4_n4_v7_l1_bidir.xml b/vtr_flow/arch/bidir/k4_n4_v7_l1_bidir.xml index 933ab020ca3..3042148ff8e 100644 --- a/vtr_flow/arch/bidir/k4_n4_v7_l1_bidir.xml +++ b/vtr_flow/arch/bidir/k4_n4_v7_l1_bidir.xml @@ -24,30 +24,34 @@ Architecture based off Stratix IV - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/bidir/k4_n4_v7_longline_bidir.xml b/vtr_flow/arch/bidir/k4_n4_v7_longline_bidir.xml index 087558b8143..6f2d6030ebe 100644 --- a/vtr_flow/arch/bidir/k4_n4_v7_longline_bidir.xml +++ b/vtr_flow/arch/bidir/k4_n4_v7_longline_bidir.xml @@ -24,30 +24,34 @@ Architecture based off Stratix IV - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/common/arch.xml b/vtr_flow/arch/common/arch.xml index 5fdb82c166b..c369cf56b25 100644 --- a/vtr_flow/arch/common/arch.xml +++ b/vtr_flow/arch/common/arch.xml @@ -13,34 +13,38 @@ - - - - - - - - - - ff_tile.in - ff_tile.clk ff_tile.cen - ff_tile.out - + + + + + + + + + + + ff_tile.in + ff_tile.clk ff_tile.cen + ff_tile.out + + - - - - - - - io_tile.in io_tile.out - io_tile.in io_tile.out - io_tile.in io_tile.out - io_tile.in io_tile.out - - + + + + + + + + io_tile.in io_tile.out + io_tile.in io_tile.out + io_tile.in io_tile.out + io_tile.in io_tile.out + + + diff --git a/vtr_flow/arch/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml b/vtr_flow/arch/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml index 5b2a4a00959..d442ce854ca 100644 --- a/vtr_flow/arch/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml +++ b/vtr_flow/arch/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml @@ -67,88 +67,96 @@ - - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_error.xml b/vtr_flow/arch/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_error.xml index 5b34bb01bd9..6dc19feea39 100644 --- a/vtr_flow/arch/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_error.xml +++ b/vtr_flow/arch/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_error.xml @@ -67,88 +67,96 @@ - - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/custom_grid/buffered_flyover_wires.xml b/vtr_flow/arch/custom_grid/buffered_flyover_wires.xml index b1932706a79..0015416e0db 100644 --- a/vtr_flow/arch/custom_grid/buffered_flyover_wires.xml +++ b/vtr_flow/arch/custom_grid/buffered_flyover_wires.xml @@ -158,45 +158,41 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - @@ -210,21 +206,33 @@ + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/custom_grid/column_io.xml b/vtr_flow/arch/custom_grid/column_io.xml index d7af343f10d..d7ae708f5f9 100644 --- a/vtr_flow/arch/custom_grid/column_io.xml +++ b/vtr_flow/arch/custom_grid/column_io.xml @@ -158,54 +158,62 @@ - - - - - - - - - + + + + + + + + + + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/custom_grid/custom_sbloc.xml b/vtr_flow/arch/custom_grid/custom_sbloc.xml index a17df3083ce..7931352eb92 100644 --- a/vtr_flow/arch/custom_grid/custom_sbloc.xml +++ b/vtr_flow/arch/custom_grid/custom_sbloc.xml @@ -158,45 +158,41 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - @@ -210,21 +206,33 @@ + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/custom_grid/fixed_grid.xml b/vtr_flow/arch/custom_grid/fixed_grid.xml index a625dfb2178..efc609f03b3 100644 --- a/vtr_flow/arch/custom_grid/fixed_grid.xml +++ b/vtr_flow/arch/custom_grid/fixed_grid.xml @@ -147,9 +147,9 @@ - - - + + + @@ -158,59 +158,67 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/custom_grid/multiple_io_types.xml b/vtr_flow/arch/custom_grid/multiple_io_types.xml index 44e1fd64338..1ce3c6af103 100644 --- a/vtr_flow/arch/custom_grid/multiple_io_types.xml +++ b/vtr_flow/arch/custom_grid/multiple_io_types.xml @@ -158,92 +158,106 @@ - - - - - - - - - - io_left.outpad io_left.inpad io_left.clock - + + + + + + + + + + + io_left.outpad io_left.inpad io_left.clock + + - - - - - - - - - - io_right.outpad io_right.inpad io_right.clock - + + + + + + + + + + + io_right.outpad io_right.inpad io_right.clock + + - - - - - - - - - - io_top.outpad io_top.inpad io_top.clock - + + + + + + + + + + + io_top.outpad io_top.inpad io_top.clock + + - - - - - - - - - - io_bottom.outpad io_bottom.inpad io_bottom.clock - + + + + + + + + + + + io_bottom.outpad io_bottom.inpad io_bottom.clock + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/custom_grid/multiwidth_blocks.xml b/vtr_flow/arch/custom_grid/multiwidth_blocks.xml index 648a7462865..dc6bb8151b9 100644 --- a/vtr_flow/arch/custom_grid/multiwidth_blocks.xml +++ b/vtr_flow/arch/custom_grid/multiwidth_blocks.xml @@ -147,9 +147,9 @@ - - - + + + @@ -158,59 +158,67 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/custom_grid/non_column.xml b/vtr_flow/arch/custom_grid/non_column.xml index 3d8ce76d129..c21c5a8653e 100644 --- a/vtr_flow/arch/custom_grid/non_column.xml +++ b/vtr_flow/arch/custom_grid/non_column.xml @@ -147,9 +147,9 @@ - - - + + + @@ -167,69 +167,79 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/custom_grid/non_column_tall_aspect_ratio.xml b/vtr_flow/arch/custom_grid/non_column_tall_aspect_ratio.xml index 35b9cc986f5..8b018ebd22c 100644 --- a/vtr_flow/arch/custom_grid/non_column_tall_aspect_ratio.xml +++ b/vtr_flow/arch/custom_grid/non_column_tall_aspect_ratio.xml @@ -147,9 +147,9 @@ - - - + + + @@ -167,69 +167,79 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/custom_grid/non_column_wide_aspect_ratio.xml b/vtr_flow/arch/custom_grid/non_column_wide_aspect_ratio.xml index 53998ad7b0c..8f1da1a17ec 100644 --- a/vtr_flow/arch/custom_grid/non_column_wide_aspect_ratio.xml +++ b/vtr_flow/arch/custom_grid/non_column_wide_aspect_ratio.xml @@ -167,69 +167,79 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/custom_grid/shorted_flyover_wires.xml b/vtr_flow/arch/custom_grid/shorted_flyover_wires.xml index babc5933049..c48c7ee7c17 100644 --- a/vtr_flow/arch/custom_grid/shorted_flyover_wires.xml +++ b/vtr_flow/arch/custom_grid/shorted_flyover_wires.xml @@ -147,9 +147,9 @@ - - - + + + @@ -158,45 +158,41 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - @@ -210,21 +206,33 @@ + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/custom_pins/k6_frac_N10_mem32K_40nm_custom_pins.xml b/vtr_flow/arch/custom_pins/k6_frac_N10_mem32K_40nm_custom_pins.xml index 2156d0c9240..d9a9d2d6ab6 100644 --- a/vtr_flow/arch/custom_pins/k6_frac_N10_mem32K_40nm_custom_pins.xml +++ b/vtr_flow/arch/custom_pins/k6_frac_N10_mem32K_40nm_custom_pins.xml @@ -136,91 +136,99 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - + + + + + + + + + + mult_36.a[0:8] mult_36.b[0:8] mult_36.out[0:17] - + mult_36.a[9:17] mult_36.b[9:17] mult_36.out[18:35] - + mult_36.a[18:26] mult_36.b[18:26] mult_36.out[36:54] - + mult_36.a[27:35] mult_36.b[27:35] mult_36.out[54:71] - + mult_36.a[0:8] mult_36.b[0:8] mult_36.out[0:17] - + mult_36.a[9:17] mult_36.b[9:17] mult_36.out[18:35] - + mult_36.a[18:26] mult_36.b[18:26] mult_36.out[36:54] - + mult_36.a[27:35] mult_36.b[27:35] mult_36.out[54:71] - + mult_36.a[0:8] mult_36.b[0:8] mult_36.out[0:17] - + mult_36.a[9:17] mult_36.b[9:17] mult_36.out[18:35] - + mult_36.a[18:26] mult_36.b[18:26] mult_36.out[36:54] - + mult_36.a[27:35] mult_36.b[27:35] mult_36.out[54:71] - + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/equivalent_sites/equivalent.xml b/vtr_flow/arch/equivalent_sites/equivalent.xml index 5e8fb3b55d8..74f20ca9e7c 100644 --- a/vtr_flow/arch/equivalent_sites/equivalent.xml +++ b/vtr_flow/arch/equivalent_sites/equivalent.xml @@ -36,50 +36,54 @@ - - - - - - - - - - io_tile.in io_tile.out - io_tile.in io_tile.out - io_tile.in io_tile.out - io_tile.in io_tile.out - - + + + + + + + + + + + io_tile.in io_tile.out + io_tile.in io_tile.out + io_tile.in io_tile.out + io_tile.in io_tile.out + + + - - - - - - - - - - - - - - - - - - - - - - pass_through_tile.in pass_through_tile.out - pass_through_tile.in pass_through_tile.out - pass_through_tile.in pass_through_tile.out - pass_through_tile.in pass_through_tile.out - - + + + + + + + + + + + + + + + + + + + + + + + pass_through_tile.in pass_through_tile.out + pass_through_tile.in pass_through_tile.out + pass_through_tile.in pass_through_tile.out + pass_through_tile.in pass_through_tile.out + + + diff --git a/vtr_flow/arch/ispd/ultrascale_ispd.xml b/vtr_flow/arch/ispd/ultrascale_ispd.xml index e8d42d3608b..4d0ea0d222c 100644 --- a/vtr_flow/arch/ispd/ultrascale_ispd.xml +++ b/vtr_flow/arch/ispd/ultrascale_ispd.xml @@ -95,10 +95,10 @@ - - - - + + + + @@ -109,21 +109,21 @@ - - - - - - - - + + + + + + + + - - - - - - + + + + + + @@ -253,59 +253,67 @@ - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I27_fleI6_fleO1_ff1_nmodes_1.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I27_fleI6_fleO1_ff1_nmodes_1.xml index 59fe9770579..a67dd51d82f 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I27_fleI6_fleO1_ff1_nmodes_1.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I27_fleI6_fleO1_ff1_nmodes_1.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI5_fleO2_ff1_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI5_fleO2_ff1_nmodes_2.xml index 099efce007d..24abc21001e 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI5_fleO2_ff1_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI5_fleO2_ff1_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI5_fleO2_ff2_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI5_fleO2_ff2_nmodes_2.xml index 21abda7ff3a..6948f6aeaa4 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI5_fleO2_ff2_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI5_fleO2_ff2_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO1_ff1_nmodes_1.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO1_ff1_nmodes_1.xml index 85ad6c4092d..efdfa2523c9 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO1_ff1_nmodes_1.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO1_ff1_nmodes_1.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO2_ff1_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO2_ff1_nmodes_2.xml index 03f756e7d85..cdc52ca3ec1 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO2_ff1_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO2_ff1_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO2_ff2_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO2_ff2_nmodes_2.xml index 24c083ddb6a..a6edfc0066d 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO2_ff2_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I48_fleI6_fleO2_ff2_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I56_fleI7_fleO2_ff1_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I56_fleI7_fleO2_ff1_nmodes_2.xml index 4121489c726..56a8ffe1d58 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I56_fleI7_fleO2_ff1_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I56_fleI7_fleO2_ff1_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I56_fleI7_fleO2_ff2_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I56_fleI7_fleO2_ff2_nmodes_2.xml index dc0f5aaa65a..0e4ead34613 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I56_fleI7_fleO2_ff2_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I56_fleI7_fleO2_ff2_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I64_fleI8_fleO2_ff1_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I64_fleI8_fleO2_ff1_nmodes_2.xml index 8bdb792db6c..a1ee93753e8 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I64_fleI8_fleO2_ff1_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I64_fleI8_fleO2_ff1_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I64_fleI8_fleO2_ff2_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I64_fleI8_fleO2_ff2_nmodes_2.xml index cd5b6834574..828a3bab898 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I64_fleI8_fleO2_ff2_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I64_fleI8_fleO2_ff2_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I72_fleI9_fleO2_ff1_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I72_fleI9_fleO2_ff1_nmodes_2.xml index 14bfda4542a..ffd3346c9e9 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I72_fleI9_fleO2_ff1_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I72_fleI9_fleO2_ff1_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I72_fleI9_fleO2_ff2_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I72_fleI9_fleO2_ff2_nmodes_2.xml index 4d93eb12952..db0a6bb5075 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I72_fleI9_fleO2_ff2_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I72_fleI9_fleO2_ff2_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I80_fleI10_fleO2_ff1_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I80_fleI10_fleO2_ff1_nmodes_2.xml index 12a18ce614e..619d7199759 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I80_fleI10_fleO2_ff1_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I80_fleI10_fleO2_ff1_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml index 98630d2609e..966accff6df 100755 --- a/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml +++ b/vtr_flow/arch/no_timing/fracturable_lut_sweep/k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData16.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData16.xml index 2c662901725..4d05a0b7ef0 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData16.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData16.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData2.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData2.xml index d0514b0901c..aaf3551a10b 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData2.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData32.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData32.xml index 5c483aa930e..ce6d633f9db 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData32.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData32.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData4.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData4.xml index 63db148c142..0c7a15b9798 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData4.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData4.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData64.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData64.xml index a358e4eb4b0..6c3ec2a6866 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData64.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData64.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData8.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData8.xml index 179c4f6ccfa..098cf7e712e 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData8.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize1024_memData8.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData16.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData16.xml index 404df585cea..85f12e94f94 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData16.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData16.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData2.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData2.xml index b9114aba6cf..47325f26d25 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData2.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData32.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData32.xml index 061eb6f8d6a..a883bdb3a15 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData32.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData32.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData4.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData4.xml index ac827bcdb58..60243e504ed 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData4.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData4.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData64.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData64.xml index 7c673eb4ee5..d59bde12a92 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData64.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData64.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData8.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData8.xml index ae83fb8714c..024fe6d54ea 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData8.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize131072_memData8.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData16.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData16.xml index b7316290906..a333d4efdce 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData16.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData16.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData2.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData2.xml index 242f7f12f9b..378007fe062 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData2.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData32.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData32.xml index 080d6c4f0eb..a244b9f40f4 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData32.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData32.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData4.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData4.xml index dffd90760f7..08e5952415b 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData4.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData4.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData64.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData64.xml index b7b8ce4e0bf..5cf7638796a 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData64.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData64.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData8.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData8.xml index 7a7db575f34..2d46ad37f9c 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData8.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize16384_memData8.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData16.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData16.xml index 5410bd729d6..3caf52eb27b 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData16.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData16.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData2.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData2.xml index 6e34b4212f8..5ba42f5c3a5 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData2.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData32.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData32.xml index ef58d19de9c..885a7ccd27b 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData32.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData32.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData4.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData4.xml index f887cd1f9de..26369a2edde 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData4.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData4.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData64.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData64.xml index 4c00d96294a..fc151742740 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData64.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData64.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData8.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData8.xml index 602bd294750..1e2bc8bc084 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData8.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize2048_memData8.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData16.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData16.xml index 17dcdefb8a4..730c688577e 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData16.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData16.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData2.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData2.xml index 71a21b7c184..f7156c15170 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData2.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData32.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData32.xml index 4dd19e9df07..0661f027c87 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData32.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData32.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData4.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData4.xml index 7657b059224..0b5ee18eee3 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData4.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData4.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData64.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData64.xml index 5b4faf666fa..d17eb715ad2 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData64.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData64.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData8.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData8.xml index e4d33b755e7..5c1a0f00859 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData8.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize262144_memData8.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData16.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData16.xml index 55541cd3135..3ab5905666e 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData16.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData16.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData2.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData2.xml index d4aab26bb9d..fb2ebfc21ac 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData2.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData32.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData32.xml index 0aac9b0cf83..7b7f94d8179 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData32.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData32.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData4.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData4.xml index 589f5ad3d27..e8afd787ee5 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData4.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData4.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData64.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData64.xml index 59fa1d78f09..7cb35635e4d 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData64.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData64.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData8.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData8.xml index 23d67220b5e..cafe79c59e2 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData8.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize32768_memData8.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData16.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData16.xml index a2d2e4df793..0652d2c8512 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData16.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData16.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData2.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData2.xml index 53370394877..608a778a417 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData2.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData32.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData32.xml index 9729f315d3f..6c3675fbd39 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData32.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData32.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData4.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData4.xml index 28588d50a4a..84fd13af58f 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData4.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData4.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData64.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData64.xml index b9eedba6199..3f9cb64927d 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData64.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData64.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData8.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData8.xml index c48b8bec86e..7bc85278884 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData8.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize4096_memData8.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData16.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData16.xml index 151e7698e85..99d192efb4b 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData16.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData16.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData2.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData2.xml index 002b45c5bb0..b96925f65f7 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData2.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData32.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData32.xml index 0d9ef1531a8..bcd4c3ef442 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData32.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData32.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData4.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData4.xml index 19a06a24ee1..dbb4542e756 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData4.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData4.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData64.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData64.xml index 3fcf05f37a6..8d4b7e12dc5 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData64.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData64.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData8.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData8.xml index ac73e606ae9..045e1d6a1f4 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData8.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize512_memData8.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData16.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData16.xml index 06e4a4504de..14c5d368e08 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData16.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData16.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData2.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData2.xml index b23cee5a648..99ce6bef077 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData2.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData32.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData32.xml index 1b6325e812d..e1166d9cbcc 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData32.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData32.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData4.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData4.xml index 167252a292a..65668622991 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData4.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData4.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData64.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData64.xml index 7746aeb75e7..a26b7c81193 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData64.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData64.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData8.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData8.xml index d7ae45457e2..510226cefc6 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData8.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize524288_memData8.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData16.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData16.xml index 947512b1310..5a79e8d52f9 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData16.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData16.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData2.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData2.xml index 04e6f2648e0..4b845093546 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData2.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData32.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData32.xml index b094da1ae80..3c4ccdef6f6 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData32.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData32.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData4.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData4.xml index 97355cb1f8f..7834ba0abfd 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData4.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData4.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData64.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData64.xml index 28eb6addc2f..e449bff44b0 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData64.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData64.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData8.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData8.xml index 4d704467857..e4498f71061 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData8.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize65536_memData8.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData16.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData16.xml index 8d294a0c2f7..422e9c10f47 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData16.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData16.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData2.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData2.xml index 409909d75d2..a06861c5eea 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData2.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData2.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData32.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData32.xml index ac3c4b679d8..f856e4e9a17 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData32.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData32.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData4.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData4.xml index 6b591134bec..c0dc3735415 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData4.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData4.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData64.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData64.xml index c080f301e6d..c0007efc701 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData64.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData64.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData8.xml b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData8.xml index 7deeb2c24d6..aa40c5a8fa3 100755 --- a/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData8.xml +++ b/vtr_flow/arch/no_timing/memory_sweep/k4_N10_memSize8192_memData8.xml @@ -52,54 +52,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml b/vtr_flow/arch/nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml index bc26c6a42b7..e9df993de4a 100644 --- a/vtr_flow/arch/nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml +++ b/vtr_flow/arch/nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml @@ -79,54 +79,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml b/vtr_flow/arch/nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml index 797d1d2f6e7..b2aa49b346d 100644 --- a/vtr_flow/arch/nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml +++ b/vtr_flow/arch/nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml @@ -79,54 +79,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L1_frac0_ff1_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L1_frac0_ff1_45nm.xml index c49ae41112b..51764f06351 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L1_frac0_ff1_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L1_frac0_ff1_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L2_frac0_ff1_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L2_frac0_ff1_45nm.xml index 382a585889f..dc79efa2946 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L2_frac0_ff1_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L2_frac0_ff1_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L3_frac0_ff1_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L3_frac0_ff1_45nm.xml index b3ca770d0d5..a9db8944ffc 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L3_frac0_ff1_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L3_frac0_ff1_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml index afe4cb6c6a8..9b1ddb05a06 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_130nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml index fda0f59f5bc..0bdc055e115 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml index a8630c4c7c8..130c058859b 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C10_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C10_45nm.xml index 7d9ab53c13a..c64fb04fe2b 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C10_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C10_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C15_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C15_45nm.xml index fe1ee636f1e..1b852add479 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C15_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C15_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C20_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C20_45nm.xml index e9600fedda3..12c6a80a2ea 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C20_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C20_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C25_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C25_45nm.xml index cbd5af7fbd9..14dff470e9c 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C25_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C25_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C30_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C30_45nm.xml index 11a90988ac2..75018055f7f 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C30_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C30_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C35_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C35_45nm.xml index 92c4f741736..61be8928c88 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C35_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C35_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C40_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C40_45nm.xml index ae845b39dfe..5e9e05d6208 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C40_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C40_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml index da2a01116ff..9dfc10e5ceb 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C45_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml index 0b66cfdea55..b70768e1819 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C50_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C5_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C5_45nm.xml index 0e8e20faa7e..3b8c458e3d6 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C5_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac0_ff1_C5_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml index 614133454ff..4e55e8a1a19 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml index 490c73f15e7..cd3b58d1ab2 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C10_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C10_45nm.xml index 5dfe501e5c1..b9559d25655 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C10_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C10_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C15_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C15_45nm.xml index a81672146f4..16f743eaf50 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C15_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C15_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C20_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C20_45nm.xml index 3e03809a74f..a591055e5c0 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C20_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C20_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C25_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C25_45nm.xml index 5d7d7869beb..0f114ab9b95 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C25_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C25_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C30_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C30_45nm.xml index 21381ff943f..6a573334b56 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C30_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C30_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C35_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C35_45nm.xml index f4720dc52a0..0d8bcbe8b66 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C35_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C35_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C40_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C40_45nm.xml index 8615138ab29..fd691e24649 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C40_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C40_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C45_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C45_45nm.xml index a3d164b9e90..512309a4926 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C45_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C45_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C50_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C50_45nm.xml index 7723512c110..d8044299714 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C50_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C50_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C55_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C55_45nm.xml index 0c93813eeba..7a8cce598e4 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C55_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C55_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C5_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C5_45nm.xml index 9e872b92471..6dbed412bd0 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C5_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C5_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C60_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C60_45nm.xml index 008e80d4829..471900a9ede 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C60_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L4_frac1_ff2_C60_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L5_frac0_ff1_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L5_frac0_ff1_45nm.xml index 3e8be2dc5f0..a6a1403580b 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L5_frac0_ff1_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L5_frac0_ff1_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi6_L6_frac0_ff1_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi6_L6_frac0_ff1_45nm.xml index 4fa56a0f98e..365a2512d76 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi6_L6_frac0_ff1_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi6_L6_frac0_ff1_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml index 73d0cba12a9..2a75d70bf4c 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml index e74e92cb560..f4ce44058a9 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml index a374dd063b4..90b9b01ae2c 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml b/vtr_flow/arch/power/k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml index de05dbdf150..68b837cab0c 100644 --- a/vtr_flow/arch/power/k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml b/vtr_flow/arch/power/k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml index bf800f56827..e962a21fe9e 100644 --- a/vtr_flow/arch/power/k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml b/vtr_flow/arch/power/k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml index c02fbf7661f..a81732ca18a 100644 --- a/vtr_flow/arch/power/k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml b/vtr_flow/arch/power/k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml index 7352f987d95..f44a99e7dba 100644 --- a/vtr_flow/arch/power/k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/power/k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml b/vtr_flow/arch/power/k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml index 7e989afeb06..d494065a660 100644 --- a/vtr_flow/arch/power/k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml +++ b/vtr_flow/arch/power/k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml @@ -57,54 +57,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/routing_mode/arch.xml b/vtr_flow/arch/routing_mode/arch.xml index e8e2ce9a7ea..4466b05c2ba 100644 --- a/vtr_flow/arch/routing_mode/arch.xml +++ b/vtr_flow/arch/routing_mode/arch.xml @@ -42,34 +42,38 @@ - - - - - - - - - - ff_tile.in - ff_tile.clk ff_tile.cen - ff_tile.out - + + + + + + + + + + + ff_tile.in + ff_tile.clk ff_tile.cen + ff_tile.out + + - - - - - - - io_tile.in io_tile.out - io_tile.in io_tile.out - io_tile.in io_tile.out - io_tile.in io_tile.out - - + + + + + + + + io_tile.in io_tile.out + io_tile.in io_tile.out + io_tile.in io_tile.out + io_tile.in io_tile.out + + + diff --git a/vtr_flow/arch/routing_mode/slicem.xml b/vtr_flow/arch/routing_mode/slicem.xml index 4215c3ace38..02033707717 100644 --- a/vtr_flow/arch/routing_mode/slicem.xml +++ b/vtr_flow/arch/routing_mode/slicem.xml @@ -3,8 +3,8 @@ - - + + @@ -14,9 +14,9 @@ - - - + + + @@ -62,74 +62,78 @@ - - - - - - - io_tile.in io_tile.out - io_tile.in io_tile.out - io_tile.in io_tile.out - io_tile.in io_tile.out - - + + + + + + + + io_tile.in io_tile.out + io_tile.in io_tile.out + io_tile.in io_tile.out + io_tile.in io_tile.out + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/sub_tiles/sub_tiles.xml b/vtr_flow/arch/sub_tiles/sub_tiles.xml new file mode 100644 index 00000000000..948b0266a80 --- /dev/null +++ b/vtr_flow/arch/sub_tiles/sub_tiles.xml @@ -0,0 +1,246 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_tile_0.in io_tile_0.out + io_tile_0.in io_tile_0.out + io_tile_0.in io_tile_0.out + io_tile_0.in io_tile_0.out + + + + + + + + + + + + + + io_tile_1.in io_tile_1.out + io_tile_1.in io_tile_1.out + io_tile_1.in io_tile_1.out + io_tile_1.in io_tile_1.out + + + + + + + + + + + + + + io_tile_2.in io_tile_2.out + io_tile_2.in io_tile_2.out + io_tile_2.in io_tile_2.out + io_tile_2.in io_tile_2.out + + + + + + + + + + + + + + + + + + + + pass_through_tile_0.in pass_through_tile_0.out + pass_through_tile_0.in pass_through_tile_0.out + pass_through_tile_0.in pass_through_tile_0.out + pass_through_tile_0.in pass_through_tile_0.out + + + + + + + + + + + + + + + + + + pass_through_tile_1.in pass_through_tile_1.out + pass_through_tile_1.in pass_through_tile_1.out + pass_through_tile_1.in pass_through_tile_1.out + pass_through_tile_1.in pass_through_tile_1.out + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + diff --git a/vtr_flow/arch/timing/EArch.xml b/vtr_flow/arch/timing/EArch.xml index 6f83218cd67..8585e14f6d4 100644 --- a/vtr_flow/arch/timing/EArch.xml +++ b/vtr_flow/arch/timing/EArch.xml @@ -138,9 +138,9 @@ - - - + + + @@ -149,62 +149,70 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml index 98d311e41ca..5e4ce7bd1eb 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml @@ -65,60 +65,68 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml index e2fad47db2a..cd7eb1a867a 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml @@ -72,9 +72,9 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - + + + @@ -83,66 +83,74 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml index fc9bbce42d7..bb0e36420b5 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml @@ -75,9 +75,9 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - + + + @@ -86,66 +86,74 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml index 22307383828..d8835fba6f2 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml @@ -72,9 +72,9 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - + + + @@ -83,66 +83,74 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml index 22b6ac44f6d..191304bbf91 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml @@ -74,9 +74,9 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - + + + @@ -85,66 +85,74 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml index cf6f3ca18e6..54b08daf89b 100644 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml @@ -70,9 +70,9 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - + + + @@ -81,65 +81,73 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml index b2676a9fb76..c8d6426c267 100644 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml @@ -76,65 +76,73 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml index b68d6759635..fb6ced886a4 100644 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml @@ -65,60 +65,68 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml index bef5c735918..c5ba6c1bcae 100644 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml @@ -65,9 +65,9 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - + + + @@ -76,65 +76,73 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml index f1eb631ad4b..86cc65a5fd3 100644 --- a/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml @@ -65,9 +65,9 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - + + + @@ -76,65 +76,73 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml index e06480a1666..7fabe02d1bc 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml @@ -83,64 +83,72 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - + + + + + + + + + + + + + - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml index a044031777d..769a4486681 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml @@ -75,9 +75,9 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - + + + @@ -86,64 +86,72 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - + + + + + + + + + + + + + - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml index 2f2559707ea..0299a404e11 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml @@ -83,64 +83,72 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - + + + + + + + + + + + + + - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml index ff01a7cb038..75f434e5276 100755 --- a/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml @@ -74,9 +74,9 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - + + + @@ -85,64 +85,72 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - + + + + + + + + + + + + + - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2ripple_N8_22nm.xml b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2ripple_N8_22nm.xml index 43e9e951b55..cd1251dc842 100644 --- a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2ripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2ripple_N8_22nm.xml @@ -81,65 +81,73 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2uripple_N8_22nm.xml b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2uripple_N8_22nm.xml index cd276646043..c095d0b7e87 100644 --- a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2uripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2uripple_N8_22nm.xml @@ -65,9 +65,9 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - + + + @@ -76,65 +76,73 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_N8_22nm.xml b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_N8_22nm.xml index 22419ea1597..5acf6d96074 100644 --- a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_N8_22nm.xml +++ b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_N8_22nm.xml @@ -65,60 +65,68 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_ripple_N8_22nm.xml b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_ripple_N8_22nm.xml index 25aa0c15803..e38a7f3df64 100644 --- a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_ripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_ripple_N8_22nm.xml @@ -76,65 +76,73 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_uripple_N8_22nm.xml b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_uripple_N8_22nm.xml index 4c60ffb98ac..de6e13aca41 100644 --- a/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_uripple_N8_22nm.xml +++ b/vtr_flow/arch/timing/fraclut_carrychain/k6_frac_uripple_N8_22nm.xml @@ -76,65 +76,73 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/global_nonuniform/x_delta_y_delta.xml b/vtr_flow/arch/timing/global_nonuniform/x_delta_y_delta.xml index 036597930b3..68c33a72d82 100644 --- a/vtr_flow/arch/timing/global_nonuniform/x_delta_y_delta.xml +++ b/vtr_flow/arch/timing/global_nonuniform/x_delta_y_delta.xml @@ -133,54 +133,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/global_nonuniform/x_delta_y_uniform.xml b/vtr_flow/arch/timing/global_nonuniform/x_delta_y_uniform.xml index 9a4dd6904f8..a1e0ede7e19 100644 --- a/vtr_flow/arch/timing/global_nonuniform/x_delta_y_uniform.xml +++ b/vtr_flow/arch/timing/global_nonuniform/x_delta_y_uniform.xml @@ -133,54 +133,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/global_nonuniform/x_gaussian_y_gaussian.xml b/vtr_flow/arch/timing/global_nonuniform/x_gaussian_y_gaussian.xml index c5c31e0b0b3..146565b61d2 100644 --- a/vtr_flow/arch/timing/global_nonuniform/x_gaussian_y_gaussian.xml +++ b/vtr_flow/arch/timing/global_nonuniform/x_gaussian_y_gaussian.xml @@ -133,54 +133,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/global_nonuniform/x_gaussian_y_uniform.xml b/vtr_flow/arch/timing/global_nonuniform/x_gaussian_y_uniform.xml index 2815c136dd3..fc3cd6115cb 100644 --- a/vtr_flow/arch/timing/global_nonuniform/x_gaussian_y_uniform.xml +++ b/vtr_flow/arch/timing/global_nonuniform/x_gaussian_y_uniform.xml @@ -133,54 +133,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/global_nonuniform/x_uniform_y_delta.xml b/vtr_flow/arch/timing/global_nonuniform/x_uniform_y_delta.xml index 396eb59cedf..7c67ecfcda8 100644 --- a/vtr_flow/arch/timing/global_nonuniform/x_uniform_y_delta.xml +++ b/vtr_flow/arch/timing/global_nonuniform/x_uniform_y_delta.xml @@ -133,54 +133,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/global_nonuniform/x_uniform_y_gaussian.xml b/vtr_flow/arch/timing/global_nonuniform/x_uniform_y_gaussian.xml index b30b0fcabd0..8ec752666b4 100644 --- a/vtr_flow/arch/timing/global_nonuniform/x_uniform_y_gaussian.xml +++ b/vtr_flow/arch/timing/global_nonuniform/x_uniform_y_gaussian.xml @@ -133,54 +133,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/hard_fpu_arch_timing.xml b/vtr_flow/arch/timing/hard_fpu_arch_timing.xml index e34a38b0851..f06d7462bc4 100755 --- a/vtr_flow/arch/timing/hard_fpu_arch_timing.xml +++ b/vtr_flow/arch/timing/hard_fpu_arch_timing.xml @@ -25,46 +25,52 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k4_N4_90nm.xml b/vtr_flow/arch/timing/k4_N4_90nm.xml index 54378686b64..ed9b55e7d87 100644 --- a/vtr_flow/arch/timing/k4_N4_90nm.xml +++ b/vtr_flow/arch/timing/k4_N4_90nm.xml @@ -16,30 +16,34 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k4_N4_90nm_default_fc_pinloc.xml b/vtr_flow/arch/timing/k4_N4_90nm_default_fc_pinloc.xml index 05d42742562..2184f46ce67 100644 --- a/vtr_flow/arch/timing/k4_N4_90nm_default_fc_pinloc.xml +++ b/vtr_flow/arch/timing/k4_N4_90nm_default_fc_pinloc.xml @@ -16,28 +16,32 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - + + + + + + + + diff --git a/vtr_flow/arch/timing/k4_N8_legacy_45nm.xml b/vtr_flow/arch/timing/k4_N8_legacy_45nm.xml index 8ebe5c09e4c..6e511f7e155 100644 --- a/vtr_flow/arch/timing/k4_N8_legacy_45nm.xml +++ b/vtr_flow/arch/timing/k4_N8_legacy_45nm.xml @@ -16,30 +16,34 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N10_40nm.xml b/vtr_flow/arch/timing/k6_N10_40nm.xml index 3f52c56efa1..711e4825539 100644 --- a/vtr_flow/arch/timing/k6_N10_40nm.xml +++ b/vtr_flow/arch/timing/k6_N10_40nm.xml @@ -26,30 +26,34 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N10_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/k6_N10_gate_boost_0.2V_22nm.xml index c7574d8e9a0..e90e8905ed4 100644 --- a/vtr_flow/arch/timing/k6_N10_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/k6_N10_gate_boost_0.2V_22nm.xml @@ -65,60 +65,68 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk - clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk - + + + + + + + + + + + + + clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk + clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N10_legacy_45nm.xml b/vtr_flow/arch/timing/k6_N10_legacy_45nm.xml index f242c90968e..dd835d48420 100644 --- a/vtr_flow/arch/timing/k6_N10_legacy_45nm.xml +++ b/vtr_flow/arch/timing/k6_N10_legacy_45nm.xml @@ -16,30 +16,34 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N10_mem32K_40nm.xml b/vtr_flow/arch/timing/k6_N10_mem32K_40nm.xml index c6922800705..9c13d117698 100644 --- a/vtr_flow/arch/timing/k6_N10_mem32K_40nm.xml +++ b/vtr_flow/arch/timing/k6_N10_mem32K_40nm.xml @@ -79,54 +79,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N10_mem32K_40nm_fc_abs.xml b/vtr_flow/arch/timing/k6_N10_mem32K_40nm_fc_abs.xml index 1d17aa21021..f33b0d5f600 100644 --- a/vtr_flow/arch/timing/k6_N10_mem32K_40nm_fc_abs.xml +++ b/vtr_flow/arch/timing/k6_N10_mem32K_40nm_fc_abs.xml @@ -79,54 +79,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N10_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/k6_N10_ripple_chain_gate_boost_0.2V_22nm.xml index 9098d3e59e0..9d04d14090d 100644 --- a/vtr_flow/arch/timing/k6_N10_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/k6_N10_ripple_chain_gate_boost_0.2V_22nm.xml @@ -69,9 +69,9 @@ to isolate one chain from the next - - - + + + @@ -80,66 +80,74 @@ to isolate one chain from the next - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk - clb.cin - clb.cout clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk - + + + + + + + + + + + + + + + + + + clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk + clb.cin + clb.cout clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N10_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/k6_N10_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml index a0750e38154..28ddddac682 100644 --- a/vtr_flow/arch/timing/k6_N10_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/k6_N10_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml @@ -78,66 +78,74 @@ carry chain from Safeen's CMOS ripple carry adder not gate boosted - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk - clb.cin - clb.cout clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk - + + + + + + + + + + + + + + + + + + clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk + clb.cin + clb.cout clb.O[0] clb.O[1] clb.O[2] clb.O[3] clb.O[4] clb.O[5] clb.O[6] clb.O[7] clb.O[8] clb.O[9] clb.I1 clb.I3 clb.I2 clb.I4 clb.clk + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N8_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/k6_N8_gate_boost_0.2V_22nm.xml index 5c0a12ea2d0..32985911798 100644 --- a/vtr_flow/arch/timing/k6_N8_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/k6_N8_gate_boost_0.2V_22nm.xml @@ -65,60 +65,68 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] - + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml index 4ac176270d8..83624069cd3 100644 --- a/vtr_flow/arch/timing/k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml @@ -72,9 +72,9 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - + + + @@ -83,66 +83,74 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml index aed96671546..d8cfddf9e6e 100644 --- a/vtr_flow/arch/timing/k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml @@ -86,66 +86,74 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml index c22b29c4e3a..3c9ea658e22 100644 --- a/vtr_flow/arch/timing/k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml @@ -83,66 +83,74 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml b/vtr_flow/arch/timing/k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml index 268dcf4b638..d016e607b1f 100644 --- a/vtr_flow/arch/timing/k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml +++ b/vtr_flow/arch/timing/k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml @@ -74,9 +74,9 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - + + + @@ -85,66 +85,74 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell. - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - - clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk - clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout - clb.cin - + + + + + + + + + + + + + + + + + + clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk + clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout + clb.cin + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_frac_N10_40nm.xml b/vtr_flow/arch/timing/k6_frac_N10_40nm.xml index 4da00d67a14..3350c13c1e3 100644 --- a/vtr_flow/arch/timing/k6_frac_N10_40nm.xml +++ b/vtr_flow/arch/timing/k6_frac_N10_40nm.xml @@ -26,30 +26,34 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml b/vtr_flow/arch/timing/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml index 0ef615a3aa4..edb7f9da706 100644 --- a/vtr_flow/arch/timing/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml +++ b/vtr_flow/arch/timing/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml @@ -85,9 +85,9 @@ - - - + + + @@ -96,61 +96,69 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml b/vtr_flow/arch/timing/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml index bd2264a60ac..98b91be1d7c 100644 --- a/vtr_flow/arch/timing/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml +++ b/vtr_flow/arch/timing/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml @@ -85,9 +85,9 @@ - - - + + + @@ -96,61 +96,69 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml index 4594c649609..12c62c90fa5 100644 --- a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml +++ b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml @@ -149,62 +149,70 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml index cead76b744f..b8d26348a0a 100644 --- a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml +++ b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml @@ -158,59 +158,67 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml index f7adb5ed34d..7f8fac49055 100644 --- a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml +++ b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml @@ -158,67 +158,75 @@ - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml index b4cc4086b65..5697d86fcc9 100644 --- a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml +++ b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml @@ -158,59 +158,67 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml index fa729857e30..5b2bf6e8137 100644 --- a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml +++ b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml @@ -147,9 +147,9 @@ - - - + + + @@ -158,67 +158,75 @@ - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k6_frac_N10_mem32K_40nm.xml b/vtr_flow/arch/timing/k6_frac_N10_mem32K_40nm.xml index aaab5da733f..a037181a6fe 100644 --- a/vtr_flow/arch/timing/k6_frac_N10_mem32K_40nm.xml +++ b/vtr_flow/arch/timing/k6_frac_N10_mem32K_40nm.xml @@ -133,54 +133,62 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/soft_fpu_arch_timing.xml b/vtr_flow/arch/timing/soft_fpu_arch_timing.xml index 42e5b5e8db5..e920edec7d1 100755 --- a/vtr_flow/arch/timing/soft_fpu_arch_timing.xml +++ b/vtr_flow/arch/timing/soft_fpu_arch_timing.xml @@ -7,30 +7,34 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - + + + + + + + + + + diff --git a/vtr_flow/arch/timing/soft_fpu_arch_timing_chain.xml b/vtr_flow/arch/timing/soft_fpu_arch_timing_chain.xml index 8854fc2242a..45a71ca737b 100644 --- a/vtr_flow/arch/timing/soft_fpu_arch_timing_chain.xml +++ b/vtr_flow/arch/timing/soft_fpu_arch_timing_chain.xml @@ -18,36 +18,40 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/xc6vlx240tff1156.xml b/vtr_flow/arch/timing/xc6vlx240tff1156.xml index d47950af431..96da93f65e6 100644 --- a/vtr_flow/arch/timing/xc6vlx240tff1156.xml +++ b/vtr_flow/arch/timing/xc6vlx240tff1156.xml @@ -77,192 +77,202 @@ - - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/titan/stratixiv_arch.timing.xml b/vtr_flow/arch/titan/stratixiv_arch.timing.xml index 1e0895ebc54..4ae23ff4c72 100644 --- a/vtr_flow/arch/titan/stratixiv_arch.timing.xml +++ b/vtr_flow/arch/titan/stratixiv_arch.timing.xml @@ -7,12 +7,12 @@ which appear to be consistent with the Stratix IV Handbook. --> - - - - + + + + - + @@ -799,28 +799,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -830,28 +830,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -861,28 +861,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -892,28 +892,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -923,28 +923,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -954,28 +954,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -985,28 +985,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1016,28 +1016,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1047,28 +1047,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1078,28 +1078,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1109,28 +1109,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1140,28 +1140,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1171,28 +1171,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1202,28 +1202,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1233,28 +1233,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1264,28 +1264,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1295,28 +1295,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1326,28 +1326,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1357,28 +1357,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1388,28 +1388,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1419,28 +1419,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1450,28 +1450,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1481,28 +1481,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1512,28 +1512,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1543,28 +1543,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1574,28 +1574,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1605,28 +1605,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -1636,28 +1636,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -2811,28 +2811,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -2842,28 +2842,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -2925,28 +2925,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -2956,28 +2956,28 @@ - - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -3066,7 +3066,7 @@ - + @@ -3099,13 +3099,13 @@ - - - - + + + + - - + + @@ -3162,16 +3162,16 @@ - - - - - - - + + + + + + + - - + + @@ -3237,16 +3237,16 @@ - - - - - - - + + + + + + + - - + + @@ -3312,16 +3312,16 @@ - - - - - - - + + + + + + + - - + + @@ -3387,18 +3387,18 @@ - - - - - - - - - + + + + + + + + + - - + + @@ -3474,22 +3474,22 @@ - - - - - - - - - - - - - + + + + + + + + + + + + + - - + + @@ -3581,19 +3581,19 @@ - - - - - - - - - - + + + + + + + + + + - - + + @@ -3672,23 +3672,23 @@ - - - - - - - - - - - - - - + + + + + + + + + + + + + + - - + + @@ -3783,18 +3783,18 @@ - - - - - - - - - + + + + + + + + + - - + + @@ -3866,17 +3866,17 @@ - - - - - - - - + + + + + + + + - - + + @@ -4155,18 +4155,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -4410,16 +4410,17 @@ - - - - - - - - - - - io.core_in[0:24] io.core_out[0:19] io.clk[0:2] - io.core_in[24:49] io.core_out[20:39] io.clk[3:4] - io.core_in[0:24] io.core_out[0:19] io.clk[0:2] - io.core_in[24:49] io.core_out[20:39] io.clk[3:4] - + io.core_in[0:24] io.core_out[0:19] io.clk[0:2] + io.core_in[24:49] io.core_out[20:39] io.clk[3:4] + io.core_in[0:24] io.core_out[0:19] io.clk[0:2] + io.core_in[24:49] io.core_out[20:39] io.clk[3:4] + + - - - - - - - - - - PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal - PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal - PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal - PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal - + + + + + + + + + + + PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal + PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal + PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal + PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal + + - - - - - - - - - - - - - - - - - + + + - - - - LAB.data_in[0:39] LAB.control_in[0:3] LAB.data_out[0:19] LAB.clk[0] - LAB.data_in[40:79] LAB.control_in[4:6] LAB.data_out[20:39] LAB.clk[1] - LAB.data_in LAB.control_in LAB.data_out LAB.clk LAB.cin LAB.sharein - LAB.cout LAB.shareout - + LAB.data_in[0:39] LAB.control_in[0:3] LAB.data_out[0:19] LAB.clk[0] + LAB.data_in[40:79] LAB.control_in[4:6] LAB.data_out[20:39] LAB.clk[1] + LAB.data_in LAB.control_in LAB.data_out LAB.clk LAB.cin LAB.sharein + LAB.cout LAB.shareout + + - - - - - - - - - - - - - - - - - - - - + - - DSP.data_in[35:0] DSP.control_in[2:0] DSP.scan_a_in[1:0] DSP.clk[0] DSP.data_out_top[17:0] DSP.scan_a_out[1:0] - DSP.data_in[71:36] DSP.control_in[4:3] DSP.scan_a_in[4:2] DSP.data_out_top[35:18] DSP.scan_a_out[3:2] DSP.signal_out[0:0] - DSP.data_in[107:72] DSP.control_in[6:5] DSP.scan_a_in[6:5] DSP.clk[1] DSP.data_out_top[53:36] DSP.scan_a_out[5:4] DSP.signal_out[1:1] - DSP.data_in[144:108] DSP.control_in[8:6] DSP.scan_a_in[8:7] DSP.data_out_top[71:54] DSP.scan_a_out[7:6] DSP.signal_out[2:2] - DSP.data_in[143:72] DSP.control_in[3:0] DSP.scan_a_in[3:0] DSP.clk[0] DSP.data_out_top[35:0] DSP.scan_a_out[3:0] DSP.signal_out[0:0] DSP.chain_in - DSP.data_in[71:0] DSP.control_in[8:4] DSP.scan_a_in[8:4] DSP.clk[1] DSP.data_out_top[71:36] DSP.scan_a_out[9:4] DSP.signal_out[2:1] - - - - DSP.data_in[179:145] DSP.control_in[11:9] DSP.scan_a_in[10:9] DSP.clk[2] DSP.data_out_bot[17:0] DSP.scan_a_out[9:8] - DSP.data_in[215:180] DSP.control_in[13:12] DSP.scan_a_in[12:11] DSP.data_out_bot[35:18] DSP.scan_a_out[11:10] DSP.signal_out[3:3] - DSP.data_in[251:216] DSP.control_in[15:14] DSP.scan_a_in[14:13] DSP.data_out_bot[53:36] DSP.scan_a_out[13:12] DSP.signal_out[4:4] - DSP.data_in[287:252] DSP.control_in[20:16] DSP.scan_a_in[17:15] DSP.clk[3] DSP.data_out_bot[71:54] DSP.scan_a_out[15:14] DSP.signal_out[5:5] - DSP.data_in[287:215] DSP.control_in[13:9] DSP.scan_a_in[13:9] DSP.clk[2] DSP.data_out_bot[35:0] DSP.scan_a_out[12:10] DSP.signal_out[3:3] - DSP.data_in[214:144] DSP.control_in[20:16] DSP.scan_a_in[17:14] DSP.clk[3] DSP.data_out_bot[71:36] DSP.scan_a_out[17:13] DSP.signal_out[5:4] - - DSP.chain_out - + + DSP.data_in[35:0] DSP.control_in[2:0] DSP.scan_a_in[1:0] DSP.clk[0] DSP.data_out_top[17:0] DSP.scan_a_out[1:0] + DSP.data_in[71:36] DSP.control_in[4:3] DSP.scan_a_in[4:2] DSP.data_out_top[35:18] DSP.scan_a_out[3:2] DSP.signal_out[0:0] + DSP.data_in[107:72] DSP.control_in[6:5] DSP.scan_a_in[6:5] DSP.clk[1] DSP.data_out_top[53:36] DSP.scan_a_out[5:4] DSP.signal_out[1:1] + DSP.data_in[144:108] DSP.control_in[8:6] DSP.scan_a_in[8:7] DSP.data_out_top[71:54] DSP.scan_a_out[7:6] DSP.signal_out[2:2] + DSP.data_in[143:72] DSP.control_in[3:0] DSP.scan_a_in[3:0] DSP.clk[0] DSP.data_out_top[35:0] DSP.scan_a_out[3:0] DSP.signal_out[0:0] DSP.chain_in + DSP.data_in[71:0] DSP.control_in[8:4] DSP.scan_a_in[8:4] DSP.clk[1] DSP.data_out_top[71:36] DSP.scan_a_out[9:4] DSP.signal_out[2:1] + + + + DSP.data_in[179:145] DSP.control_in[11:9] DSP.scan_a_in[10:9] DSP.clk[2] DSP.data_out_bot[17:0] DSP.scan_a_out[9:8] + DSP.data_in[215:180] DSP.control_in[13:12] DSP.scan_a_in[12:11] DSP.data_out_bot[35:18] DSP.scan_a_out[11:10] DSP.signal_out[3:3] + DSP.data_in[251:216] DSP.control_in[15:14] DSP.scan_a_in[14:13] DSP.data_out_bot[53:36] DSP.scan_a_out[13:12] DSP.signal_out[4:4] + DSP.data_in[287:252] DSP.control_in[20:16] DSP.scan_a_in[17:15] DSP.clk[3] DSP.data_out_bot[71:54] DSP.scan_a_out[15:14] DSP.signal_out[5:5] + DSP.data_in[287:215] DSP.control_in[13:9] DSP.scan_a_in[13:9] DSP.clk[2] DSP.data_out_bot[35:0] DSP.scan_a_out[12:10] DSP.signal_out[3:3] + DSP.data_in[214:144] DSP.control_in[20:16] DSP.scan_a_in[17:14] DSP.clk[3] DSP.data_out_bot[71:36] DSP.scan_a_out[17:13] DSP.signal_out[5:4] + + DSP.chain_out + + - - - - - - - - - - - - - M9K.data_addr_control_in[51:0] M9K.data_out[17:0] M9K.control_out[1:0] M9K.clk_in[0] - M9K.data_addr_control_in[103:52] M9K.data_out[35:18] M9K.control_out[2:2] M9K.clk_in[1] - M9K.data_addr_control_in M9K.data_out M9K.control_out M9K.clk_in - - + M9K.data_addr_control_in[51:0] M9K.data_out[17:0] M9K.control_out[1:0] M9K.clk_in[0] + M9K.data_addr_control_in[103:52] M9K.data_out[35:18] M9K.control_out[2:2] M9K.clk_in[1] + M9K.data_addr_control_in M9K.data_out M9K.control_out M9K.clk_in + + + - - - - - - - - - - - - - M144K.data_addr_control_in[24:0] M144K.data_out[7:0] - M144K.data_addr_control_in[50:25] M144K.data_out[15:8] - M144K.data_addr_control_in[76:51] M144K.data_out[22:16] - M144K.data_addr_control_in[102:77] M144K.data_out[29:23] - M144K.data_addr_control_in[128:103] M144K.data_out[36:30] M144K.control_out[0] M144K.clk_in[0] - M144K.data_addr_control_in[154:129] M144K.data_out[43:37] M144K.control_out[1] - M144K.data_addr_control_in[180:155] M144K.data_out[51:44] - M144K.data_addr_control_in[206:181] M144K.data_out[59:52] - M144K.data_addr_control_in[232:207] M144K.data_out[67:60] - M144K.data_addr_control_in[258:233] M144K.data_out[75:68] - M144K.data_addr_control_in[284:259] M144K.data_out[82:76] - M144K.data_addr_control_in[310:285] M144K.data_out[89:83] M144K.control_out[2] - M144K.data_addr_control_in[336:311] M144K.data_out[96:90] M144K.clk_in[1] - M144K.data_addr_control_in[362:337] M144K.data_out[103:97] - M144K.data_addr_control_in[388:363] M144K.data_out[111:104] - M144K.data_addr_control_in[415:389] M144K.data_out[119:112] - M144K.data_addr_control_in[51:0] M144K.data_out[14:0] - M144K.data_addr_control_in[103:52] M144K.data_out[29:15] - M144K.data_addr_control_in[155:104] M144K.data_out[44:30] M144K.control_out[0] - M144K.data_addr_control_in[207:156] M144K.data_out[59:45] M144K.control_out[1] M144K.clk_in[0] - M144K.data_addr_control_in[259:208] M144K.data_out[74:60] M144K.control_out[2] M144K.clk_in[1] - M144K.data_addr_control_in[311:260] M144K.data_out[89:75] - M144K.data_addr_control_in[363:312] M144K.data_out[104:90] - M144K.data_addr_control_in[415:364] M144K.data_out[119:105] - - - - - - - - - + M144K.data_addr_control_in[24:0] M144K.data_out[7:0] + M144K.data_addr_control_in[50:25] M144K.data_out[15:8] + M144K.data_addr_control_in[76:51] M144K.data_out[22:16] + M144K.data_addr_control_in[102:77] M144K.data_out[29:23] + M144K.data_addr_control_in[128:103] M144K.data_out[36:30] M144K.control_out[0] M144K.clk_in[0] + M144K.data_addr_control_in[154:129] M144K.data_out[43:37] M144K.control_out[1] + M144K.data_addr_control_in[180:155] M144K.data_out[51:44] + M144K.data_addr_control_in[206:181] M144K.data_out[59:52] + M144K.data_addr_control_in[232:207] M144K.data_out[67:60] + M144K.data_addr_control_in[258:233] M144K.data_out[75:68] + M144K.data_addr_control_in[284:259] M144K.data_out[82:76] + M144K.data_addr_control_in[310:285] M144K.data_out[89:83] M144K.control_out[2] + M144K.data_addr_control_in[336:311] M144K.data_out[96:90] M144K.clk_in[1] + M144K.data_addr_control_in[362:337] M144K.data_out[103:97] + M144K.data_addr_control_in[388:363] M144K.data_out[111:104] + M144K.data_addr_control_in[415:389] M144K.data_out[119:112] + M144K.data_addr_control_in[51:0] M144K.data_out[14:0] + M144K.data_addr_control_in[103:52] M144K.data_out[29:15] + M144K.data_addr_control_in[155:104] M144K.data_out[44:30] M144K.control_out[0] + M144K.data_addr_control_in[207:156] M144K.data_out[59:45] M144K.control_out[1] M144K.clk_in[0] + M144K.data_addr_control_in[259:208] M144K.data_out[74:60] M144K.control_out[2] M144K.clk_in[1] + M144K.data_addr_control_in[311:260] M144K.data_out[89:75] + M144K.data_addr_control_in[363:312] M144K.data_out[104:90] + M144K.data_addr_control_in[415:364] M144K.data_out[119:105] + + + + + + + + + + diff --git a/vtr_flow/benchmarks/microbenchmarks/sub_tiles.blif b/vtr_flow/benchmarks/microbenchmarks/sub_tiles.blif new file mode 100644 index 00000000000..6a1218dfa0b --- /dev/null +++ b/vtr_flow/benchmarks/microbenchmarks/sub_tiles.blif @@ -0,0 +1,28 @@ +.model top +.inputs in_0 in_1 in_2 in_3 in_4 in_5 in_6 +.outputs out_0 out_1 out_2 out_3 out_4 out_5 out_6 +.names $false +.names $true +1 +.subckt IO_0 in=in_0 out=wire_0 +.subckt IO_1 in=wire_1 out=out_0 + +.subckt IO_0 in=in_1 out=wire_1 +.subckt IO_1 in=wire_1 out=out_1 + +.subckt IO_1 in=in_2 out=wire_2 +.subckt IO_3 in=wire_2 out=out_2 + +.subckt IO_1 in=in_3 out=wire_3 +.subckt IO_2 in=wire_3 out=out_3 + +.subckt IO_0 in=in_4 out=wire_4 +.subckt IO_3 in=wire_4 out=out_4 + +.subckt IO_3 in=in_5 out=wire_5 +.subckt IO_2 in=wire_5 out=out_5 + +.subckt IO_1 in=in_6 out=wire_6 +.subckt IO_1 in=wire_6 out=out_6 + +.end diff --git a/vtr_flow/scripts/upgrade_arch.py b/vtr_flow/scripts/upgrade_arch.py index 17d27bd8dfa..5869aa47380 100755 --- a/vtr_flow/scripts/upgrade_arch.py +++ b/vtr_flow/scripts/upgrade_arch.py @@ -42,6 +42,7 @@ def __init__(self): "add_missing_comb_model_internal_timing_edges", "add_tile_tags", "add_site_directs", + "add_sub_tiles", ] def parse_args(): @@ -150,6 +151,11 @@ def main(): if result: modified = True + if "add_sub_tiles" in args.features: + result = add_sub_tiles(arch) + if result: + modified = True + if modified: if args.debug: root.write(sys.stdout, pretty_print=args.pretty) @@ -1025,5 +1031,76 @@ def add_site_directs(arch): return True +def add_sub_tiles(arch): + """ + This function adds the sub tiles tags to the input architecture. + Each physical tile must contain at least one sub tile. + + Note: the example below is only for explanatory reasons, the port/tile names are invented. + + BEFORE: + + + + + + + + + + + + + + AFTER: + + + + + + + + + + + + + + + + """ + + TAGS_TO_SWAP = ['fc', 'pinlocations', 'input', 'output', 'clock', 'equivalent_sites'] + + def swap_tags(sub_tile, tile): + # Moving tags from top level pb_type to tile + for child in tile: + if child.tag in TAGS_TO_SWAP: + tile.remove(child) + sub_tile.append(child) + + modified = False + + for tile in arch.iter('tile'): + if tile.findall('./sub_tile'): + continue + + sub_tile_name = tile.attrib['name'] + sub_tile = ET.Element('sub_tile', name='{}'.format(sub_tile_name)) + + # Transfer capacity to sub tile + if 'capacity' in tile.attrib.keys(): + sub_tile.attrib['capacity'] = tile.attrib['capacity'] + del tile.attrib['capacity'] + + #Transfer tags to swap from tile to sub tile + swap_tags(sub_tile, tile) + + tile.append(sub_tile) + + modified = True + + return modified + if __name__ == "__main__": main() diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/k6_frac_N10_mem32K_40nm_clk_buf.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/k6_frac_N10_mem32K_40nm_clk_buf.xml index fbd951a970e..a741ef8d227 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/k6_frac_N10_mem32K_40nm_clk_buf.xml +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/k6_frac_N10_mem32K_40nm_clk_buf.xml @@ -91,7 +91,6 @@ - @@ -100,7 +99,6 @@ - @@ -110,7 +108,6 @@ - @@ -153,63 +150,73 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + @@ -328,12 +335,11 @@ - - + @@ -344,7 +350,7 @@ - + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml index f7752f6f7ac..4b7840140df 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml @@ -91,7 +91,6 @@ - @@ -100,7 +99,6 @@ - @@ -110,7 +108,6 @@ - @@ -118,15 +115,13 @@ - - - + + - @@ -136,7 +131,6 @@ - @@ -179,91 +173,99 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + @@ -383,62 +385,53 @@ - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + - - - - - + + + + - @@ -446,7 +439,6 @@ - @@ -456,32 +448,31 @@ - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - + @@ -492,7 +483,7 @@ - + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/k6_frac_N10_mem32K_40nm_clk_pll_valid.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/k6_frac_N10_mem32K_40nm_clk_pll_valid.xml index 34340272bf8..a259fd1a37d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/k6_frac_N10_mem32K_40nm_clk_pll_valid.xml +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/k6_frac_N10_mem32K_40nm_clk_pll_valid.xml @@ -91,7 +91,6 @@ - @@ -100,7 +99,6 @@ - @@ -110,7 +108,6 @@ - @@ -118,7 +115,6 @@ - @@ -126,7 +122,6 @@ - @@ -136,7 +131,6 @@ - @@ -179,91 +173,99 @@ - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + - - - - - - - + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - + + + + + + + + + + + + + + @@ -383,89 +385,80 @@ - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + - - - - - + + + + - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - + @@ -476,7 +469,7 @@ - + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/config.txt new file mode 100644 index 00000000000..dc63ac20d84 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/config.txt @@ -0,0 +1,27 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/microbenchmarks + +# Path to directory of architectures to use +archs_dir=arch/sub_tiles + +# Add circuits to list to sweep +circuit_list_add=sub_tiles.blif + +# Add architectures to list to sweep +arch_list_add=sub_tiles.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Script parameters +script_params=-track_memory_usage -lut_size 1 -starting_stage vpr diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt new file mode 100644 index 00000000000..f2bbe2ba396 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time +sub_tiles.xml sub_tiles.blif common 2.58 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 v8.0.0-rc2-1568-g7a7333ca8-dirty success acomodi /data/vtr-symbiflow/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/run015/sub_tiles.xml/sub_tiles.blif/common 38400 1 1 3 4 0 3 4 3 3 9 -1 auto 0.00 6 2.22 3.85145 -3.85145 -3.85145 1 3 2 14813.4 29626.8 -1 -1 0.01 3 2 4 4 432 283 3.85145 -3.85145 -3.85145 0 0 -1 -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index c43a2e144ff..98719d2d176 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -62,3 +62,4 @@ regression_tests/vtr_reg_strong/strong_clock_aliases regression_tests/vtr_reg_strong/strong_graphics_commands regression_tests/vtr_reg_strong/strong_clock_pll regression_tests/vtr_reg_strong/strong_place_effort_scaling +regression_tests/vtr_reg_strong/strong_sub_tiles