diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst
index c5f932049d2..364f6275c14 100644
--- a/doc/src/vpr/command_line_usage.rst
+++ b/doc/src/vpr/command_line_usage.rst
@@ -182,6 +182,17 @@ General Options
 
      **Default:** ``ideal``
 
+.. option:: --two_stage_clock_routing {on | off}
+
+    Routes clock nets in two stages using a dedicated clock network.
+
+     * First stage: From the net source (e.g. an I/O pin) to a dedicated clock network root (e.g. center of chip)
+     * Second stage: From the clock network root to net sinks.
+
+    Note this option only works when specifying a clock architecture, see :ref:`Clock Architecture Format <clock_architecture_format>`; it does not work when reading a routing resource graph (i.e. :option:`--read_rr_graph`).
+
+     **Default:** ``off``
+
 .. option:: --exit_before_pack {on | off}
 
     Causes VPR to exit before packing starts (useful for statistics collection).