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Constants generated in VTR/VPR (i.e. vcc and gnd in BLIF file) are currently NOT routed through the fabric. This is done because it is assumed pins can be arbitrarily tied high/low, and so there is no need to route these signals.
There are two related issues.
gnd and vcc constants are packed into LUTs and placed even though by default they are not routed.
Some FPGA architectures must generate and route constants from LUTs; there is no hardware to tie pins high low.
Solution
Add a command line option to allow for routing constants. All that this needs to do is toggle the execution of the loop at base/check_netlist.cpp:90
Ensure that constant generators are NOT packed and placed if they are not routed.
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Problem
Constants generated in VTR/VPR (i.e. vcc and gnd in BLIF file) are currently NOT routed through the fabric. This is done because it is assumed pins can be arbitrarily tied high/low, and so there is no need to route these signals.
There are two related issues.
Solution
Add a command line option to allow for routing constants. All that this needs to do is toggle the execution of the loop at base/check_netlist.cpp:90
Ensure that constant generators are NOT packed and placed if they are not routed.
The text was updated successfully, but these errors were encountered: