Cell parameters in post P&R verilog

[mkurc-ant]

Cell parameters representation is not correctly preserved during the whole synthesis + P&R flow resulting them having incorrect values in post P&N verilog file.

This may not be strictly a VPR issue but solving it may require enhancing it.

Expected Behaviour

A parameter of a cell in a design preserves its type and bit width throughout the whole synthesis + P&R flow.

Current Behaviour

Cell parameters expressed as binary numbers (eg. 4'b1010) end up in post P&R verilog netlis as integers (eg. 1010`). This renders any post P&R simulation impossible.

The journey of a parameter value through Yosys synthesis + VPR P&R flow looks like following:

1. Input Verilog netlist
   For example a cell of type LUT may have a 1-bit wide INIT parameter set to 0110100101100001:

   LUT #(.INIT(16'b0110100101100001)) my_lut (...);
   

   The parameter is provided as an integer expressed in binary form.

2. Synthesized EBLIF netlist
   Yosys stores EBLIF parameters either as quoted strings or as binary numbers where the number of digits is equal to the desired bit width of a parameter:

   .subckt LUT ...
   .param INIT 0110100101100001
   .cname my_lut
   

3. VPR preserves the parameter as it is throuought the P&R flow. The only place where it value matters is in the genfasm utility. genfasm binds each bit with its corresponding bit of an assigned multi-bit FASM feature.

4. VPR writes post P&R verilog netlist where the parameter values are assigned as they are:

   LUT #(.INIT(0110100101100001)) my_lut (...);
   

   Here the binary value is written as decimal which is obviously incorrect.

Possible Solution

I'm not entirely sure how this issue should be solved and whether at Yosys or VPR side. But I have a couple of ideas:

1. Modify EBLIF output in Yosys so that it can write 16'b0110100101100001 instead of 0110100101100001
   Not sure though is there any "standard" for the extended BLIF and what it has to say about cell parameter types. This approach would also require modifying VPR (or just genfasm) to understand 16'b-like prefix.

2. Make VPR assume that all non-string cell parameters in EBLIF are binary integers. Use the knowledge to prepend appropriate prefix during post P&R verilog writeout.

3. Others ?

Steps to Reproduce

Context

QuickLogic architectures use custom cells for LUTs (not .names) which have INIT parameters mapped to FASM features. I want to make post P&R simulation of VPR-generated netlists possible.

Your Environment

• VTR revision used:
• Operating System and version:
• Compiler version:

[mkurc-ant]

EBLIF specification (the only I could find) is in the VPR documentation: https://docs.verilogtorouting.org/en/latest/vpr/file_formats/#param

Yosys BLIF/EBLIF writeout code:

• https://github.com/YosysHQ/yosys/blob/73d611990d7f39b4e14ffc367c646686f0d2b209/backends/blif/blif.cc#L160
• https://github.com/YosysHQ/yosys/blob/73d611990d7f39b4e14ffc367c646686f0d2b209/kernel/rtlil.cc#L274