VPR fail on check_net

[eshellko]

There is a design with generated clock. VPR fails during check_net in read_blif.c.
It happen when clock generated using combo logic (.names) like this:

.names ctrl main_clk gate_clk
01 1

During search foreach net
for (i = 0; i < num_logical_nets; i++) {
Every connected pin checked
for (j = 0; j <= vpack_net[i].num_sinks; j++) {
And for every global net index of clock, connected to logic block get

                    if (vpack_net[i].is_global) {
                        L_check_net = logical_block[iblk].clock_net;

And then check made that clock_net for logic block equal to index of currently checked net (i).
if (L_check_net != i) {
But in case of .names there is not clock_net assigned to logic block and L_check_net = -1 @(OPEN). In some cases report message vpack_net[L_check_net].name uses -1 out-of-bound index and causes seg-fault.

                        "You have a signal that enters both clock ports and normal input ports.\n"
                                "Input net for block %s #%d is net %s #%d but connecting net is %s #%d.\n",
                        logical_block[iblk].name, iblk,
                        vpack_net[L_check_net].name, L_check_net,
                        vpack_net[i].name, i);

Depending of many factors this out-of-bound access can produce message like this:

Input net for block gate_clk #9 is net (null) #-1 but connecting net is main_clk #0.

My propose is to add check for L_check_net == OPEN and produce different log messages in this case.

[kmurray]

Various updates to VPR have fixed this issue.

For the above example VPR now reports:

Warning 2: Inferred implicit clock source gate_clk.out[0] for netlist clock gate_clk (possibly data used as clock)
Warning 3: Timing edge from gate_clk.in[0] to gate_clk.out[0] will not be created since gate_clk.out[0] has been identified as a clock generator
Warning 4: Timing edge from gate_clk.in[1] to gate_clk.out[0] will not be created since gate_clk.out[0] has been identified as a clock generator