Error 1: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][0] #38441 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 2: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][8] #38449 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 3: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|read_capture_clk_div2[5] #38490 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 4: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|read_buffering[5].read_subgroup[0].wraddress[1] #38491 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 5: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][3] #38529 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 6: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][11] #38537 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 7: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][2] #38561 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 8: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][10] #38569 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 9: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][1] #38593 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 10: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][9] #38601 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 11: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][4] #38625 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 12: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][12] #38633 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 13: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][14] #38657 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 14: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][13] #38665 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 15: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][15] #38673 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 16: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][7] #38690 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 17: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][6] #38706 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 18: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][5] #38730 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 19: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|read_data_out[15] #101520 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 20: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|read_buffering[5].read_subgroup[0].wraddress[0] #101529 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 21: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][15] #101531 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 22: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][15] #101533 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 23: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][15] #101535 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 24: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|read_data_out[9] #101551 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 25: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][9] #101552 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 26: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][9] #101553 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 27: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][9] #101554 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 28: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|read_data_out[10] #101568 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 29: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][10] #101569 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 30: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][10] #101570 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 31: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][10] #101571 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 32: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|read_data_out[14] #101617 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 33: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][14] #101618 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 34: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][14] #101619 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 35: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][14] #101620 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 36: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|read_data_out[11] #101632 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 37: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|read_data_out[12] #101671 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 38: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][12] #101672 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 39: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][12] #101673 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 40: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][12] #101674 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 41: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|read_data_out[13] #101700 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 42: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][13] #101701 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 43: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][13] #101702 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 44: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][13] #101703 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 45: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][11] #102024 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 46: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][11] #102025 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 47: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][11] #102026 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 48: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|read_data_out[8] #102733 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 49: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][2] #106101 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 50: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][2] #106102 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 51: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][2] #106103 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 52: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][3] #108028 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 53: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][3] #108029 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 54: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][3] #108030 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 55: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][4] #108557 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 56: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][4] #108558 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 57: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][4] #108559 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 58: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][5] #108638 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 59: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][5] #108639 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 60: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][5] #108640 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 61: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][6] #109948 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 62: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][6] #109949 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 63: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][6] #109950 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 64: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][7] #109985 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 65: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][7] #109986 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 66: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][7] #109987 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 67: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][0] #123572 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 68: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][0] #123573 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 69: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][0] #123574 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 70: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][8] #179962 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 71: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][8] #179963 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 72: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][8] #179964 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 73: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[2][1] #195841 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 74: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[1][1] #195842 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 75: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[3][1] #195843 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 76: 
Type: Blif file
File: SRC/base/read_blif.c
Line: 128
Message: Found 75 fatal errors in the input netlist.

/var/spool/pbs/mom_priv/jobs/13818.master17.phanpy.gent.vsc.SC: line 11: logout: not login shell: use `exit'