Error 1:
Type: Packing
File: SRC/pack/output_clustering.c
Line: 47
Message: in print_string: String DirectRFTest_and_DPD_SV_DirectRFDesign_DSPBA:theDirectRFTest_and_DPD_SV_DirectRFDesign_DSPBA|DirectRFTest_and_DPD_SV_DirectRFDesign_DSPBA_DPD_Stage:theDirectRFTest_and_DPD_SV_DirectRFDesign_DSPBA_DPD_Stage|DirectRFTest_and_DPD_SV_DirectRFDesign_DSPBA_DPD_Stage_Forward_path3:theDirectRFTest_and_DPD_SV_DirectRFDesign_DSPBA_DPD_Stage_Forward_path3|dspba_delay:ld_reg_Forward_path_middelstage3_Lower_0_to_Forward_path_middelstage3_Mult3_aR_x_bI_Forward_path_middelstage3_Mult3_I_add_Forward_path_middelstage3_Mult3_aI_x_bR_merged_Forward_path_middelstage3_Add_I_add_Forward_path_middelstage3_Mult2_aR_x_bI_Forward_path_middelstage3_Mult2_I_add_Forward_path_middelstage3_Mult2_aI_x_bR_merged_merged_cma_10_q_to_Forward_path_middelstage3_Mult3_aR_x_bI_Forward_path_middelstage3_Mult3_I_add_Forward_path_middelstage3_Mult3_aI_x_bR_merged_Forward_path_middelstage3_Add_I_add_Forward_path_middelstage3_Mult2_aR_x_bI_Forward_path_middelstage3_Mult2_I_add_Forward_path_middelstage3_Mult2_aI_x_bR_merged_merged_cma_k|delay_signals[0][15] is too long for desired maximum line length.

Error 1: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][0] #38441 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 2: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][8] #38449 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 3: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|read_capture_clk_div2[5] #38490 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 4: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|read_buffering[5].read_subgroup[0].wraddress[1] #38491 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 5: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][3] #38529 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 6: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][11] #38537 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 7: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][2] #38561 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 8: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][10] #38569 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 9: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][1] #38593 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 10: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][9] #38601 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 11: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][4] #38625 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 12: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][12] #38633 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 13: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][14] #38657 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 14: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][13] #38665 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.
Error 15: You have a signal that enters both clock ports and normal input ports.
Input net for block ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_read_datapath:uread_datapath|ddr_p0_flop_mem:read_buffering[5].read_subgroup[0].uread_fifo|data_stored[0][15] #38673 is net (null) #-1 but connecting net is ddr:ddr_inst|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_pads:uio_pads|ddr_p0_altdqdqs:dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|dqsbusout #212424.