module top(
input clk,
input ena,
input aclr,
input [15:0] ax,
input [7:0] ay,
input [15:0] bx,
input [7:0] by,
input [63:0] chainin,
output [63:0] chainout,
output reg [23:0] resulta
); 

wire [10:0] mode;
assign mode = 11'b1010_1010_011;

int_sop_2 mac_component (
 .mode_sigs(mode),
 .clk(clk),
 .reset(aclr),
 .ax(ax),
 .ay(ay),
 .bx(bx),
 .by(by),
 .chainin(chainin),
 .resulta(resulta),
 .chainout(chainout)
); 

always@(posedge clk) begin 

resulta <= resulta + ax + 2'b10; 

end

endmodule