=============================================
    Verilog-to-Routing Regression Testing    
=============================================

Running vtr_reg_strong
-------------------------------------------------------------------------------
scripts/run_vtr_task.pl -short_task_names -l /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt -script run_vtr_flow.py 

cin_tie_off:              k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4 --circuit_file mult_4x4.pre-vpr.blif --min_route_chan_width_hint 26
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 12.54 seconds)
cin_tie_off:              k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9 --circuit_file mult_9x9.pre-vpr.blif --min_route_chan_width_hint 52
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 16.73 seconds)
soft_multipliers:         k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4 --circuit_file mult_4x4.pre-vpr.blif
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.52 seconds)
soft_multipliers:         k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5 --circuit_file mult_5x5.pre-vpr.blif
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 28.49 seconds)
soft_multipliers:         k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6 --circuit_file mult_6x6.pre-vpr.blif
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 25.12 seconds)
soft_multipliers:         k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7 --circuit_file mult_7x7.pre-vpr.blif
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 14.27 seconds)
soft_multipliers:         k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8 --circuit_file mult_8x8.pre-vpr.blif
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 16.40 seconds)
soft_multipliers:         k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9 --circuit_file mult_9x9.pre-vpr.blif
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 30.61 seconds)
two_chains:               k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2 --circuit_file diffeq2.pre-vpr.blif --min_route_chan_width_hint 60
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 80.90 seconds)
dedicated_clock:          timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml mkPktMerge --circuit_file mkPktMerge.pre-vpr.blif --clock_modeling dedicated_network --min_route_chan_width_hint 36
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 73.03 seconds)
dedicated_clock:          timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml mkPktMerge --circuit_file mkPktMerge.pre-vpr.blif --clock_modeling dedicated_network --min_route_chan_width_hint 36
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 74.37 seconds)
dedicated_clock:          timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml mkPktMerge --circuit_file mkPktMerge.pre-vpr.blif --clock_modeling dedicated_network --min_route_chan_width_hint 40
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 74.85 seconds)
titan:                    stratixiv_arch.timing.xml/ucsb_152_tap_fir_stratixiv_arch_timing.blif/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing --circuit_file ucsb_152_tap_fir_stratixiv_arch_timing.pre-vpr.blif --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/benchmarks/titan_other_blif/ucsb_152_tap_fir_stratixiv_arch_timing.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 374.06 seconds)
no_timing:                k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common		OK (took 8.84 seconds)
mcnc:                     k4_N4_90nm.xml/diffeq.blif/common                     		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k4_N4_90nm.xml diffeq --circuit_file diffeq.pre-vpr.blif --min_route_chan_width_hint 24
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 38.42 seconds)
mcnc:                     k4_N4_90nm.xml/ex5p.blif/common                       		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k4_N4_90nm.xml ex5p --circuit_file ex5p.pre-vpr.blif --min_route_chan_width_hint 36
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 85.61 seconds)
mcnc:                     k4_N4_90nm.xml/s298.blif/common                       		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k4_N4_90nm.xml s298 --circuit_file s298.pre-vpr.blif --min_route_chan_width_hint 26
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 54.78 seconds)
flyover_wires:            shorted_flyover_wires.xml/raygentop.v/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr shorted_flyover_wires.xml raygentop --circuit_file raygentop.pre-vpr.blif --min_route_chan_width_hint 66
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 80.69 seconds)
flyover_wires:            buffered_flyover_wires.xml/raygentop.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr buffered_flyover_wires.xml raygentop --circuit_file raygentop.pre-vpr.blif --min_route_chan_width_hint 68
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 86.22 seconds)
custom_pin_locs:          k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics --circuit_file ch_intrinsics.pre-vpr.blif --min_route_chan_width_hint 50
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 10.86 seconds)
custom_switch_block:      k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/ch_intrinsics.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics --circuit_file ch_intrinsics.pre-vpr.blif --route_chan_width 200 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 12.94 seconds)
custom_grid:              fixed_grid.xml/raygentop.v/common                     		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr fixed_grid.xml raygentop --circuit_file raygentop.pre-vpr.blif --min_route_chan_width_hint 50
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 98.71 seconds)
custom_grid:              column_io.xml/raygentop.v/common                      		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr column_io.xml raygentop --circuit_file raygentop.pre-vpr.blif --min_route_chan_width_hint 52
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 152.24 seconds)
custom_grid:              multiwidth_blocks.xml/raygentop.v/common              		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr multiwidth_blocks.xml raygentop --circuit_file raygentop.pre-vpr.blif --min_route_chan_width_hint 66
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 79.84 seconds)
custom_grid:              non_column.xml/raygentop.v/common                     		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr non_column.xml raygentop --circuit_file raygentop.pre-vpr.blif --min_route_chan_width_hint 42
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 170.60 seconds)
custom_grid:              non_column_tall_aspect_ratio.xml/raygentop.v/common   		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr non_column_tall_aspect_ratio.xml raygentop --circuit_file raygentop.pre-vpr.blif --min_route_chan_width_hint 48
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 144.88 seconds)
custom_grid:              non_column_wide_aspect_ratio.xml/raygentop.v/common   		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr non_column_wide_aspect_ratio.xml raygentop --circuit_file raygentop.pre-vpr.blif --min_route_chan_width_hint 46
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 137.46 seconds)
custom_grid:              custom_sbloc.xml/raygentop.v/common                   		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr custom_sbloc.xml raygentop --circuit_file raygentop.pre-vpr.blif --min_route_chan_width_hint 64
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 85.70 seconds)
custom_grid:              multiple_io_types.xml/raygentop.v/common              		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr multiple_io_types.xml raygentop --circuit_file raygentop.pre-vpr.blif --min_route_chan_width_hint 54
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 554.02 seconds)
place_delay_model:        stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr stratixiv_arch.timing.xml styr --circuit_file styr.pre-vpr.blif --place_delay_model delta --min_route_chan_width_hint 18
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 44.66 seconds)
place_delay_model:        stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr stratixiv_arch.timing.xml styr --circuit_file styr.pre-vpr.blif --place_delay_model delta_override --min_route_chan_width_hint 18
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 44.96 seconds)
place_delay_calc_method:  stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr stratixiv_arch.timing.xml styr --circuit_file styr.pre-vpr.blif --place_delay_model delta --place_delta_delay_matrix_calculation_method astar --min_route_chan_width_hint 18
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 45.36 seconds)
place_delay_calc_method:  stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr stratixiv_arch.timing.xml styr --circuit_file styr.pre-vpr.blif --place_delay_model delta_override --place_delta_delay_matrix_calculation_method astar --min_route_chan_width_hint 18
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 44.99 seconds)
place_delay_calc_method:  stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr stratixiv_arch.timing.xml styr --circuit_file styr.pre-vpr.blif --place_delay_model delta --place_delta_delay_matrix_calculation_method dijkstra --min_route_chan_width_hint 16
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 47.65 seconds)
place_delay_calc_method:  stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr stratixiv_arch.timing.xml styr --circuit_file styr.pre-vpr.blif --place_delay_model delta_override --place_delta_delay_matrix_calculation_method dijkstra --min_route_chan_width_hint 20
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 47.30 seconds)
fracturable_luts:         k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common		OK (took 11.77 seconds)
fpu_hard_block_arch:      hard_fpu_arch_timing.xml/mm3.v/common                 		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr hard_fpu_arch_timing.xml mm3 --circuit_file mm3.pre-vpr.blif --route_chan_width 72 --cluster_seed_type max_inputs --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 16.04 seconds)
timing:                   k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common    		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_mem32K_40nm.xml ch_intrinsics --circuit_file ch_intrinsics.pre-vpr.blif --min_route_chan_width_hint 50
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 10.68 seconds)
depop:                    k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B --circuit_file mkSMAdapter4B.pre-vpr.blif --min_route_chan_width_hint 80
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 95.73 seconds)
router_init_timing:       k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_all_critical		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml ex5p --circuit_file ex5p.pre-vpr.blif --route_chan_width 80 --router_lookahead map --router_initial_timing all_critical --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 9.37 seconds)
router_init_timing:       k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_lookahead		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml ex5p --circuit_file ex5p.pre-vpr.blif --route_chan_width 80 --router_lookahead map --router_initial_timing lookahead --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 10.93 seconds)
router_update_lb_delays:  k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_off		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml ex5p --circuit_file ex5p.pre-vpr.blif --route_chan_width 70 --router_update_lower_bound_delays off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 9.18 seconds)
router_update_lb_delays:  k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_on		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml ex5p --circuit_file ex5p.pre-vpr.blif --route_chan_width 70 --router_update_lower_bound_delays on --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 10.14 seconds)
power:                    k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common    		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_mem32K_40nm.xml ch_intrinsics --circuit_file ch_intrinsics.pre-vpr.blif --min_route_chan_width_hint 52 --power --tech_properties /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tech/PTM_45nm/45nm.xml
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 17.65 seconds)
power:                    k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_mem32K_40nm.xml diffeq1 --circuit_file diffeq1.pre-vpr.blif --min_route_chan_width_hint 48 --power --tech_properties /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tech/PTM_45nm/45nm.xml
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 49.65 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/const_true.blif/common           		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml const_true --circuit_file const_true.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.45 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/const_false.blif/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml const_false --circuit_file const_false.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.44 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/always_true.blif/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml always_true --circuit_file always_true.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.44 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/always_false.blif/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml always_false --circuit_file always_false.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.43 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/and.blif/common                  		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml and --circuit_file and.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.46 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/multiconnected_lut.blif/common   		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml multiconnected_lut --circuit_file multiconnected_lut.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.45 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/multiconnected_lut2.blif/common  		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml multiconnected_lut2 --circuit_file multiconnected_lut2.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.46 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/and_latch.blif/common            		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml and_latch --circuit_file and_latch.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.46 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/false_path_mux.blif/common       		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml false_path_mux --circuit_file false_path_mux.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.45 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/mult_2x2.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml mult_2x2 --circuit_file mult_2x2.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.47 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/mult_3x3.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml mult_3x3 --circuit_file mult_3x3.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.49 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/mult_3x4.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml mult_3x4 --circuit_file mult_3x4.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.72 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/mult_4x4.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml mult_4x4 --circuit_file mult_4x4.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.81 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/mult_5x5.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml mult_5x5 --circuit_file mult_5x5.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.95 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/mult_5x6.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml mult_5x6 --circuit_file mult_5x6.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 1.21 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/rca_1bit.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml rca_1bit --circuit_file rca_1bit.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.45 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/rca_2bit.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml rca_2bit --circuit_file rca_2bit.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.46 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/rca_3bit.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml rca_3bit --circuit_file rca_3bit.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.51 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/rca_4bit.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml rca_4bit --circuit_file rca_4bit.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.51 seconds)
func_formal_flow:         k6_frac_N10_40nm.xml/rca_5bit.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml rca_5bit --circuit_file rca_5bit.pre-vpr.blif --route_chan_width 200 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.51 seconds)
func_formal_vpr:          k6_frac_N10_40nm.xml/const_true.blif/common           		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml const_true --circuit_file const_true.pre-vpr.blif --route_chan_width 100 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.29 seconds)
func_formal_vpr:          k6_frac_N10_40nm.xml/const_false.blif/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml const_false --circuit_file const_false.pre-vpr.blif --route_chan_width 100 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.29 seconds)
func_formal_vpr:          k6_frac_N10_40nm.xml/always_true.blif/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml always_true --circuit_file always_true.pre-vpr.blif --route_chan_width 100 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.37 seconds)
func_formal_vpr:          k6_frac_N10_40nm.xml/always_false.blif/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml always_false --circuit_file always_false.pre-vpr.blif --route_chan_width 100 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.38 seconds)
func_formal_vpr:          k6_frac_N10_40nm.xml/multiconnected_lut.blif/common   		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml multiconnected_lut --circuit_file multiconnected_lut.pre-vpr.blif --route_chan_width 100 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.30 seconds)
func_formal_vpr:          k6_frac_N10_40nm.xml/multiconnected_lut2.blif/common  		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml multiconnected_lut2 --circuit_file multiconnected_lut2.pre-vpr.blif --route_chan_width 100 --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.30 seconds)
bounding_box:             k6_N10_mem32K_40nm.xml/stereovision3.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --place_algorithm bounding_box --min_route_chan_width_hint 20
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.29 seconds)
breadth_first:            k6_N10_mem32K_40nm.xml/stereovision3.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --router_algorithm breadth_first --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.02 seconds)
echo_files:               k6_N10_mem32K_40nm.xml/stereovision3.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --echo_file on --route_chan_width 40 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.19 seconds)
constant_outputs:         k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml constant_outputs_only --circuit_file constant_outputs_only.pre-vpr.blif --min_route_chan_width_hint 2
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.47 seconds)
sweep_constant_outputs:   k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml ch_intrinsics --circuit_file ch_intrinsics.pre-vpr.blif --sweep_constant_primary_outputs on --min_route_chan_width_hint 42
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 5.91 seconds)
fix_pins_random:          k6_N10_mem32K_40nm.xml/stereovision3.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --fix_pins random --min_route_chan_width_hint 22
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.26 seconds)
global_routing:           timing/k6_N10_mem32K_40nm.xml/stereovision3.v/common  		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_type global --min_route_chan_width_hint 10
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.60 seconds)
global_routing:           nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml/stereovision3.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm_nonuniform.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_type global --min_route_chan_width_hint 14
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.51 seconds)
global_routing:           nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml/stereovision3.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm_pulse.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_type global --min_route_chan_width_hint 14
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.63 seconds)
manual_annealing:         k6_frac_N10_40nm.xml/stereovision3.v/common           		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --init_t 90 --exit_t 0.001 --alpha_t 0.75 --inner_num 0.5 --min_route_chan_width_hint 36
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.77 seconds)
pack:                     k6_N10_mem32K_40nm.xml/stereovision3.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --pack
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 1.84 seconds)
pack_and_place:           k6_N10_mem32K_40nm.xml/stereovision3.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --pack --place --max_router_iterations 150 --route_chan_width 300
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.33 seconds)
fc_abs:                   k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common  		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm_fc_abs.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --min_route_chan_width_hint 16
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.61 seconds)
multiclock:               k6_frac_N10_mem32K_40nm.xml/multiclock.blif/common    		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_mem32K_40nm.xml multiclock --circuit_file multiclock.pre-vpr.blif --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/multiclock.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.71 seconds)
minimax_budgets:          k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --routing_budgets_algorithm minimax --route_chan_width 100 --max_router_iterations 150 --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/stereovision3.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.44 seconds)
scale_delay_budgets:      k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --routing_budgets_algorithm scale_delay --route_chan_width 100 --max_router_iterations 150 --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/stereovision3.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.29 seconds)
verify_rr_graph:          k4_N4_90nm.xml/stereovision3.v/common                 		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k4_N4_90nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --max_router_iterations 150 --write_rr_graph rr_graph.xml
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.01 seconds)
verify_rr_graph:          k6_frac_N10_40nm.xml/stereovision3.v/common           		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --max_router_iterations 150 --write_rr_graph rr_graph.xml
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 2.85 seconds)
verify_rr_graph_bin:      k4_N4_90nm.xml/stereovision3.v/common                 		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k4_N4_90nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --max_router_iterations 150 --write_rr_graph rr_graph.bin
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.93 seconds)
verify_rr_graph_bin:      k6_frac_N10_40nm.xml/stereovision3.v/common           		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --max_router_iterations 150 --write_rr_graph rr_graph.bin
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 2.84 seconds)
analysis_only:            k6_N10_mem32K_40nm.xml/stereovision3.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 2.99 seconds)
analysis_only:            k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.47 seconds)
route_only:               k6_N10_mem32K_40nm.xml/stereovision3.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.07 seconds)
route_only:               k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.55 seconds)
eblif_vpr:                k6_frac_N10_40nm.xml/test_eblif.eblif/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml test_eblif --circuit_file test_eblif.pre-vpr.eblif --min_route_chan_width_hint 20
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.33 seconds)
eblif_vpr:                k6_frac_N10_40nm.xml/conn_order.eblif/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml conn_order --circuit_file conn_order.pre-vpr.eblif --min_route_chan_width_hint 20
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.33 seconds)
default_fc_pinlocs:       k4_N4_90nm_default_fc_pinloc.xml/diffeq.blif/common   		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k4_N4_90nm_default_fc_pinloc.xml diffeq --circuit_file diffeq.pre-vpr.blif --min_route_chan_width_hint 24
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 38.55 seconds)
bidir:                    k4_n4_v7_bidir.xml/styr.blif/common                   		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k4_n4_v7_bidir.xml styr --circuit_file styr.pre-vpr.blif --min_route_chan_width_hint 14
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 7.28 seconds)
bidir:                    k4_n4_v7_longline_bidir.xml/styr.blif/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k4_n4_v7_longline_bidir.xml styr --circuit_file styr.pre-vpr.blif --min_route_chan_width_hint 18
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 8.20 seconds)
bidir:                    k4_n4_v7_l1_bidir.xml/styr.blif/common                		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k4_n4_v7_l1_bidir.xml styr --circuit_file styr.pre-vpr.blif --min_route_chan_width_hint 12
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 8.18 seconds)
bidir:                    k4_n4_v7_bidir_pass_gate.xml/styr.blif/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k4_n4_v7_bidir_pass_gate.xml styr --circuit_file styr.pre-vpr.blif --min_route_chan_width_hint 18
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 9.69 seconds)
detailed_timing:          k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common    		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_mem32K_40nm.xml ch_intrinsics --circuit_file ch_intrinsics.pre-vpr.blif --timing_report_detail aggregated --timing_report_skew on --min_route_chan_width_hint 50
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 11.15 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_1    		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml styr --circuit_file styr.pre-vpr.blif --target_ext_pin_util 1 --min_route_chan_width_hint 38
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.74 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_0.7  		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml styr --circuit_file styr.pre-vpr.blif --target_ext_pin_util 0.7 --min_route_chan_width_hint 38
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.72 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_0.1,0.5		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml styr --circuit_file styr.pre-vpr.blif --target_ext_pin_util 0.1,0.5 --min_route_chan_width_hint 26
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 13.97 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_0.5,0.3		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml styr --circuit_file styr.pre-vpr.blif --target_ext_pin_util 0.5,0.3 --min_route_chan_width_hint 28
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.61 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_0.0  		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml styr --circuit_file styr.pre-vpr.blif --target_ext_pin_util 0.0 --min_route_chan_width_hint 26
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 14.24 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.7		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml styr --circuit_file styr.pre-vpr.blif --target_ext_pin_util clb:0.7 --min_route_chan_width_hint 38
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.71 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.7_0.8		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml styr --circuit_file styr.pre-vpr.blif --target_ext_pin_util clb:0.7 0.8 --min_route_chan_width_hint 38
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.74 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.1_0.8		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml styr --circuit_file styr.pre-vpr.blif --target_ext_pin_util clb:0.1 0.8 --min_route_chan_width_hint 26
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 14.92 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml styr --circuit_file styr.pre-vpr.blif --target_ext_pin_util io:0.1,0.1 clb:0.7 0.8,1.0 --min_route_chan_width_hint 38
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.70 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_-0.1 		OK* (took 0.38 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_1.1  		OK* (took 0.40 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0		OK* (took 0.39 seconds)
target_pin_util:          EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0		OK* (took 0.39 seconds)
clock_modeling:           timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_40nm.xml d_flip_flop --circuit_file d_flip_flop.pre-vpr.blif --clock_modeling ideal --route_chan_width 60 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.56 seconds)
clock_modeling:           timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_40nm.xml d_flip_flop --circuit_file d_flip_flop.pre-vpr.blif --clock_modeling route --route_chan_width 60 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.53 seconds)
clock_modeling:           timing/k6_N10_mem32K_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml d_flip_flop --circuit_file d_flip_flop.pre-vpr.blif --clock_modeling ideal --route_chan_width 60 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.70 seconds)
clock_modeling:           timing/k6_N10_mem32K_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml d_flip_flop --circuit_file d_flip_flop.pre-vpr.blif --clock_modeling route --route_chan_width 60 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.69 seconds)
clock_modeling:           timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_40nm.xml mkPktMerge --circuit_file mkPktMerge.pre-vpr.blif --clock_modeling ideal --route_chan_width 60 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 6.25 seconds)
clock_modeling:           timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_40nm.xml mkPktMerge --circuit_file mkPktMerge.pre-vpr.blif --clock_modeling route --route_chan_width 60 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 6.46 seconds)
clock_modeling:           timing/k6_N10_mem32K_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml mkPktMerge --circuit_file mkPktMerge.pre-vpr.blif --clock_modeling ideal --route_chan_width 60 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 25.28 seconds)
clock_modeling:           timing/k6_N10_mem32K_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml mkPktMerge --circuit_file mkPktMerge.pre-vpr.blif --clock_modeling route --route_chan_width 60 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 26.29 seconds)
unroute_analysis:         k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_20		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml traffic --circuit_file traffic.pre-vpr.blif --pack --place --route_chan_width 20 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.58 seconds)
unroute_analysis:         k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_20_--analysis		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml traffic --circuit_file traffic.pre-vpr.blif --pack --place --route_chan_width 20 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.59 seconds)
unroute_analysis:         k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_8		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml traffic --circuit_file traffic.pre-vpr.blif --pack --place --route_chan_width 8 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: expected 'exited with return code 2' but was 'exited with return code 1' (took 0.59 seconds)
unroute_analysis:         k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_8_--analysis		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml traffic --circuit_file traffic.pre-vpr.blif --pack --place --route_chan_width 8 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: expected 'exited with return code 2' but was 'exited with return code 1' (took 0.58 seconds)
router_lookahead:         k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_classic		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml ex5p --circuit_file ex5p.pre-vpr.blif --route_chan_width 60 --router_lookahead classic --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 9.09 seconds)
router_lookahead:         k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_map		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml ex5p --circuit_file ex5p.pre-vpr.blif --route_chan_width 60 --router_lookahead map --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 9.37 seconds)
eblif_vpr_write:          arch.xml/eblif_write.eblif/common                     		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr arch.xml eblif_write --circuit_file eblif_write.pre-vpr.eblif --gen_post_synthesis_netlist on --min_route_chan_width_hint 2
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.35 seconds)
routing_modes:            arch.xml/ndff.blif/common                             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr arch.xml ndff --circuit_file ndff.pre-vpr.blif --min_route_chan_width_hint 4
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.42 seconds)
routing_differing_modes:  slicem.xml/carry_chain.blif/common                    		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr slicem.xml carry_chain --circuit_file carry_chain.pre-vpr.blif --min_route_chan_width_hint 28
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 1.71 seconds)
binary:                   k6_N10_mem32K_40nm.xml/stereovision3.v/common_--verify_binary_search_off		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --verify_binary_search off --min_route_chan_width_hint 22
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.14 seconds)
binary:                   k6_N10_mem32K_40nm.xml/stereovision3.v/common_--verify_binary_search_on		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --verify_binary_search on --min_route_chan_width_hint 22
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 5.27 seconds)
full_stats:               k6_N10_mem32K_40nm.xml/stereovision3.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --full_stats on --route_chan_width 40 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 2.93 seconds)
global_nonuniform:        x_gaussian_y_uniform.xml/stereovision3.v/common       		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr x_gaussian_y_uniform.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_type global --min_route_chan_width_hint 12
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.67 seconds)
global_nonuniform:        x_uniform_y_gaussian.xml/stereovision3.v/common       		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr x_uniform_y_gaussian.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_type global --min_route_chan_width_hint 10
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.02 seconds)
global_nonuniform:        x_gaussian_y_gaussian.xml/stereovision3.v/common      		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr x_gaussian_y_gaussian.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_type global --min_route_chan_width_hint 12
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.07 seconds)
global_nonuniform:        x_delta_y_uniform.xml/stereovision3.v/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr x_delta_y_uniform.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_type global --min_route_chan_width_hint 48
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.09 seconds)
global_nonuniform:        x_delta_y_delta.xml/stereovision3.v/common            		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr x_delta_y_delta.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_type global --min_route_chan_width_hint 48
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.20 seconds)
global_nonuniform:        x_uniform_y_delta.xml/stereovision3.v/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr x_uniform_y_delta.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_type global --min_route_chan_width_hint 38
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.10 seconds)
sdc:                      k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/A.sdc		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml multiclock --circuit_file multiclock.pre-vpr.blif --min_route_chan_width_hint 8 --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/A.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.55 seconds)
sdc:                      k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/B.sdc		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml multiclock --circuit_file multiclock.pre-vpr.blif --min_route_chan_width_hint 8 --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/B.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.51 seconds)
sdc:                      k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/C.sdc		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml multiclock --circuit_file multiclock.pre-vpr.blif --min_route_chan_width_hint 8 --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/C.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.56 seconds)
sdc:                      k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/D.sdc		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml multiclock --circuit_file multiclock.pre-vpr.blif --min_route_chan_width_hint 8 --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/D.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.58 seconds)
sdc:                      k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/E.sdc		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml multiclock --circuit_file multiclock.pre-vpr.blif --min_route_chan_width_hint 6 --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/E.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.59 seconds)
sdc:                      k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/F.sdc		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml multiclock --circuit_file multiclock.pre-vpr.blif --min_route_chan_width_hint 8 --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/F.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.57 seconds)
timing_report_detail:     k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_netlist		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock --circuit_file multiclock.pre-vpr.blif --timing_report_detail netlist --min_route_chan_width_hint 20
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.72 seconds)
timing_report_detail:     k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_aggregated		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock --circuit_file multiclock.pre-vpr.blif --timing_report_detail aggregated --min_route_chan_width_hint 20
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.73 seconds)
timing_report_detail:     k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_detailed		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock --circuit_file multiclock.pre-vpr.blif --timing_report_detail detailed --min_route_chan_width_hint 20
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.74 seconds)
route_reconverge:         k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B --circuit_file mkSMAdapter4B.pre-vpr.blif --router_max_convergence_count 3 --min_route_chan_width_hint 80
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 100.49 seconds)
clock_buf:                k6_frac_N10_mem32K_40nm_clk_buf.xml/multiclock_buf.blif/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf --circuit_file multiclock_buf.pre-vpr.blif --absorb_buffer_luts off --clustering_pin_feasibility_filter off
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 2.96 seconds)
equivalent_sites:         equivalent.xml/equivalent.blif/common                 		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr equivalent.xml equivalent --circuit_file equivalent.pre-vpr.blif --min_route_chan_width_hint 2
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.34 seconds)
absorb_buffers:           k6_frac_N10_40nm.xml/riscv_core_lut6.blif/common_--absorb_buffer_luts_on		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml riscv_core_lut6 --circuit_file riscv_core_lut6.pre-vpr.blif --pack --absorb_buffer_luts on
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 6.99 seconds)
absorb_buffers:           k6_frac_N10_40nm.xml/riscv_core_lut6.blif/common_--absorb_buffer_luts_off		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml riscv_core_lut6 --circuit_file riscv_core_lut6.pre-vpr.blif --pack --absorb_buffer_luts off
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 6.41 seconds)
clock_aliases:            timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk.sdc		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_40nm.xml clock_aliases --circuit_file clock_aliases.pre-vpr.blif --absorb_buffer_luts on --min_route_chan_width_hint 8 --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/clock_aliases/clk.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.58 seconds)
clock_aliases:            timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_40nm.xml clock_aliases --circuit_file clock_aliases.pre-vpr.blif --absorb_buffer_luts on --min_route_chan_width_hint 8 --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/clock_aliases/clk_assign.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.55 seconds)
clock_aliases:            timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_40nm.xml clock_aliases --circuit_file clock_aliases.pre-vpr.blif --absorb_buffer_luts on --min_route_chan_width_hint 8 --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/clock_aliases/counter_clk.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.56 seconds)
clock_aliases_set_delay:  timing/k6_N10_40nm.xml/clock_set_delay_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_40nm.xml clock_set_delay_aliases --circuit_file clock_set_delay_aliases.pre-vpr.blif --absorb_buffer_luts on --sdc_file /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/sdc/samples/clock_aliases/set_delay.sdc
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.52 seconds)
graphics_commands:        k6_N10_mem32K_40nm.xml/stereovision3.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --graphics_commands set_draw_block_outlines 0; set_draw_block_text 0; set_draw_block_internals 2; set_draw_net_max_fanout 128; save_graphics place.png; set_nets 1; save_graphics nets1.png; set_nets 2; save_graphics nets2.png; set_nets 0; set_cpd 1; save_graphics cpd1.png; --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 5.71 seconds)
clock_pll:                k6_frac_N10_mem32K_40nm_clk_pll_valid.xml/multiclock_buf.blif/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf --circuit_file multiclock_buf.pre-vpr.blif --absorb_buffer_luts off --clustering_pin_feasibility_filter off --route_chan_width 40 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 2.33 seconds)
clock_pll:                k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml/multiclock_buf.blif/common		OK* (took 0.16 seconds)
place_effort_scaling:     EArch.xml/ex5p.blif/common_--place_effort_scaling_circuit		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml ex5p --circuit_file ex5p.pre-vpr.blif --pack --place --place_effort_scaling circuit --max_router_iterations 150 --route_chan_width 300
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 17.35 seconds)
place_effort_scaling:     EArch.xml/ex5p.blif/common_--place_effort_scaling_device_circuit		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml ex5p --circuit_file ex5p.pre-vpr.blif --pack --place --place_effort_scaling device_circuit --max_router_iterations 150 --route_chan_width 300
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 18.06 seconds)
place_effort_scaling:     EArch.xml/ex5p.blif/common_--place_effort_scaling_circuit_--target_utilization_0.1		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml ex5p --circuit_file ex5p.pre-vpr.blif --pack --place --place_effort_scaling circuit --target_utilization 0.1 --max_router_iterations 150 --route_chan_width 300
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 45.69 seconds)
place_effort_scaling:     EArch.xml/ex5p.blif/common_--place_effort_scaling_device_circuit_--target_utilization_0.1		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr EArch.xml ex5p --circuit_file ex5p.pre-vpr.blif --pack --place --place_effort_scaling device_circuit --target_utilization 0.1 --max_router_iterations 150 --route_chan_width 300
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 52.43 seconds)
sub_tiles:                sub_tiles.xml/sub_tiles.blif/common                   		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr sub_tiles.xml sub_tiles --circuit_file sub_tiles.pre-vpr.blif --min_route_chan_width_hint 6
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 13.31 seconds)
check_route_options:      sub_tiles.xml/sub_tiles.blif/common_--check_route_full		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr sub_tiles.xml sub_tiles --circuit_file sub_tiles.pre-vpr.blif --check_route full --min_route_chan_width_hint 6
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 13.26 seconds)
check_route_options:      sub_tiles.xml/sub_tiles.blif/common_--check_route_quick		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr sub_tiles.xml sub_tiles --circuit_file sub_tiles.pre-vpr.blif --check_route quick --min_route_chan_width_hint 6
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 13.25 seconds)
check_route_options:      sub_tiles.xml/sub_tiles.blif/common_--check_route_off 		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr sub_tiles.xml sub_tiles --circuit_file sub_tiles.pre-vpr.blif --check_route off --min_route_chan_width_hint 6
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 13.29 seconds)
pack_disable:             k6_frac_N10_40nm.xml/mult_5x6.blif/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_40nm.xml mult_5x6 --circuit_file mult_5x6.pre-vpr.blif --min_route_chan_width_hint 30
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 1.20 seconds)
pack_disable:             k6_frac_N10_40nm_disable_packing.xml/mult_5x6.blif/common		OK* (took 0.20 seconds)
timing_update_type:       k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_auto		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --timing_update_type auto --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 2.99 seconds)
timing_update_type:       k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_full		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --timing_update_type full --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 3.02 seconds)
timing_update_type:       k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_incremental		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --timing_update_type incremental --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 2.79 seconds)
timing_update_type:       k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_incremental_--quench_recompute_divider_999999999		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --timing_update_type incremental --quench_recompute_divider 999999999 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 2.79 seconds)
timing_update_diff:       k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3 --circuit_file stereovision3.pre-vpr.blif --route_chan_width 100 --max_router_iterations 150
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 4.58 seconds)
blocks_with_no_inputs:    k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common         		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml ch_intrinsics --circuit_file ch_intrinsics.pre-vpr.blif --min_route_chan_width_hint 38
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 10.05 seconds)
blocks_with_no_inputs:    k6_N10_mem32K_40nm_i_or_o.xml/ch_intrinsics.v/common  		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics --circuit_file ch_intrinsics.pre-vpr.blif --min_route_chan_width_hint 32
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 238.21 seconds)
blocks_with_no_inputs:    k6_N10_mem32K_40nm.xml/diffeq1.v/common               		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml diffeq1 --circuit_file diffeq1.pre-vpr.blif --min_route_chan_width_hint 44
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 34.80 seconds)
blocks_with_no_inputs:    k6_N10_mem32K_40nm_i_or_o.xml/diffeq1.v/common        		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm_i_or_o.xml diffeq1 --circuit_file diffeq1.pre-vpr.blif --min_route_chan_width_hint 40
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 53.98 seconds)
blocks_with_no_inputs:    k6_N10_mem32K_40nm.xml/single_wire.v/common           		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml single_wire --circuit_file single_wire.pre-vpr.blif --min_route_chan_width_hint 14
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.76 seconds)
blocks_with_no_inputs:    k6_N10_mem32K_40nm_i_or_o.xml/single_wire.v/common    		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm_i_or_o.xml single_wire --circuit_file single_wire.pre-vpr.blif --min_route_chan_width_hint 4
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.81 seconds)
blocks_with_no_inputs:    k6_N10_mem32K_40nm.xml/single_ff.v/common             		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml single_ff --circuit_file single_ff.pre-vpr.blif --min_route_chan_width_hint 2
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.75 seconds)
blocks_with_no_inputs:    k6_N10_mem32K_40nm_i_or_o.xml/single_ff.v/common      		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm_i_or_o.xml single_ff --circuit_file single_ff.pre-vpr.blif --min_route_chan_width_hint 8
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 0.80 seconds)
fix_clusters:             fix_clusters_test_arch.xml/apex2.blif/common          		Error: vpr
	full command:  /usr/bin/env time -v /home/khalid88/Documents/vtr-verilog-to-routing/vpr/vpr fix_clusters_test_arch.xml apex2 --circuit_file apex2.pre-vpr.blif --fix_clusters ../../../../apex2_block_locations.place --min_route_chan_width_hint 164
	returncode  :  1
	log file    :  vpr.out
failed: vpr (took 45.66 seconds)
Elapsed time: 4259.8 seconds

Parsing test results... 
scripts/parse_vtr_task.pl -l /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt  
regression_tests/vtr_reg_strong/strong_verify_rr_graph...[Pass]
regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin...[Pass]
regression_tests/vtr_reg_strong/strong_analysis_only...[Pass]
regression_tests/vtr_reg_strong/strong_route_only...[Pass]

Checking test results... 

Calculating QoR results... 
scripts/parse_vtr_task.pl -l /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt -check_golden -calc_geomean  
regression_tests/vtr_reg_strong/strong_cin_tie_off...[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common min_chan_width_route_time: golden = 0.04 result = 8.20
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common max_vpr_mem: golden = 26016 result = 614752
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common crit_path_routed_wirelength: golden = 166 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common crit_path_routing_area_total: golden = 45067.1 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common crit_path_routing_area_per_tile: golden = 1802.68 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common critical_path_delay: golden = 3.84065 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 3.84065 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common setup_TNS: golden = -36.0874 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common setup_WNS: golden = -3.84065 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common max_vpr_mem: golden = 28404 result = 1013048
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common crit_path_routed_wirelength: golden = 980 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common crit_path_routing_area_total: golden = 143382. result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common crit_path_routing_area_per_tile: golden = 3982.83 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common critical_path_delay: golden = 5.39047 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 5.39047 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common setup_TNS: golden = -120.052 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common setup_WNS: golden = -5.39047 result = -1
regression_tests/vtr_reg_strong/strong_soft_multipliers...[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common max_vpr_mem: golden = 24292 result = 600648
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common crit_path_routed_wirelength: golden = 169 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common crit_path_routing_area_total: golden = 37105.9 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common crit_path_routing_area_per_tile: golden = 1484.24 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common critical_path_delay: golden = 2.41865 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 2.41865 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common setup_TNS: golden = -34.9802 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common setup_WNS: golden = -2.41865 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common max_vpr_mem: golden = 24492 result = 988932
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common crit_path_routed_wirelength: golden = 156 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common crit_path_routing_area_total: golden = 26343.3 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common crit_path_routing_area_per_tile: golden = 1646.46 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common critical_path_delay: golden = 3.64419 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 3.64419 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common setup_TNS: golden = -46.6251 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common setup_WNS: golden = -3.64419 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common max_vpr_mem: golden = 25360 result = 995844
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common crit_path_routed_wirelength: golden = 254 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common crit_path_routing_area_total: golden = 90821.2 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common crit_path_routing_area_per_tile: golden = 3632.85 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common critical_path_delay: golden = 3.38467 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 3.38467 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common setup_TNS: golden = -55.0874 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common setup_WNS: golden = -3.38467 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common max_vpr_mem: golden = 25616 result = 993356
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common crit_path_routed_wirelength: golden = 395 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common crit_path_routing_area_total: golden = 73020.3 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common crit_path_routing_area_per_tile: golden = 2920.81 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common critical_path_delay: golden = 3.85568 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 3.85568 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common setup_TNS: golden = -71.6886 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common setup_WNS: golden = -3.85568 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common max_vpr_mem: golden = 26020 result = 995392
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common crit_path_routed_wirelength: golden = 505 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common crit_path_routing_area_total: golden = 82390.3 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common crit_path_routing_area_per_tile: golden = 3295.61 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common critical_path_delay: golden = 5.22085 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 5.22085 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common setup_TNS: golden = -95.6248 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common setup_WNS: golden = -5.22085 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common min_chan_width_route_time: golden = 0.17 result = 2.96
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common max_vpr_mem: golden = 26564 result = 1014816
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common crit_path_routed_wirelength: golden = 755 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common crit_path_routing_area_total: golden = 146644. result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common crit_path_routing_area_per_tile: golden = 4073.44 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common critical_path_delay: golden = 5.26704 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 5.26704 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common setup_TNS: golden = -107.994 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common setup_WNS: golden = -5.26704 result = -1
regression_tests/vtr_reg_strong/strong_two_chains...[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common place_time: golden = 1.15 result = 12.31
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common max_vpr_mem: golden = 51964 result = 1011072
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common crit_path_routed_wirelength: golden = 10840 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common crit_path_routing_area_total: golden = 2.06264e+06 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common crit_path_routing_area_per_tile: golden = 6366.18 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common critical_path_delay: golden = 17.4691 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 17.4691 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common setup_TNS: golden = -1077.83 result = -1
[Fail] 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common setup_WNS: golden = -17.4691 result = -1
regression_tests/vtr_reg_strong/strong_dedicated_clock...[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network vpr_status: golden = success result = exited with return code 1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network max_vpr_mem: golden = 71668 result = 1210996
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_routed_wirelength: golden = 13986 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_routing_area_total: golden = 2.42825e+06 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_routing_area_per_tile: golden = 3097.26 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_route_time: golden = 1.74 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network critical_path_delay: golden = 4.66801 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network geomean_nonvirtual_intradomain_critical_path_delay: golden = 4.66801 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network setup_TNS: golden = -4358.27 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network setup_WNS: golden = -4.66801 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network vpr_status: golden = success result = exited with return code 1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network max_vpr_mem: golden = 73024 result = 1213040
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_routed_wirelength: golden = 13962 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_routing_area_total: golden = 2.47848e+06 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_routing_area_per_tile: golden = 3161.33 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_route_time: golden = 1.34 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network critical_path_delay: golden = 4.1019 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network geomean_nonvirtual_intradomain_critical_path_delay: golden = 4.1019 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network setup_TNS: golden = -4151.44 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network setup_WNS: golden = -4.1019 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network vpr_status: golden = success result = exited with return code 1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network max_vpr_mem: golden = 73400 result = 1213552
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_routed_wirelength: golden = 15345 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_routing_area_total: golden = 2.68809e+06 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_routing_area_per_tile: golden = 3428.68 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network crit_path_route_time: golden = 1.98 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network critical_path_delay: golden = 5.42665 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network geomean_nonvirtual_intradomain_critical_path_delay: golden = 5.42665 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network setup_TNS: golden = -4393.57 result = -1
[Fail] 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network setup_WNS: golden = -5.42665 result = -1
regression_tests/vtr_reg_strong/strong_titan...[Fail] 
 stratixiv_arch.timing.xml/ucsb_152_tap_fir_stratixiv_arch_timing.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 stratixiv_arch.timing.xml/ucsb_152_tap_fir_stratixiv_arch_timing.blif/common place_time: golden = 17.33 result = 178.35
[Fail] 
 stratixiv_arch.timing.xml/ucsb_152_tap_fir_stratixiv_arch_timing.blif/common max_vpr_mem: golden = 997336 result = 4277596
regression_tests/vtr_reg_strong/strong_no_timing...[Fail] 
 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common max_vpr_mem: golden = 36072 result = 698540
regression_tests/vtr_reg_strong/strong_mcnc...[Fail] 
 k4_N4_90nm.xml/diffeq.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k4_N4_90nm.xml/diffeq.blif/common max_vpr_mem: golden = 52456 result = 932180
[Fail] 
 k4_N4_90nm.xml/diffeq.blif/common crit_path_routed_wirelength: golden = 11171 result = -1
[Fail] 
 k4_N4_90nm.xml/diffeq.blif/common crit_path_routing_area_total: golden = 1.04508e+06 result = -1
[Fail] 
 k4_N4_90nm.xml/diffeq.blif/common crit_path_routing_area_per_tile: golden = 1975.57 result = -1
[Fail] 
 k4_N4_90nm.xml/diffeq.blif/common critical_path_delay: golden = 6.8984 result = -1
[Fail] 
 k4_N4_90nm.xml/diffeq.blif/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 6.8984 result = -1
[Fail] 
 k4_N4_90nm.xml/diffeq.blif/common setup_TNS: golden = -1482.36 result = -1
[Fail] 
 k4_N4_90nm.xml/diffeq.blif/common setup_WNS: golden = -6.8984 result = -1
[Fail] 
 k4_N4_90nm.xml/ex5p.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k4_N4_90nm.xml/ex5p.blif/common max_vpr_mem: golden = 44252 result = 938028
[Fail] 
 k4_N4_90nm.xml/ex5p.blif/common crit_path_routed_wirelength: golden = 13567 result = -1
[Fail] 
 k4_N4_90nm.xml/ex5p.blif/common crit_path_routing_area_total: golden = 1.20592e+06 result = -1
[Fail] 
 k4_N4_90nm.xml/ex5p.blif/common crit_path_routing_area_per_tile: golden = 2734.52 result = -1
[Fail] 
 k4_N4_90nm.xml/ex5p.blif/common critical_path_delay: golden = 6.73044 result = -1
[Fail] 
 k4_N4_90nm.xml/ex5p.blif/common geomean_nonvirtual_intradomain_critical_path_delay: golden = nan result = -1
[Fail] 
 k4_N4_90nm.xml/ex5p.blif/common setup_TNS: golden = -286.327 result = -1
[Fail] 
 k4_N4_90nm.xml/ex5p.blif/common setup_WNS: golden = -6.73044 result = -1
[Fail] 
 k4_N4_90nm.xml/s298.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k4_N4_90nm.xml/s298.blif/common max_vpr_mem: golden = 57704 result = 1108632
[Fail] 
 k4_N4_90nm.xml/s298.blif/common crit_path_routed_wirelength: golden = 17192 result = -1
[Fail] 
 k4_N4_90nm.xml/s298.blif/common crit_path_routing_area_total: golden = 1.43821e+06 result = -1
[Fail] 
 k4_N4_90nm.xml/s298.blif/common crit_path_routing_area_per_tile: golden = 2127.53 result = -1
[Fail] 
 k4_N4_90nm.xml/s298.blif/common critical_path_delay: golden = 11.2577 result = -1
[Fail] 
 k4_N4_90nm.xml/s298.blif/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 11.2577 result = -1
[Fail] 
 k4_N4_90nm.xml/s298.blif/common setup_TNS: golden = -91.3533 result = -1
[Fail] 
 k4_N4_90nm.xml/s298.blif/common setup_WNS: golden = -11.2577 result = -1
regression_tests/vtr_reg_strong/strong_flyover_wires...[Fail] 
 shorted_flyover_wires.xml/raygentop.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 shorted_flyover_wires.xml/raygentop.v/common max_vpr_mem: golden = 66264 result = 1280100
[Fail] 
 shorted_flyover_wires.xml/raygentop.v/common crit_path_routed_wirelength: golden = 22609 result = -1
[Fail] 
 shorted_flyover_wires.xml/raygentop.v/common crit_path_routing_area_total: golden = 1.43513e+06 result = -1
[Fail] 
 shorted_flyover_wires.xml/raygentop.v/common crit_path_routing_area_per_tile: golden = 3975.42 result = -1
[Fail] 
 shorted_flyover_wires.xml/raygentop.v/common crit_path_route_time: golden = 1.02 result = -1
[Fail] 
 shorted_flyover_wires.xml/raygentop.v/common critical_path_delay: golden = 5.32517 result = -1
[Fail] 
 shorted_flyover_wires.xml/raygentop.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 5.32517 result = -1
[Fail] 
 shorted_flyover_wires.xml/raygentop.v/common setup_TNS: golden = -2957.12 result = -1
[Fail] 
 shorted_flyover_wires.xml/raygentop.v/common setup_WNS: golden = -5.32517 result = -1
[Fail] 
 buffered_flyover_wires.xml/raygentop.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 buffered_flyover_wires.xml/raygentop.v/common max_vpr_mem: golden = 66324 result = 1309588
[Fail] 
 buffered_flyover_wires.xml/raygentop.v/common crit_path_routed_wirelength: golden = 21304 result = -1
[Fail] 
 buffered_flyover_wires.xml/raygentop.v/common crit_path_routing_area_total: golden = 1.52022e+06 result = -1
[Fail] 
 buffered_flyover_wires.xml/raygentop.v/common crit_path_routing_area_per_tile: golden = 4211.15 result = -1
[Fail] 
 buffered_flyover_wires.xml/raygentop.v/common critical_path_delay: golden = 4.95972 result = -1
[Fail] 
 buffered_flyover_wires.xml/raygentop.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 4.95972 result = -1
[Fail] 
 buffered_flyover_wires.xml/raygentop.v/common setup_TNS: golden = -3001.08 result = -1
[Fail] 
 buffered_flyover_wires.xml/raygentop.v/common setup_WNS: golden = -4.95972 result = -1
regression_tests/vtr_reg_strong/strong_custom_pin_locs...[Fail] 
 k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common max_vpr_mem: golden = 36108 result = 590424
[Fail] 
 k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common crit_path_routed_wirelength: golden = 1316 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common crit_path_routing_area_total: golden = 561550. result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common crit_path_routing_area_per_tile: golden = 3899.65 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common critical_path_delay: golden = 2.47507 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 2.47507 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common setup_TNS: golden = -237.488 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common setup_WNS: golden = -2.47507 result = -1
regression_tests/vtr_reg_strong/strong_custom_switch_block...[Fail] 
 k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/ch_intrinsics.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/ch_intrinsics.v/common max_vpr_mem: golden = 36036 result = 537836
regression_tests/vtr_reg_strong/strong_custom_grid...[Fail] 
 fixed_grid.xml/raygentop.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 fixed_grid.xml/raygentop.v/common max_vpr_mem: golden = 79440 result = 1329516
[Fail] 
 fixed_grid.xml/raygentop.v/common crit_path_routed_wirelength: golden = 22100 result = -1
[Fail] 
 fixed_grid.xml/raygentop.v/common crit_path_routing_area_total: golden = 2.70140e+06 result = -1
[Fail] 
 fixed_grid.xml/raygentop.v/common crit_path_routing_area_per_tile: golden = 4322.25 result = -1
[Fail] 
 fixed_grid.xml/raygentop.v/common critical_path_delay: golden = 4.87864 result = -1
[Fail] 
 fixed_grid.xml/raygentop.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 4.87864 result = -1
[Fail] 
 fixed_grid.xml/raygentop.v/common setup_TNS: golden = -2997.81 result = -1
[Fail] 
 fixed_grid.xml/raygentop.v/common setup_WNS: golden = -4.87864 result = -1
[Fail] 
 column_io.xml/raygentop.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 column_io.xml/raygentop.v/common min_chan_width_route_time: golden = 5.87 result = 103.22
[Fail] 
 column_io.xml/raygentop.v/common max_vpr_mem: golden = 73260 result = 1353936
[Fail] 
 column_io.xml/raygentop.v/common crit_path_routed_wirelength: golden = 21443 result = -1
[Fail] 
 column_io.xml/raygentop.v/common crit_path_routing_area_total: golden = 2.55773e+06 result = -1
[Fail] 
 column_io.xml/raygentop.v/common crit_path_routing_area_per_tile: golden = 4092.38 result = -1
[Fail] 
 column_io.xml/raygentop.v/common critical_path_delay: golden = 4.88861 result = -1
[Fail] 
 column_io.xml/raygentop.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 4.88861 result = -1
[Fail] 
 column_io.xml/raygentop.v/common setup_TNS: golden = -3042.94 result = -1
[Fail] 
 column_io.xml/raygentop.v/common setup_WNS: golden = -4.88861 result = -1
[Fail] 
 multiwidth_blocks.xml/raygentop.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 multiwidth_blocks.xml/raygentop.v/common max_vpr_mem: golden = 67544 result = 1305072
[Fail] 
 multiwidth_blocks.xml/raygentop.v/common crit_path_routed_wirelength: golden = 19187 result = -1
[Fail] 
 multiwidth_blocks.xml/raygentop.v/common crit_path_routing_area_total: golden = 1.57029e+06 result = -1
[Fail] 
 multiwidth_blocks.xml/raygentop.v/common crit_path_routing_area_per_tile: golden = 4349.83 result = -1
[Fail] 
 multiwidth_blocks.xml/raygentop.v/common critical_path_delay: golden = 4.85255 result = -1
[Fail] 
 multiwidth_blocks.xml/raygentop.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 4.85255 result = -1
[Fail] 
 multiwidth_blocks.xml/raygentop.v/common setup_TNS: golden = -2921.26 result = -1
[Fail] 
 multiwidth_blocks.xml/raygentop.v/common setup_WNS: golden = -4.85255 result = -1
[Fail] 
 non_column.xml/raygentop.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 non_column.xml/raygentop.v/common max_vpr_mem: golden = 98700 result = 1818400
[Fail] 
 non_column.xml/raygentop.v/common crit_path_routed_wirelength: golden = 25196 result = -1
[Fail] 
 non_column.xml/raygentop.v/common crit_path_routing_area_total: golden = 3.33682e+06 result = -1
[Fail] 
 non_column.xml/raygentop.v/common crit_path_routing_area_per_tile: golden = 3064.11 result = -1
[Fail] 
 non_column.xml/raygentop.v/common critical_path_delay: golden = 5.14301 result = -1
[Fail] 
 non_column.xml/raygentop.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 5.14301 result = -1
[Fail] 
 non_column.xml/raygentop.v/common setup_TNS: golden = -3217.38 result = -1
[Fail] 
 non_column.xml/raygentop.v/common setup_WNS: golden = -5.14301 result = -1
[Fail] 
 non_column_tall_aspect_ratio.xml/raygentop.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 non_column_tall_aspect_ratio.xml/raygentop.v/common max_vpr_mem: golden = 99468 result = 1813504
[Fail] 
 non_column_tall_aspect_ratio.xml/raygentop.v/common crit_path_routed_wirelength: golden = 22800 result = -1
[Fail] 
 non_column_tall_aspect_ratio.xml/raygentop.v/common crit_path_routing_area_total: golden = 3.85688e+06 result = -1
[Fail] 
 non_column_tall_aspect_ratio.xml/raygentop.v/common crit_path_routing_area_per_tile: golden = 3645.44 result = -1
[Fail] 
 non_column_tall_aspect_ratio.xml/raygentop.v/common critical_path_delay: golden = 5.24897 result = -1
[Fail] 
 non_column_tall_aspect_ratio.xml/raygentop.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 5.24897 result = -1
[Fail] 
 non_column_tall_aspect_ratio.xml/raygentop.v/common setup_TNS: golden = -3134.25 result = -1
[Fail] 
 non_column_tall_aspect_ratio.xml/raygentop.v/common setup_WNS: golden = -5.24897 result = -1
[Fail] 
 non_column_wide_aspect_ratio.xml/raygentop.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 non_column_wide_aspect_ratio.xml/raygentop.v/common max_vpr_mem: golden = 94324 result = 1791252
[Fail] 
 non_column_wide_aspect_ratio.xml/raygentop.v/common crit_path_routed_wirelength: golden = 23948 result = -1
[Fail] 
 non_column_wide_aspect_ratio.xml/raygentop.v/common crit_path_routing_area_total: golden = 3.26968e+06 result = -1
[Fail] 
 non_column_wide_aspect_ratio.xml/raygentop.v/common crit_path_routing_area_per_tile: golden = 3456.32 result = -1
[Fail] 
 non_column_wide_aspect_ratio.xml/raygentop.v/common critical_path_delay: golden = 5.14016 result = -1
[Fail] 
 non_column_wide_aspect_ratio.xml/raygentop.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 5.14016 result = -1
[Fail] 
 non_column_wide_aspect_ratio.xml/raygentop.v/common setup_TNS: golden = -3266.42 result = -1
[Fail] 
 non_column_wide_aspect_ratio.xml/raygentop.v/common setup_WNS: golden = -5.14016 result = -1
[Fail] 
 custom_sbloc.xml/raygentop.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 custom_sbloc.xml/raygentop.v/common max_vpr_mem: golden = 67116 result = 1301376
[Fail] 
 custom_sbloc.xml/raygentop.v/common crit_path_routed_wirelength: golden = 19687 result = -1
[Fail] 
 custom_sbloc.xml/raygentop.v/common crit_path_routing_area_total: golden = 1.50465e+06 result = -1
[Fail] 
 custom_sbloc.xml/raygentop.v/common crit_path_routing_area_per_tile: golden = 4168.01 result = -1
[Fail] 
 custom_sbloc.xml/raygentop.v/common critical_path_delay: golden = 4.82034 result = -1
[Fail] 
 custom_sbloc.xml/raygentop.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 4.82034 result = -1
[Fail] 
 custom_sbloc.xml/raygentop.v/common setup_TNS: golden = -3060.92 result = -1
[Fail] 
 custom_sbloc.xml/raygentop.v/common setup_WNS: golden = -4.82034 result = -1
[Fail] 
 multiple_io_types.xml/raygentop.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 multiple_io_types.xml/raygentop.v/common max_vpr_mem: golden = 418024 result = 1996332
[Fail] 
 multiple_io_types.xml/raygentop.v/common crit_path_routed_wirelength: golden = 47802 result = -1
[Fail] 
 multiple_io_types.xml/raygentop.v/common crit_path_routing_area_total: golden = 1.71824e+07 result = -1
[Fail] 
 multiple_io_types.xml/raygentop.v/common crit_path_routing_area_per_tile: golden = 3827.68 result = -1
[Fail] 
 multiple_io_types.xml/raygentop.v/common crit_path_route_time: golden = 1.01 result = -1
[Fail] 
 multiple_io_types.xml/raygentop.v/common critical_path_delay: golden = 7.06436 result = -1
[Fail] 
 multiple_io_types.xml/raygentop.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 7.06436 result = -1
[Fail] 
 multiple_io_types.xml/raygentop.v/common setup_TNS: golden = -4977.72 result = -1
[Fail] 
 multiple_io_types.xml/raygentop.v/common setup_WNS: golden = -7.06436 result = -1
regression_tests/vtr_reg_strong/strong_place_delay_model...[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta vpr_status: golden = success result = exited with return code 1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta max_vpr_mem: golden = 780580 result = 3042932
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta crit_path_routed_wirelength: golden = 593 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta crit_path_routing_area_total: golden = 84868.6 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta crit_path_routing_area_per_tile: golden = 1212.41 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta critical_path_delay: golden = 6.65205 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta geomean_nonvirtual_intradomain_critical_path_delay: golden = 6.65205 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta setup_TNS: golden = -74.8754 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta setup_WNS: golden = -6.65205 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override vpr_status: golden = success result = exited with return code 1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override max_vpr_mem: golden = 780184 result = 3044388
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override crit_path_routed_wirelength: golden = 713 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override crit_path_routing_area_total: golden = 84868.6 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override crit_path_routing_area_per_tile: golden = 1212.41 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override critical_path_delay: golden = 6.76883 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override geomean_nonvirtual_intradomain_critical_path_delay: golden = 6.76883 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override setup_TNS: golden = -76.011 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override setup_WNS: golden = -6.76883 result = -1
regression_tests/vtr_reg_strong/strong_place_delay_calc_method...[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar vpr_status: golden = success result = exited with return code 1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar max_vpr_mem: golden = 780400 result = 3043052
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar crit_path_routed_wirelength: golden = 593 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar crit_path_routing_area_total: golden = 84868.6 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar crit_path_routing_area_per_tile: golden = 1212.41 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar critical_path_delay: golden = 6.65205 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar geomean_nonvirtual_intradomain_critical_path_delay: golden = 6.65205 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar setup_TNS: golden = -74.8754 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar setup_WNS: golden = -6.65205 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar vpr_status: golden = success result = exited with return code 1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar max_vpr_mem: golden = 781148 result = 3043900
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar crit_path_routed_wirelength: golden = 713 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar crit_path_routing_area_total: golden = 84868.6 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar crit_path_routing_area_per_tile: golden = 1212.41 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar critical_path_delay: golden = 6.76883 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar geomean_nonvirtual_intradomain_critical_path_delay: golden = 6.76883 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar setup_TNS: golden = -76.011 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar setup_WNS: golden = -6.76883 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra vpr_status: golden = success result = exited with return code 1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra max_vpr_mem: golden = 780984 result = 3106216
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra crit_path_routed_wirelength: golden = 796 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra crit_path_routing_area_total: golden = 74567.7 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra crit_path_routing_area_per_tile: golden = 1065.25 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra critical_path_delay: golden = 6.72193 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra geomean_nonvirtual_intradomain_critical_path_delay: golden = 6.72193 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra setup_TNS: golden = -76.6759 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra setup_WNS: golden = -6.72193 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra vpr_status: golden = success result = exited with return code 1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra max_vpr_mem: golden = 783068 result = 3105316
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra crit_path_routed_wirelength: golden = 617 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra crit_path_routing_area_total: golden = 92858.8 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra crit_path_routing_area_per_tile: golden = 1326.55 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra critical_path_delay: golden = 6.62068 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra geomean_nonvirtual_intradomain_critical_path_delay: golden = 6.62068 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra setup_TNS: golden = -74.4118 result = -1
[Fail] 
 stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra setup_WNS: golden = -6.62068 result = -1
regression_tests/vtr_reg_strong/strong_fracturable_luts...[Fail] 
 k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common max_vpr_mem: golden = 36352 result = 610408
regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch...[Fail] 
 hard_fpu_arch_timing.xml/mm3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 hard_fpu_arch_timing.xml/mm3.v/common place_time: golden = 0.30 result = 3.16
[Fail] 
 hard_fpu_arch_timing.xml/mm3.v/common max_vpr_mem: golden = 34840 result = 867652
regression_tests/vtr_reg_strong/strong_timing...[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common max_vpr_mem: golden = 35428 result = 590276
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common crit_path_routed_wirelength: golden = 1368 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common crit_path_routing_area_total: golden = 539112. result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common crit_path_routing_area_per_tile: golden = 3743.83 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common critical_path_delay: golden = 2.56877 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 2.56877 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common setup_TNS: golden = -239.947 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common setup_WNS: golden = -2.56877 result = -1
regression_tests/vtr_reg_strong/strong_depop...[Fail] 
 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common max_vpr_mem: golden = 72028 result = 1307096
[Fail] 
 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common crit_path_routed_wirelength: golden = 18693 result = -1
[Fail] 
 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common crit_path_routing_area_total: golden = 2.64606e+06 result = -1
[Fail] 
 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common crit_path_routing_area_per_tile: golden = 6615.15 result = -1
[Fail] 
 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common critical_path_delay: golden = 4.84767 result = -1
[Fail] 
 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 4.84767 result = -1
[Fail] 
 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common setup_TNS: golden = -2845.86 result = -1
[Fail] 
 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common setup_WNS: golden = -4.84767 result = -1
regression_tests/vtr_reg_strong/strong_router_init_timing...[Fail] 
 k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_all_critical vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_all_critical max_vpr_mem: golden = 38260 result = 487504
[Fail] 
 k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_lookahead vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_lookahead place_time: golden = 0.40 result = 5.06
[Fail] 
 k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_lookahead max_vpr_mem: golden = 38368 result = 488832
regression_tests/vtr_reg_strong/strong_router_update_lb_delays...[Fail] 
 k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_off vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_off max_vpr_mem: golden = 38780 result = 485832
[Fail] 
 k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_on vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_on place_time: golden = 0.40 result = 4.97
[Fail] 
 k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_on max_vpr_mem: golden = 38900 result = 485448
regression_tests/vtr_reg_strong/strong_power...[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common max_vpr_mem: golden = 38012 result = 598076
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common crit_path_routed_wirelength: golden = 1268 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common crit_path_routing_area_total: golden = 551878. result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common crit_path_routing_area_per_tile: golden = 3832.49 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common critical_path_delay: golden = 2.26669 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 2.26669 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common setup_TNS: golden = -234.063 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common setup_WNS: golden = -2.26669 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common max_vpr_mem: golden = 48288 result = 761548
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common crit_path_routed_wirelength: golden = 10180 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common crit_path_routing_area_total: golden = 968034. result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common crit_path_routing_area_per_tile: golden = 3781.38 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common critical_path_delay: golden = 22.4129 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 22.4129 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common setup_TNS: golden = -2167.74 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common setup_WNS: golden = -22.4129 result = -1
[Fail] 
 k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common clock_power_perc: golden = 0.01655 result = 0.01421
regression_tests/vtr_reg_strong/strong_func_formal_flow...[Fail] 
 k6_frac_N10_40nm.xml/const_true.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/const_true.blif/common max_vpr_mem: golden = 19384 result = 217704
[Fail] 
 k6_frac_N10_40nm.xml/const_false.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/const_false.blif/common max_vpr_mem: golden = 19200 result = 217708
[Fail] 
 k6_frac_N10_40nm.xml/always_true.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/always_true.blif/common max_vpr_mem: golden = 19464 result = 217820
[Fail] 
 k6_frac_N10_40nm.xml/always_false.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/always_false.blif/common max_vpr_mem: golden = 19452 result = 218268
[Fail] 
 k6_frac_N10_40nm.xml/and.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/and.blif/common max_vpr_mem: golden = 19516 result = 219072
[Fail] 
 k6_frac_N10_40nm.xml/multiconnected_lut.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/multiconnected_lut.blif/common max_vpr_mem: golden = 19588 result = 218528
[Fail] 
 k6_frac_N10_40nm.xml/multiconnected_lut2.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/multiconnected_lut2.blif/common max_vpr_mem: golden = 19464 result = 218720
[Fail] 
 k6_frac_N10_40nm.xml/and_latch.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/and_latch.blif/common max_vpr_mem: golden = 19532 result = 218924
[Fail] 
 k6_frac_N10_40nm.xml/false_path_mux.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/false_path_mux.blif/common max_vpr_mem: golden = 19300 result = 218696
[Fail] 
 k6_frac_N10_40nm.xml/mult_2x2.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/mult_2x2.blif/common max_vpr_mem: golden = 19568 result = 220236
[Fail] 
 k6_frac_N10_40nm.xml/mult_3x3.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/mult_3x3.blif/common max_vpr_mem: golden = 19484 result = 220840
[Fail] 
 k6_frac_N10_40nm.xml/mult_3x4.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/mult_3x4.blif/common max_vpr_mem: golden = 20132 result = 229996
[Fail] 
 k6_frac_N10_40nm.xml/mult_4x4.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/mult_4x4.blif/common max_vpr_mem: golden = 20320 result = 231400
[Fail] 
 k6_frac_N10_40nm.xml/mult_5x5.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/mult_5x5.blif/common max_vpr_mem: golden = 20556 result = 240756
[Fail] 
 k6_frac_N10_40nm.xml/mult_5x6.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/mult_5x6.blif/common max_vpr_mem: golden = 21488 result = 247196
[Fail] 
 k6_frac_N10_40nm.xml/rca_1bit.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/rca_1bit.blif/common max_vpr_mem: golden = 19580 result = 219576
[Fail] 
 k6_frac_N10_40nm.xml/rca_2bit.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/rca_2bit.blif/common max_vpr_mem: golden = 19544 result = 219412
[Fail] 
 k6_frac_N10_40nm.xml/rca_3bit.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/rca_3bit.blif/common max_vpr_mem: golden = 19516 result = 220708
[Fail] 
 k6_frac_N10_40nm.xml/rca_4bit.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/rca_4bit.blif/common max_vpr_mem: golden = 19552 result = 221476
[Fail] 
 k6_frac_N10_40nm.xml/rca_5bit.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/rca_5bit.blif/common max_vpr_mem: golden = 19584 result = 221664
regression_tests/vtr_reg_strong/strong_func_formal_vpr...[Fail] 
 k6_frac_N10_40nm.xml/const_true.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/const_true.blif/common max_vpr_mem: golden = 19160 result = 217252
[Fail] 
 k6_frac_N10_40nm.xml/const_false.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/const_false.blif/common max_vpr_mem: golden = 19108 result = 217696
[Fail] 
 k6_frac_N10_40nm.xml/always_true.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/always_true.blif/common max_vpr_mem: golden = 20012 result = 234484
[Fail] 
 k6_frac_N10_40nm.xml/always_false.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/always_false.blif/common max_vpr_mem: golden = 20108 result = 234076
[Fail] 
 k6_frac_N10_40nm.xml/multiconnected_lut.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/multiconnected_lut.blif/common max_vpr_mem: golden = 19164 result = 218632
[Fail] 
 k6_frac_N10_40nm.xml/multiconnected_lut2.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/multiconnected_lut2.blif/common max_vpr_mem: golden = 19080 result = 218672
regression_tests/vtr_reg_strong/strong_bounding_box...[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common max_vpr_mem: golden = 28704 result = 319168
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common crit_path_routed_wirelength: golden = 571 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common crit_path_routing_area_total: golden = 65453.8 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common crit_path_routing_area_per_tile: golden = 1335.79 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common critical_path_delay: golden = 2.58874 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 2.37064 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common setup_TNS: golden = -190.862 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common setup_WNS: golden = -2.58874 result = -1
regression_tests/vtr_reg_strong/strong_breadth_first...[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common max_vpr_mem: golden = 28652 result = 304624
regression_tests/vtr_reg_strong/strong_echo_files...[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common max_vpr_mem: golden = 27508 result = 311216
regression_tests/vtr_reg_strong/strong_constant_outputs...[Fail] 
 k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common max_vpr_mem: golden = 25076 result = 237148
[Fail] 
 k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common crit_path_routed_wirelength: golden = 0 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common crit_path_routing_area_total: golden = 1342.00 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common crit_path_routing_area_per_tile: golden = 83.8749 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common critical_path_delay: golden = nan result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common geomean_nonvirtual_intradomain_critical_path_delay: golden = nan result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common setup_TNS: golden = 0 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common setup_WNS: golden = 0 result = -1
regression_tests/vtr_reg_strong/strong_sweep_constant_outputs...[Fail] 
 k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common max_vpr_mem: golden = 30424 result = 445288
[Fail] 
 k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common crit_path_routed_wirelength: golden = 1097 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common crit_path_routing_area_total: golden = 165046. result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common crit_path_routing_area_per_tile: golden = 2578.84 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common critical_path_delay: golden = 2.1112 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 2.1112 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common setup_TNS: golden = -216.052 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common setup_WNS: golden = -2.1112 result = -1
regression_tests/vtr_reg_strong/strong_fix_pins_random...[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common max_vpr_mem: golden = 29336 result = 325656
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common crit_path_routed_wirelength: golden = 719 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common crit_path_routing_area_total: golden = 69322.2 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common crit_path_routing_area_per_tile: golden = 1414.74 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common critical_path_delay: golden = 2.65665 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 2.40886 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common setup_TNS: golden = -195.159 result = -1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common setup_WNS: golden = -2.65665 result = -1
regression_tests/vtr_reg_strong/strong_global_routing...[Fail] 
 timing/k6_N10_mem32K_40nm.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 timing/k6_N10_mem32K_40nm.xml/stereovision3.v/common max_vpr_mem: golden = 27316 result = 315596
[Fail] 
 timing/k6_N10_mem32K_40nm.xml/stereovision3.v/common crit_path_routed_wirelength: golden = 322 result = -1
[Fail] 
 timing/k6_N10_mem32K_40nm.xml/stereovision3.v/common critical_path_delay: golden = 1.93141 result = -1
[Fail] 
 timing/k6_N10_mem32K_40nm.xml/stereovision3.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 1.88461 result = -1
[Fail] 
 timing/k6_N10_mem32K_40nm.xml/stereovision3.v/common setup_TNS: golden = -141.327 result = -1
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml/stereovision3.v/common max_vpr_mem: golden = 27144 result = 312408
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml/stereovision3.v/common crit_path_routed_wirelength: golden = 324 result = -1
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml/stereovision3.v/common critical_path_delay: golden = 1.93141 result = -1
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml/stereovision3.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 1.88461 result = -1
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml/stereovision3.v/common setup_TNS: golden = -141.327 result = -1
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml/stereovision3.v/common max_vpr_mem: golden = 27188 result = 310332
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml/stereovision3.v/common crit_path_routed_wirelength: golden = 353 result = -1
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml/stereovision3.v/common critical_path_delay: golden = 1.93141 result = -1
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml/stereovision3.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 1.88461 result = -1
[Fail] 
 nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml/stereovision3.v/common setup_TNS: golden = -141.327 result = -1
regression_tests/vtr_reg_strong/strong_manual_annealing...[Fail] 
 k6_frac_N10_40nm.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_40nm.xml/stereovision3.v/common max_vpr_mem: golden = 23524 result = 309512
[Fail] 
 k6_frac_N10_40nm.xml/stereovision3.v/common crit_path_routed_wirelength: golden = 545 result = -1
[Fail] 
 k6_frac_N10_40nm.xml/stereovision3.v/common crit_path_routing_area_total: golden = 80896.3 result = -1
[Fail] 
 k6_frac_N10_40nm.xml/stereovision3.v/common crit_path_routing_area_per_tile: golden = 2247.12 result = -1
[Fail] 
 k6_frac_N10_40nm.xml/stereovision3.v/common critical_path_delay: golden = 2.50329 result = -1
[Fail] 
 k6_frac_N10_40nm.xml/stereovision3.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 2.28128 result = -1
[Fail] 
 k6_frac_N10_40nm.xml/stereovision3.v/common setup_TNS: golden = -182.979 result = -1
[Fail] 
 k6_frac_N10_40nm.xml/stereovision3.v/common setup_WNS: golden = -2.50329 result = -1
regression_tests/vtr_reg_strong/strong_pack...[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common max_vpr_mem: golden = 27252 result = 264976
regression_tests/vtr_reg_strong/strong_pack_and_place...[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm.xml/stereovision3.v/common max_vpr_mem: golden = 28084 result = 302980
regression_tests/vtr_reg_strong/strong_fc_abs...[Fail] 
 k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common max_vpr_mem: golden = 30384 result = 324112
[Fail] 
 k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common crit_path_routed_wirelength: golden = 502 result = -1
[Fail] 
 k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common crit_path_routing_area_total: golden = 104221. result = -1
[Fail] 
 k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common crit_path_routing_area_per_tile: golden = 2126.97 result = -1
[Fail] 
 k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common critical_path_delay: golden = 2.88672 result = -1
[Fail] 
 k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common geomean_nonvirtual_intradomain_critical_path_delay: golden = 2.66584 result = -1
[Fail] 
 k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common setup_TNS: golden = -203.092 result = -1
[Fail] 
 k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common setup_WNS: golden = -2.88672 result = -1
regression_tests/vtr_reg_strong/strong_multiclock...[Pass]
regression_tests/vtr_reg_strong/strong_minimax_budgets...[Fail] 
 k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common max_vpr_mem: golden = 31620 result = 518424
regression_tests/vtr_reg_strong/strong_scale_delay_budgets...[Fail] 
 k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common vpr_status: golden = success result = exited with return code 1
[Fail] 
 k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common max_vpr_mem: golden = 30972 result = 515436
regression_tests/vtr_reg_strong/strong_verify_rr_graph...[Pass]
regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin...[Pass]
regression_tests/vtr_reg_strong/strong_analysis_only...[Pass]
regression_tests/vtr_reg_strong/strong_route_only...[Pass]

Test 'vtr_reg_strong' had 234 qor test failures

Test 'vtr_reg_strong' had 179 run failures

Test complete

Error: 413 tests failed!