/usr/bin/env time -v /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/../vpr/vpr k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2 --circuit_file diffeq2.pre-vpr.blif --timing_update_type incremental --max_logged_overused_rr_nodes 50 --route_chan_width 32 --generate_rr_node_overuse_report off VPR FPGA Placement and Routing. Version: 8.1.0-dev+db47f5d97-dirty Revision: v8.0.0-2239-gdb47f5d97-dirty Compiled: 2020-07-29T19:33:46 Compiler: GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 Build Info: release VTR_ASSERT_LEVEL=2 University of Toronto verilogtorouting.org vtr-users@googlegroups.com This is free open source code under MIT license. VPR was run with the following command-line: /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/../vpr/vpr k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2 --circuit_file diffeq2.pre-vpr.blif --timing_update_type incremental --max_logged_overused_rr_nodes 50 --route_chan_width 32 --generate_rr_node_overuse_report off Using up to 1 parallel worker(s) Architecture file: k6_frac_N10_frac_chain_mem32K_40nm.xml Circuit name: diffeq2 # Loading Architecture Description # Loading Architecture Description took 0.01 seconds (max_rss 14.8 MiB, delta_rss +1.2 MiB) # Building complex block graph Warning 1: io[0].clock[0] unconnected pin in architecture. # Building complex block graph took 0.02 seconds (max_rss 20.7 MiB, delta_rss +5.9 MiB) # Load circuit Found constant-zero generator 'unconn' Found constant-one generator 'vcc' Found constant-zero generator 'gnd' # Load circuit took 0.01 seconds (max_rss 22.6 MiB, delta_rss +2.0 MiB) # Clean circuit Absorbed 96 LUT buffers Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs Inferred 12 additional primitive pins as constant generators due to constant inputs Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs Inferred 0 additional primitive pins as constant generators due to constant inputs Swept input(s) : 0 Swept output(s) : 0 (0 dangling, 0 constant) Swept net(s) : 284 Swept block(s) : 0 Constant Pins Marked: 12 # Clean circuit took 0.00 seconds (max_rss 22.6 MiB, delta_rss +0.0 MiB) # Compress circuit # Compress circuit took 0.00 seconds (max_rss 22.6 MiB, delta_rss +0.0 MiB) # Verify circuit # Verify circuit took 0.00 seconds (max_rss 22.6 MiB, delta_rss +0.0 MiB) Circuit Statistics: Blocks: 607 .input : 66 .latch : 96 .output : 96 0-LUT : 2 6-LUT : 198 adder : 142 multiply: 7 Nets : 866 Avg Fanout: 2.0 Max Fanout: 96.0 Min Fanout: 1.0 Netlist Clocks: 1 # Build Timing Graph Timing Graph Nodes: 2638 Timing Graph Edges: 18014 Timing Graph Levels: 78 # Build Timing Graph took 0.01 seconds (max_rss 24.6 MiB, delta_rss +1.6 MiB) Netlist contains 1 clocks Netlist Clock 'diffeq_f_systemC^clk' Fanout: 96 pins (3.6%), 96 blocks (15.8%) # Load Timing Constraints SDC file 'diffeq2.sdc' not found Setting default timing constraints: * constrain all primay inputs and primary outputs on netlist clock 'diffeq_f_systemC^clk' * optimize netlist clock to run as fast as possible Timing constraints created 1 clocks Constrained Clock 'diffeq_f_systemC^clk' Source: 'diffeq_f_systemC^clk.inpad[0]' # Load Timing Constraints took 0.00 seconds (max_rss 24.6 MiB, delta_rss +0.0 MiB) Timing analysis: ON Circuit netlist file: diffeq2.net Circuit placement file: diffeq2.place Circuit routing file: diffeq2.route Circuit SDC file: diffeq2.sdc Packer: ENABLED Placer: ENABLED Router: ENABLED Analysis: ENABLED NetlistOpts.abosrb_buffer_luts : true NetlistOpts.sweep_dangling_primary_ios : true NetlistOpts.sweep_dangling_nets : true NetlistOpts.sweep_dangling_blocks : true NetlistOpts.sweep_constant_primary_outputs: false NetlistOpts.netlist_verbosity : 1 NetlistOpts.const_gen_inference : COMB_SEQ PackerOpts.allow_unrelated_clustering: auto PackerOpts.alpha_clustering: 0.750000 PackerOpts.beta_clustering: 0.900000 PackerOpts.cluster_seed_type: BLEND2 PackerOpts.connection_driven: true PackerOpts.global_clocks: true PackerOpts.hill_climbing_flag: false PackerOpts.inter_cluster_net_delay: 1.000000 PackerOpts.timing_driven: true PackerOpts.target_external_pin_util: auto PlacerOpts.place_freq: PLACE_ONCE PlacerOpts.place_algorithm: PATH_TIMING_DRIVEN_PLACE PlacerOpts.pad_loc_type: FREE PlacerOpts.place_cost_exp: 1.000000 PlacerOpts.place_chan_width: 32 PlacerOpts.inner_loop_recompute_divider: 0 PlacerOpts.recompute_crit_iter: 1 PlacerOpts.timing_tradeoff: 0.500000 PlacerOpts.td_place_exp_first: 1.000000 PlacerOpts.td_place_exp_last: 8.000000 PlacerOpts.delay_offset: 0.000000 PlacerOpts.delay_ramp_delta_threshold: -1 PlacerOpts.delay_ramp_slope: 330440800 PlacerOpts.tsu_rel_margin: 1.000000 PlacerOpts.tsu_abs_margin: 0.000000 PlacerOpts.post_place_timing_report_file: PlacerOpts.allowed_tiles_for_delay_model: PlacerOpts.delay_model_reducer: MIN PlacerOpts.delay_model_type: DELTA PlacerOpts.rlim_escape_fraction: 0.000000 PlacerOpts.move_stats_file: PlacerOpts.placement_saves_per_temperature: 0 PlacerOpts.effort_scaling: CIRCUIT PlacerOpts.place_delta_delay_matrix_calculation_method: ASTAR_ROUTE PlaceOpts.seed: 1 AnnealSched.type: AUTO_SCHED AnnealSched.inner_num: 1.000000 RouterOpts.route_type: DETAILED RouterOpts.router_algorithm: TIMING_DRIVEN RouterOpts.base_cost_type: DELAY_NORMALIZED_LENGTH RouterOpts.fixed_channel_width: 32 RouterOpts.check_route: FULL RouterOpts.trim_empty_chan: false RouterOpts.trim_obs_chan: false RouterOpts.acc_fac: 1.000000 RouterOpts.bb_factor: 3 RouterOpts.bend_cost: 0.000000 RouterOpts.first_iter_pres_fac: 0.000000 RouterOpts.initial_pres_fac: 0.500000 RouterOpts.pres_fac_mult: 1.300000 RouterOpts.max_router_iterations: 50 RouterOpts.min_incremental_reroute_fanout: 16 RouterOpts.do_check_rr_graph: true RouterOpts.verify_binary_search: false RouterOpts.min_channel_width_hint: 0 RouterOpts.read_rr_edge_metadata: false RouterOpts.exit_after_first_routing_iteration: false RouterOpts.astar_fac: 1.200000 RouterOpts.criticality_exp: 1.000000 RouterOpts.max_criticality: 0.990000 RouterOpts.init_wirelength_abort_threshold: 0.850000 RouterOpts.save_routing_per_iteration: false RouterOpts.congested_routing_iteration_threshold_frac: 1.000000 RouterOpts.high_fanout_threshold: 64 RouterOpts.router_debug_net: -2 RouterOpts.router_debug_sink_rr: -2 RouterOpts.router_debug_iteration: -2 RouterOpts.max_convergence_count: 1 RouterOpts.reconvergence_cpd_threshold: 0.990000 RouterOpts.update_lower_bound_delays: true RouterOpts.first_iteration_timing_report_file: RouterOpts.incr_reroute_delay_ripup: AUTO RouterOpts.route_bb_update: DYNAMIC RouterOpts.lookahead_type: MAP RouterOpts.initial_timing: LOOKAHEAD RouterOpts.router_heap: BINARY_HEAP RouterOpts.routing_failure_predictor = SAFE RouterOpts.routing_budgets_algorithm = DISABLE AnalysisOpts.gen_post_synthesis_netlist: false AnalysisOpts.timing_report_npaths: 100 AnalysisOpts.timing_report_skew: false AnalysisOpts.echo_dot_timing_graph_node: -1 AnalysisOpts.timing_report_detail: NETLIST RoutingArch.directionality: UNI_DIRECTIONAL RoutingArch.switch_block_type: WILTON RoutingArch.Fs: 3 # Packing Begin packing 'diffeq2.pre-vpr.blif'. After removing unused inputs... total blocks: 607, total nets: 866, total inputs: 66, total outputs: 96 Begin prepacking. There is one chain in this architecture called "chain" with the following starting points: clb[0]/fle[0]/lut5inter[0]/ble5[0]/arithmetic[0]/adder[0].cin[0] Finish prepacking. Using inter-cluster delay: 1.33777e-09 Packing with pin utilization targets: io:1,1 clb:0.8,1 mult_36:1,1 memory:1,1 Packing with high fanout thresholds: io:128 clb:32 mult_36:128 memory:128 Warning 2: Block type 'mult_36' grid location specification startx (6 = 6) falls outside device horizontal range [0,2] Warning 3: Block type 'EMPTY' grid location specification startx (6 = 6) falls outside device horizontal range [0,2] Not enough resources expand FPGA size to (3 x 3) Complex block 0: 'diffeq_f_systemC^MIN~46-0[0]' (clb) .................... Warning 4: Block type 'mult_36' grid location specification startx (6 = 6) falls outside device horizontal range [0,3] Warning 5: Block type 'EMPTY' grid location specification startx (6 = 6) falls outside device horizontal range [0,3] Not enough resources expand FPGA size to (4 x 4) Complex block 1: 'diffeq_f_systemC^MIN~43-0[0]' (clb) .................... Warning 6: Block type 'mult_36' grid location specification startx (6 = 6) falls outside device horizontal range [0,4] Warning 7: Block type 'EMPTY' grid location specification startx (6 = 6) falls outside device horizontal range [0,4] Not enough resources expand FPGA size to (5 x 5) Complex block 2: 'diffeq_f_systemC^ADD~40-0[0]' (clb) . Complex block 3: 'diffeq_f_systemC^ADD~39-0[0]' (clb) . Not enough resources expand FPGA size to (8 x 8) Complex block 4: 'diffeq_f_systemC^MUL~0[0]' (mult_36) . Not enough resources expand FPGA size to (10 x 10) Complex block 5: 'diffeq_f_systemC^MUL~41[0]' (mult_36) . Not enough resources expand FPGA size to (14 x 14) Complex block 6: 'diffeq_f_systemC^MUL~44[0]' (mult_36) . Not enough resources expand FPGA size to (16 x 16) Complex block 7: 'diffeq_f_systemC^MUL~42-0[0]' (mult_36) . Complex block 8: 'diffeq_f_systemC^MUL~45-0[0]' (mult_36) . Complex block 9: 'diffeq_f_systemC^MUL~42-1[0]' (mult_36) . Not enough resources expand FPGA size to (18 x 18) Complex block 10: 'diffeq_f_systemC^MUL~45-1[0]' (mult_36) . Complex block 11: 'diffeq_f_systemC^MIN~46-20[0]' (clb) ................. Complex block 12: 'diffeq_f_systemC^MIN~43-20[0]' (clb) ................. Complex block 13: 'diffeq_f_systemC^ADD~40-20[0]' (clb) ..... Complex block 14: 'diffeq_f_systemC^ADD~39-20[0]' (clb) ..... Complex block 15: 'diffeq_f_systemC^MUL~42-add0-0[0]' (clb) ........ Complex block 16: 'n1063' (clb) .......... Complex block 17: 'n1203' (clb) .......... Complex block 18: 'n1368' (clb) ........... Complex block 19: 'n1098' (clb) .......... Complex block 20: 'n1388' (clb) .......... Complex block 21: 'n1248' (clb) .......... Complex block 22: 'n1253' (clb) ........... Complex block 23: 'n1408' (clb) ............. Complex block 24: 'n1433' (clb) ............ Complex block 25: 'n1458' (clb) ........... Complex block 26: 'n1023' (clb) ........ Complex block 27: 'out:diffeq_f_systemC^xport~0' (io) . Complex block 28: 'out:diffeq_f_systemC^xport~1' (io) . Complex block 29: 'out:diffeq_f_systemC^xport~2' (io) . Complex block 30: 'out:diffeq_f_systemC^xport~3' (io) . Complex block 31: 'out:diffeq_f_systemC^xport~4' (io) . Complex block 32: 'out:diffeq_f_systemC^xport~5' (io) . Complex block 33: 'out:diffeq_f_systemC^xport~6' (io) . Complex block 34: 'out:diffeq_f_systemC^xport~7' (io) . Complex block 35: 'out:diffeq_f_systemC^xport~8' (io) . Complex block 36: 'out:diffeq_f_systemC^xport~9' (io) . Complex block 37: 'out:diffeq_f_systemC^xport~10' (io) . Complex block 38: 'out:diffeq_f_systemC^xport~11' (io) . Complex block 39: 'out:diffeq_f_systemC^xport~12' (io) . Complex block 40: 'out:diffeq_f_systemC^xport~13' (io) . Complex block 41: 'out:diffeq_f_systemC^xport~14' (io) . Complex block 42: 'out:diffeq_f_systemC^xport~15' (io) . Complex block 43: 'out:diffeq_f_systemC^xport~16' (io) . Complex block 44: 'out:diffeq_f_systemC^xport~17' (io) . Complex block 45: 'out:diffeq_f_systemC^xport~18' (io) . Complex block 46: 'out:diffeq_f_systemC^xport~19' (io) . Complex block 47: 'out:diffeq_f_systemC^xport~20' (io) . Complex block 48: 'out:diffeq_f_systemC^xport~21' (io) . Complex block 49: 'out:diffeq_f_systemC^xport~22' (io) . Complex block 50: 'out:diffeq_f_systemC^xport~23' (io) . Complex block 51: 'out:diffeq_f_systemC^xport~24' (io) . Complex block 52: 'out:diffeq_f_systemC^xport~25' (io) . Complex block 53: 'out:diffeq_f_systemC^xport~26' (io) . Complex block 54: 'out:diffeq_f_systemC^xport~27' (io) . Complex block 55: 'out:diffeq_f_systemC^xport~28' (io) . Complex block 56: 'out:diffeq_f_systemC^xport~29' (io) . Complex block 57: 'out:diffeq_f_systemC^xport~30' (io) . Complex block 58: 'out:diffeq_f_systemC^xport~31' (io) . Complex block 59: 'out:diffeq_f_systemC^yport~0' (io) . Complex block 60: 'out:diffeq_f_systemC^yport~1' (io) . Complex block 61: 'out:diffeq_f_systemC^yport~2' (io) . Complex block 62: 'out:diffeq_f_systemC^yport~3' (io) . Complex block 63: 'out:diffeq_f_systemC^yport~4' (io) . Complex block 64: 'out:diffeq_f_systemC^yport~5' (io) . Complex block 65: 'out:diffeq_f_systemC^yport~6' (io) . Complex block 66: 'out:diffeq_f_systemC^yport~7' (io) . Complex block 67: 'out:diffeq_f_systemC^yport~8' (io) . Complex block 68: 'out:diffeq_f_systemC^yport~9' (io) . Complex block 69: 'out:diffeq_f_systemC^yport~10' (io) . Complex block 70: 'out:diffeq_f_systemC^yport~11' (io) . Complex block 71: 'out:diffeq_f_systemC^yport~12' (io) . Complex block 72: 'out:diffeq_f_systemC^yport~13' (io) . Complex block 73: 'out:diffeq_f_systemC^yport~14' (io) . Complex block 74: 'out:diffeq_f_systemC^yport~15' (io) . Complex block 75: 'out:diffeq_f_systemC^yport~16' (io) . Complex block 76: 'out:diffeq_f_systemC^yport~17' (io) . Complex block 77: 'out:diffeq_f_systemC^yport~18' (io) . Complex block 78: 'out:diffeq_f_systemC^yport~19' (io) . Complex block 79: 'out:diffeq_f_systemC^yport~20' (io) . Complex block 80: 'out:diffeq_f_systemC^yport~21' (io) . Complex block 81: 'out:diffeq_f_systemC^yport~22' (io) . Complex block 82: 'out:diffeq_f_systemC^yport~23' (io) . Complex block 83: 'out:diffeq_f_systemC^yport~24' (io) . Complex block 84: 'out:diffeq_f_systemC^yport~25' (io) . Complex block 85: 'out:diffeq_f_systemC^yport~26' (io) . Complex block 86: 'out:diffeq_f_systemC^yport~27' (io) . Complex block 87: 'out:diffeq_f_systemC^yport~28' (io) . Complex block 88: 'out:diffeq_f_systemC^yport~29' (io) . Complex block 89: 'out:diffeq_f_systemC^yport~30' (io) . Complex block 90: 'out:diffeq_f_systemC^yport~31' (io) . Complex block 91: 'out:diffeq_f_systemC^uport~0' (io) . Complex block 92: 'out:diffeq_f_systemC^uport~1' (io) . Complex block 93: 'out:diffeq_f_systemC^uport~2' (io) . Complex block 94: 'out:diffeq_f_systemC^uport~3' (io) . Complex block 95: 'out:diffeq_f_systemC^uport~4' (io) . Complex block 96: 'out:diffeq_f_systemC^uport~5' (io) . Complex block 97: 'out:diffeq_f_systemC^uport~6' (io) . Complex block 98: 'out:diffeq_f_systemC^uport~7' (io) . Complex block 99: 'out:diffeq_f_systemC^uport~8' (io) . Complex block 100: 'out:diffeq_f_systemC^uport~9' (io) . Complex block 101: 'out:diffeq_f_systemC^uport~10' (io) . Complex block 102: 'out:diffeq_f_systemC^uport~11' (io) . Complex block 103: 'out:diffeq_f_systemC^uport~12' (io) . Complex block 104: 'out:diffeq_f_systemC^uport~13' (io) . Complex block 105: 'out:diffeq_f_systemC^uport~14' (io) . Complex block 106: 'out:diffeq_f_systemC^uport~15' (io) . Complex block 107: 'out:diffeq_f_systemC^uport~16' (io) . Complex block 108: 'out:diffeq_f_systemC^uport~17' (io) . Complex block 109: 'out:diffeq_f_systemC^uport~18' (io) . Complex block 110: 'out:diffeq_f_systemC^uport~19' (io) . Complex block 111: 'out:diffeq_f_systemC^uport~20' (io) . Complex block 112: 'out:diffeq_f_systemC^uport~21' (io) . Complex block 113: 'out:diffeq_f_systemC^uport~22' (io) . Complex block 114: 'out:diffeq_f_systemC^uport~23' (io) . Complex block 115: 'out:diffeq_f_systemC^uport~24' (io) . Complex block 116: 'out:diffeq_f_systemC^uport~25' (io) . Complex block 117: 'out:diffeq_f_systemC^uport~26' (io) . Complex block 118: 'out:diffeq_f_systemC^uport~27' (io) . Complex block 119: 'out:diffeq_f_systemC^uport~28' (io) . Complex block 120: 'out:diffeq_f_systemC^uport~29' (io) . Complex block 121: 'out:diffeq_f_systemC^uport~30' (io) . Complex block 122: 'out:diffeq_f_systemC^uport~31' (io) . Complex block 123: 'diffeq_f_systemC^clk' (io) . Complex block 124: 'diffeq_f_systemC^reset' (io) . Complex block 125: 'diffeq_f_systemC^aport~0' (io) . Complex block 126: 'diffeq_f_systemC^aport~1' (io) . Complex block 127: 'diffeq_f_systemC^aport~2' (io) . Complex block 128: 'diffeq_f_systemC^aport~3' (io) . Complex block 129: 'diffeq_f_systemC^aport~4' (io) . Complex block 130: 'diffeq_f_systemC^aport~5' (io) . Complex block 131: 'diffeq_f_systemC^aport~6' (io) . Complex block 132: 'diffeq_f_systemC^aport~7' (io) . Complex block 133: 'diffeq_f_systemC^aport~8' (io) . Complex block 134: 'diffeq_f_systemC^aport~9' (io) . Complex block 135: 'diffeq_f_systemC^aport~10' (io) . Complex block 136: 'diffeq_f_systemC^aport~11' (io) . Complex block 137: 'diffeq_f_systemC^aport~12' (io) . Complex block 138: 'diffeq_f_systemC^aport~13' (io) . Complex block 139: 'diffeq_f_systemC^aport~14' (io) . Complex block 140: 'diffeq_f_systemC^aport~15' (io) . Complex block 141: 'diffeq_f_systemC^aport~16' (io) . Complex block 142: 'diffeq_f_systemC^aport~17' (io) . Complex block 143: 'diffeq_f_systemC^aport~18' (io) . Complex block 144: 'diffeq_f_systemC^aport~19' (io) . Complex block 145: 'diffeq_f_systemC^aport~20' (io) . Complex block 146: 'diffeq_f_systemC^aport~21' (io) . Complex block 147: 'diffeq_f_systemC^aport~22' (io) . Complex block 148: 'diffeq_f_systemC^aport~23' (io) . Complex block 149: 'diffeq_f_systemC^aport~24' (io) . Complex block 150: 'diffeq_f_systemC^aport~25' (io) . Complex block 151: 'diffeq_f_systemC^aport~26' (io) . Complex block 152: 'diffeq_f_systemC^aport~27' (io) . Complex block 153: 'diffeq_f_systemC^aport~28' (io) . Complex block 154: 'diffeq_f_systemC^aport~29' (io) . Complex block 155: 'diffeq_f_systemC^aport~30' (io) . Complex block 156: 'diffeq_f_systemC^aport~31' (io) . Complex block 157: 'diffeq_f_systemC^dxport~0' (io) . Complex block 158: 'diffeq_f_systemC^dxport~1' (io) . Complex block 159: 'diffeq_f_systemC^dxport~2' (io) . Complex block 160: 'diffeq_f_systemC^dxport~3' (io) . Complex block 161: 'diffeq_f_systemC^dxport~4' (io) . Complex block 162: 'diffeq_f_systemC^dxport~5' (io) . Complex block 163: 'diffeq_f_systemC^dxport~6' (io) . Complex block 164: 'diffeq_f_systemC^dxport~7' (io) . Complex block 165: 'diffeq_f_systemC^dxport~8' (io) . Complex block 166: 'diffeq_f_systemC^dxport~9' (io) . Complex block 167: 'diffeq_f_systemC^dxport~10' (io) . Complex block 168: 'diffeq_f_systemC^dxport~11' (io) . Complex block 169: 'diffeq_f_systemC^dxport~12' (io) . Complex block 170: 'diffeq_f_systemC^dxport~13' (io) . Complex block 171: 'diffeq_f_systemC^dxport~14' (io) . Complex block 172: 'diffeq_f_systemC^dxport~15' (io) . Complex block 173: 'diffeq_f_systemC^dxport~16' (io) . Complex block 174: 'diffeq_f_systemC^dxport~17' (io) . Complex block 175: 'diffeq_f_systemC^dxport~18' (io) . Complex block 176: 'diffeq_f_systemC^dxport~19' (io) . Complex block 177: 'diffeq_f_systemC^dxport~20' (io) . Complex block 178: 'diffeq_f_systemC^dxport~21' (io) . Complex block 179: 'diffeq_f_systemC^dxport~22' (io) . Complex block 180: 'diffeq_f_systemC^dxport~23' (io) . Complex block 181: 'diffeq_f_systemC^dxport~24' (io) . Complex block 182: 'diffeq_f_systemC^dxport~25' (io) . Complex block 183: 'diffeq_f_systemC^dxport~26' (io) . Complex block 184: 'diffeq_f_systemC^dxport~27' (io) . Complex block 185: 'diffeq_f_systemC^dxport~28' (io) . Complex block 186: 'diffeq_f_systemC^dxport~29' (io) . Complex block 187: 'diffeq_f_systemC^dxport~30' (io) . Complex block 188: 'diffeq_f_systemC^dxport~31' (io) . Logic Element (fle) detailed count: Total number of Logic Elements used : 198 LEs used for logic and registers : 96 LEs used for logic only : 102 LEs used for registers only : 0 EMPTY: # blocks: 0, average # input + clock pins used: 0, average # output pins used: 0 io: # blocks: 162, average # input + clock pins used: 0.592593, average # output pins used: 0.407407 clb: # blocks: 20, average # input + clock pins used: 24.1, average # output pins used: 12.45 mult_36: # blocks: 7, average # input + clock pins used: 64, average # output pins used: 33.1429 memory: # blocks: 0, average # input + clock pins used: 0, average # output pins used: 0 Absorbed logical nets 319 out of 866 nets, 547 nets not absorbed. Incr Slack updates 1 in 5.5193e-05 sec Full Max Req/Worst Slack updates 1 in 6.141e-06 sec Incr Max Req/Worst Slack updates 0 in 0 sec Incr Criticality updates 0 in 0 sec Full Criticality updates 1 in 7.3059e-05 sec FPGA sized to 18 x 18 (auto) Device Utilization: 0.21 (target 1.00) Block Utilization: 0.32 Type: io Block Utilization: 0.10 Type: clb Block Utilization: 0.88 Type: mult_36 Netlist conversion complete. # Packing took 0.34 seconds (max_rss 27.6 MiB, delta_rss +2.9 MiB) # Load Packing Begin loading packed FPGA netlist file. Netlist generated from file 'diffeq2.net'. Detected 2 constant generators (to see names run with higher pack verbosity) Finished loading packed FPGA netlist file (took 0.060579 seconds). Warning 8: Treated 2 constant nets as global which will not be routed (to see net names increase packer verbosity). # Load Packing took 0.06 seconds (max_rss 67.0 MiB, delta_rss +39.4 MiB) Warning 9: Netlist contains 74 global net to non-global architecture pin connections Netlist num_nets: 547 Netlist num_blocks: 189 Netlist EMPTY blocks: 0. Netlist io blocks: 162. Netlist clb blocks: 20. Netlist mult_36 blocks: 7. Netlist memory blocks: 0. Netlist inputs pins: 66 Netlist output pins: 96 Pb types usage... io : 162 inpad : 66 outpad : 96 clb : 20 fle : 198 lut5inter : 183 ble5 : 263 flut5 : 121 lut5 : 121 lut : 121 ff : 96 arithmetic : 142 lut4 : 64 lut : 64 adder : 142 ble6 : 15 lut6 : 15 lut : 15 mult_36 : 7 mult_36x36_slice : 7 mult_36x36 : 7 # Create Device ## Build Device Grid FPGA sized to 18 x 18: 324 grid tiles (auto) Resource usage... Netlist 162 blocks of type: io Architecture 512 blocks of type: io Netlist 20 blocks of type: clb Architecture 192 blocks of type: clb Netlist 7 blocks of type: mult_36 Architecture 8 blocks of type: mult_36 Netlist 0 blocks of type: memory Architecture 4 blocks of type: memory Device Utilization: 0.21 (target 1.00) Physical Tile io: Block Utilization: 0.32 Logical Block: io Physical Tile clb: Block Utilization: 0.10 Logical Block: clb Physical Tile mult_36: Block Utilization: 0.88 Logical Block: mult_36 Physical Tile memory: Block Utilization: 0.00 Logical Block: memory FPGA size limited by block type(s): mult_36 ## Build Device Grid took 0.00 seconds (max_rss 67.4 MiB, delta_rss +0.0 MiB) ## Build routing resource graph Warning 10: in check_rr_node: RR node: 2125 type: OPIN location: (1,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 11: in check_rr_node: RR node: 4641 type: OPIN location: (3,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 12: in check_rr_node: RR node: 6273 type: OPIN location: (4,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 13: in check_rr_node: RR node: 7905 type: OPIN location: (5,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 14: in check_rr_node: RR node: 10929 type: OPIN location: (7,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 15: in check_rr_node: RR node: 12561 type: OPIN location: (8,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 16: in check_rr_node: RR node: 14193 type: OPIN location: (9,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 17: in check_rr_node: RR node: 16709 type: OPIN location: (11,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 18: in check_rr_node: RR node: 18341 type: OPIN location: (12,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 19: in check_rr_node: RR node: 19973 type: OPIN location: (13,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 20: in check_rr_node: RR node: 22997 type: OPIN location: (15,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 21: in check_rr_node: RR node: 24629 type: OPIN location: (16,1) pin: 61 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 22: in check_rr_graph: fringe node 24 IPIN at (0,1) has no fanin. This is possible on a fringe node based on low Fc_out, N, and certain lengths. ## Build routing resource graph took 0.05 seconds (max_rss 67.9 MiB, delta_rss +0.5 MiB) RR Graph Nodes: 33144 RR Graph Edges: 115280 # Create Device took 0.06 seconds (max_rss 67.9 MiB, delta_rss +0.5 MiB) # Computing router lookahead map ## Computing wire lookahead ## Computing wire lookahead took 0.14 seconds (max_rss 67.9 MiB, delta_rss +0.0 MiB) ## Computing src/opin lookahead Warning 23: Found no reachable wires from SOURCE (clb[0].cout[0]) at (1,1) Warning 24: Found no reachable wires from OPIN (clb.cout[0]) at (1,1) ## Computing src/opin lookahead took 0.00 seconds (max_rss 67.9 MiB, delta_rss +0.0 MiB) # Computing router lookahead map took 0.14 seconds (max_rss 67.9 MiB, delta_rss +0.0 MiB) # Placement ## Computing placement delta delay look-up RR graph channel widths unchanged, skipping RR graph rebuild ### Computing delta delays ### Computing delta delays took 0.03 seconds (max_rss 67.9 MiB, delta_rss +0.0 MiB) ## Computing placement delta delay look-up took 0.03 seconds (max_rss 67.9 MiB, delta_rss +0.0 MiB) ## Initial Placement ## Initial Placement took 0.00 seconds (max_rss 67.9 MiB, delta_rss +0.0 MiB) There are 938 point to point connections in this circuit. BB estimate of min-dist (placement) wire length: 8672 Completed placement consistency check successfully. Initial placement cost: 1 bb_cost: 271.002 td_cost: 2.81837e-07 Initial placement estimated Critical Path Delay (CPD): 13.344 ns Initial placement estimated setup Total Negative Slack (sTNS): -873.726 ns Initial placement estimated setup Worst Negative Slack (sWNS): -13.344 ns Initial placement estimated setup slack histogram: [ -1.3e-08: -1.2e-08) 30 ( 15.6%) |*************** [ -1.2e-08: -1.1e-08) 2 ( 1.0%) |* [ -1.1e-08: -9.5e-09) 0 ( 0.0%) | [ -9.5e-09: -8.2e-09) 0 ( 0.0%) | [ -8.2e-09: -6.9e-09) 31 ( 16.1%) |**************** [ -6.9e-09: -5.6e-09) 6 ( 3.1%) |*** [ -5.6e-09: -4.3e-09) 27 ( 14.1%) |************** [ -4.3e-09: -3e-09) 0 ( 0.0%) | [ -3e-09: -1.7e-09) 0 ( 0.0%) | [ -1.7e-09: -3.8e-10) 96 ( 50.0%) |************************************************ Placement contains 4 placement macros involving 8 blocks (average macro size 2.000000) Moves per temperature: 1084 Warning 25: Starting t: 188 of 189 configurations accepted. ---- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ Tnum Time T Av Cost Av BB Cost Av TD Cost CPD sTNS sWNS Ac Rate Std Dev R lim Crit Exp Tot Moves Alpha (sec) (ns) (ns) (ns) ---- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ 1 0.0 8.0e-01 0.962 278.11 2.951e-07 13.754 -895 -13.754 0.993 0.0439 17.0 1.00 1084 0.200 2 0.0 4.0e-01 0.973 275.22 2.8316e-07 13.753 -918 -13.753 0.994 0.0261 17.0 1.00 2168 0.500 3 0.0 2.0e-01 1.030 265.65 2.8531e-07 12.818 -888 -12.818 0.989 0.0475 17.0 1.00 3252 0.500 4 0.0 9.9e-02 1.043 275.24 2.9006e-07 13.232 -892 -13.232 0.991 0.0423 17.0 1.00 4336 0.500 5 0.0 5.0e-02 0.990 259.74 2.7691e-07 13.501 -862 -13.501 0.973 0.0404 17.0 1.00 5420 0.500 6 0.0 2.5e-02 1.024 252.60 2.667e-07 13.037 -848 -13.037 0.945 0.0358 17.0 1.00 6504 0.500 7 0.0 2.2e-02 0.962 235.68 2.6732e-07 12.623 -845 -12.623 0.945 0.0201 17.0 1.00 7588 0.900 8 0.0 2.0e-02 1.016 236.83 2.4779e-07 13.124 -858 -13.124 0.923 0.0273 17.0 1.00 8672 0.900 9 0.0 1.8e-02 0.965 224.82 2.4431e-07 13.019 -874 -13.019 0.917 0.0365 17.0 1.00 9756 0.900 10 0.0 1.6e-02 1.018 226.68 2.3833e-07 12.635 -865 -12.635 0.908 0.0296 17.0 1.00 10840 0.900 11 0.0 1.5e-02 0.990 229.65 2.4865e-07 12.634 -849 -12.634 0.896 0.0306 17.0 1.00 11924 0.900 12 0.0 1.3e-02 0.986 214.99 2.2247e-07 13.158 -863 -13.158 0.900 0.0328 17.0 1.00 13008 0.900 13 0.0 1.2e-02 0.971 217.23 2.3278e-07 13.489 -866 -13.489 0.899 0.0153 17.0 1.00 14092 0.900 14 0.0 1.1e-02 0.982 213.22 2.2393e-07 12.390 -808 -12.390 0.872 0.0155 17.0 1.00 15176 0.900 15 0.0 9.6e-03 1.014 211.93 2.1848e-07 13.247 -805 -13.247 0.891 0.0220 17.0 1.00 16260 0.900 16 0.0 8.7e-03 0.970 212.22 2.2257e-07 12.806 -842 -12.806 0.891 0.0184 17.0 1.00 17344 0.900 17 0.0 7.8e-03 1.011 210.84 2.2051e-07 12.665 -808 -12.665 0.864 0.0284 17.0 1.00 18428 0.900 18 0.0 7.0e-03 0.963 215.29 2.1242e-07 12.998 -836 -12.998 0.882 0.0203 17.0 1.00 19512 0.900 19 0.0 6.3e-03 0.981 207.51 2.1438e-07 12.210 -821 -12.210 0.862 0.0129 17.0 1.00 20596 0.900 20 0.0 5.7e-03 0.965 197.85 2.0821e-07 12.418 -824 -12.418 0.851 0.0147 17.0 1.00 21680 0.900 21 0.0 5.1e-03 0.985 192.97 2.0174e-07 12.328 -799 -12.328 0.836 0.0075 17.0 1.00 22764 0.900 22 0.0 4.6e-03 1.004 190.48 2.0505e-07 12.298 -810 -12.298 0.829 0.0152 17.0 1.00 23848 0.900 23 0.0 4.1e-03 0.979 190.74 2.0949e-07 12.586 -828 -12.586 0.800 0.0114 17.0 1.00 24932 0.900 24 0.0 3.9e-03 0.993 186.99 2.0833e-07 12.475 -816 -12.475 0.805 0.0171 17.0 1.00 26016 0.950 25 0.0 3.5e-03 1.013 190.62 2.0169e-07 12.532 -800 -12.532 0.813 0.0101 17.0 1.00 27100 0.900 26 0.0 3.2e-03 0.981 190.60 2.0443e-07 12.476 -810 -12.476 0.798 0.0072 17.0 1.00 28184 0.900 27 0.0 3.0e-03 0.977 191.93 2.0461e-07 12.314 -814 -12.314 0.815 0.0157 17.0 1.00 29268 0.950 28 0.0 2.7e-03 1.000 189.21 1.9801e-07 12.430 -807 -12.430 0.784 0.0050 17.0 1.00 30352 0.900 29 0.0 2.6e-03 0.989 186.27 2.001e-07 12.214 -796 -12.214 0.776 0.0059 17.0 1.00 31436 0.950 30 0.0 2.5e-03 0.994 184.22 1.9803e-07 12.214 -782 -12.214 0.774 0.0053 17.0 1.00 32520 0.950 31 0.0 2.3e-03 0.997 182.10 1.919e-07 12.557 -777 -12.557 0.782 0.0040 17.0 1.00 33604 0.950 32 0.0 2.2e-03 1.005 183.90 1.9169e-07 12.557 -782 -12.557 0.786 0.0046 17.0 1.00 34688 0.950 33 0.0 2.1e-03 0.995 182.86 1.9008e-07 12.505 -779 -12.505 0.782 0.0056 17.0 1.00 35772 0.950 34 0.0 2.0e-03 0.997 182.11 1.9095e-07 12.384 -785 -12.384 0.792 0.0038 17.0 1.00 36856 0.950 35 0.0 1.9e-03 0.992 181.58 1.9146e-07 12.384 -779 -12.384 0.766 0.0055 17.0 1.00 37940 0.950 36 0.0 1.8e-03 1.014 183.69 1.912e-07 12.384 -772 -12.384 0.770 0.0065 17.0 1.00 39024 0.950 37 0.0 1.7e-03 0.983 181.49 1.9012e-07 12.467 -793 -12.467 0.771 0.0057 17.0 1.00 40108 0.950 38 0.0 1.6e-03 0.999 180.46 1.8857e-07 12.467 -775 -12.467 0.749 0.0026 17.0 1.00 41192 0.950 39 0.0 1.6e-03 0.998 181.09 1.8959e-07 12.467 -785 -12.467 0.760 0.0049 17.0 1.00 42276 0.950 40 0.0 1.5e-03 1.000 179.46 1.8852e-07 12.467 -778 -12.467 0.726 0.0062 17.0 1.00 43360 0.950 41 0.0 1.4e-03 0.999 178.16 1.9043e-07 12.333 -777 -12.333 0.708 0.0031 17.0 1.00 44444 0.950 42 0.0 1.3e-03 0.988 174.64 1.8772e-07 12.582 -795 -12.582 0.681 0.0048 17.0 1.00 45528 0.950 43 0.0 1.3e-03 1.005 174.35 1.8819e-07 12.627 -797 -12.627 0.673 0.0063 17.0 1.00 46612 0.950 44 0.0 1.2e-03 0.994 172.62 1.8567e-07 12.627 -787 -12.627 0.634 0.0045 17.0 1.00 47696 0.950 45 0.0 1.1e-03 0.977 167.72 1.8105e-07 12.528 -782 -12.528 0.599 0.0103 17.0 1.00 48780 0.950 46 0.0 1.1e-03 1.008 167.65 1.8311e-07 12.426 -780 -12.426 0.591 0.0092 17.0 1.00 49864 0.950 47 0.0 1.0e-03 0.992 167.56 1.8363e-07 12.341 -785 -12.341 0.577 0.0045 17.0 1.00 50948 0.950 48 0.0 9.8e-04 0.990 166.00 1.8199e-07 12.352 -782 -12.352 0.548 0.0075 17.0 1.00 52032 0.950 49 0.0 9.3e-04 0.996 164.32 1.8169e-07 12.237 -773 -12.237 0.541 0.0037 17.0 1.00 53116 0.950 50 0.0 8.8e-04 1.000 163.71 1.7914e-07 12.426 -774 -12.426 0.533 0.0068 17.0 1.00 54200 0.950 51 0.0 8.4e-04 1.010 165.26 1.8128e-07 12.228 -753 -12.228 0.551 0.0038 17.0 1.00 55284 0.950 52 0.0 8.0e-04 0.998 165.78 1.7853e-07 12.582 -785 -12.582 0.533 0.0052 17.0 1.00 56368 0.950 53 0.0 7.6e-04 0.996 162.75 1.7512e-07 12.627 -783 -12.627 0.487 0.0036 17.0 1.00 57452 0.950 54 0.0 7.2e-04 0.999 161.98 1.7903e-07 12.234 -760 -12.234 0.497 0.0054 17.0 1.00 58536 0.950 55 0.0 6.8e-04 1.002 160.48 1.7728e-07 12.497 -766 -12.497 0.508 0.0028 17.0 1.00 59620 0.950 56 0.0 6.5e-04 1.007 162.20 1.7755e-07 12.393 -760 -12.393 0.484 0.0043 17.0 1.00 60704 0.950 57 0.0 6.2e-04 0.996 160.68 1.7498e-07 12.497 -770 -12.497 0.448 0.0027 17.0 1.00 61788 0.950 58 0.0 5.9e-04 0.994 159.83 1.7616e-07 12.323 -759 -12.323 0.436 0.0035 17.0 1.00 62872 0.950 59 0.0 5.6e-04 1.002 159.24 1.7706e-07 12.224 -753 -12.224 0.519 0.0033 16.9 1.03 63956 0.950 60 0.0 5.3e-04 0.994 158.87 1.7496e-07 12.582 -775 -12.582 0.410 0.0032 17.0 1.00 65040 0.950 61 0.0 5.0e-04 1.001 159.07 1.6558e-07 12.348 -755 -12.348 0.522 0.0034 16.5 1.23 66124 0.950 62 0.0 4.8e-04 0.992 156.82 1.7645e-07 12.348 -762 -12.348 0.370 0.0028 17.0 1.00 67208 0.950 63 0.0 4.5e-04 0.999 157.30 1.538e-07 12.348 -751 -12.348 0.512 0.0027 15.8 1.52 68292 0.950 64 0.0 4.3e-04 0.998 156.75 1.7613e-07 12.242 -750 -12.242 0.450 0.0019 16.9 1.02 69376 0.950 65 0.0 4.1e-04 0.991 155.24 1.7581e-07 12.333 -751 -12.333 0.343 0.0038 17.0 1.00 70460 0.950 66 0.0 3.9e-04 0.995 155.56 1.474e-07 12.333 -750 -12.333 0.433 0.0034 15.4 1.72 71544 0.950 67 0.0 3.7e-04 1.002 155.20 1.4612e-07 12.333 -758 -12.333 0.448 0.0021 15.2 1.77 72628 0.950 68 0.0 3.5e-04 1.004 156.84 1.4757e-07 12.333 -753 -12.333 0.444 0.0025 15.4 1.71 73712 0.950 69 0.0 3.3e-04 0.993 155.32 1.4852e-07 12.333 -756 -12.333 0.423 0.0047 15.4 1.69 74796 0.950 70 0.0 3.2e-04 1.001 153.92 1.4523e-07 12.333 -751 -12.333 0.387 0.0009 15.2 1.80 75880 0.950 71 0.0 3.0e-04 0.998 154.28 1.3589e-07 12.341 -751 -12.341 0.377 0.0024 14.4 2.15 76964 0.950 72 0.0 2.9e-04 0.998 152.88 1.286e-07 12.341 -760 -12.341 0.367 0.0014 13.5 2.54 78048 0.950 73 0.0 2.7e-04 0.999 153.44 1.2199e-07 12.341 -752 -12.341 0.395 0.0012 12.5 2.97 79132 0.950 74 0.0 2.6e-04 0.999 152.86 1.1889e-07 12.341 -754 -12.341 0.406 0.0015 11.9 3.22 80216 0.950 75 0.0 2.4e-04 0.999 154.20 1.1596e-07 12.341 -755 -12.341 0.382 0.0014 11.5 3.40 81300 0.950 76 0.0 2.3e-04 0.999 154.05 1.1206e-07 12.323 -754 -12.323 0.395 0.0033 10.9 3.69 82384 0.950 77 0.0 2.2e-04 0.998 153.08 1.0939e-07 12.323 -759 -12.323 0.354 0.0013 10.4 3.90 83468 0.950 78 0.0 2.1e-04 1.000 153.29 1.0548e-07 12.323 -758 -12.323 0.387 0.0015 9.5 4.29 84552 0.950 79 0.0 2.0e-04 0.999 152.38 1.0348e-07 12.323 -758 -12.323 0.349 0.0008 9.0 4.52 85636 0.950 80 0.0 1.9e-04 0.999 151.98 1.0074e-07 12.323 -762 -12.323 0.333 0.0013 8.1 4.87 86720 0.950 81 0.0 1.8e-04 1.001 152.48 9.7796e-08 12.323 -761 -12.323 0.374 0.0010 7.3 5.25 87804 0.950 82 0.0 1.7e-04 0.999 153.12 9.5952e-08 12.323 -759 -12.323 0.351 0.0009 6.8 5.47 88888 0.950 83 0.0 1.6e-04 0.997 153.19 9.3992e-08 12.323 -761 -12.323 0.360 0.0018 6.2 5.73 89972 0.950 84 0.0 1.5e-04 0.996 151.81 9.232e-08 12.323 -757 -12.323 0.351 0.0023 5.7 5.95 91056 0.950 85 0.0 1.5e-04 0.994 149.50 9.0756e-08 12.323 -758 -12.323 0.368 0.0021 5.2 6.17 92140 0.950 86 0.0 1.4e-04 1.000 149.04 9.6587e-08 12.078 -752 -12.078 0.369 0.0006 4.8 6.33 93224 0.950 87 0.0 1.3e-04 0.997 148.59 9.5713e-08 12.078 -755 -12.078 0.370 0.0013 4.5 6.48 94308 0.950 88 0.0 1.3e-04 1.000 148.41 9.4833e-08 12.078 -749 -12.078 0.345 0.0011 4.2 6.62 95392 0.950 89 0.0 1.2e-04 0.996 147.76 9.3646e-08 12.078 -744 -12.078 0.397 0.0013 3.8 6.79 96476 0.950 90 0.0 1.1e-04 1.000 147.18 9.1571e-08 12.120 -745 -12.120 0.344 0.0006 3.6 6.86 97560 0.950 91 0.0 1.1e-04 0.999 147.03 9.093e-08 12.120 -744 -12.120 0.369 0.0004 3.3 7.01 98644 0.950 92 0.0 1.0e-04 0.999 146.88 9.0618e-08 12.120 -741 -12.120 0.353 0.0005 3.0 7.11 99728 0.950 93 0.0 9.7e-05 0.999 146.91 8.9959e-08 12.120 -741 -12.120 0.381 0.0011 2.8 7.23 100812 0.950 94 0.0 9.2e-05 0.998 146.22 8.9408e-08 12.120 -743 -12.120 0.389 0.0008 2.6 7.30 101896 0.950 95 0.0 8.8e-05 0.999 146.02 8.8934e-08 12.120 -743 -12.120 0.388 0.0004 2.5 7.36 102980 0.950 96 0.0 8.3e-05 1.000 145.72 8.8862e-08 12.120 -742 -12.120 0.382 0.0003 2.3 7.41 104064 0.950 97 0.0 7.9e-05 0.999 145.22 8.86e-08 12.120 -742 -12.120 0.402 0.0008 2.2 7.47 105148 0.950 98 0.0 7.5e-05 1.000 144.99 8.8413e-08 12.120 -741 -12.120 0.351 0.0003 2.1 7.51 106232 0.950 99 0.0 7.1e-05 0.999 144.52 8.8266e-08 12.120 -740 -12.120 0.370 0.0002 1.9 7.59 107316 0.950 100 0.0 6.8e-05 0.999 144.64 8.7761e-08 12.120 -741 -12.120 0.389 0.0002 1.8 7.65 108400 0.950 101 0.0 6.5e-05 1.000 144.80 8.7499e-08 12.120 -741 -12.120 0.374 0.0001 1.7 7.69 109484 0.950 102 0.0 6.1e-05 1.000 144.88 8.7341e-08 12.120 -741 -12.120 0.380 0.0004 1.6 7.74 110568 0.950 103 0.0 5.8e-05 1.000 144.87 8.7127e-08 12.120 -741 -12.120 0.353 0.0003 1.5 7.78 111652 0.950 104 0.0 5.5e-05 1.000 144.95 8.6792e-08 12.120 -741 -12.120 0.364 0.0001 1.4 7.84 112736 0.950 105 0.0 5.3e-05 1.000 144.93 8.6587e-08 12.120 -740 -12.120 0.366 0.0006 1.3 7.89 113820 0.950 106 0.0 5.0e-05 1.000 144.58 8.6451e-08 12.120 -741 -12.120 0.334 0.0002 1.2 7.93 114904 0.950 107 0.0 4.7e-05 1.000 144.46 8.6315e-08 12.120 -741 -12.120 0.329 0.0003 1.0 7.98 115988 0.950 108 0.0 4.5e-05 1.000 144.46 8.6184e-08 12.120 -741 -12.120 0.352 0.0004 1.0 8.00 117072 0.950 109 0.0 4.3e-05 1.000 144.46 8.6109e-08 12.120 -741 -12.120 0.341 0.0003 1.0 8.00 118156 0.950 110 0.0 4.1e-05 0.999 144.32 8.6093e-08 12.120 -742 -12.120 0.334 0.0003 1.0 8.00 119240 0.950 111 0.0 3.9e-05 1.000 144.18 8.6169e-08 12.120 -741 -12.120 0.348 0.0001 1.0 8.00 120324 0.950 112 0.0 3.7e-05 1.000 144.17 8.6123e-08 12.120 -741 -12.120 0.295 0.0001 1.0 8.00 121408 0.950 113 0.0 3.5e-05 1.000 144.27 8.6096e-08 12.120 -741 -12.120 0.300 0.0001 1.0 8.00 122492 0.950 114 0.0 3.3e-05 1.000 144.19 8.6097e-08 12.120 -740 -12.120 0.320 0.0002 1.0 8.00 123576 0.950 115 0.0 3.1e-05 1.000 144.03 8.6157e-08 12.120 -742 -12.120 0.327 0.0003 1.0 8.00 124660 0.950 116 0.0 3.0e-05 1.000 143.98 8.6169e-08 12.120 -742 -12.120 0.286 0.0001 1.0 8.00 125744 0.950 117 0.0 2.8e-05 1.000 143.97 8.6168e-08 12.120 -741 -12.120 0.302 0.0000 1.0 8.00 126828 0.950 118 0.0 2.7e-05 1.000 143.99 8.6113e-08 12.120 -741 -12.120 0.325 0.0001 1.0 8.00 127912 0.950 119 0.0 2.6e-05 1.000 143.99 8.6094e-08 12.120 -741 -12.120 0.312 0.0001 1.0 8.00 128996 0.950 120 0.0 2.4e-05 1.000 143.97 8.6102e-08 12.120 -741 -12.120 0.327 0.0002 1.0 8.00 130080 0.950 121 0.0 2.3e-05 1.000 143.91 8.6095e-08 12.120 -741 -12.120 0.312 0.0000 1.0 8.00 131164 0.950 122 0.0 2.2e-05 1.000 143.92 8.6096e-08 12.120 -741 -12.120 0.296 0.0000 1.0 8.00 132248 0.950 123 0.0 2.1e-05 1.000 143.90 8.61e-08 12.120 -741 -12.120 0.299 0.0000 1.0 8.00 133332 0.950 124 0.0 2.0e-05 1.000 143.90 8.6097e-08 12.120 -741 -12.120 0.290 0.0000 1.0 8.00 134416 0.950 125 0.0 1.9e-05 1.000 143.89 8.6095e-08 12.120 -742 -12.120 0.286 0.0000 1.0 8.00 135500 0.950 126 0.0 1.8e-05 1.000 143.90 8.61e-08 12.120 -742 -12.120 0.297 0.0000 1.0 8.00 136584 0.950 127 0.0 1.7e-05 1.000 143.87 8.6094e-08 12.120 -741 -12.120 0.257 0.0001 1.0 8.00 137668 0.950 128 0.0 1.6e-05 1.000 143.85 8.6096e-08 12.120 -741 -12.120 0.302 0.0000 1.0 8.00 138752 0.950 129 0.0 1.5e-05 1.000 143.88 8.6095e-08 12.120 -741 -12.120 0.294 0.0001 1.0 8.00 139836 0.950 130 0.0 1.5e-05 1.000 143.89 8.6094e-08 12.120 -741 -12.120 0.285 0.0000 1.0 8.00 140920 0.950 131 0.0 1.4e-05 1.000 143.86 8.6096e-08 12.120 -741 -12.120 0.297 0.0000 1.0 8.00 142004 0.950 132 0.0 1.3e-05 1.000 143.86 8.6091e-08 12.120 -741 -12.120 0.322 0.0000 1.0 8.00 143088 0.950 133 0.0 1.2e-05 1.000 143.86 8.6093e-08 12.120 -742 -12.120 0.317 0.0000 1.0 8.00 144172 0.950 134 0.0 1.2e-05 1.000 143.85 8.6093e-08 12.120 -741 -12.120 0.263 0.0000 1.0 8.00 145256 0.950 135 0.0 1.1e-05 1.000 143.85 8.6094e-08 12.120 -741 -12.120 0.274 0.0000 1.0 8.00 146340 0.950 136 0.0 1.1e-05 1.000 143.85 8.6091e-08 12.120 -741 -12.120 0.276 0.0000 1.0 8.00 147424 0.950 137 0.0 1.0e-05 1.000 143.84 8.6093e-08 12.120 -741 -12.120 0.274 0.0000 1.0 8.00 148508 0.950 138 0.0 9.7e-06 1.000 143.85 8.609e-08 12.120 -741 -12.120 0.304 0.0000 1.0 8.00 149592 0.950 139 0.0 9.2e-06 1.000 143.85 8.6093e-08 12.120 -741 -12.120 0.268 0.0000 1.0 8.00 150676 0.950 140 0.0 0.0e+00 1.000 143.84 8.6091e-08 12.120 -741 -12.120 0.083 0.0000 1.0 8.00 151760 0.950 ## Placement Quench took 0.00 seconds (max_rss 67.9 MiB) BB estimate of min-dist (placement) wire length: 4603 Completed placement consistency check successfully. Swaps called: 151949 Aborted Move Reasons: duplicate block move to location: 9 macro_from swap to location illegal: 235 Placement estimated critical path delay (least slack): 12.1197 ns, Fmax: 82.51 MHz Placement estimated setup Worst Negative Slack (sWNS): -12.1197 ns Placement estimated setup Total Negative Slack (sTNS): -740.514 ns Placement estimated setup slack histogram: [ -1.2e-08: -1.1e-08) 30 ( 15.6%) |*************** [ -1.1e-08: -9.8e-09) 2 ( 1.0%) |* [ -9.8e-09: -8.6e-09) 0 ( 0.0%) | [ -8.6e-09: -7.4e-09) 0 ( 0.0%) | [ -7.4e-09: -6.3e-09) 24 ( 12.5%) |************ [ -6.3e-09: -5.1e-09) 8 ( 4.2%) |**** [ -5.1e-09: -3.9e-09) 0 ( 0.0%) | [ -3.9e-09: -2.8e-09) 32 ( 16.7%) |**************** [ -2.8e-09: -1.6e-09) 0 ( 0.0%) | [ -1.6e-09: -4.3e-10) 96 ( 50.0%) |************************************************ Placement estimated geomean non-virtual intra-domain period: 12.1197 ns (82.51 MHz) Placement estimated fanout-weighted geomean non-virtual intra-domain period: 12.1197 ns (82.51 MHz) Placement cost: 0.99977, bb_cost: 143.831, td_cost: 8.61023e-08, Placement resource usage: io implemented as io : 162 clb implemented as clb : 20 mult_36 implemented as mult_36: 7 Placement number of temperatures: 140 Placement total # of swap attempts: 151949 Swaps accepted: 79109 (52.1 %) Swaps rejected: 72596 (47.8 %) Swaps aborted : 244 ( 0.2 %) Placement Quench timing analysis took 0.000368542 seconds (0.000330824 STA, 3.7718e-05 slack) (1 full updates: 1 setup, 0 hold, 0 combined). Placement Total timing analysis took 0.146908 seconds (0.135032 STA, 0.011876 slack) (142 full updates: 142 setup, 0 hold, 0 combined). update_td_costs: connections 0.000949709 nets 0 sum_nets 0.000583226 total 0.00163347 # Placement took 0.48 seconds (max_rss 67.9 MiB, delta_rss +0.0 MiB) # Routing RR graph channel widths unchanged, skipping RR graph rebuild Confirming router algorithm: TIMING_DRIVEN. ## Initializing router criticalities Initial Net Connection Criticality Histogram: [ 0: 0.1) 200 ( 19.5%) |************************* [ 0.1: 0.2) 80 ( 7.8%) |********** [ 0.2: 0.3) 113 ( 11.0%) |************** [ 0.3: 0.4) 45 ( 4.4%) |****** [ 0.4: 0.5) 11 ( 1.1%) |* [ 0.5: 0.6) 82 ( 8.0%) |********** [ 0.6: 0.7) 32 ( 3.1%) |**** [ 0.7: 0.8) 2 ( 0.2%) | [ 0.8: 0.9) 80 ( 7.8%) |********** [ 0.9: 1) 381 ( 37.1%) |*********************************************** ## Initializing router criticalities took 0.01 seconds (max_rss 67.9 MiB, delta_rss +0.0 MiB) ---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wirelength CPD sTNS sWNS hTNS hWNS Est Succ (sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter ---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- 1 0.0 0.0 0 365756 544 938 680 ( 2.052%) 8700 (50.0%) 13.231 -849.8 -13.231 0.000 0.000 N/A Incr Slack updates 142 in 0.00445613 sec Full Max Req/Worst Slack updates 34 in 0.000162615 sec Incr Max Req/Worst Slack updates 108 in 0.000404686 sec Incr Criticality updates 82 in 0.0021563 sec Full Criticality updates 60 in 0.00396201 sec 2 0.0 0.5 28 362867 515 907 614 ( 1.853%) 8808 (50.6%) 13.231 -851.8 -13.231 0.000 0.000 N/A 3 0.0 0.6 11 391592 490 871 602 ( 1.816%) 9175 (52.7%) 13.279 -870.1 -13.279 0.000 0.000 N/A 4 0.0 0.8 31 417267 472 856 541 ( 1.632%) 9532 (54.8%) 13.293 -879.4 -13.293 0.000 0.000 N/A 5 0.0 1.1 29 412488 455 843 504 ( 1.521%) 9658 (55.5%) 13.290 -889.1 -13.290 0.000 0.000 N/A 6 0.0 1.4 19 436734 436 818 481 ( 1.451%) 10064 (57.8%) 13.284 -896.3 -13.284 0.000 0.000 N/A 7 0.0 1.9 18 447502 414 778 444 ( 1.340%) 10266 (59.0%) 13.316 -900.2 -13.316 0.000 0.000 N/A 8 0.1 2.4 29 501235 412 778 397 ( 1.198%) 10736 (61.7%) 13.301 -914.2 -13.301 0.000 0.000 N/A 9 0.1 3.1 19 525711 392 754 372 ( 1.122%) 10931 (62.8%) 13.301 -929.3 -13.301 0.000 0.000 N/A 10 0.1 4.1 35 600805 360 726 332 ( 1.002%) 11373 (65.3%) 13.301 -923.5 -13.301 0.000 0.000 83 11 0.1 5.3 44 681143 368 731 313 ( 0.944%) 11643 (66.9%) 13.301 -965.8 -13.301 0.000 0.000 73 12 0.1 6.9 26 728092 353 709 316 ( 0.953%) 11976 (68.8%) 13.418 -991.2 -13.418 0.000 0.000 76 13 0.1 9.0 30 780697 373 733 322 ( 0.972%) 12505 (71.8%) 13.435 -982.7 -13.435 0.000 0.000 91 14 0.1 11.6 42 812225 351 720 314 ( 0.947%) 12687 (72.9%) 13.457 -996.0 -13.457 0.000 0.000 113 15 0.1 15.1 40 859705 358 723 302 ( 0.911%) 12977 (74.5%) 13.679 -1027. -13.679 0.000 0.000 167 Routing aborted, the predicted iteration for a successful route (167.4) is too high. Routing failed. Failed routing attempt #0 Total number of overused nodes: 302 Total number of overused nodes is larger than the logging limit. Displaying the first 50 entries Routing Failure Diagnostics: Printing Overused Nodes Information ------ ------- ---------- --------- -------- ------------ ------- ------- ------- ------- ------- ------- No. NodeId Occupancy Capacity RR Node Direction Side PTC Xlow Ylow Xhigh Yhigh type NUM ------ ------- ---------- --------- -------- ------------ ------- ------- ------- ------- ------- ------- 0 11136 2 1 IPIN N/A LEFT 7 7 4 7 4 1 11139 3 1 IPIN N/A BOTTOM 10 7 4 7 4 2 11219 2 1 IPIN N/A LEFT 3 7 5 7 5 3 11224 2 1 IPIN N/A TOP 8 7 5 7 5 4 11250 2 1 IPIN N/A BOTTOM 34 7 5 7 5 5 11314 2 1 IPIN N/A LEFT 11 7 6 7 6 6 11390 2 1 IPIN N/A TOP 0 7 7 7 7 7 11394 2 1 IPIN N/A TOP 4 7 7 7 7 8 11397 2 1 IPIN N/A LEFT 7 7 7 7 7 9 11399 2 1 IPIN N/A RIGHT 9 7 7 7 7 10 11404 2 1 IPIN N/A BOTTOM 14 7 7 7 7 11 11410 2 1 IPIN N/A TOP 20 7 7 7 7 12 11418 2 1 IPIN N/A TOP 28 7 7 7 7 13 11419 2 1 IPIN N/A RIGHT 29 7 7 7 7 14 11422 2 1 IPIN N/A TOP 32 7 7 7 7 15 11425 2 1 IPIN N/A LEFT 35 7 7 7 7 16 11426 2 1 IPIN N/A TOP 36 7 7 7 7 17 11657 2 1 IPIN N/A BOTTOM 6 7 10 7 10 18 11659 2 1 IPIN N/A TOP 8 7 10 7 10 19 11677 2 1 IPIN N/A BOTTOM 26 7 10 7 10 20 11742 2 1 IPIN N/A TOP 4 7 11 7 11 21 11746 2 1 IPIN N/A TOP 8 7 11 7 11 22 11767 2 1 IPIN N/A RIGHT 29 7 11 7 11 23 11770 2 1 IPIN N/A TOP 32 7 11 7 11 24 11773 2 1 IPIN N/A LEFT 35 7 11 7 11 25 11775 2 1 IPIN N/A RIGHT 37 7 11 7 11 26 11833 2 1 IPIN N/A TOP 8 7 12 7 12 27 11940 2 1 IPIN N/A TOP 28 7 13 7 13 28 11948 2 1 IPIN N/A TOP 36 7 13 7 13 29 11999 2 1 IPIN N/A TOP 0 7 14 7 14 30 12027 2 1 IPIN N/A TOP 28 7 14 7 14 31 12033 2 1 IPIN N/A BOTTOM 34 7 14 7 14 32 12038 2 1 IPIN N/A LEFT 39 7 14 7 14 33 12683 2 1 IPIN N/A RIGHT 9 8 3 8 3 34 12762 2 1 IPIN N/A RIGHT 1 8 4 8 4 35 12766 2 1 IPIN N/A RIGHT 5 8 4 8 4 36 12769 2 1 IPIN N/A TOP 8 8 4 8 4 37 12778 2 1 IPIN N/A RIGHT 17 8 4 8 4 38 12786 2 1 IPIN N/A RIGHT 25 8 4 8 4 39 12849 2 1 IPIN N/A RIGHT 1 8 5 8 5 40 12851 2 1 IPIN N/A LEFT 3 8 5 8 5 41 12857 2 1 IPIN N/A RIGHT 9 8 5 8 5 42 12861 2 1 IPIN N/A RIGHT 13 8 5 8 5 43 12863 2 1 IPIN N/A LEFT 15 8 5 8 5 44 12870 2 1 IPIN N/A BOTTOM 22 8 5 8 5 45 27991 2 1 CHANX DEC_DIR N/A 15 1 0 3 0 46 28001 2 1 CHANX DEC_DIR N/A 25 1 0 4 0 47 28013 2 1 CHANX DEC_DIR N/A 19 2 0 5 0 48 28016 2 1 CHANX INC_DIR N/A 4 3 0 6 0 49 28021 2 1 CHANX DEC_DIR N/A 21 3 0 6 0 Final Net Connection Criticality Histogram: [ 0: 0.1) 153 ( 14.9%) |***************** [ 0.1: 0.2) 57 ( 5.6%) |****** [ 0.2: 0.3) 84 ( 8.2%) |********* [ 0.3: 0.4) 96 ( 9.4%) |*********** [ 0.4: 0.5) 43 ( 4.2%) |***** [ 0.5: 0.6) 70 ( 6.8%) |******** [ 0.6: 0.7) 59 ( 5.8%) |******* [ 0.7: 0.8) 1 ( 0.1%) | [ 0.8: 0.9) 42 ( 4.1%) |***** [ 0.9: 1) 421 ( 41.0%) |*********************************************** Router Stats: total_nets_routed: 6293 total_connections_routed: 11885 total_heap_pushes: 8323819 total_heap_pops: 2538687 # Routing took 1.03 seconds (max_rss 67.9 MiB, delta_rss +0.0 MiB) Circuit is unroutable with a channel width factor of 32. For a detailed report on the RR node overuse information (report_overused_nodes.rpt), specify --generate_rr_node_overuse_report on. VPR failed to implement circuit The entire flow of VPR took 2.20 seconds (max_rss 67.9 MiB) Incr Slack updates 16 in 0.00078641 sec Full Max Req/Worst Slack updates 5 in 2.5948e-05 sec Incr Max Req/Worst Slack updates 11 in 5.9685e-05 sec Incr Criticality updates 4 in 0.000253393 sec Full Criticality updates 12 in 0.000871482 sec Command exited with non-zero status 2 Command being timed: "/home/hubingra/master/vtr-verilog-to-routing/vtr_flow/../vpr/vpr k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2 --circuit_file diffeq2.pre-vpr.blif --timing_update_type incremental --max_logged_overused_rr_nodes 50 --route_chan_width 32 --generate_rr_node_overuse_report off" User time (seconds): 2.14 System time (seconds): 0.07 Percent of CPU this job got: 99% Elapsed (wall clock) time (h:mm:ss or m:ss): 0:02.21 Average shared text size (kbytes): 0 Average unshared data size (kbytes): 0 Average stack size (kbytes): 0 Average total size (kbytes): 0 Maximum resident set size (kbytes): 69556 Average resident set size (kbytes): 0 Major (requiring I/O) page faults: 0 Minor (reclaiming a frame) page faults: 26120 Voluntary context switches: 1 Involuntary context switches: 3 Swaps: 0 File system inputs: 7458 File system outputs: 3965 Socket messages sent: 0 Socket messages received: 0 Signals delivered: 0 Page size (bytes): 4096 Exit status: 2