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[test][strong_odin]
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‎vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.15 vpr 57.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 -1 782a17c Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-08-16T12:48:04 -1 -1 59008 1 4 28 32 2 10 9 4 4 16 clb auto 19.2 MiB 0.00 20 27 15 8 4 57.6 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 3.6649e-05 3.0788e-05 0.000332461 0.000302474 8 12 5 72000 72000 5593.62 349.601 0.01 0.00463095 0.00390158 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00184241 0.00173742
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timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.15 vpr 57.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 -1 782a17c Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-08-16T12:48:04 -1 -1 58880 1 4 28 32 2 10 9 4 4 16 clb auto 19.1 MiB 0.00 20 27 15 8 4 57.5 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 3.6368e-05 3.0868e-05 0.000334423 0.000304918 8 12 5 72000 72000 5593.62 349.601 0.01 0.00434957 0.00368628 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00187403 0.00175995
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timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.15 vpr 57.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 -1 782a17c Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-08-16T12:48:04 -1 -1 58748 1 4 28 32 2 10 9 4 4 16 clb auto 19.1 MiB 0.00 20 27 15 8 4 57.4 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 3.6097e-05 3.0537e-05 0.000332419 0.000303054 8 12 5 72000 72000 5593.62 349.601 0.01 0.00433458 0.00365113 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00181848 0.00171448
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timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 4.13 vpr 202.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 84e0337-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:44:22 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 207748 1 4 28 32 2 10 9 4 4 16 clb auto 51.9 MiB 0.14 20 27 15 8 4 193.9 MiB 0.03 0.00 2.44626 0 0 2.44626 0.51 0.000583271 0.000535066 0.00308541 0.00258587 8 12 5 72000 72000 5593.62 349.601 0.86 0.0614891 0.0547303 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.010886 0.00952369
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timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 4.18 vpr 203.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 84e0337-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:44:22 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 208344 1 4 28 32 2 10 9 4 4 16 clb auto 52.0 MiB 0.14 20 27 15 8 4 194.0 MiB 0.03 0.00 2.44626 0 0 2.44626 0.51 0.000579833 0.000533235 0.00309464 0.0025854 8 12 5 72000 72000 5593.62 349.601 0.86 0.0608434 0.0541405 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.0108096 0.00946964
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timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 4.13 vpr 202.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 84e0337-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:44:22 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 207504 1 4 28 32 2 10 9 4 4 16 clb auto 51.4 MiB 0.14 20 27 15 8 4 193.1 MiB 0.03 0.00 2.44626 0 0 2.44626 0.51 0.000572304 0.000525073 0.00310109 0.00259353 8 12 5 72000 72000 5593.62 349.601 0.86 0.0611009 0.054383 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.0108444 0.00950833

‎vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.70 vpr 54.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 55736 2 2 22 24 2 4 6 4 4 16 clb auto 16.0 MiB 0.00 4 54.4 MiB 0.00 0.00 1.293 0 0 1.293 0.02 3.0248e-05 2.3255e-05 0.00029412 0.000252171 6 6 1 215576 107788 3924.73 245.296 0.09 0.0011793 0.00104221 9 3 5 5 233 128 1.293 1.293 0 0 0 0 5503.53 343.971 0.00 0.06 0.000728173 0.000642893
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 3.91 vpr 202.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 84e0337-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:44:22 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 207240 2 2 22 24 2 4 6 4 4 16 clb auto 51.8 MiB 0.10 4 15 2 10 3 193.1 MiB 0.02 0.00 1.297 0 0 1.297 0.50 0.000500888 0.000459494 0.00266891 0.00218049 4 6 2 72000 36000 2827.54 176.721 0.84 0.0129763 0.0108607 644 852 -1 6 2 4 4 138 80 1.297 1.297 0 0 0 0 4025.56 251.598 0.01 0.02 0.16 -1 -1 0.01 0.00609768 0.00517486

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