Merge pull request #1948 from verilog-to-routing/S10_architecture_file

Stratix 10 architecture description

Author: vaughnbetz

.gitignore

@@ -33,10 +33,9 @@ temp/
 #
 titan_release*.tar.gz
 vtr_flow/arch/titan/*.xml
-vtr_flow/benchmarks/titan_blif/*.blif
-vtr_flow/benchmarks/titan_blif/*.sdc
-vtr_flow/benchmarks/titan_other_blif/*.blif
-vtr_flow/benchmarks/titan_other_blif/*.sdc
+vtr_flow/benchmarks/titan_blif/other_benchmarks
+vtr_flow/benchmarks/titan_blif/titan23
+vtr_flow/benchmarks/titan_blif/titan_new
 
 
 #

doc/src/vtr/benchmarks.rst

@@ -55,12 +55,12 @@ The VTR benchmarks are also included as pre-synthesized BLIF files under: ::
 
 Titan Benchmarks
 ----------------
-The Titan benchmarks :cite:`murray_titan,murray_timing_driven_titan` are a set of large modern FPGA benchmarks.
+The Titan benchmarks are a set of large modern FPGA benchmarks compatible with Intel Stratix IV :cite:`murray_titan,murray_timing_driven_titan` and Stratix 10 :cite:`talaei_titan2` devices.
 The pre-synthesized versions of these benchmarks are compatible with recent versions of VPR.
 
 The Titan benchmarks are suitable for large-scale FPGA CAD research, and FPGA architecture research which does not require synthesizing new netlist primitives.
 
-.. note:: The Titan benchmarks are not included with the VTR release (due to their size). However they can be downloaded and extracted by running ``make get_titan_benchmarks`` from the root of the VTR tree.  They can also be `downloaded manually <http://www.eecg.utoronto.ca/~kmurray/titan/>`_.
+.. note:: The Titan benchmarks are not included with the VTR release (due to their size). However they can be downloaded and extracted by running ``make get_titan_benchmarks`` from the root of the VTR tree.  They can also be `downloaded manually <https://www.eecg.utoronto.ca/~vaughn/titan/>`_.
 
 .. seealso:: :ref:`titan_benchmarks_tutorial`
 

doc/src/vtr/cad_flow.rst

@@ -24,7 +24,7 @@ CAD Flow Variations
 
 Titan CAD Flow
 ~~~~~~~~~~~~~~
-The Titan CAD Flow :cite:`murray_titan,murray_timing_driven_titan` interfaces Intel's Quartus tool with VPR.
+The Titan CAD Flow :cite:`murray_titan,murray_timing_driven_titan, talaei_titan2` interfaces Intel's Quartus tool with VPR.
 This allows designs requiring industrial strength language coverage and IP to be brought into VPR.
 
 Other CAD Flow Variants

doc/src/z_references.bib

@@ -288,6 +288,13 @@ @article{murray_timing_driven_titan
     keywords = {Benchmarks, CAD, FPGA},
 }
 
+@article{talaei_titan2,
+    author = {K. Talaei Khoozani, A. Ahmadian Dehkordi, V. Betz},
+    title = {Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture Capture},
+    journal = {International Conference on Field-Programmable Logic and Applications},
+    year = {2023},
+}
+
 @inproceedings{murray_titan,
     author={Murray, K.E. and Whitty, S. and Liu, S. and Luu, J. and Betz, V.},
     booktitle={Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on},

utils/vqm2blif/src/base/cleanup.cpp

@@ -676,7 +676,7 @@ void verify_netlist ( t_node** nodes, int num_nodes, busvec* buses, std::unorder
 				net_source = (t_net*)temp_net->source;
 
                 //PIN_INOUT should have been removed earlier
-				VTR_ASSERT((net_source->pin->type == PIN_INPUT)||(net_source->pin->type == PIN_WIRE));
+				VTR_ASSERT((net_source->pin->type == PIN_OUTPUT) || (net_source->pin->type == PIN_INPUT)||(net_source->pin->type == PIN_WIRE));
 
 				VTR_ASSERT((unsigned int)net_source->bus_index < child_count.size());
 				VTR_ASSERT((unsigned int)net_source->wire_index < child_count[net_source->bus_index].size());

vtr_flow/arch/titan/README.rst

@@ -2,7 +2,7 @@ Titan Benchmarks
 --------------------------------------------------
 This folder contains architecture files for use with Titan.
 
-The `Titan <http://www.eecg.utoronto.ca/~kmurray/titan/>` benchmarks are distributed
+The `Titan <http://www.eecg.utoronto.ca/~vaughn/titan/>` benchmarks are distributed
 separately from VTR due to their large size.
 
 To integrate them into VTR run:
@@ -15,18 +15,17 @@ This will download and extract the benchmark netlists to:
 
     <vtr>/vtr_flow/benchmarks/titan_blif/
 
-and
-
-    <vtr>/vtr_flow/benchmarks/titan_other_blif/
-
-where 'titan_blif' contains the main Titan23 benchmarks, and 'titan_other_blif' contains smaller 
-titan-like benchmarks which are useful for testing (but should not be used for architecture and 
-CAD evaluation).
 
 
 Directory Structure
 --------------------------------------------------
 
+stratix10_arch.timing.xml:
+    A detailed capture of Intel's Stratix 10 FPGA architecture, with 
+    small architectural adjustments to ensure compatibility with VPR. It 
+    incorporates a timing model that has been fine-tuned to match the 
+    Stratix 10 timing model integrated into Intel's Quartus Prime CAD tools.
+
 stratixiv_arch.timing.xml:
     An enhanced capture of Altera's Stratix IV FPGA architecture. It makes some 
     relatively minor architectural approximations to be compatible with VPR. It