Merge pull request #740 from CAS-Atlantic/generate_expansion

ODIN II: support nested loops in generate

Author: jeanlego

ODIN_II/SRC/ast_loop_unroll.cpp

@@ -33,14 +33,14 @@ inline bool is_unsupported_pre(ast_node_t* node){
 bool is_unsupported_post(ast_node_t* node, ast_node_t* symbol);
 bool is_unsupported_condition(ast_node_t* node, ast_node_t* symbol);
 
-ast_node_t* for_preprocessor(ast_node_t *ast_module, ast_node_t* node, ast_node_t ****instances, int *num_unrolled, int *num_original);
-ast_node_t* replace_fors(ast_node_t *ast_module, ast_node_t* node, ast_node_t ****instances, int *num_unrolled, int *num_original);
+ast_node_t* for_preprocessor(ast_node_t *ast_module, ast_node_t* node, ast_node_t ***removed_instances, int *num_removed);
+ast_node_t* replace_fors(ast_node_t *ast_module, ast_node_t* node, ast_node_t ***removed_instances, int *num_removed);
 ast_node_t* resolve_for(ast_node_t *ast_module, ast_node_t* node, ast_node_t ****instances, int *num_unrolled, int *num_original);
 int resolve_pre_condition(ast_node_t* node, ast_node_t** number);
 condition_function resolve_condition(ast_node_t* node, ast_node_t* symbol, int* error_code);
 post_condition_function resolve_binary_operation(ast_node_t* node);
 post_condition_function resolve_post_condition(ast_node_t* assignment, ast_node_t* symbol, int* error_code);
-ast_node_t* dup_and_fill_body(ast_node_t *ast_module, ast_node_t* body, ast_node_t* pre, ast_node_t** value, int* error_code, ast_node_t ****instances, int *num_unrolled, int *num_original);
+ast_node_t* dup_and_fill_body(ast_node_t *ast_module, ast_node_t* body, ast_node_t* pre, ast_node_t** value, int* error_code, ast_node_t ****instances, int *num_unrolled, int *num_original, bool is_nested);
 ast_node_t *replace_named_module(ast_node_t* module, ast_node_t** value);
 
 #endif

ODIN_II/SRC/include/ast_loop_unroll.h

@@ -349,6 +349,7 @@ struct typ
 		short is_wire;
 		short is_reg;
 		short is_integer;
+		short is_genvar;
 		short is_signed;
 		short is_initialized; // should the variable be initialized with some value?
 		long initial_value;

ODIN_II/SRC/include/odin_types.h

@@ -16,6 +16,7 @@ const char *name_based_on_op(operation_list op);
 
 char *make_signal_name(char *signal_name, int bit);
 char *make_full_ref_name(const char *previous, const char *module_name, const char *module_instance_name, const char *signal_name, long bit);
+char *make_full_name_w_o_array_ref(const char *previous, const char *module_name, const char *module_instance_name);
 
 char *twos_complement(char *str);
 int is_string_of_radix(char *string, int radix);

ODIN_II/SRC/include/odin_util.h

@@ -127,6 +127,33 @@ char *make_full_ref_name(const char *previous, const char *module_name, const ch
 	return vtr::strdup(return_string.str().c_str());
 }
 
+/*---------------------------------------------------------------------------------------------
+ * (function: make_full_name_w_o_array_ref)
+// {previous_string}.module_name+instance_name
+ *-------------------------------------------------------------------------------------------*/
+char *make_full_name_w_o_array_ref(const char *previous, const char *module_name, const char *module_instance_name)
+{
+
+	std::stringstream return_string;
+	if(previous)								 
+		return_string << previous;
+
+	if(module_name) 							 
+		return_string	<< "." << module_name << "+" << module_instance_name;
+		
+
+	std::string name = return_string.str();
+
+	size_t idx = name.find_first_of('[', 0);
+	if (idx != std::string::npos)
+	{
+		// delete array refs
+		name.erase(idx, std::string::npos);
+	}
+	
+	return vtr::strdup(name.c_str());
+}
+
 /*---------------------------------------------------------------------------------------------
  * (function: twos_complement)
  * Changes a bit string to its twos complement value

ODIN_II/SRC/odin_util.cpp

@@ -864,11 +864,15 @@ ast_node_t *markAndProcessSymbolListWith(ids top_type, ids id, ast_node_t *symbo
 					symbol_list->children[i]->types.variable.is_reg = true;
 					break;
 				case INTEGER:
-			    case GENVAR:
 					oassert(is_signed && "Integers must always be signed");
 					symbol_list->children[i]->types.variable.is_signed = is_signed;			
 					symbol_list->children[i]->types.variable.is_integer = true;
 					break;
+			    case GENVAR:
+					oassert(is_signed && "Genvars must always be signed");
+					symbol_list->children[i]->types.variable.is_signed = is_signed;			
+					symbol_list->children[i]->types.variable.is_integer = true; // TODO: flip to is_genvar
+					break;
 				default:
 					oassert(false);
 			}

ODIN_II/SRC/parse_making_ast.cpp

@@ -101,14 +101,16 @@ int yylex(void);
 %type <node> gate_declaration single_input_gate_instance
 %type <node> module_instantiation module_instance function_instance list_of_module_connections list_of_function_connections
 %type <node> list_of_multiple_inputs_gate_connections
-%type <node> module_connection always statement function_statement blocking_assignment generate
-%type <node> non_blocking_assignment case_item_list case_items seq_block generate_for
-%type <node> stmt_list delay_control event_expression_list event_expression
+%type <node> module_connection always statement function_statement blocking_assignment
+%type <node> non_blocking_assignment conditional_statement case_statement case_item_list case_items seq_block
+%type <node> stmt_list delay_control event_expression_list event_expression loop_statement
 %type <node> expression primary probable_expression_list expression_list module_parameter
-%type <node> list_of_module_parameters
+%type <node> list_of_module_parameters localparam_declaration
 %type <node> specify_block list_of_specify_items specify_item specparam_declaration
 %type <node> specify_pal_connect_declaration c_function_expression_list c_function
 %type <node> initial_block parallel_connection list_of_blocking_assignment
+%type <node> list_of_generate_items generate_item generate loop_generate_construct if_generate_construct 
+%type <node> case_generate_construct case_generate_item_list case_generate_items generate_block
 
 %%
 
@@ -193,19 +195,31 @@ module_item:
 	| input_declaration	 	{$$ = $1;}
 	| output_declaration 	{$$ = $1;}
 	| inout_declaration 	{$$ = $1;}
-	| net_declaration 		{$$ = $1;}
-	| genvar_declaration	{$$ = $1;}
-	| integer_declaration 	{$$ = $1;}
-	| continuous_assign		{$$ = $1;}
-	| gate_declaration		{$$ = $1;}
-	| generate				{$$ = $1;}
-	| module_instantiation	{$$ = $1;}
-	| function_declaration	{$$ = $1;}
-	| initial_block			{$$ = $1;}
-	| always				{$$ = $1;}
-	| defparam_declaration	{$$ = $1;}
 	| specify_block			{$$ = $1;}
-	| c_function ';'		{$$ = $1;}
+	| generate_item			{$$ = $1;}
+	| generate				{$$ = $1;}
+	;
+
+list_of_generate_items:
+	list_of_generate_items generate_item	{$$ = newList_entry($1, $2);}
+	| generate_item							{$$ = newList(BLOCK, $1);}
+
+generate_item:
+	localparam_declaration		{$$ = $1;}
+	| net_declaration 			{$$ = $1;}
+	| genvar_declaration		{$$ = $1;}
+	| integer_declaration 		{$$ = $1;}
+	| continuous_assign			{$$ = $1;}
+	| gate_declaration			{$$ = $1;}
+	| module_instantiation		{$$ = $1;}
+	| function_declaration		{$$ = $1;}
+	| initial_block				{$$ = $1;}
+	| always					{$$ = $1;}
+	| defparam_declaration		{$$ = $1;}
+	| c_function ';'			{$$ = $1;}
+	| if_generate_construct		{$$ = $1;}
+	| case_generate_construct	{$$ = $1;}
+	| loop_generate_construct	{$$ = $1;}
 	;
 
 function_declaration:
@@ -242,8 +256,11 @@ function_input_declaration:
 
 parameter_declaration:
 	vPARAMETER vSIGNED variable_list ';'	{$$ = markAndProcessSymbolListWith(MODULE,PARAMETER, $3, true);}
-	| vLOCALPARAM vSIGNED variable_list ';'	{$$ = markAndProcessSymbolListWith(MODULE,LOCALPARAM, $3, true);}
 	| vPARAMETER variable_list ';'			{$$ = markAndProcessSymbolListWith(MODULE,PARAMETER, $2, false);}
+	;
+
+localparam_declaration:
+	vLOCALPARAM vSIGNED variable_list ';'	{$$ = markAndProcessSymbolListWith(MODULE,LOCALPARAM, $3, true);}
 	| vLOCALPARAM variable_list ';'			{$$ = markAndProcessSymbolListWith(MODULE,LOCALPARAM, $2, false);}
 	;
 
@@ -424,28 +441,65 @@ always:
 	;
 
 generate:
-	vGENERATE generate_for vENDGENERATE	{$$ = newGenerate($2, yylineno);}
+	vGENERATE list_of_generate_items vENDGENERATE	{$$ = newGenerate($2, yylineno);}
+	;
+
+loop_generate_construct:
+	vFOR '(' blocking_assignment ';' expression ';' blocking_assignment ')' generate_block	{$$ = newFor($3, $5, $7, $9, yylineno);}
+	; 
+
+if_generate_construct:
+	vIF '(' expression ')' generate_block %prec LOWER_THAN_ELSE		{$$ = newIf($3, $5, NULL, yylineno);}
+	| vIF '(' expression ')' generate_block vELSE generate_block	{$$ = newIf($3, $5, $7, yylineno);}
+	;
+
+case_generate_construct:
+	vCASE '(' expression ')' case_generate_item_list vENDCASE			{$$ = newCase($3, $5, yylineno);}
+	;
+
+case_generate_item_list:
+	case_generate_item_list case_generate_items	{$$ = newList_entry($1, $2);}
+	| case_generate_items			{$$ = newList(CASE_LIST, $1);}
+	;
+
+case_generate_items:
+	expression ':' generate_block	{$$ = newCaseItem($1, $3, yylineno);}
+	| vDEFAULT ':' generate_block	{$$ = newDefaultCase($3, yylineno);}
+	;
+
+generate_block:
+	generate_item										{$$ = $1;}
+	| vBEGIN list_of_generate_items vEND				{$$ = $2;}
+	| vBEGIN ':' vSYMBOL_ID list_of_generate_items vEND	{$$ = $4;}
 	;
 
 function_statement:
 	statement	{$$ = newAlways(NULL, $1, yylineno);}
 	;
 
-generate_for:
-	vFOR '(' blocking_assignment ';' expression ';' blocking_assignment ')' vBEGIN module_instantiation vEND	{$$ = newFor($3, $5, $7, $10, yylineno);}
-	; 
-
 statement:
 	seq_block													{$$ = $1;}
 	| c_function ';'											{$$ = $1;}
 	| blocking_assignment ';'									{$$ = $1;}
 	| non_blocking_assignment ';'								{$$ = $1;}
-	| vIF '(' expression ')' statement %prec LOWER_THAN_ELSE				{$$ = newIf($3, $5, NULL, yylineno);}
-	| vIF '(' expression ')' statement vELSE statement					{$$ = newIf($3, $5, $7, yylineno);}
-	| vCASE '(' expression ')' case_item_list vENDCASE					{$$ = newCase($3, $5, yylineno);}
-	| vFOR '(' blocking_assignment ';' expression ';' blocking_assignment ')' statement	{$$ = newFor($3, $5, $7, $9, yylineno);}
+	| conditional_statement										{$$ = $1;}
+	| case_statement											{$$ = $1;}
+	| loop_statement											{$$ = $1;}
+	| ';'														{$$ = NULL;}
+	;
+
+loop_statement:
+	vFOR '(' blocking_assignment ';' expression ';' blocking_assignment ')' statement	{$$ = newFor($3, $5, $7, $9, yylineno);}
 	| vWHILE '(' expression ')' statement							{$$ = newWhile($3, $5, yylineno);}
-	| ';'											{$$ = NULL;}
+	;
+
+case_statement:
+	vCASE '(' expression ')' case_item_list vENDCASE			{$$ = newCase($3, $5, yylineno);}
+	;
+
+conditional_statement:
+	vIF '(' expression ')' statement %prec LOWER_THAN_ELSE	{$$ = newIf($3, $5, NULL, yylineno);}
+	| vIF '(' expression ')' statement vELSE statement			{$$ = newIf($3, $5, $7, yylineno);}
 	;
 
 list_of_specify_items:

ODIN_II/SRC/verilog_bison.y

@@ -0,0 +1,28 @@
+module down_counter
+(
+    clk, out1
+);
+    input rst1, rst2, clk;
+    output reg [15:0] out1;
+
+    wire [15:0] a;
+
+    genvar i;
+    genvar j;
+    generate
+        for (i=0; i<4; i=i+1) begin : outer_loop
+            for (j=0; j<4; j=j+1) begin : inner_loop
+                assign a[(i*4)+j] = 1'b1;
+            end
+        end
+    endgenerate
+
+    always @ (posedge clk)
+    begin
+        if (rst1 && rst2)
+            out1 <= a;
+        else
+            out1 <= out1 - 1;
+    end
+
+endmodule

ODIN_II/regression_test/benchmark/micro/generate.v

@@ -0,0 +1,101 @@
+GLOBAL_SIM_BASE_CLK rst1 rst2 clk
+1 0 1 1 
+0 1 0 1 
+1 1 0 0 
+0 1 1 0 
+1 0 0 1 
+0 0 1 1 
+1 0 0 0 
+0 1 1 0 
+1 0 1 1 
+0 0 1 1 
+1 1 1 0 
+0 1 0 0 
+1 0 1 1 
+0 0 0 1 
+1 0 0 0 
+0 1 0 0 
+1 1 0 1 
+0 1 0 1 
+1 1 0 0 
+0 0 1 0 
+1 0 0 1 
+0 0 1 1 
+1 1 0 0 
+0 0 1 0 
+1 0 0 1 
+0 0 0 1 
+1 1 1 0 
+0 0 0 0 
+1 0 0 1 
+0 1 0 1 
+1 1 1 0 
+0 1 1 0 
+1 1 1 1 
+0 1 0 1 
+1 1 1 0 
+0 1 0 0 
+1 1 0 1 
+0 1 0 1 
+1 1 0 0 
+0 1 1 0 
+1 0 0 1 
+0 0 1 1 
+1 0 0 0 
+0 0 1 0 
+1 1 1 1 
+0 1 1 1 
+1 1 0 0 
+0 1 1 0 
+1 1 0 1 
+0 1 0 1 
+1 0 1 0 
+0 0 0 0 
+1 0 0 1 
+0 1 1 1 
+1 1 0 0 
+0 1 0 0 
+1 0 1 1 
+0 0 1 1 
+1 0 1 0 
+0 0 0 0 
+1 0 1 1 
+0 0 0 1 
+1 0 1 0 
+0 0 0 0 
+1 0 0 1 
+0 1 0 1 
+1 0 0 0 
+0 0 0 0 
+1 1 1 1 
+0 1 1 1 
+1 0 1 0 
+0 1 1 0 
+1 0 1 1 
+0 0 0 1 
+1 0 0 0 
+0 0 0 0 
+1 1 1 1 
+0 0 1 1 
+1 0 1 0 
+0 0 0 0 
+1 1 1 1 
+0 1 1 1 
+1 0 1 0 
+0 1 1 0 
+1 0 0 1 
+0 0 0 1 
+1 1 0 0 
+0 0 0 0 
+1 1 0 1 
+0 0 0 1 
+1 0 0 0 
+0 1 1 0 
+1 1 0 1 
+0 1 1 1 
+1 1 0 0 
+0 0 1 0 
+1 1 0 1 
+0 0 0 1 
+1 0 0 0 
+0 1 0 0