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Merge pull request #3022 from AlexandreSinger/feature-models-cleanup
[LibArchFPGA] Added Library Model IDs as constexpr
2 parents d504b0a + 3ba6acb commit f689cdb

17 files changed

+56
-96
lines changed

‎libs/libarchfpga/src/logic_types.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ LogicalModels::LogicalModels() {
2828
//INPAD
2929
{
3030
LogicalModelId inpad_model_id = create_logical_model(MODEL_INPUT);
31+
VTR_ASSERT_OPT(inpad_model_id == MODEL_INPUT_ID);
3132
t_model& inpad_model = get_model(inpad_model_id);
3233

3334
inpad_model.inputs = nullptr;
@@ -47,6 +48,7 @@ LogicalModels::LogicalModels() {
4748
//OUTPAD
4849
{
4950
LogicalModelId outpad_model_id = create_logical_model(MODEL_OUTPUT);
51+
VTR_ASSERT_OPT(outpad_model_id == MODEL_OUTPUT_ID);
5052
t_model& outpad_model = get_model(outpad_model_id);
5153

5254
outpad_model.inputs = new t_model_ports;
@@ -66,6 +68,7 @@ LogicalModels::LogicalModels() {
6668
//LATCH
6769
{
6870
LogicalModelId latch_model_id = create_logical_model(MODEL_LATCH);
71+
VTR_ASSERT_OPT(latch_model_id == MODEL_LATCH_ID);
6972
t_model& latch_model = get_model(latch_model_id);
7073
t_model_ports* latch_model_input_port_1 = new t_model_ports;
7174
t_model_ports* latch_model_input_port_2 = new t_model_ports;
@@ -104,6 +107,7 @@ LogicalModels::LogicalModels() {
104107
//NAMES
105108
{
106109
LogicalModelId names_model_id = create_logical_model(MODEL_NAMES);
110+
VTR_ASSERT_OPT(names_model_id == MODEL_NAMES_ID);
107111
t_model& names_model = get_model(names_model_id);
108112

109113
names_model.inputs = new t_model_ports;

‎libs/libarchfpga/src/logic_types.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,13 @@ class LogicalModels {
9797
static constexpr const char* MODEL_INPUT = ".input";
9898
static constexpr const char* MODEL_OUTPUT = ".output";
9999

100+
// The IDs of each of the library models. These are known ahead of time,
101+
// and making these constexpr can save having to look them up in this class.
102+
static constexpr LogicalModelId MODEL_INPUT_ID = LogicalModelId(0);
103+
static constexpr LogicalModelId MODEL_OUTPUT_ID = LogicalModelId(1);
104+
static constexpr LogicalModelId MODEL_LATCH_ID = LogicalModelId(2);
105+
static constexpr LogicalModelId MODEL_NAMES_ID = LogicalModelId(3);
106+
100107
// Iterator for the logical model IDs array.
101108
typedef typename vtr::vector_map<LogicalModelId, LogicalModelId>::const_iterator model_iterator;
102109

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1290,7 +1290,7 @@ struct ArchReader {
12901290
lut->parent_mode = mode;
12911291

12921292
lut->blif_model = vtr::strdup(LogicalModels::MODEL_NAMES);
1293-
lut->model_id = get_model(arch_, LogicalModels::MODEL_NAMES);
1293+
lut->model_id = LogicalModels::MODEL_NAMES_ID;
12941294

12951295
lut->num_ports = 2;
12961296
lut->ports = (t_port*)vtr::calloc(lut->num_ports, sizeof(t_port));
@@ -1397,7 +1397,7 @@ struct ArchReader {
13971397
opad->num_ports = num_ports;
13981398
opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
13991399
opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT);
1400-
opad->model_id = get_model(arch_, LogicalModels::MODEL_OUTPUT);
1400+
opad->model_id = LogicalModels::MODEL_OUTPUT_ID;
14011401

14021402
opad->ports[0] = get_generic_port(arch_, opad, IN_PORT, "outpad", LogicalModels::MODEL_OUTPUT);
14031403
omode->pb_type_children[0] = *opad;
@@ -1419,7 +1419,7 @@ struct ArchReader {
14191419
ipad->num_ports = num_ports;
14201420
ipad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
14211421
ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT);
1422-
ipad->model_id = get_model(arch_, LogicalModels::MODEL_INPUT);
1422+
ipad->model_id = LogicalModels::MODEL_INPUT_ID;
14231423

14241424
ipad->ports[0] = get_generic_port(arch_, ipad, OUT_PORT, "inpad", LogicalModels::MODEL_INPUT);
14251425
imode->pb_type_children[0] = *ipad;

‎vpr/src/base/atom_netlist.cpp

Lines changed: 3 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -14,33 +14,20 @@
1414
*
1515
*/
1616
AtomNetlist::AtomNetlist(std::string name, std::string id)
17-
: Netlist<AtomBlockId, AtomPortId, AtomPinId, AtomNetId>(name, id)
18-
, inpad_model_(LogicalModelId::INVALID())
19-
, outpad_model_(LogicalModelId::INVALID()) {}
17+
: Netlist<AtomBlockId, AtomPortId, AtomPinId, AtomNetId>(name, id) {}
2018

2119
/*
2220
*
2321
* Blocks
2422
*
2523
*/
26-
void AtomNetlist::set_block_types(LogicalModelId inpad, LogicalModelId outpad) {
27-
VTR_ASSERT(inpad.is_valid());
28-
VTR_ASSERT(outpad.is_valid());
29-
30-
inpad_model_ = inpad;
31-
outpad_model_ = outpad;
32-
}
33-
3424
AtomBlockType AtomNetlist::block_type(const AtomBlockId id) const {
35-
VTR_ASSERT(inpad_model_.is_valid());
36-
VTR_ASSERT(outpad_model_.is_valid());
37-
3825
LogicalModelId blk_model = block_model(id);
3926

4027
AtomBlockType type = AtomBlockType::BLOCK;
41-
if (blk_model == inpad_model_) {
28+
if (blk_model == LogicalModels::MODEL_INPUT_ID) {
4229
type = AtomBlockType::INPAD;
43-
} else if (blk_model == outpad_model_) {
30+
} else if (blk_model == LogicalModels::MODEL_OUTPUT_ID) {
4431
type = AtomBlockType::OUTPAD;
4532
} else {
4633
type = AtomBlockType::BLOCK;

‎vpr/src/base/atom_netlist.h

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -93,11 +93,6 @@ class AtomNetlist : public Netlist<AtomBlockId, AtomPortId, AtomPinId, AtomNetId
9393
typedef std::vector<std::vector<vtr::LogicValue>> TruthTable;
9494

9595
public: //Public Accessors
96-
/*
97-
* Blocks
98-
*/
99-
void set_block_types(LogicalModelId inpad, LogicalModelId outpad);
100-
10196
///@brief Returns the type of the specified block
10297
AtomBlockType block_type(const AtomBlockId id) const;
10398

@@ -264,14 +259,6 @@ class AtomNetlist : public Netlist<AtomBlockId, AtomPortId, AtomPinId, AtomNetId
264259
vtr::vector_map<AtomBlockId, LogicalModelId> block_models_; //Architecture model of each block
265260
vtr::vector_map<AtomBlockId, TruthTable> block_truth_tables_; //Truth tables of each block
266261

267-
// Input IOs and output IOs always exist and have their own architecture
268-
// models. While their models are already included in block_models_, we
269-
// also store direct pointers to them to make checks of whether a block is
270-
// an INPAD or OUTPAD fast, as such checks are common in some netlist
271-
// operations (e.g. clean-up of an input netlist).
272-
LogicalModelId inpad_model_;
273-
LogicalModelId outpad_model_;
274-
275262
//Port data
276263
vtr::vector_map<AtomPortId, const t_model_ports*> port_models_; //Architecture port models of each port
277264

‎vpr/src/base/atom_netlist_utils.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ std::vector<AtomPortId> find_combinationally_connected_input_ports(const AtomNet
3434
///@brief Returns the set of clock ports which are combinationally connected to output_port
3535
std::vector<AtomPortId> find_combinationally_connected_clock_ports(const AtomNetlist& netlist, AtomPortId output_port);
3636

37-
bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models);
37+
bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk);
3838
bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models, std::string* reason = nullptr);
3939
bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models, std::string* reason = nullptr);
4040
bool is_removable_output(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr);
@@ -137,7 +137,7 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalMod
137137
}
138138

139139
//Latch
140-
LogicalModelId latch_model = models.get_model_by_name(LogicalModels::MODEL_LATCH);
140+
LogicalModelId latch_model = LogicalModels::MODEL_LATCH_ID;
141141
for (auto blk_id : netlist.blocks()) {
142142
if (netlist.block_type(blk_id) == AtomBlockType::BLOCK) {
143143
LogicalModelId blk_model = netlist.block_model(blk_id);
@@ -225,7 +225,7 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalMod
225225
}
226226

227227
//Names
228-
LogicalModelId names_model = models.get_model_by_name(LogicalModels::MODEL_NAMES);
228+
LogicalModelId names_model = LogicalModels::MODEL_NAMES_ID;
229229
for (auto blk_id : netlist.blocks()) {
230230
if (netlist.block_type(blk_id) == AtomBlockType::BLOCK) {
231231
LogicalModelId blk_model = netlist.block_model(blk_id);
@@ -292,8 +292,8 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalMod
292292
}
293293

294294
//Subckt
295-
LogicalModelId input_model = models.get_model_by_name(LogicalModels::MODEL_INPUT);
296-
LogicalModelId output_model = models.get_model_by_name(LogicalModels::MODEL_OUTPUT);
295+
LogicalModelId input_model = LogicalModels::MODEL_INPUT_ID;
296+
LogicalModelId output_model = LogicalModels::MODEL_OUTPUT_ID;
297297
std::set<LogicalModelId> subckt_models;
298298
for (auto blk_id : netlist.blocks()) {
299299
LogicalModelId blk_model = netlist.block_model(blk_id);
@@ -690,7 +690,7 @@ void absorb_buffer_luts(AtomNetlist& netlist, const LogicalModels& models, int v
690690

691691
//Remove the buffer luts
692692
for (auto blk : netlist.blocks()) {
693-
if (is_buffer_lut(netlist, blk, models)) {
693+
if (is_buffer_lut(netlist, blk)) {
694694
if (remove_buffer_lut(netlist, blk, models, verbosity)) {
695695
++removed_buffer_count;
696696
}
@@ -701,9 +701,9 @@ void absorb_buffer_luts(AtomNetlist& netlist, const LogicalModels& models, int v
701701
//TODO: absorb inverter LUTs?
702702
}
703703

704-
bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models) {
704+
bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk) {
705705
if (netlist.block_type(blk) == AtomBlockType::BLOCK) {
706-
const LogicalModelId names_model = models.get_model_by_name(LogicalModels::MODEL_NAMES);
706+
const LogicalModelId names_model = LogicalModels::MODEL_NAMES_ID;
707707
if (netlist.block_model(blk) != names_model) return false;
708708

709709
auto input_ports = netlist.block_input_ports(blk);
@@ -1412,7 +1412,7 @@ std::set<AtomPinId> find_netlist_logical_clock_drivers(const AtomNetlist& netlis
14121412
//to find the true source
14131413
size_t assumed_buffer_count = 0;
14141414
std::set<AtomNetId> prev_clock_nets;
1415-
LogicalModelId names_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES);
1415+
LogicalModelId names_model_id = LogicalModels::MODEL_NAMES_ID;
14161416
while (prev_clock_nets != clock_nets) { //Still tracing back
14171417
prev_clock_nets = clock_nets;
14181418
clock_nets.clear();

‎vpr/src/base/check_netlist.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -128,7 +128,6 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi
128128
static int check_clb_conn(ClusterBlockId iblk, int num_conn) {
129129
auto& cluster_ctx = g_vpr_ctx.clustering();
130130
auto& clb_nlist = cluster_ctx.clb_nlist;
131-
const LogicalModels& models = g_vpr_ctx.device().arch->models;
132131

133132
int error = 0;
134133
t_logical_block_type_ptr type = clb_nlist.block_type(iblk);
@@ -137,15 +136,15 @@ static int check_clb_conn(ClusterBlockId iblk, int num_conn) {
137136
for (auto pin_id : clb_nlist.block_pins(iblk)) {
138137
auto pin_type = clb_nlist.pin_type(pin_id);
139138

140-
if (pin_type == PinType::SINK && !clb_nlist.block_contains_primary_output(iblk, models)) {
139+
if (pin_type == PinType::SINK && !clb_nlist.block_contains_primary_output(iblk)) {
141140
//Input only and not a Primary-Output block
142141
VTR_LOG_WARN(
143142
"Logic block #%d (%s) has only 1 input pin '%s'"
144143
" -- the whole block is hanging logic that should be swept.\n",
145144
iblk, clb_nlist.block_name(iblk).c_str(),
146145
clb_nlist.pin_name(pin_id).c_str());
147146
}
148-
if (pin_type == PinType::DRIVER && !clb_nlist.block_contains_primary_input(iblk, models)) {
147+
if (pin_type == PinType::DRIVER && !clb_nlist.block_contains_primary_input(iblk)) {
149148
//Output only and not a Primary-Input block
150149
VTR_LOG_WARN(
151150
"Logic block #%d (%s) has only 1 output pin '%s'."

‎vpr/src/base/clustered_netlist.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -60,17 +60,17 @@ ClusterPinId ClusteredNetlist::block_pin(const ClusterBlockId blk, const int log
6060
return block_logical_pins_[blk][logical_pin_index];
6161
}
6262

63-
bool ClusteredNetlist::block_contains_primary_input(const ClusterBlockId blk, const LogicalModels& models) const {
63+
bool ClusteredNetlist::block_contains_primary_input(const ClusterBlockId blk) const {
6464
const t_pb* pb = block_pb(blk);
65-
LogicalModelId input_model_id = models.get_model_by_name(LogicalModels::MODEL_INPUT);
65+
LogicalModelId input_model_id = LogicalModels::MODEL_INPUT_ID;
6666
const t_pb* primary_input_pb = pb->find_pb_for_model(input_model_id);
6767
return primary_input_pb != nullptr;
6868
}
6969

7070
///@brief Returns true if the specified block contains a primary output (e.g. BLIF .output primitive)
71-
bool ClusteredNetlist::block_contains_primary_output(const ClusterBlockId blk, const LogicalModels& models) const {
71+
bool ClusteredNetlist::block_contains_primary_output(const ClusterBlockId blk) const {
7272
const t_pb* pb = block_pb(blk);
73-
LogicalModelId output_model_id = models.get_model_by_name(LogicalModels::MODEL_OUTPUT);
73+
LogicalModelId output_model_id = LogicalModels::MODEL_OUTPUT_ID;
7474
const t_pb* primary_output_pb = pb->find_pb_for_model(output_model_id);
7575
return primary_output_pb != nullptr;
7676
}

‎vpr/src/base/clustered_netlist.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -140,10 +140,10 @@ class ClusteredNetlist : public Netlist<ClusterBlockId, ClusterPortId, ClusterPi
140140
ClusterPinId block_pin(const ClusterBlockId blk, const int logical_pin_index) const;
141141

142142
////@brief Returns true if the specified block contains a primary input (e.g. BLIF .input primitive)
143-
bool block_contains_primary_input(const ClusterBlockId blk, const LogicalModels& models) const;
143+
bool block_contains_primary_input(const ClusterBlockId blk) const;
144144

145145
///@brief Returns true if the specified block contains a primary output (e.g. BLIF .output primitive)
146-
bool block_contains_primary_output(const ClusterBlockId blk, const LogicalModels& models) const;
146+
bool block_contains_primary_output(const ClusterBlockId blk) const;
147147

148148
/*
149149
* Pins

‎vpr/src/base/read_blif.cpp

Lines changed: 4 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -45,10 +45,6 @@ struct BlifAllocCallback : public blifparse::Callback {
4545
, blif_format_(blif_format) {
4646
VTR_ASSERT(blif_format_ == e_circuit_format::BLIF
4747
|| blif_format_ == e_circuit_format::EBLIF);
48-
inpad_model_ = models.get_model_by_name(LogicalModels::MODEL_INPUT);
49-
outpad_model_ = models.get_model_by_name(LogicalModels::MODEL_OUTPUT);
50-
51-
main_netlist_.set_block_types(inpad_model_, outpad_model_);
5248
}
5349

5450
static constexpr const char* OUTPAD_NAME_PREFIX = "out:";
@@ -68,14 +64,13 @@ struct BlifAllocCallback : public blifparse::Callback {
6864
//Create a new model, and set it's name
6965

7066
blif_models_.emplace_back(model_name, netlist_id_);
71-
blif_models_.back().set_block_types(inpad_model_, outpad_model_);
7267
blif_models_black_box_.emplace_back(false);
7368
ended_ = false;
7469
set_curr_block(AtomBlockId::INVALID()); //This statement doesn't define a block, so mark invalid
7570
}
7671

7772
void inputs(std::vector<std::string> input_names) override {
78-
LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_INPUT);
73+
LogicalModelId blk_model_id = LogicalModels::MODEL_INPUT_ID;
7974
const t_model& blk_model = models_.get_model(blk_model_id);
8075

8176
VTR_ASSERT_MSG(!blk_model.inputs, "Inpad model has an input port");
@@ -94,7 +89,7 @@ struct BlifAllocCallback : public blifparse::Callback {
9489
}
9590

9691
void outputs(std::vector<std::string> output_names) override {
97-
LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_OUTPUT);
92+
LogicalModelId blk_model_id = LogicalModels::MODEL_OUTPUT_ID;
9893
const t_model& blk_model = models_.get_model(blk_model_id);
9994

10095
VTR_ASSERT_MSG(!blk_model.outputs, "Outpad model has an output port");
@@ -115,7 +110,7 @@ struct BlifAllocCallback : public blifparse::Callback {
115110
}
116111

117112
void names(std::vector<std::string> nets, std::vector<std::vector<blifparse::LogicValue>> so_cover) override {
118-
LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_NAMES);
113+
LogicalModelId blk_model_id = LogicalModels::MODEL_NAMES_ID;
119114
const t_model& blk_model = models_.get_model(blk_model_id);
120115

121116
VTR_ASSERT_MSG(nets.size() > 0, "BLIF .names has no connections");
@@ -199,7 +194,7 @@ struct BlifAllocCallback : public blifparse::Callback {
199194
vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Latch must have a clock\n");
200195
}
201196

202-
LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_LATCH);
197+
LogicalModelId blk_model_id = LogicalModels::MODEL_LATCH_ID;
203198
const t_model& blk_model = models_.get_model(blk_model_id);
204199

205200
VTR_ASSERT_MSG(blk_model.inputs, "Has one input port");
@@ -617,8 +612,6 @@ struct BlifAllocCallback : public blifparse::Callback {
617612
AtomNetlist& main_netlist_; ///<User object we fill
618613
const std::string netlist_id_; ///<Unique identifier based on the contents of the blif file
619614
const LogicalModels& models_;
620-
LogicalModelId inpad_model_;
621-
LogicalModelId outpad_model_;
622615

623616
size_t unique_subckt_name_counter_ = 0;
624617

‎vpr/src/base/read_circuit.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ static void show_circuit_stats(const AtomNetlist& netlist, const LogicalModels&
149149
// Count the block statistics
150150
std::map<std::string, size_t> block_type_counts;
151151
std::map<std::string, size_t> lut_size_counts;
152-
LogicalModelId names_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES);
152+
LogicalModelId names_model_id = LogicalModels::MODEL_NAMES_ID;
153153
for (auto blk_id : netlist.blocks()) {
154154
// For each model, count the number of occurrences in the netlist.
155155
LogicalModelId blk_model_id = netlist.block_model(blk_id);

‎vpr/src/base/read_interchange_netlist.cpp

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -54,10 +54,6 @@ struct NetlistReader {
5454
auto str_list = nr_.getStrList();
5555
main_netlist_ = AtomNetlist(str_list[top_cell_instance_.getName()], netlist_id);
5656

57-
inpad_model_ = models_.get_model_by_name(LogicalModels::MODEL_INPUT);
58-
outpad_model_ = models_.get_model_by_name(LogicalModels::MODEL_OUTPUT);
59-
main_netlist_.set_block_types(inpad_model_, outpad_model_);
60-
6157
prepare_port_net_maps();
6258

6359
VTR_LOG("Reading IOs...\n");
@@ -75,8 +71,6 @@ struct NetlistReader {
7571

7672
const char* netlist_file_;
7773

78-
LogicalModelId inpad_model_;
79-
LogicalModelId outpad_model_;
8074
const LogicalModels& models_;
8175
const t_arch& arch_;
8276

@@ -137,9 +131,9 @@ struct NetlistReader {
137131
}
138132

139133
void read_ios() {
140-
LogicalModelId input_model_id = models_.get_model_by_name(LogicalModels::MODEL_INPUT);
134+
LogicalModelId input_model_id = LogicalModels::MODEL_INPUT_ID;
141135
const t_model& input_model = models_.get_model(input_model_id);
142-
LogicalModelId output_model_id = models_.get_model_by_name(LogicalModels::MODEL_OUTPUT);
136+
LogicalModelId output_model_id = LogicalModels::MODEL_OUTPUT_ID;
143137
const t_model& output_model = models_.get_model(output_model_id);
144138

145139
auto str_list = nr_.getStrList();
@@ -187,7 +181,7 @@ struct NetlistReader {
187181
}
188182

189183
void read_names() {
190-
LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_NAMES);
184+
LogicalModelId blk_model_id = LogicalModels::MODEL_NAMES_ID;
191185
const t_model& blk_model = models_.get_model(blk_model_id);
192186

193187
// Set the max size of the LUT

‎vpr/src/pack/cluster_util.cpp

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -273,11 +273,8 @@ void print_pb_type_count(const ClusteredNetlist& clb_nlist) {
273273
VTR_LOG("\n");
274274
}
275275

276-
t_logical_block_type_ptr identify_logic_block_type(const vtr::vector<LogicalModelId, std::vector<t_logical_block_type_ptr>>& primitive_candidate_block_types,
277-
const LogicalModels& models) {
278-
LogicalModelId lut_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES);
279-
280-
VTR_ASSERT(lut_model_id.is_valid());
276+
t_logical_block_type_ptr identify_logic_block_type(const vtr::vector<LogicalModelId, std::vector<t_logical_block_type_ptr>>& primitive_candidate_block_types) {
277+
LogicalModelId lut_model_id = LogicalModels::MODEL_NAMES_ID;
281278
if (primitive_candidate_block_types[lut_model_id].size() == 0)
282279
return nullptr;
283280

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