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Commit f5ef6c4

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Run make format
Signed-off-by: Alessandro Comodi <[email protected]>
1 parent 67419ff commit f5ef6c4

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2 files changed

+3
-5
lines changed

2 files changed

+3
-5
lines changed

libs/libarchfpga/src/arch_util.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -345,7 +345,6 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
345345
delete[] pb_graph_node->clock_pins[i];
346346
}
347347

348-
349348
vtr::free(pb_graph_node->input_pins);
350349
vtr::free(pb_graph_node->output_pins);
351350
vtr::free(pb_graph_node->clock_pins);
@@ -362,14 +361,14 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
362361
if (pb_graph_node->interconnect_pins[i] == nullptr) continue;
363362

364363
t_mode* mode = &pb_graph_node->pb_type->modes[i];
365-
364+
366365
for (j = 0; j < mode->num_interconnect; ++j) {
367366
//The interconnect_pins data structures are only initialized for power analysis and
368367
//are bizarrely baroque...
369368
t_interconnect* interconn = pb_graph_node->interconnect_pins[i][j].interconnect;
370369
VTR_ASSERT(interconn == &mode->interconnect[j]);
371370

372-
t_interconnect_power* interconn_power = interconn->interconnect_power;
371+
t_interconnect_power* interconn_power = interconn->interconnect_power;
373372
for (int iport = 0; iport < interconn_power->num_input_ports; ++iport) {
374373
vtr::free(pb_graph_node->interconnect_pins[i][j].input_pins[iport]);
375374
}
@@ -385,7 +384,6 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
385384
vtr::free(pb_graph_node->interconnect_pins);
386385
vtr::free(pb_graph_node->pb_node_power);
387386

388-
389387
for (i = 0; i < pb_type->num_modes; i++) {
390388
for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) {
391389
for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) {

vpr/src/power/PowerSpicedComponent.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ PowerCallibInputs::PowerCallibInputs(PowerSpicedComponent* parent_,
2020
: parent(parent_)
2121
, num_inputs(inputs)
2222
, sorted(false)
23-
, done_callibration( false) {
23+
, done_callibration(false) {
2424
/* Add min/max bounding entries */
2525
add_size(0);
2626
add_size(std::numeric_limits<float>::max());

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