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Merge pull request #3129 from verilog-to-routing/subtile_pin_loc
Subtile Pin Location
2 parents f81a1bf + fb431b4 commit f44c58a

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-666
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16 files changed

+884
-666
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‎doc/src/arch/reference.rst

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1167,6 +1167,24 @@ The following tags are common to all ``<tile>`` tags:
11671167
11681168
**Default:** ``0``
11691169
1170+
If the subtile capacity is greater than 1, you can specify the capacity range when defining the pin locations. For example:
1171+
1172+
.. code-block:: xml
1173+
1174+
<sub_tile name="io_bottom" capacity="6">
1175+
<equivalent_sites>
1176+
<site pb_type="io"/>
1177+
</equivalent_sites>
1178+
<input name="outpad" num_pins="1"/>
1179+
<output name="inpad" num_pins="1"/>
1180+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
1181+
<pinlocations pattern="custom">
1182+
<loc side="top">io_bottom[0:1].outpad io_bottom[0:3].inpad io_bottom[2:5].outpad io_bottom[4:5].inpad</loc>
1183+
</pinlocations>
1184+
</sub_tile>
1185+
1186+
If no capacity range is specified, it is assumed that the location applies to all capacity instances.
1187+
11701188
Physical equivalence for a pin is specified by listing a pin more than once for different locations.
11711189
For example, a LUT whose output can exit from the top and bottom of a block will have its output pin specified twice: once for the top and once for the bottom.
11721190

‎libs/libarchfpga/src/main.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ int main(int argc, char** argv) {
4343
printf("Reading in architecture\n");
4444

4545
/* function declarations */
46-
XmlReadArch(argv[1], atoi(argv[2]), &arch, physical_tile_types, logical_block_types);
46+
xml_read_arch(argv[1], atoi(argv[2]), &arch, physical_tile_types, logical_block_types);
4747

4848
printf("Printing Results\n");
4949

‎libs/libarchfpga/src/physical_types.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,13 @@ class t_metadata_value {
9797
// Return string value.
9898
vtr::interned_string as_string() const { return value_; }
9999

100+
t_metadata_value& operator=(const t_metadata_value& o) noexcept {
101+
if (this != &o) {
102+
value_ = o.value_;
103+
}
104+
return *this;
105+
}
106+
100107
private:
101108
vtr::interned_string value_;
102109
};

‎libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 840 additions & 616 deletions
Large diffs are not rendered by default.

‎libs/libarchfpga/src/read_xml_arch_file.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,11 @@ extern "C" {
1212
#define EMPTY_TYPE_INDEX 0
1313

1414
/* function declarations */
15-
void XmlReadArch(const char* ArchFile,
16-
const bool timing_enabled,
17-
t_arch* arch,
18-
std::vector<t_physical_tile_type>& PhysicalTileTypes,
19-
std::vector<t_logical_block_type>& LogicalBlockTypes);
15+
void xml_read_arch(const char* ArchFile,
16+
const bool timing_enabled,
17+
t_arch* arch,
18+
std::vector<t_physical_tile_type>& PhysicalTileTypes,
19+
std::vector<t_logical_block_type>& LogicalBlockTypes);
2020

2121
#ifdef __cplusplus
2222
}

‎odin_ii/src/core/odin_ii.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -311,7 +311,7 @@ netlist_t* start_odin_ii(int argc, char** argv) {
311311

312312
printf("Reading FPGA Architecture file\n");
313313
try {
314-
XmlReadArch(global_args.arch_file.value().c_str(), false, &Arch, physical_tile_types, logical_block_types);
314+
xml_read_arch(global_args.arch_file.value().c_str(), false, &Arch, physical_tile_types, logical_block_types);
315315
set_physical_lut_size();
316316
} catch (vtr::VtrError& vtr_error) {
317317
printf("Odin Failed to load architecture file: %s with exit code%d\n", vtr_error.what(), ERROR_PARSE_ARCH);

‎parmys/parmys-plugin/parmys.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -962,7 +962,7 @@ struct ParMYSPass : public Pass {
962962

963963
log("Reading FPGA Architecture file\n");
964964
try {
965-
XmlReadArch(arch_file_path.c_str(), false, &Arch, physical_tile_types, logical_block_types);
965+
xml_read_arch(arch_file_path.c_str(), false, &Arch, physical_tile_types, logical_block_types);
966966
set_physical_lut_size(logical_block_types);
967967
} catch (vtr::VtrError &vtr_error) {
968968
log_error("Parmys Failed to load architecture file: %s with exit code%d at line: %ld\n", vtr_error.what(), ERROR_PARSE_ARCH,

‎parmys/parmys-plugin/parmys_arch.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,7 @@ struct ParmysArchPass : public Pass {
111111
std::vector<t_logical_block_type> logical_block_types;
112112

113113
try {
114-
XmlReadArch(arch_file_path.c_str(), false, &arch, physical_tile_types, logical_block_types);
114+
xml_read_arch(arch_file_path.c_str(), false, &arch, physical_tile_types, logical_block_types);
115115
} catch (vtr::VtrError &vtr_error) {
116116
log_error("Parmys Failed to load architecture file: %s with exit code %s at line: %ld\n", vtr_error.what(), "ERROR_PARSE_ARCH",
117117
vtr_error.line());

‎utils/vqm2blif/src/main.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,7 @@ int main(int argc, char* argv[])
326326
// required when decomposing INOUT pins into input and output pins
327327
cout << "\n>> Parsing architecture file " << arch_file << endl ;
328328
try {
329-
XmlReadArch( arch_file.c_str(), false, &arch, physical_tile_types, logical_block_types); //Architecture (XML) Parser call
329+
xml_read_arch( arch_file.c_str(), false, &arch, physical_tile_types, logical_block_types); //Architecture (XML) Parser call
330330
} catch (const vtr::VtrError& e) {
331331
cout << "Error at line " << e.line() << " in " << e.filename() << ": " << e.what() << endl;
332332
exit(1);

‎vpr/src/base/SetupVPR.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -159,11 +159,11 @@ void SetupVPR(const t_options* options,
159159
vtr::ScopedStartFinishTimer t("Loading Architecture Description");
160160
switch (options->arch_format) {
161161
case e_arch_format::VTR:
162-
XmlReadArch(options->ArchFile.value().c_str(),
163-
timingenabled,
164-
arch,
165-
device_ctx.physical_tile_types,
166-
device_ctx.logical_block_types);
162+
xml_read_arch(options->ArchFile.value().c_str(),
163+
timingenabled,
164+
arch,
165+
device_ctx.physical_tile_types,
166+
device_ctx.logical_block_types);
167167
break;
168168
case e_arch_format::FPGAInterchange:
169169
VTR_LOG("Use FPGA Interchange device\n");

‎vpr/src/base/read_netlist.cpp

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -250,23 +250,6 @@ ClusteredNetlist read_netlist(const char* net_file,
250250

251251
VTR_LOG("Finished loading packed FPGA netlist file (took %g seconds).\n", (float)(end - begin) / CLOCKS_PER_SEC);
252252

253-
size_t num_pb_route_used = 0;
254-
size_t num_pb_route_alloc = 0;
255-
size_t num_pb_pins = 0;
256-
for (auto clb : clb_nlist.blocks()) {
257-
t_pb* pb = clb_nlist.block_pb(clb);
258-
259-
for (int ipin = 0; ipin < pb->pb_graph_node->total_pb_pins; ++ipin) {
260-
if (pb->pb_route.count(ipin)) {
261-
++num_pb_route_alloc;
262-
if (pb->pb_route[ipin].atom_net_id) {
263-
++num_pb_route_used;
264-
}
265-
}
266-
++num_pb_pins;
267-
}
268-
}
269-
270253
return clb_nlist;
271254
}
272255

‎vpr/src/draw/draw_toggle_functions.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -18,11 +18,6 @@
1818
#include <X11/keysym.h>
1919
#endif
2020

21-
//The arrow head position for turning/straight-thru connections in a switch box
22-
constexpr float SB_EDGE_TURN_ARROW_POSITION = 0.2;
23-
constexpr float SB_EDGE_STRAIGHT_ARROW_POSITION = 0.95;
24-
constexpr float EMPTY_BLOCK_LIGHTEN_FACTOR = 0.20;
25-
2621
/**
2722
* @brief toggles net drawing status based on status of combo box
2823
* updates draw_state->show_nets

‎vpr/src/draw/ui_setup.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -268,18 +268,15 @@ void load_block_names(ezgl::application* app) {
268268
auto& cluster_ctx = g_vpr_ctx.clustering();
269269
auto& atom_ctx = g_vpr_ctx.atom();
270270
GtkTreeIter iter;
271-
int i = 0;
272271
for (ClusterBlockId id : cluster_ctx.clb_nlist.blocks()) {
273272
gtk_list_store_append(blockStorage, &iter);
274273
gtk_list_store_set(blockStorage, &iter,
275274
0, (cluster_ctx.clb_nlist.block_name(id)).c_str(), -1);
276-
i++;
277275
}
278276
for (AtomBlockId id : atom_ctx.netlist().blocks()) {
279277
gtk_list_store_append(blockStorage, &iter);
280278
gtk_list_store_set(blockStorage, &iter,
281279
0, (atom_ctx.netlist().block_name(id)).c_str(), -1);
282-
i++;
283280
}
284281
}
285282

@@ -293,12 +290,10 @@ void load_net_names(ezgl::application* app) {
293290
auto& atom_ctx = g_vpr_ctx.atom();
294291
GtkTreeIter iter;
295292
//Loading net names
296-
int i = 0;
297293
for (AtomNetId id : atom_ctx.netlist().nets()) {
298294
gtk_list_store_append(netStorage, &iter);
299295
gtk_list_store_set(netStorage, &iter,
300296
0, (atom_ctx.netlist().net_name(id)).c_str(), -1);
301-
i++;
302297
}
303298
}
304299

‎vpr/src/pack/pb_type_graph_annotations.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) {
118118
* Add the pattern name to the pack_pattern field for each pb_graph_edge that is used in a pack pattern
119119
*/
120120
static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const std::string& value) {
121-
int i, j, k, m, n, p, iedge;
121+
int i, j, m, n, iedge;
122122
t_pb_graph_pin ***in_port, ***out_port;
123123
int *num_in_ptrs, *num_out_ptrs, num_in_sets, num_out_sets;
124124
t_pb_graph_node** children = nullptr;
@@ -130,10 +130,8 @@ static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* p
130130
annot_out_pins, &num_out_ptrs, &num_out_sets, false, false);
131131

132132
/* Discover edge then annotate edge with name of pack pattern */
133-
k = 0;
134133
for (i = 0; i < num_in_sets; i++) {
135134
for (j = 0; j < num_in_ptrs[i]; j++) {
136-
p = 0;
137135
for (m = 0; m < num_out_sets; m++) {
138136
for (n = 0; n < num_out_ptrs[m]; n++) {
139137
for (iedge = 0; iedge < in_port[i][j]->num_output_edges; iedge++) {
@@ -148,10 +146,8 @@ static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* p
148146
in_port[i][j]->output_edges[iedge]->pack_pattern_names.resize(in_port[i][j]->output_edges[iedge]->num_pack_patterns);
149147
in_port[i][j]->output_edges[iedge]->pack_pattern_names[in_port[i][j]->output_edges[iedge]->num_pack_patterns - 1] = value.c_str(); // TODO: convert to std::string
150148
}
151-
p++;
152149
}
153150
}
154-
k++;
155151
}
156152
}
157153

‎vpr/src/place/noc_place_utils.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ class NocCostHandler {
3131
NocCostHandler(const NocCostHandler&) = delete;
3232
NocCostHandler& operator=(const NocCostHandler&) = delete;
3333
NocCostHandler(NocCostHandler&&) = default;
34-
NocCostHandler& operator=(NocCostHandler&&) = default;
34+
NocCostHandler& operator=(NocCostHandler&&) = delete;
3535

3636
/**
3737
* @brief Check if the internal reference to block_locs is pointing to the same

‎vpr/test/test_vpr.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,8 @@ TEST_CASE("read_arch_metadata", "[vpr]") {
2323
std::vector<t_physical_tile_type> physical_tile_types;
2424
std::vector<t_logical_block_type> logical_block_types;
2525

26-
XmlReadArch(kArchFile, /*timing_enabled=*/false,
27-
&arch, physical_tile_types, logical_block_types);
26+
xml_read_arch(kArchFile, /*timing_enabled=*/false,
27+
&arch, physical_tile_types, logical_block_types);
2828

2929
auto type_str = arch.strings.intern_string(vtr::string_view("type"));
3030
auto pb_type_type = arch.strings.intern_string(vtr::string_view("pb_type_type"));

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