[CI] Added System Verilog Regression Tests to GitHub Runners

The system verilog regression tests were put into the currently
not-working nightly tests. Since they are so small, putting them in the
GitHub runners tests instead so they do not regress.

The strong parmys test also has system verilog tests (I think); however,
that test may be too large for the GitHub runners. We may consider
moving that test to the SAVI workflows in the future.

Author: AlexandreSinger

.github/workflows/nightly_test.yml

@@ -65,9 +65,8 @@ jobs:
           - {test: "vtr_reg_strong",             cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                                         extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON",                          extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
-          - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DSYNLIG_SYSTEMVERILOG=ON",                                     extra_pkgs: ""} 
           - {test: "odin_reg_strong",            cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
-          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DSYNLIG_SYSTEMVERILOG=ON",                                     extra_pkgs: ""}
+          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DSYNLIG_SYSTEMVERILOG=ON",                                    extra_pkgs: ""}
 
     env:
       DEBIAN_FRONTEND: "noninteractive"

.github/workflows/test.yml

@@ -97,7 +97,7 @@ jobs:
       run: ./dev/${{ matrix.script }}
 
 
-  UniTests:
+  UnitTests:
     name: 'U: C++ Unit Tests'
     runs-on: ubuntu-24.04
     steps:
@@ -366,6 +366,40 @@ jobs:
           ./.github/scripts/build.sh
           ./run_reg_test.py parmys_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count }}
 
+  SystemVerilog:
+    name: 'System Verilog Regression'
+    runs-on: ubuntu-24.04
+    steps:
+
+    - uses: actions/setup-python@v5
+      with:
+        python-version: 3.12.3
+
+    # NOTE: This is using recursive on purpose. In order to use the System
+    #       Verilog feature, need submodules inside of a submodule.
+    - uses: actions/checkout@v4
+      with:
+        submodules: 'recursive'
+
+    - name: Get number of CPU cores
+      uses: SimenB/github-actions-cpu-cores@v2
+      id: cpu-cores
+
+    - name: Install dependencies
+      run: ./.github/scripts/install_dependencies.sh
+
+    - uses: hendrikmuhs/[email protected]
+
+    - name: Test
+      env:
+        CMAKE_PARAMS: '-DSYNLIG_SYSTEMVERILOG=ON'
+        NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
+      run: |
+        git submodule sync --recursive  # Sync submodules
+        git submodule update --init --recursive  # Ensure they are initialized & updated'
+        export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
+        ./.github/scripts/build.sh
+        ./run_reg_test.py vtr_reg_system_verilog -show_failures -j${{ steps.cpu-cores.outputs.count}}
 
   ODINII:
     name: 'ODIN-II Basic Test'
@@ -508,11 +542,12 @@ jobs:
     needs:
       - Build
       - Format
-      - UniTests
+      - UnitTests
       - Warnings
       - Regression
       - Sanitized
       - Parmys
+      - SystemVerilog
       - ODINII
       - VQM2BLIF
       - Compatibility