Odin: update regression results

Author: jeanlego

ODIN_II/regression_test/benchmark/task/large/synthesis_result.json

@@ -1208,5 +1208,55 @@
         "Average Path": 5,
         "Estimated LUTs": 2053,
         "Total Node": 1358
+    },
+    "large/single_ff/k6_frac_N10_frac_chain_mem32K_40nm": {
+        "test_name": "large/single_ff/k6_frac_N10_frac_chain_mem32K_40nm",
+        "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+        "verilog": "single_ff.v",
+        "exit": 0,
+        "errors": [],
+        "warnings": [],
+        "max_rss(MiB)": 5.6,
+        "exec_time(ms)": 6.1,
+        "synthesis_time(ms)": 0.1,
+        "Latch Drivers": 1,
+        "Pi": 1,
+        "Po": 1,
+        "logic element": 0,
+        "latch": 1,
+        "Adder": 0,
+        "Multiplier": 0,
+        "Memory": 0,
+        "Hard Ip": -1,
+        "generic logic size": 4,
+        "Longest Path": 3,
+        "Average Path": 3,
+        "Estimated LUTs": 0,
+        "Total Node": 2
+    },
+    "large/single_wire/k6_frac_N10_frac_chain_mem32K_40nm": {
+        "test_name": "large/single_wire/k6_frac_N10_frac_chain_mem32K_40nm",
+        "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+        "verilog": "single_wire.v",
+        "exit": 0,
+        "errors": [],
+        "warnings": [],
+        "max_rss(MiB)": 5.7,
+        "exec_time(ms)": 5.9,
+        "synthesis_time(ms)": 0.1,
+        "Latch Drivers": 0,
+        "Pi": 1,
+        "Po": 1,
+        "logic element": 0,
+        "latch": 0,
+        "Adder": 0,
+        "Multiplier": 0,
+        "Memory": 0,
+        "Hard Ip": -1,
+        "generic logic size": 4,
+        "Longest Path": 2,
+        "Average Path": 2,
+        "Estimated LUTs": 0,
+        "Total Node": 0
     }
 }