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Odin: update regression results
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ODIN_II/regression_test/benchmark/task/large/synthesis_result.json

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"Average Path": 5,
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"Estimated LUTs": 2053,
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"Total Node": 1358
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},
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"large/single_ff/k6_frac_N10_frac_chain_mem32K_40nm": {
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"test_name": "large/single_ff/k6_frac_N10_frac_chain_mem32K_40nm",
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"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
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"verilog": "single_ff.v",
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"exit": 0,
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"errors": [],
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"warnings": [],
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"max_rss(MiB)": 5.6,
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"exec_time(ms)": 6.1,
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"synthesis_time(ms)": 0.1,
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"Latch Drivers": 1,
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"Pi": 1,
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"Po": 1,
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"logic element": 0,
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"latch": 1,
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"Adder": 0,
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"Multiplier": 0,
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"Memory": 0,
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"Hard Ip": -1,
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"generic logic size": 4,
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"Longest Path": 3,
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"Average Path": 3,
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"Estimated LUTs": 0,
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"Total Node": 2
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},
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"large/single_wire/k6_frac_N10_frac_chain_mem32K_40nm": {
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"test_name": "large/single_wire/k6_frac_N10_frac_chain_mem32K_40nm",
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"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
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"verilog": "single_wire.v",
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"exit": 0,
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"errors": [],
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"warnings": [],
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"max_rss(MiB)": 5.7,
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"exec_time(ms)": 5.9,
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"synthesis_time(ms)": 0.1,
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"Latch Drivers": 0,
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"Pi": 1,
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"Po": 1,
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"logic element": 0,
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"latch": 0,
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"Adder": 0,
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"Multiplier": 0,
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"Memory": 0,
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"Hard Ip": -1,
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"generic logic size": 4,
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"Longest Path": 2,
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"Average Path": 2,
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"Estimated LUTs": 0,
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"Total Node": 0
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}
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}

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