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move PortPinToBlockPinConverter to vpr_utils
1 parent 4ccc910 commit f0a0a42

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4 files changed

+87
-82
lines changed

4 files changed

+87
-82
lines changed

vpr/src/place/place_macro.cpp

Lines changed: 18 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,8 @@ static void mark_direct_of_ports(int idirect,
3636
std::string_view src_string,
3737
int line,
3838
std::vector<std::vector<int>>& idirect_from_blk_pin,
39-
std::vector<std::vector<int>>& direct_type_from_blk_pin);
39+
std::vector<std::vector<int>>& direct_type_from_blk_pin,
40+
const PortPinToBlockPinConverter& port_pin_to_block_pin);
4041

4142
/* Mark the pin entry in idirect_from_blk_pin with idirect and the pin entry in *
4243
* direct_type_from_blk_pin with direct_type from start_pin_index to *
@@ -51,7 +52,8 @@ static void mark_direct_of_pins(int start_pin_index,
5152
std::vector<std::vector<int>>& direct_type_from_blk_pin,
5253
int direct_type,
5354
int line,
54-
std::string_view src_string);
55+
std::string_view src_string,
56+
const PortPinToBlockPinConverter& port_pin_to_block_pin);
5557

5658
const std::vector<t_pl_macro>& PlaceMacros::macros() const {
5759
return pl_macros_;
@@ -390,6 +392,8 @@ void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector<t_direc
390392
direct_type_from_blk_pin_[type.index].resize(type.num_pins, OPEN);
391393
}
392394

395+
const PortPinToBlockPinConverter port_pin_to_block_pin;
396+
393397
/* Load the values */
394398
// Go through directs and find pins with possible direct connections
395399
for (size_t idirect = 0; idirect < directs.size(); idirect++) {
@@ -410,13 +414,15 @@ void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector<t_direc
410414
mark_direct_of_ports(idirect, SOURCE, from_pb_type_name, from_port_name,
411415
from_end_pin_index, from_start_pin_index, directs[idirect].from_pin,
412416
directs[idirect].line,
413-
idirect_from_blk_pin_, direct_type_from_blk_pin_);
417+
idirect_from_blk_pin_, direct_type_from_blk_pin_,
418+
port_pin_to_block_pin);
414419

415420
// Then, find blocks with the same name as to_pb_type_name and from_port_name
416421
mark_direct_of_ports(idirect, SINK, to_pb_type_name, to_port_name,
417422
to_end_pin_index, to_start_pin_index, directs[idirect].to_pin,
418423
directs[idirect].line,
419-
idirect_from_blk_pin_, direct_type_from_blk_pin_);
424+
idirect_from_blk_pin_, direct_type_from_blk_pin_,
425+
port_pin_to_block_pin);
420426

421427
} // Finish going through all the directs
422428
}
@@ -430,7 +436,8 @@ static void mark_direct_of_ports(int idirect,
430436
std::string_view src_string,
431437
int line,
432438
std::vector<std::vector<int>>& idirect_from_blk_pin,
433-
std::vector<std::vector<int>>& direct_type_from_blk_pin) {
439+
std::vector<std::vector<int>>& direct_type_from_blk_pin,
440+
const PortPinToBlockPinConverter& port_pin_to_block_pin) {
434441
/* Go through all the ports in all the blocks to find the port that has the same *
435442
* name as port_name and belongs to the block type that has the name pb_type_name. *
436443
* Then, check that whether start_pin_index and end_pin_index are specified. If *
@@ -467,11 +474,13 @@ static void mark_direct_of_ports(int idirect,
467474
if (start_pin_index >= 0 || end_pin_index >= 0) {
468475
mark_direct_of_pins(start_pin_index, end_pin_index, itype,
469476
isub_tile, iport, idirect_from_blk_pin, idirect,
470-
direct_type_from_blk_pin, direct_type, line, src_string);
477+
direct_type_from_blk_pin, direct_type, line, src_string,
478+
port_pin_to_block_pin);
471479
} else {
472480
mark_direct_of_pins(0, num_port_pins - 1, itype,
473481
isub_tile, iport, idirect_from_blk_pin, idirect,
474-
direct_type_from_blk_pin, direct_type, line, src_string);
482+
direct_type_from_blk_pin, direct_type, line, src_string,
483+
port_pin_to_block_pin);
475484
}
476485
} // Do nothing if port_name does not match
477486
} // Finish going through all the ports
@@ -490,14 +499,13 @@ static void mark_direct_of_pins(int start_pin_index,
490499
std::vector<std::vector<int>>& direct_type_from_blk_pin,
491500
int direct_type,
492501
int line,
493-
std::string_view src_string) {
502+
std::string_view src_string,
503+
const PortPinToBlockPinConverter& port_pin_to_block_pin) {
494504
/* Mark the pin entry in idirect_from_blk_pin with idirect and the pin entry in *
495505
* direct_type_from_blk_pin with direct_type from start_pin_index to *
496506
* end_pin_index. */
497507
auto& device_ctx = g_vpr_ctx.device();
498508

499-
PortPinToBlockPinConverter port_pin_to_block_pin;
500-
501509
// Mark pins with indices from start_pin_index to end_pin_index, inclusive
502510
for (int iport_pin = start_pin_index; iport_pin <= end_pin_index; iport_pin++) {
503511
int iblk_pin = port_pin_to_block_pin.get_blk_pin_from_port_pin(itype, isub_tile, iport, iport_pin);
@@ -663,35 +671,3 @@ static void validate_macros(const std::vector<t_pl_macro>& macros) {
663671
}
664672
}
665673

666-
PortPinToBlockPinConverter::PortPinToBlockPinConverter() {
667-
auto& device_ctx = g_vpr_ctx.device();
668-
auto& types = device_ctx.physical_tile_types;
669-
670-
// Resize and initialize the values to OPEN (-1).
671-
size_t num_types = types.size();
672-
blk_pin_from_port_pin_.resize(num_types);
673-
674-
for (size_t itype = 1; itype < num_types; itype++) {
675-
int blk_pin_count = 0;
676-
auto& type = types[itype];
677-
size_t num_sub_tiles = type.sub_tiles.size();
678-
blk_pin_from_port_pin_[itype].resize(num_sub_tiles);
679-
for (size_t isub_tile = 0; isub_tile < num_sub_tiles; isub_tile++) {
680-
size_t num_ports = type.sub_tiles[isub_tile].ports.size();
681-
blk_pin_from_port_pin_[itype][isub_tile].resize(num_ports);
682-
for (size_t iport = 0; iport < num_ports; iport++) {
683-
int num_pins = type.sub_tiles[isub_tile].ports[iport].num_pins;
684-
for (int ipin = 0; ipin < num_pins; ipin++) {
685-
blk_pin_from_port_pin_[itype][isub_tile][iport].push_back(blk_pin_count);
686-
blk_pin_count++;
687-
}
688-
}
689-
}
690-
}
691-
}
692-
693-
int PortPinToBlockPinConverter::get_blk_pin_from_port_pin(int blk_type_index, int sub_tile, int port, int port_pin) {
694-
// Return the port and port_pin for the pin.
695-
int blk_pin = blk_pin_from_port_pin_[blk_type_index][sub_tile][port][port_pin];
696-
return blk_pin;
697-
}

vpr/src/place/place_macro.h

Lines changed: 0 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -251,41 +251,4 @@ class PlaceMacros {
251251
void alloc_and_load_idirect_from_blk_pin_(const std::vector<t_direct_inf>& directs);
252252
};
253253

254-
255-
/**
256-
* @class PortPinToBlockPinConverter
257-
* @brief Maps the block pins indices for all block types to the corresponding port indices and port_pin indices.
258-
*
259-
* @details This is necessary since there are different netlist conventions - in the cluster level,
260-
* ports and port pins are used while in the post-pack level, block pins are used.
261-
*/
262-
class PortPinToBlockPinConverter {
263-
public:
264-
/**
265-
* @brief Allocates and loads blk_pin_from_port_pin_ array.
266-
*/
267-
PortPinToBlockPinConverter();
268-
269-
/**
270-
* @brief Converts port and port pin indices of a specific block type to block pin index.
271-
*
272-
* @details The reason block type is used instead of blocks is to save memory.
273-
*
274-
* @param blk_type_index The block type index.
275-
* @param sub_tile The subtile index within the specified block type.
276-
* @param port The port number whose block pin number is desired.
277-
* @param port_pin The port pin number in the specified port whose block pin number is desired.
278-
* @return int The block pin index corresponding to the given port and port pin numbers.
279-
*/
280-
int get_blk_pin_from_port_pin(int blk_type_index, int sub_tile, int port, int port_pin);
281-
282-
private:
283-
/**
284-
* @brief This array allows us to quickly find what block pin a port pin corresponds to.
285-
* @details A 4D array that should be indexed as following:
286-
* [0...device_ctx.physical_tile_types.size()-1][0..num_sub_tiles][0...num_ports-1][0...num_port_pins-1]
287-
*/
288-
std::vector<std::vector<std::vector<std::vector<int>>>> blk_pin_from_port_pin_;
289-
};
290-
291254
#endif

vpr/src/util/vpr_utils.cpp

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2171,3 +2171,36 @@ float get_min_cross_layer_delay() {
21712171

21722172
return min_delay;
21732173
}
2174+
2175+
PortPinToBlockPinConverter::PortPinToBlockPinConverter() {
2176+
const auto& device_ctx = g_vpr_ctx.device();
2177+
const auto& types = device_ctx.physical_tile_types;
2178+
2179+
// Resize and initialize the values to OPEN (-1).
2180+
size_t num_types = types.size();
2181+
blk_pin_from_port_pin_.resize(num_types);
2182+
2183+
for (size_t itype = 1; itype < num_types; itype++) {
2184+
int blk_pin_count = 0;
2185+
auto& type = types[itype];
2186+
size_t num_sub_tiles = type.sub_tiles.size();
2187+
blk_pin_from_port_pin_[itype].resize(num_sub_tiles);
2188+
for (size_t isub_tile = 0; isub_tile < num_sub_tiles; isub_tile++) {
2189+
size_t num_ports = type.sub_tiles[isub_tile].ports.size();
2190+
blk_pin_from_port_pin_[itype][isub_tile].resize(num_ports);
2191+
for (size_t iport = 0; iport < num_ports; iport++) {
2192+
int num_pins = type.sub_tiles[isub_tile].ports[iport].num_pins;
2193+
for (int ipin = 0; ipin < num_pins; ipin++) {
2194+
blk_pin_from_port_pin_[itype][isub_tile][iport].push_back(blk_pin_count);
2195+
blk_pin_count++;
2196+
}
2197+
}
2198+
}
2199+
}
2200+
}
2201+
2202+
int PortPinToBlockPinConverter::get_blk_pin_from_port_pin(int blk_type_index, int sub_tile, int port, int port_pin) const {
2203+
// Return the port and port_pin for the pin.
2204+
int blk_pin = blk_pin_from_port_pin_[blk_type_index][sub_tile][port][port_pin];
2205+
return blk_pin;
2206+
}

vpr/src/util/vpr_utils.h

Lines changed: 36 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -312,11 +312,44 @@ void apply_route_constraints(const UserRouteConstraints& constraint);
312312
/**
313313
* @brief Iterate over all inter-layer switch types and return the minimum delay of it.
314314
* useful four router lookahead to to have some estimate of the cost of crossing a layer
315-
* @param arch_switch_inf
316-
* @param segment_inf
317-
* @param wire_to_ipin_arch_sw_id
318315
* @return
319316
*/
320317
float get_min_cross_layer_delay();
321318

319+
/**
320+
* @class PortPinToBlockPinConverter
321+
* @brief Maps the block pins indices for all block types to the corresponding port indices and port_pin indices.
322+
*
323+
* @details This is necessary since there are different netlist conventions - in the cluster level,
324+
* ports and port pins are used while in the post-pack level, block pins are used.
325+
*/
326+
class PortPinToBlockPinConverter {
327+
public:
328+
/**
329+
* @brief Allocates and loads blk_pin_from_port_pin_ array.
330+
*/
331+
PortPinToBlockPinConverter();
332+
333+
/**
334+
* @brief Converts port and port pin indices of a specific block type to block pin index.
335+
*
336+
* @details The reason block type is used instead of blocks is to save memory.
337+
*
338+
* @param blk_type_index The block type index.
339+
* @param sub_tile The subtile index within the specified block type.
340+
* @param port The port number whose block pin number is desired.
341+
* @param port_pin The port pin number in the specified port whose block pin number is desired.
342+
* @return int The block pin index corresponding to the given port and port pin numbers.
343+
*/
344+
int get_blk_pin_from_port_pin(int blk_type_index, int sub_tile, int port, int port_pin) const;
345+
346+
private:
347+
/**
348+
* @brief This array allows us to quickly find what block pin a port pin corresponds to.
349+
* @details A 4D array that should be indexed as following:
350+
* [0...device_ctx.physical_tile_types.size()-1][0..num_sub_tiles][0...num_ports-1][0...num_port_pins-1]
351+
*/
352+
std::vector<std::vector<std::vector<std::vector<int>>>> blk_pin_from_port_pin_;
353+
};
354+
322355
#endif

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