place: added placement priority and check direct pin mappings

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

libs/libarchfpga/src/physical_types.h

@@ -609,6 +609,9 @@ struct t_physical_tile_type {
 
     std::vector<std::string> equivalent_sites_names;
     std::vector<t_logical_block_type_ptr> equivalent_sites;
+    
+    /* Unordered map indexed by the logical block index. 
+     * tile_block_pin_directs_map[logical block index][logical block pin] -> physical tile pin */
     std::unordered_map<int, std::unordered_map<int, int>> tile_block_pin_directs_map;
 
     /* Returns the indices of pins that contain a clock for this physical logic block */
@@ -666,6 +669,7 @@ struct t_logical_block_type {
     int index = -1; /* index of type descriptor in array (allows for index referencing) */
 
     std::vector<t_physical_tile_type_ptr> equivalent_tiles;
+    std::map<int, std::vector<t_physical_tile_type_ptr>> placement_priority;
 };
 
 /*************************************************************************************************

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -220,13 +220,16 @@ e_side string_to_side(std::string side_str);
 static void link_physical_logical_types(std::vector<t_physical_tile_type>& PhysicalTileTypes,
                                         std::vector<t_logical_block_type>& LogicalBlockTypes);
 
-static void check_port_equivalence(t_physical_tile_type& physical_tile, t_logical_block_type& logical_block);
+static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block);
 
 static const t_physical_tile_port* get_port_by_name(t_physical_tile_type_ptr type, const char* port_name);
 static const t_port* get_port_by_name(t_logical_block_type_ptr type, const char* port_name);
 
+static const t_physical_tile_port* get_port_by_pin(t_physical_tile_type_ptr type, int pin);
+static const t_port* get_port_by_pin(t_logical_block_type_ptr type, int pin);
+
 template<typename T>
-static T get_type_by_name(const char* type_name, std::vector<T>& types);
+static T* get_type_by_name(const char* type_name, std::vector<T>& types);
 
 /*
  *
@@ -3221,7 +3224,10 @@ static void ProcessTileEquivalentSites(pugi::xml_node Parent,
 
         auto LogicalBlockType = get_type_by_name<t_logical_block_type>(Prop.c_str(), LogicalBlockTypes);
 
-        ProcessEquivalentSiteDirects(CurSite, PhysicalTileType, &LogicalBlockType, Prop, loc_data);
+        auto priority = get_attribute(CurSite, "priority", loc_data, ReqOpt::OPTIONAL).as_int(0);
+        LogicalBlockType->placement_priority[priority].push_back(PhysicalTileType);
+
+        ProcessEquivalentSiteDirects(CurSite, PhysicalTileType, LogicalBlockType, Prop, loc_data);
 
         CurSite = CurSite.next_sibling(CurSite.name());
     }
@@ -4754,7 +4760,7 @@ static void link_physical_logical_types(std::vector<t_physical_tile_type>& Physi
                     physical_tile.equivalent_sites.push_back(&logical_block);
                     logical_block.equivalent_tiles.push_back(&physical_tile);
 
-                    // TODO: Add check direct interconnect between site and tile add also pin mapping of integers
+                    check_port_direct_mappings(&physical_tile, &logical_block);
 
                     logical_block_added++;
                     break;
@@ -4769,24 +4775,34 @@ static void link_physical_logical_types(std::vector<t_physical_tile_type>& Physi
     }
 }
 
-static void check_port_equivalence(t_physical_tile_type& physical_tile, t_logical_block_type& logical_block) {
-    auto pb_type = logical_block.pb_type;
-    auto pb_type_ports = pb_type->ports;
+static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block) {
+    auto pb_type = logical_block->pb_type;
 
-    if (pb_type->num_ports != (int)physical_tile.ports.size()) {
+    if (pb_type->num_pins > physical_tile->num_pins) {
         archfpga_throw(__FILE__, __LINE__,
-                       "Logical and Physical types have a different number of ports.\n");
+                       "Logical Block (%s) has more pins than the Physical Tile (%s).\n",
+                       logical_block->name, physical_tile->name);
     }
 
-    for (auto& tile_port : physical_tile.ports) {
-        auto block_port = pb_type_ports[tile_port.index];
+    auto& pin_direct_mapping = physical_tile->tile_block_pin_directs_map.at(logical_block->index);
 
-        if (0 != strcmp(tile_port.name, block_port.name)
-            || tile_port.type != block_port.type
-            || tile_port.num_pins != block_port.num_pins
-            || tile_port.equivalent != block_port.equivalent) {
+    if (pb_type->num_pins != (int)pin_direct_mapping.size()) {
+        archfpga_throw(__FILE__, __LINE__,
+                       "Logical Block (%s) has more pins than the one specified in the direct mapping.\n",
+                       logical_block->name);
+    }
+
+    for (auto pin_map : pin_direct_mapping) {
+        auto block_port = get_port_by_pin(logical_block, pin_map.first);
+        auto tile_port = get_port_by_pin(physical_tile, pin_map.second);
+
+        if (0 != strcmp(tile_port->name, block_port->name)
+            || tile_port->type != block_port->type
+            || tile_port->num_pins != block_port->num_pins
+            || tile_port->equivalent != block_port->equivalent) {
             archfpga_throw(__FILE__, __LINE__,
-                           "Logical and Physical types do not have equivalent port specifications.\n");
+                           "Logical (%s) and Physical (%s) types do not have equivalent port specifications.\n",
+                           logical_block->name, physical_tile->name);
         }
     }
 }
@@ -4814,11 +4830,34 @@ static const t_port* get_port_by_name(t_logical_block_type_ptr type, const char*
     return nullptr;
 }
 
+static const t_physical_tile_port* get_port_by_pin(t_physical_tile_type_ptr type, int pin) {
+    for (auto port : type->ports) {
+        if (pin >= port.absolute_first_pin_index && pin < port.num_pins) {
+            return &type->ports[port.index];
+        }
+    }
+
+    return nullptr;
+}
+
+static const t_port* get_port_by_pin(t_logical_block_type_ptr type, int pin) {
+    auto pb_type = type->pb_type;
+
+    for (int i = 0; i < pb_type->num_ports; i++) {
+        auto port = pb_type->ports[i];
+        if (pin >= port.absolute_first_pin_index && pin < port.num_pins) {
+            return &pb_type->ports[port.index];
+        }
+    }
+
+    return nullptr;
+}
+
 template<typename T>
-static T get_type_by_name(const char* type_name, std::vector<T>& types) {
-    for (auto type : types) {
+static T* get_type_by_name(const char* type_name, std::vector<T>& types) {
+    for (auto& type : types) {
         if (0 == strcmp(type.name, type_name)) {
-            return type;
+            return &type;
         }
     }
 

vpr/src/place/place.cpp

@@ -418,6 +418,8 @@ static void placement_inner_loop(float t,
 
 static void recompute_costs_from_scratch(const t_placer_opts& placer_opts, const PlaceDelayModel* delay_model, t_placer_costs* costs);
 
+static t_physical_tile_type_ptr pick_highest_priority_type(t_logical_block_type_ptr logical_block, int num_needed_types, int* free_locations);
+
 static void calc_placer_stats(t_placer_statistics& stats, float& success_rat, double& std_dev, const t_placer_costs& costs, const int move_lim);
 
 static void generate_post_place_timing_reports(const t_placer_opts& placer_opts,
@@ -2408,16 +2410,18 @@ static void initial_placement_pl_macros(int macros_max_num_tries, int* free_loca
         // Assume that all the blocks in the macro are of the same type
         blk_id = pl_macros[imacro].members[0].blk_index;
         auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id);
-        auto type = pick_random_placement_type(logical_block);
-        itype = type->index;
-        if (free_locations[itype] < int(pl_macros[imacro].members.size())) {
+        auto type = pick_highest_priority_type(logical_block, int(pl_macros[imacro].members.size()), free_locations);
+
+        if (type == nullptr) {
             VPR_FATAL_ERROR(VPR_ERROR_PLACE,
                             "Initial placement failed.\n"
                             "Could not place macro length %zu with head block %s (#%zu); not enough free locations of type %s (#%d).\n"
                             "VPR cannot auto-size for your circuit, please resize the FPGA manually.\n",
                             pl_macros[imacro].members.size(), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), type->name, itype);
         }
 
+        itype = type->index;
+
         // Try to place the macro first, if can be placed - place them, otherwise try again
         for (itry = 0; itry < macros_max_num_tries && macro_placed == false; itry++) {
             // Choose a random position for the head
@@ -2484,15 +2488,17 @@ static void initial_placement_blocks(int* free_locations, enum e_pad_loc_type pa
              * that location again, so remove it from the free_locations array.
              */
 
-            itype = pick_random_placement_type(logical_block)->index;
+            auto type = pick_highest_priority_type(logical_block, 1, free_locations);
 
-            if (free_locations[itype] <= 0) {
+            if (type == nullptr) {
                 VPR_FATAL_ERROR(VPR_ERROR_PLACE,
                                 "Initial placement failed.\n"
                                 "Could not place block %s (#%zu); no free locations of type %s (#%d).\n",
                                 cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), device_ctx.physical_tile_types[itype].name, itype);
             }
 
+            itype = type->index;
+
             t_pl_loc to;
             initial_placement_location(free_locations, ipos, itype, to);
 
@@ -2844,6 +2850,19 @@ int check_macro_placement_consistency() {
     return error;
 }
 
+static t_physical_tile_type_ptr pick_highest_priority_type(t_logical_block_type_ptr logical_block, int num_needed_types, int* free_locations) {
+    // Loop through the ordered map to get tiles in a decreasing priority order
+    for (auto& physical_tiles : logical_block->placement_priority) {
+        for (auto tile : physical_tiles.second) {
+            if (free_locations[tile->index] >= num_needed_types) {
+                return tile;
+            }
+        }
+    }
+
+    return nullptr;
+}
+
 #ifdef VERBOSE
 static void print_clb_placement(const char* fname) {
     /* Prints out the clb placements to a file.  */

vpr/src/util/vpr_utils.cpp

@@ -2283,34 +2283,6 @@ void place_sync_external_block_connections(ClusterBlockId iblk) {
     place_ctx.block_locs[iblk].nets_and_pins_synced_to_z_coordinate = true;
 }
 
-void update_physical_pin_indices() {
-    auto& cluster_ctx = g_vpr_ctx.mutable_clustering();
-    auto& clb_nlist = cluster_ctx.clb_nlist;
-
-    for (auto blk : clb_nlist.blocks()) {
-        auto logical_block = clb_nlist.block_type(blk);
-        auto physical_tile = physical_tile_type(blk);
-
-        // Physical tile and logical block are already compatible
-        if (physical_tile == physical_tile_type(logical_block)) {
-            continue;
-        }
-
-        for (auto pin : clb_nlist.block_pins(blk)) {
-            int block_pin = clb_nlist.pin_logical_index(pin);
-
-            auto pin_directs_map = physical_tile->tile_block_pin_directs_map;
-            auto map_result = pin_directs_map.find(logical_block->index);
-            std::unordered_map<int, int> map = map_result->second;
-
-            auto pin_result = map.find(block_pin);
-            auto phys_pin = pin_result->second;
-
-            clb_nlist.set_pin_physical_index(pin, phys_pin);
-        }
-    }
-}
-
 int get_max_num_pins(t_logical_block_type_ptr logical_block) {
     int max_num_pins = 0;
 

vpr/src/util/vpr_utils.h

@@ -172,7 +172,6 @@ void print_usage_by_wire_length();
 AtomBlockId find_memory_sibling(const t_pb* pb);
 
 void place_sync_external_block_connections(ClusterBlockId iblk);
-void update_physical_pin_indices();
 int get_max_num_pins(t_logical_block_type_ptr logical_block);
 
 bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block);