equivalent: avoid using logical_block_type() func

Also solved draw.cpp issue

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -642,7 +642,7 @@ static void SetupPinLocationsAndPinClasses(pugi::xml_node Locations,
             if (port.equivalent != PortEquivalence::NONE) {
                 PhysicalTileType->class_inf[num_class].num_pins = port.num_pins;
                 PhysicalTileType->class_inf[num_class].pinlist = (int*)vtr::malloc(sizeof(int) * port.num_pins);
-                PhysicalTileType->class_inf[num_class].equivalence = PhysicalTileType->ports[i].equivalent;
+                PhysicalTileType->class_inf[num_class].equivalence = port.equivalent;
             }
 
             for (k = 0; k < port.num_pins; ++k) {

vpr/src/base/vpr_api.cpp

@@ -438,11 +438,14 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) {
             continue;
         }
 
-        float util = 0.;
         if (device_ctx.grid.num_instances(&type) != 0) {
-            util = float(num_type_instances[logical_block_type(&type)]) / device_ctx.grid.num_instances(&type);
+            float util = 0.;
+            VTR_LOG("\tPhysical Tile %s:\n", type.name);
+            for (auto logical_block : type.equivalent_sites) {
+                util = float(num_type_instances[logical_block]) / device_ctx.grid.num_instances(&type);
+                VTR_LOG("\tBlock Utilization: %.2f Logical Block: %s\n", util, logical_block->name);
+            }
         }
-        VTR_LOG("\tBlock Utilization: %.2f Type: %s\n", util, type.name);
     }
     VTR_LOG("\n");
 

vpr/src/draw/draw.cpp

@@ -2730,9 +2730,13 @@ void deselect_all() {
 }
 
 static void draw_reset_blk_color(ClusterBlockId blk_id) {
+    auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist;
+
+    auto logical_block = clb_nlist.block_type(blk_id);
+
     t_draw_state* draw_state = get_draw_state_vars();
 
-    draw_state->block_color[blk_id] = get_block_type_color(physical_tile_type(blk_id));
+    draw_state->block_color[blk_id] = get_block_type_color(pick_random_physical_type(logical_block));
 }
 
 /**
@@ -3690,7 +3694,7 @@ static void highlight_blocks(double x, double y) {
         }
     }
 
-    if (clb_index == EMPTY_BLOCK_ID) {
+    if (clb_index == EMPTY_BLOCK_ID || clb_index == ClusterBlockId::INVALID()) {
         //Nothing found
         return;
     }

vpr/src/draw/draw_types.cpp

@@ -95,7 +95,7 @@ ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(const ClusterBlockId clb_in
 
 ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index) {
     auto& device_ctx = g_vpr_ctx.device();
-    return get_pb_bbox(grid_x, grid_y, sub_block_index, *logical_block_type(device_ctx.grid[grid_x][grid_y].type)->pb_graph_head);
+    return get_pb_bbox(grid_x, grid_y, sub_block_index, *pick_random_logical_type(device_ctx.grid[grid_x][grid_y].type)->pb_graph_head);
 }
 
 #endif // NO_GRAPHICS

vpr/src/draw/intra_logic_block.cpp

@@ -92,10 +92,12 @@ void draw_internal_init_blk() {
     auto& device_ctx = g_vpr_ctx.device();
     for (const auto& type : device_ctx.physical_tile_types) {
         /* Empty block has no sub_blocks */
-        if (&type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE)
+        if (is_empty_type(&type)) {
             continue;
+        }
 
-        pb_graph_head_node = logical_block_type(&type)->pb_graph_head;
+        auto logical_block = pick_random_logical_type(&type);
+        pb_graph_head_node = logical_block->pb_graph_head;
         int type_descriptor_index = type.index;
 
         int num_sub_tiles = type.capacity;
@@ -129,7 +131,7 @@ void draw_internal_init_blk() {
                                   clb_bbox.width(), clb_bbox.height());
 
         /* Determine the max number of sub_block levels in the FPGA */
-        draw_state->max_sub_blk_lvl = std::max(draw_internal_find_max_lvl(*logical_block_type(&type)->pb_type),
+        draw_state->max_sub_blk_lvl = std::max(draw_internal_find_max_lvl(*logical_block->pb_type),
                                                draw_state->max_sub_blk_lvl);
     }
 }

vpr/src/power/power.cpp

@@ -601,26 +601,34 @@ static void power_usage_blocks(t_power_usage* power_usage) {
 
     power_reset_tile_usage();
 
+    t_logical_block_type_ptr logical_block;
+
     /* Loop through all grid locations */
     for (size_t x = 0; x < device_ctx.grid.width(); x++) {
         for (size_t y = 0; y < device_ctx.grid.height(); y++) {
+            auto physical_tile = device_ctx.grid[x][y].type;
+
             if ((device_ctx.grid[x][y].width_offset != 0)
                 || (device_ctx.grid[x][y].height_offset != 0)
-                || (device_ctx.grid[x][y].type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE)) {
+                || is_empty_type(physical_tile)) {
                 continue;
             }
 
-            for (int z = 0; z < device_ctx.grid[x][y].type->capacity; z++) {
+            for (int z = 0; z < physical_tile->capacity; z++) {
                 t_pb* pb = nullptr;
                 t_power_usage pb_power;
 
                 ClusterBlockId iblk = place_ctx.grid_blocks[x][y].blocks[z];
 
-                if (iblk != EMPTY_BLOCK_ID && iblk != INVALID_BLOCK_ID)
+                if (iblk != EMPTY_BLOCK_ID && iblk != INVALID_BLOCK_ID) {
                     pb = cluster_ctx.clb_nlist.block_pb(iblk);
+                    logical_block = cluster_ctx.clb_nlist.block_type(iblk);
+                } else {
+                    logical_block = pick_random_logical_type(physical_tile);
+                }
 
                 /* Calculate power of this CLB */
-                power_usage_pb(&pb_power, pb, logical_block_type(device_ctx.grid[x][y].type)->pb_graph_head, iblk);
+                power_usage_pb(&pb_power, pb, logical_block->pb_graph_head, iblk);
                 power_add_usage(power_usage, &pb_power);
             }
         }

vpr/src/route/clock_connection_builders.cpp

@@ -208,8 +208,16 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra
             auto width_offset = grid[x][y].width_offset;
             auto height_offset = grid[x][y].height_offset;
 
-            // Ignore gird locations that do not have blocks
-            if (!logical_block_type(type)->pb_type) {
+            // Ignore grid locations that do not have blocks
+            bool has_pb_type = false;
+            for (auto logical_block : type->equivalent_sites) {
+                if (logical_block->pb_type) {
+                    has_pb_type = true;
+                    break;
+                }
+            }
+
+            if (!has_pb_type) {
                 continue;
             }
 

vpr/src/util/vpr_utils.cpp

@@ -637,20 +637,6 @@ t_physical_tile_type_ptr physical_tile_type(ClusterBlockId blk) {
     return device_ctx.grid[loc.x][loc.y].type;
 }
 
-t_logical_block_type_ptr logical_block_type(t_physical_tile_type_ptr physical_tile_type) {
-    auto& device_ctx = g_vpr_ctx.device();
-    auto& logical_blocks = device_ctx.logical_block_types;
-
-    // Loop through the ordered map to get tiles in a decreasing priority order
-    for (auto& logical_blocks_ids : physical_tile_type->logical_blocks_priority) {
-        for (auto block_id : logical_blocks_ids.second) {
-            return &logical_blocks[block_id];
-        }
-    }
-
-    VPR_THROW(VPR_ERROR_OTHER, "No corresponding logical block type found for physical tile type %s\n", physical_tile_type->name);
-}
-
 /* Each node in the pb_graph for a top-level pb_type can be uniquely identified
  * by its pins. Since the pins in a cluster of a certain type are densely indexed,
  * this function will find the pin index (int pin_count_in_cluster) of the first
@@ -2178,6 +2164,19 @@ t_physical_tile_type_ptr pick_random_physical_type(t_logical_block_type_ptr logi
     return equivalent_tiles[index];
 }
 
+t_logical_block_type_ptr pick_random_logical_type(t_physical_tile_type_ptr physical_tile) {
+    auto equivalent_sites = physical_tile->equivalent_sites;
+
+    size_t num_equivalent_sites = equivalent_sites.size();
+    int index = 0;
+
+    if (num_equivalent_sites > 1) {
+        index = vtr::irand((int)equivalent_sites.size() - 1);
+    }
+
+    return equivalent_sites[index];
+}
+
 int get_logical_pin(t_physical_tile_type_ptr physical_tile,
                     t_logical_block_type_ptr logical_block,
                     int pin) {

vpr/src/util/vpr_utils.h

@@ -28,9 +28,8 @@ bool is_io_type(t_physical_tile_type_ptr type);
 bool is_empty_type(t_physical_tile_type_ptr type);
 bool is_empty_type(t_logical_block_type_ptr type);
 
-//Returns the corresponding physical/logical type given the logical/physical type as parameter
+//Returns the corresponding physical type given the logical type as parameter
 t_physical_tile_type_ptr physical_tile_type(ClusterBlockId blk);
-t_logical_block_type_ptr logical_block_type(t_physical_tile_type_ptr physical_tile_type);
 
 int get_unique_pb_graph_node_id(const t_pb_graph_node* pb_graph_node);
 
@@ -172,6 +171,7 @@ int get_max_num_pins(t_logical_block_type_ptr logical_block);
 
 bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block);
 t_physical_tile_type_ptr pick_random_physical_type(t_logical_block_type_ptr logical_block);
+t_logical_block_type_ptr pick_random_logical_type(t_physical_tile_type_ptr physical_tile);
 
 int get_logical_pin(t_physical_tile_type_ptr physical_tile,
                     t_logical_block_type_ptr logical_block,