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vtr_flow: update golden results
Signed-off-by: Alessandro Comodi <[email protected]>
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vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/golden_results.txt

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vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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k4_n4_v7_bidir.xml styr.blif common 1.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_bidir.xml/styr.blif/common 23568 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1270 0.23 0.00 5.57595 -70.6881 -5.57595 5.57595 0.000181897 0.00014297 0.0196268 0.0159363 16 2004 29 2.43e+06 2.01e+06 -1 -1 0.40 0.07519 0.0633621 1902 24 1378 4371 246547 28194 7.23996 7.23996 -92.3987 -7.23996 0 0 -1 -1 0.05 0.0147415 0.0130549
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k4_n4_v7_longline_bidir.xml styr.blif common 1.93 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_longline_bidir.xml/styr.blif/common 21548 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1234 0.26 0.00 5.77027 -74.3866 -5.77027 5.77027 0.000190686 0.000150269 0.0199143 0.0162876 18 2361 37 2.43e+06 2.01e+06 -1 -1 0.54 0.0814192 0.0687497 2409 21 1514 4799 386424 43001 8.75717 8.75717 -109.461 -8.75717 0 0 -1 -1 0.06 0.0144257 0.0128624
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k4_n4_v7_l1_bidir.xml styr.blif common 1.88 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_l1_bidir.xml/styr.blif/common 21528 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1235 0.26 0.00 6.82024 -77.4787 -6.82024 6.82024 0.000179396 0.000141516 0.0197106 0.0159732 10 1513 47 2.43e+06 2.01e+06 -1 -1 0.91 0.0669803 0.0566492 1294 23 1248 4320 389587 82246 8.65232 8.65232 -101.426 -8.65232 0 0 -1 -1 0.10 0.0187415 0.0166916
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k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.37 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_bidir_pass_gate.xml/styr.blif/common 23280 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1244 0.54 0.00 5.39221 -64.0616 -5.39221 5.39221 0.000181231 0.000144846 0.0215371 0.0174077 16 2062 32 2.43e+06 2.01e+06 -1 -1 1.20 0.113886 0.0960411 2100 30 1484 4823 1048337 136252 11.9977 11.9977 -129.445 -11.9977 0 0 -1 -1 0.13 0.0186144 0.0165004
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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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k4_n4_v7_bidir.xml styr.blif common 4.91 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2984-g40f8a4e03 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-101-generic x86_64 2020-11-17T11:05:23 acomodi /data/vtr-symbiflow 29040 10 10 253 263 1 169 87 11 11 121 clb auto 0.14 1235 0.70 0.01 5.05357 -66.5826 -5.05357 5.05357 0.22 0.0119668 0.0118854 0.531624 0.493778 17 1920 22 2.43e+06 2.01e+06 -1 -1 2.42 2.01203 1.8362 1948 21 1206 3974 274707 30902 8.42601 8.42601 -111.292 -8.42601 0 0 -1 -1 0.06 0.25 0.197704 0.182356
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k4_n4_v7_longline_bidir.xml styr.blif common 4.83 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2984-g40f8a4e03 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-101-generic x86_64 2020-11-17T11:05:23 acomodi /data/vtr-symbiflow 28580 10 10 253 263 1 169 87 11 11 121 clb auto 0.04 1245 0.76 0.02 6.47241 -71.6651 -6.47241 6.47241 0.30 0.0150534 0.0149012 0.600001 0.556758 18 2431 30 2.43e+06 2.01e+06 -1 -1 2.25 2.01433 1.84958 2290 24 1297 4221 358510 38820 8.88802 8.88802 -109.464 -8.88802 0 0 -1 -1 0.08 0.46 0.378923 0.329292
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k4_n4_v7_l1_bidir.xml styr.blif common 5.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2984-g40f8a4e03 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-101-generic x86_64 2020-11-17T11:05:23 acomodi /data/vtr-symbiflow 30380 10 10 253 263 1 169 87 11 11 121 clb auto 0.06 1258 0.72 0.00 6.27331 -78.4269 -6.27331 6.27331 0.30 0.000733412 0.00066024 0.534306 0.491898 11 1571 34 2.43e+06 2.01e+06 -1 -1 3.19 2.33726 2.17152 1279 26 1416 4518 323510 57783 8.17749 8.17749 -93.3598 -8.17749 0 0 -1 -1 0.07 0.32 0.209706 0.163317
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k4_n4_v7_bidir_pass_gate.xml styr.blif common 6.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2984-g40f8a4e03 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-101-generic x86_64 2020-11-17T11:05:23 acomodi /data/vtr-symbiflow 28716 10 10 253 263 1 169 87 11 11 121 clb auto 0.09 1252 0.96 0.00 6.10352 -65.9001 -6.10352 6.10352 0.81 0.00138439 0.000647292 0.762789 0.704237 16 2074 33 2.43e+06 2.01e+06 -1 -1 3.09 2.49754 2.31807 2002 28 1472 4983 1224648 177463 19.1006 19.1006 -250.242 -19.1006 0 0 -1 -1 0.10 0.30 0.0381586 0.0337189

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