Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into pb_graph_bug_fixes

Author: amin1377

ODIN_II/SRC/BLIFElaborate.cpp

@@ -485,7 +485,7 @@ static void resolve_arithmetic_nodes(nnode_t* node, uintptr_t traverse_mark_numb
             if (!hard_multipliers)
                 check_constant_multipication(node, traverse_mark_number, netlist);
             else
-                check_multiplier_port_size(node, netlist);
+                check_multiplier_port_size(node);
 
             /* Adding to mult_list for future checking on hard blocks */
             mult_list = insert_in_vptr_list(mult_list, node);

ODIN_II/SRC/include/multipliers.h

@@ -56,7 +56,7 @@ extern void define_mult_function(nnode_t* node, FILE* out);
 extern void split_multiplier(nnode_t* node, int a0, int b0, int a1, int b1, netlist_t* netlist);
 extern void iterate_multipliers(netlist_t* netlist);
 extern bool check_constant_multipication(nnode_t* node, uintptr_t traverse_mark_number, netlist_t* netlist);
-extern void check_multiplier_port_size(nnode_t* node, netlist_t* netlist);
+extern void check_multiplier_port_size(nnode_t* node);
 extern bool is_ast_multiplier(ast_node_t* node);
 extern void clean_multipliers();
 extern void free_multipliers();

ODIN_II/SRC/multipliers.cpp

@@ -1769,10 +1769,9 @@ bool is_ast_multiplier(ast_node_t* node) {
  * we need to expand output pins with pad pins
  * 
  * @param node pointer to the multiplication node
- * @param netlist pointer to the current netlist file
  * -----------------------------------------------------------------------
  */
-void check_multiplier_port_size(nnode_t* node, netlist_t* netlist) {
+void check_multiplier_port_size(nnode_t* node) {
     /* Can only perform the optimisation if hard multipliers exist! */
     if (hard_multipliers == NULL)
         return;
@@ -1795,8 +1794,16 @@ void check_multiplier_port_size(nnode_t* node, netlist_t* netlist) {
         for (int i = 0; i < node->num_output_pins; i++) {
             if (i < sizeout)
                 node->output_pins[i] = old_output_pins[i];
-            else
-                add_output_pin_to_node(node, get_pad_pin(netlist), i);
+            else {
+                npin_t* new_pin = allocate_npin();
+                new_pin->name = append_string("", "%s~dummy_output~%d", node->name, 0);
+                nnet_t* new_net = allocate_nnet();
+
+                // hook the output pin into the node
+                add_output_pin_to_node(node, new_pin, i);
+                // hook up new pin 1 into the new net
+                add_driver_pin_to_net(new_net, new_pin);
+            }
         }
         // CLEAN UP
         vtr::free(old_output_pins);

ODIN_II/SRC/partial_map.cpp

@@ -58,8 +58,8 @@ void partial_map_node(nnode_t* node, short traverse_number, netlist_t* netlist);
 void instantiate_not_logic(nnode_t* node, short mark, netlist_t* netlist);
 bool eliminate_buffer(nnode_t* node, short, netlist_t*);
 void instantiate_bitwise_logic(nnode_t* node, operation_list op, short mark, netlist_t* netlist);
-void instantiate_bitwise_reduction(nnode_t* node, operation_list op, short mark, netlist_t* netlist);
-void instantiate_logical_logic(nnode_t* node, operation_list op, short mark, netlist_t* netlist);
+void instantiate_bitwise_reduction(nnode_t* node, operation_list op, short mark);
+void instantiate_logical_logic(nnode_t* node, operation_list op, short mark);
 void instantiate_EQUAL(nnode_t* node, operation_list type, short mark, netlist_t* netlist);
 void instantiate_GE(nnode_t* node, operation_list type, short mark, netlist_t* netlist);
 void instantiate_GT(nnode_t* node, operation_list type, short mark, netlist_t* netlist);
@@ -155,7 +155,7 @@ void partial_map_node(nnode_t* node, short traverse_number, netlist_t* netlist)
             if (node->num_input_port_sizes >= 2) {
                 instantiate_bitwise_logic(node, node->type, traverse_number, netlist);
             } else if (node->num_input_port_sizes == 1) {
-                instantiate_bitwise_reduction(node, node->type, traverse_number, netlist);
+                instantiate_bitwise_reduction(node, node->type, traverse_number);
             } else
                 oassert(false);
             break;
@@ -167,7 +167,7 @@ void partial_map_node(nnode_t* node, short traverse_number, netlist_t* netlist)
         case LOGICAL_XOR:
         case LOGICAL_XNOR:
             if (node->num_input_port_sizes == 2) {
-                instantiate_logical_logic(node, node->type, traverse_number, netlist);
+                instantiate_logical_logic(node, node->type, traverse_number);
             }
             break;
 
@@ -602,7 +602,7 @@ bool eliminate_buffer(nnode_t* node, short, netlist_t*) {
 /*---------------------------------------------------------------------------------------------
  * (function: instantiate_logical_logic )
  *-------------------------------------------------------------------------------------------*/
-void instantiate_logical_logic(nnode_t* node, operation_list op, short mark, netlist_t* netlist) {
+void instantiate_logical_logic(nnode_t* node, operation_list op, short mark) {
     int i;
     int port_B_offset;
     int width_a;
@@ -627,28 +627,18 @@ void instantiate_logical_logic(nnode_t* node, operation_list op, short mark, net
     /* connect inputs.  In the case that a signal is smaller than the other then zero pad */
     for (i = 0; i < width_a; i++) {
         /* Joining the inputs to the input 1 of that gate */
-        if (i < width_a) {
-            remap_pin_to_new_node(node->input_pins[i], reduction1, i);
-        } else {
-            /* ELSE - the B input does not exist, so this answer goes right through */
-            add_input_pin_to_node(reduction1, get_zero_pin(netlist), i);
-        }
+        remap_pin_to_new_node(node->input_pins[i], reduction1, i);
     }
     for (i = 0; i < width_b; i++) {
         /* Joining the inputs to the input 1 of that gate */
-        if (i < width_b) {
-            remap_pin_to_new_node(node->input_pins[i + port_B_offset], reduction2, i);
-        } else {
-            /* ELSE - the B input does not exist, so this answer goes right through */
-            add_input_pin_to_node(reduction2, get_zero_pin(netlist), i);
-        }
+        remap_pin_to_new_node(node->input_pins[i + port_B_offset], reduction2, i);
     }
 
     connect_nodes(reduction1, 0, new_logic_cell, 0);
     connect_nodes(reduction2, 0, new_logic_cell, 1);
 
-    instantiate_bitwise_reduction(reduction1, BITWISE_OR, mark, netlist);
-    instantiate_bitwise_reduction(reduction2, BITWISE_OR, mark, netlist);
+    instantiate_bitwise_reduction(reduction1, BITWISE_OR, mark);
+    instantiate_bitwise_reduction(reduction2, BITWISE_OR, mark);
 
     remap_pin_to_new_node(node->output_pins[0], new_logic_cell, 0);
     free_nnode(node);
@@ -657,7 +647,7 @@ void instantiate_logical_logic(nnode_t* node, operation_list op, short mark, net
  * (function: instantiate_bitwise_reduction )
  * 	Makes 2 input gates to break into bitwise
  *-------------------------------------------------------------------------------------------*/
-void instantiate_bitwise_reduction(nnode_t* node, operation_list op, short mark, netlist_t* netlist) {
+void instantiate_bitwise_reduction(nnode_t* node, operation_list op, short mark) {
     int i;
     int width_a;
     nnode_t* new_logic_cell;
@@ -705,12 +695,7 @@ void instantiate_bitwise_reduction(nnode_t* node, operation_list op, short mark,
     /* connect inputs.  In the case that a signal is smaller than the other then zero pad */
     for (i = 0; i < width_a; i++) {
         /* Joining the inputs to the input 1 of that gate */
-        if (i < width_a) {
-            remap_pin_to_new_node(node->input_pins[i], new_logic_cell, i);
-        } else {
-            /* ELSE - the B input does not exist, so this answer goes right through */
-            add_input_pin_to_node(new_logic_cell, get_zero_pin(netlist), i);
-        }
+        remap_pin_to_new_node(node->input_pins[i], new_logic_cell, i);
     }
 
     remap_pin_to_new_node(node->output_pins[0], new_logic_cell, 0);