[Yosys]: Updating Yosys execution python scripts by adding a system run command of 'write_arch_bb'

	 to generate the declaration of complex blocks and reading them as black box by Yosys

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

vtr_flow/misc/yosyslib/synthesis.tcl

@@ -18,6 +18,9 @@ yosys -import
 # XXX (input circuit) is replaced with filename by the run_vtr_flow script
 read_verilog -sv -nolatches XXX
 
+# read the custom complex blocks in the architecture
+read_verilog -lib CCC
+
 # These commands follow the generic `synth'
 # command script inside Yosys
 # The -libdir argument allows Yosys to search the current 
@@ -64,7 +67,7 @@ opt -full
 techmap 
 opt -fast
 
-# We read the definitions for all the VTR primitives
+# read the definitions for all the VTR primitives
 # as blackboxes
 read_verilog -lib TTT/adder.v
 read_verilog -lib TTT/multiply.v

vtr_flow/scripts/python_libs/vtr/paths.py

@@ -22,6 +22,10 @@
 yosys_lib_path = vtr_flow_path / "misc" / "yosyslib"
 yosys_script_path = yosys_lib_path / "synthesis.tcl"
 
+# ARCHFPGA paths
+archfpga_path = root_path / "ArchFPGA"
+write_arch_bb_exe_path = root_path / "build/libs/libarchfpga/write_arch_bb"
+
 # ABC paths
 abc_path = root_path / "abc"
 abc_exe_path = abc_path / "abc"

vtr_flow/scripts/python_libs/vtr/yosys/yosys.py

@@ -25,6 +25,7 @@
     "DPRAM": "dual_port_ram.v",
     "SPRAMR": "spram_rename.v",
     "DPRAMR": "dpram_rename.v",
+    "DSPBB": "arch_dsps.v",
 }
 
 
@@ -58,6 +59,7 @@ def init_script_file(
     yosys_dpram_full_path,
     yosys_spram_rename_full_path,
     yosys_dpram_rename_full_path,
+    architecture_dsp_full_path,
     circuit_list,
     output_netlist,
     memory_addr_width,
@@ -81,6 +83,7 @@ def init_script_file(
             "DDD": yosys_dpram_full_path,
             "SSR": yosys_spram_rename_full_path,
             "DDR": yosys_dpram_rename_full_path,
+            "CCC": architecture_dsp_full_path,
             "TTT": str(vtr.paths.yosys_lib_path),
             "ZZZ": output_netlist,
         },
@@ -99,7 +102,7 @@ def init_script_file(
     vtr.file_replace(yosys_dpram_rename_full_path, {"PPP": memory_addr_width})
 
 
-# pylint: disable=too-many-arguments, too-many-locals
+# pylint: disable=too-many-arguments, too-many-locals, too-many-statements
 def run(
     architecture_file,
     circuit_file,
@@ -202,6 +205,21 @@ def run(
     shutil.copyfile(yosys_base_spram_rename, yosys_spram_rename_full_path)
     shutil.copyfile(yosys_base_dpram_rename, yosys_dpram_rename_full_path)
 
+    write_arch_bb_exec = str(vtr.paths.write_arch_bb_exe_path)
+    architecture_dsp_full_path = str(vtr.paths.scripts_path / temp_dir / YOSYS_LIB_FILES["DSPBB"])
+
+    # executing write_arch_bb to extract the black box definitions of the given arch file
+    command_runner.run_system_command(
+        [
+            write_arch_bb_exec,
+            str(vtr.paths.scripts_path / architecture_file),
+            architecture_dsp_full_path,
+        ],
+        temp_dir=temp_dir,
+        log_filename="write_arch_bb.log",
+        indent_depth=1,
+    )
+
     # Create a list showing all (.v) and (.vh) files
     circuit_list = create_circuits_list(circuit_file, include_files)
 
@@ -212,6 +230,7 @@ def run(
         yosys_dpram_full_path,
         yosys_spram_rename_full_path,
         yosys_dpram_rename_full_path,
+        architecture_dsp_full_path,
         circuit_list,
         output_netlist.name,
         vtr.determine_memory_addr_width(str(architecture_file)),
@@ -236,4 +255,4 @@ def run(
     )
 
 
-# pylint: enable=too-many-arguments, too-many-locals
+# pylint: enable=too-many-arguments, too-many-locals, too-many-statements