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acomodiacomodi
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fix compilation errors
Signed-off-by: Alessandro Comodi <[email protected]>
1 parent fb147ad commit e867548

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12 files changed

+208
-192
lines changed

12 files changed

+208
-192
lines changed

‎libs/libarchfpga/src/arch_util.cpp

Lines changed: 3 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -222,38 +222,10 @@ void free_type_descriptors(std::vector<t_physical_tile_type>& type_descriptors)
222222
continue;
223223
}
224224

225-
for (int width = 0; width < type.width; ++width) {
226-
for (int height = 0; height < type.height; ++height) {
227-
for (int side = 0; side < 4; ++side) {
228-
for (int pin = 0; pin < type.num_pin_loc_assignments[width][height][side]; ++pin) {
229-
if (type.pin_loc_assignments[width][height][side][pin])
230-
vtr::free(type.pin_loc_assignments[width][height][side][pin]);
231-
}
232-
vtr::free(type.pinloc[width][height][side]);
233-
vtr::free(type.pin_loc_assignments[width][height][side]);
234-
}
235-
vtr::free(type.pinloc[width][height]);
236-
vtr::free(type.pin_loc_assignments[width][height]);
237-
vtr::free(type.num_pin_loc_assignments[width][height]);
225+
for (auto& sub_tile : type.sub_tiles) {
226+
for (auto port : sub_tile.ports) {
227+
vtr::free(port.name);
238228
}
239-
vtr::free(type.pinloc[width]);
240-
vtr::free(type.pin_loc_assignments[width]);
241-
vtr::free(type.num_pin_loc_assignments[width]);
242-
}
243-
vtr::free(type.pinloc);
244-
vtr::free(type.pin_loc_assignments);
245-
vtr::free(type.num_pin_loc_assignments);
246-
247-
for (int j = 0; j < type.num_class; ++j) {
248-
vtr::free(type.class_inf[j].pinlist);
249-
}
250-
vtr::free(type.class_inf);
251-
vtr::free(type.is_ignored_pin);
252-
vtr::free(type.is_pin_global);
253-
vtr::free(type.pin_class);
254-
255-
for (auto port : type.ports) {
256-
vtr::free(port.name);
257229
}
258230
}
259231
type_descriptors.clear();
@@ -547,11 +519,6 @@ t_physical_tile_type SetupEmptyPhysicalType() {
547519
type.capacity = 0;
548520
type.num_drivers = 0;
549521
type.num_receivers = 0;
550-
type.pinloc = nullptr;
551-
type.num_class = 0;
552-
type.class_inf = nullptr;
553-
type.pin_class = nullptr;
554-
type.is_ignored_pin = nullptr;
555522
type.area = UNDEFINED;
556523
type.switchblock_locations = vtr::Matrix<e_sb_type>({{size_t(type.width), size_t(type.height)}}, e_sb_type::FULL);
557524
type.switchblock_switch_overrides = vtr::Matrix<int>({{size_t(type.width), size_t(type.height)}}, DEFAULT_SWITCH);

‎libs/libarchfpga/src/physical_types.h

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,7 @@ struct t_physical_tile_port;
5858
struct t_equivalent_site;
5959
struct t_physical_tile_type;
6060
typedef const t_physical_tile_type* t_physical_tile_type_ptr;
61+
struct t_sub_tile;
6162
struct t_logical_block_type;
6263
typedef const t_logical_block_type* t_logical_block_type_ptr;
6364
struct t_logical_pin;
@@ -630,6 +631,8 @@ struct t_physical_tile_type {
630631
* A sub tile adds flexibility in the tile composition description.
631632
*/
632633
struct t_sub_tile {
634+
char* name = nullptr;
635+
633636
// Mapping between the sub tile's pins and the physical pins corresponding
634637
// to the physical tile type.
635638
std::vector<int> sub_tile_to_tile_pin_indices;
@@ -638,18 +641,22 @@ struct t_sub_tile {
638641

639642
std::vector<t_logical_block_type_ptr> equivalent_sites;
640643

644+
int capacity = 0;
645+
641646
int index = -1;
642-
}
647+
};
643648

644649
/** A logical pin defines the pin index of a logical block type (i.e. a top level PB type)
645650
* This structure wraps the int value of the logical pin to allow its storage in the
646651
* vtr::bimap container.
647652
*/
648653
struct t_logical_pin {
649654
int pin = -1;
655+
int sub_tile_index = -1;
650656

651-
t_logical_pin(int value) {
657+
t_logical_pin(int index, int value) {
652658
pin = value;
659+
sub_tile_index = index;
653660
}
654661

655662
bool operator==(const t_logical_pin o) const {

‎libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 127 additions & 102 deletions
Large diffs are not rendered by default.

‎vpr/src/base/clock_modeling.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
void ClockModeling::treat_clock_pins_as_non_globals() {
66
auto& device_ctx = g_vpr_ctx.mutable_device();
77

8-
for (const auto& type : device_ctx.physical_tile_types) {
8+
for (auto& type : device_ctx.physical_tile_types) {
99
if (!is_empty_type(&type)) {
1010
for (auto clock_pin_idx : type.get_clock_pins_indices()) {
1111
// clock pins should be originally considered as global when reading the architecture

‎vpr/src/place/timing_place_lookup.cpp

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -220,22 +220,24 @@ std::vector<int> get_best_classes(enum e_pin_type pintype, t_physical_tile_type_
220220
*/
221221

222222
std::vector<int> best_classes;
223-
223+
int best_class_index = 0;
224224
//Collect all classes of matching type which do not have all their pins ignored
225-
for (int i = 0; i < type->num_class; i++) {
226-
if (type->class_inf[i].type == pintype) {
225+
for (auto class_inf : type->class_inf) {
226+
if (class_inf.type == pintype) {
227227
bool all_ignored = true;
228-
for (int ipin = 0; ipin < type->class_inf[i].num_pins; ++ipin) {
229-
int pin = type->class_inf[i].pinlist[ipin];
228+
for (int ipin = 0; ipin < class_inf.num_pins; ++ipin) {
229+
int pin = class_inf.pinlist[ipin];
230230
if (!type->is_ignored_pin[pin]) {
231231
all_ignored = false;
232232
break;
233233
}
234234
}
235235
if (!all_ignored) {
236-
best_classes.push_back(i);
236+
best_classes.push_back(best_class_index);
237237
}
238238
}
239+
240+
best_class_index++;
239241
}
240242

241243
//Sort classe so largest pin class is first

‎vpr/src/route/check_route.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -555,7 +555,7 @@ void recompute_occupancy_from_scratch() {
555555
* (CLB outputs used up by being directly wired to subblocks used only *
556556
* locally). */
557557
for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
558-
for (iclass = 0; iclass < physical_tile_type(blk_id)->num_class; iclass++) {
558+
for (iclass = 0; iclass < (int)physical_tile_type(blk_id)->class_inf.size(); iclass++) {
559559
num_local_opins = route_ctx.clb_opins_used_locally[blk_id][iclass].size();
560560
/* Will always be 0 for pads or SINK classes. */
561561
for (ipin = 0; ipin < num_local_opins; ipin++) {
@@ -579,7 +579,7 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_
579579
auto& device_ctx = g_vpr_ctx.device();
580580

581581
for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
582-
for (iclass = 0; iclass < physical_tile_type(blk_id)->num_class; iclass++) {
582+
for (iclass = 0; iclass < (int)physical_tile_type(blk_id)->class_inf.size(); iclass++) {
583583
num_local_opins = clb_opins_used_locally[blk_id][iclass].size();
584584
/* Always 0 for pads and for SINK classes */
585585

‎vpr/src/route/check_rr_graph.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -357,7 +357,7 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext&
357357

358358
switch (rr_type) {
359359
case SOURCE:
360-
if (ptc_num >= type->num_class
360+
if (ptc_num >= (int)type->class_inf.size()
361361
|| type->class_inf[ptc_num].type != DRIVER) {
362362
VPR_ERROR(VPR_ERROR_ROUTE,
363363
"in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num);
@@ -369,7 +369,7 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext&
369369
break;
370370

371371
case SINK:
372-
if (ptc_num >= type->num_class
372+
if (ptc_num >= (int)type->class_inf.size()
373373
|| type->class_inf[ptc_num].type != RECEIVER) {
374374
VPR_ERROR(VPR_ERROR_ROUTE,
375375
"in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num);

‎vpr/src/route/route_common.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -847,7 +847,7 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() {
847847
auto type = physical_tile_type(blk_id);
848848

849849
get_class_range_for_block(blk_id, &class_low, &class_high);
850-
clb_opins_used_locally[blk_id].resize(type->num_class);
850+
clb_opins_used_locally[blk_id].resize((int)type->class_inf.size());
851851

852852
if (is_io_type(type)) continue;
853853

@@ -1026,8 +1026,8 @@ static vtr::vector<ClusterBlockId, std::vector<int>> load_rr_clb_sources(const t
10261026
for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
10271027
auto type = physical_tile_type(blk_id);
10281028
get_class_range_for_block(blk_id, &class_low, &class_high);
1029-
rr_blk_source[blk_id].resize(type->num_class);
1030-
for (iclass = 0; iclass < type->num_class; iclass++) {
1029+
rr_blk_source[blk_id].resize((int)type->class_inf.size());
1030+
for (iclass = 0; iclass < (int)type->class_inf.size(); iclass++) {
10311031
if (iclass >= class_low && iclass <= class_high) {
10321032
i = place_ctx.block_locs[blk_id].loc.x;
10331033
j = place_ctx.block_locs[blk_id].loc.y;
@@ -1371,7 +1371,7 @@ void reserve_locally_used_opins(HeapInterface* heap, float pres_fac, float acc_f
13711371
if (rip_up_local_opins) {
13721372
for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
13731373
type = physical_tile_type(blk_id);
1374-
for (iclass = 0; iclass < type->num_class; iclass++) {
1374+
for (iclass = 0; iclass < (int)type->class_inf.size(); iclass++) {
13751375
num_local_opin = route_ctx.clb_opins_used_locally[blk_id][iclass].size();
13761376

13771377
if (num_local_opin == 0) continue;
@@ -1392,7 +1392,7 @@ void reserve_locally_used_opins(HeapInterface* heap, float pres_fac, float acc_f
13921392

13931393
for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
13941394
type = physical_tile_type(blk_id);
1395-
for (iclass = 0; iclass < type->num_class; iclass++) {
1395+
for (iclass = 0; iclass < (int)type->class_inf.size(); iclass++) {
13961396
num_local_opin = route_ctx.clb_opins_used_locally[blk_id][iclass].size();
13971397

13981398
if (num_local_opin == 0) continue;

‎vpr/src/route/rr_graph.cpp

Lines changed: 23 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1396,10 +1396,10 @@ static void build_rr_sinks_sources(const int i,
13961396
return;
13971397

13981398
auto type = grid[i][j].type;
1399-
int num_class = type->num_class;
1400-
t_class* class_inf = type->class_inf;
1399+
int num_class = (int)type->class_inf.size();
1400+
std::vector<t_class> class_inf = type->class_inf;
14011401
int num_pins = type->num_pins;
1402-
int* pin_class = type->pin_class;
1402+
std::vector<int> pin_class = type->pin_class;
14031403

14041404
/* SINK and SOURCE-to-OPIN edges */
14051405
for (int iclass = 0; iclass < num_class; ++iclass) {
@@ -2613,10 +2613,16 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in
26132613
clb_to_clb_directs[i].from_clb_type = physical_tile;
26142614

26152615
bool port_found = false;
2616-
for (const auto& port : physical_tile->ports) {
2617-
if (0 == strcmp(port.name, port_name)) {
2618-
tile_port = port;
2619-
port_found = true;
2616+
for (const auto& sub_tile : physical_tile->sub_tiles) {
2617+
for (const auto& port : sub_tile.ports) {
2618+
if (0 == strcmp(port.name, port_name)) {
2619+
tile_port = port;
2620+
port_found = true;
2621+
break;
2622+
}
2623+
}
2624+
2625+
if (port_found) {
26202626
break;
26212627
}
26222628
}
@@ -2655,10 +2661,16 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in
26552661
clb_to_clb_directs[i].to_clb_type = physical_tile;
26562662

26572663
port_found = false;
2658-
for (const auto& port : physical_tile->ports) {
2659-
if (0 == strcmp(port.name, port_name)) {
2660-
tile_port = port;
2661-
port_found = true;
2664+
for (const auto& sub_tile : physical_tile->sub_tiles) {
2665+
for (const auto& port : sub_tile.ports) {
2666+
if (0 == strcmp(port.name, port_name)) {
2667+
tile_port = port;
2668+
port_found = true;
2669+
break;
2670+
}
2671+
}
2672+
2673+
if (port_found) {
26622674
break;
26632675
}
26642676
}

‎vpr/src/route/rr_graph2.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1067,8 +1067,8 @@ static void load_block_rr_indices(const DeviceGrid& grid,
10671067

10681068
//Assign indices for SINKs and SOURCEs
10691069
// Note that SINKS/SOURCES have no side, so we always use side 0
1070-
for (int iclass = 0; iclass < type->num_class; ++iclass) {
1071-
auto class_type = type->class_inf[iclass].type;
1070+
for (const auto& class_inf : type->class_inf) {
1071+
auto class_type = class_inf.type;
10721072
if (class_type == DRIVER) {
10731073
indices[SOURCE][x][y][0].push_back(*index);
10741074
indices[SINK][x][y][0].push_back(OPEN);
@@ -1079,8 +1079,8 @@ static void load_block_rr_indices(const DeviceGrid& grid,
10791079
}
10801080
++(*index);
10811081
}
1082-
VTR_ASSERT(indices[SOURCE][x][y][0].size() == size_t(type->num_class));
1083-
VTR_ASSERT(indices[SINK][x][y][0].size() == size_t(type->num_class));
1082+
VTR_ASSERT(indices[SOURCE][x][y][0].size() == type->class_inf.size());
1083+
VTR_ASSERT(indices[SINK][x][y][0].size() == type->class_inf.size());
10841084

10851085
//Assign indices for IPINs and OPINs at all offsets from root
10861086
for (int ipin = 0; ipin < type->num_pins; ++ipin) {
@@ -1454,7 +1454,7 @@ int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices,
14541454
* and ptc gives the number of this resource. ptc is the class number,
14551455
* pin number or track number, depending on what type of resource this
14561456
* is. All ptcs start at 0 and go up to pins_per_clb-1 or the equivalent.
1457-
* There are type->num_class SOURCEs + SINKs, type->num_pins IPINs + OPINs,
1457+
* There are (int)type->class_inf.size() SOURCEs + SINKs, type->num_pins IPINs + OPINs,
14581458
* and max_chan_width CHANX and CHANY (each).
14591459
*
14601460
* Note that for segments (CHANX and CHANY) of length > 1, the segment is
@@ -1497,12 +1497,12 @@ int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices,
14971497

14981498
switch (rr_type) {
14991499
case SOURCE:
1500-
VTR_ASSERT(ptc < type->num_class);
1500+
VTR_ASSERT(ptc < (int)type->class_inf.size());
15011501
VTR_ASSERT(type->class_inf[ptc].type == DRIVER);
15021502
break;
15031503

15041504
case SINK:
1505-
VTR_ASSERT(ptc < type->num_class);
1505+
VTR_ASSERT(ptc < (int)type->class_inf.size());
15061506
VTR_ASSERT(type->class_inf[ptc].type == RECEIVER);
15071507
break;
15081508

‎vpr/src/route/rr_graph_uxsdcxx_serializer.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1215,7 +1215,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
12151215
return tile->width;
12161216
}
12171217
inline size_t num_block_type_pin_class(const t_physical_tile_type*& tile) final {
1218-
return tile->num_class;
1218+
return (int)tile->class_inf.size();
12191219
}
12201220
inline const std::pair<const t_physical_tile_type*, const t_class*> get_block_type_pin_class(int n, const t_physical_tile_type*& tile) final {
12211221
return std::make_pair(tile, &tile->class_inf[n]);
@@ -1271,7 +1271,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
12711271
}
12721272
inline void preallocate_block_type_pin_class(std::pair<const t_physical_tile_type*, int>& context, size_t size) final {
12731273
const t_physical_tile_type* tile = context.first;
1274-
if (tile->num_class != (ssize_t)size) {
1274+
if ((int)tile->class_inf.size() != (ssize_t)size) {
12751275
report_error("Architecture file does not match block type");
12761276
}
12771277
}
@@ -1281,7 +1281,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
12811281
int& num_classes = context.second;
12821282

12831283
// Count number of pin classes
1284-
if (num_classes >= tile->num_class) {
1284+
if (num_classes >= (int)tile->class_inf.size()) {
12851285
report_error("Architecture file does not match block type");
12861286
}
12871287
const t_class* class_inf = &context.first->class_inf[num_classes++];
@@ -1296,7 +1296,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
12961296
inline void finish_block_types_block_type(std::pair<const t_physical_tile_type*, int>& context) final {
12971297
const t_physical_tile_type* tile = context.first;
12981298
int num_classes = context.second;
1299-
if (tile->num_class != num_classes) {
1299+
if ((int)tile->class_inf.size() != num_classes) {
13001300
report_error("Architecture file does not match block type");
13011301
}
13021302
}

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