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Merge pull request #2800 from verilog-to-routing/temp_annealer_class
PlacementAnnealer class
2 parents c8d3111 + 8c0fdfc commit e7f964e

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‎libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.cpp

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -200,7 +200,7 @@ NodeId TimingGraph::add_node(const NodeType type) {
200200

201201
EdgeId TimingGraph::add_edge(const EdgeType type, const NodeId src_node, const NodeId sink_node) {
202202
//We require that the source/sink node must already be in the graph,
203-
// so we can update them with thier edge references
203+
// so we can update them with their edge references
204204
TATUM_ASSERT(valid_node_id(src_node));
205205
TATUM_ASSERT(valid_node_id(sink_node));
206206

@@ -211,7 +211,7 @@ EdgeId TimingGraph::add_edge(const EdgeType type, const NodeId src_node, const N
211211
EdgeId edge_id = EdgeId(edge_ids_.size());
212212
edge_ids_.push_back(edge_id);
213213

214-
//Create the edgge
214+
//Create the edge
215215
edge_types_.push_back(type);
216216
edge_src_nodes_.push_back(src_node);
217217
edge_sink_nodes_.push_back(sink_node);
@@ -318,7 +318,7 @@ GraphIdMaps TimingGraph::compress() {
318318
levelize();
319319
validate();
320320

321-
return {node_id_map, edge_id_map};
321+
return {std::move(node_id_map), std::move(edge_id_map)};
322322
}
323323

324324
void TimingGraph::levelize() {
@@ -474,21 +474,20 @@ GraphIdMaps TimingGraph::optimize_layout() {
474474

475475
levelize();
476476

477-
return {node_id_map, edge_id_map};
477+
return {std::move(node_id_map), std::move(edge_id_map)};
478478
}
479479

480480
tatum::util::linear_map<EdgeId,EdgeId> TimingGraph::optimize_edge_layout() const {
481481
//Make all edges in a level be contiguous in memory
482482

483483
//Determine the edges driven by each level of the graph
484-
std::vector<std::vector<EdgeId>> edge_levels;
484+
std::vector<std::vector<EdgeId>> edge_levels(levels().size());
485485
for(LevelId level_id : levels()) {
486-
edge_levels.push_back(std::vector<EdgeId>());
487-
for(auto node_id : level_nodes(level_id)) {
486+
for(NodeId node_id : level_nodes(level_id)) {
488487

489488
//We walk the nodes according to the input-edge order.
490489
//This is the same order used by the arrival-time traversal (which is responsible
491-
//for most of the analyzer run-time), so matching it's order exactly results in
490+
//for most of the analyzer run-time), so matching its order exactly results in
492491
//better cache locality
493492
for(EdgeId edge_id : node_in_edges(node_id)) {
494493

@@ -498,7 +497,7 @@ tatum::util::linear_map<EdgeId,EdgeId> TimingGraph::optimize_edge_layout() const
498497
}
499498
}
500499

501-
//Maps from from original to new edge id, used to update node to edge refs
500+
//Maps from original to new edge id, used to update node to edge refs
502501
tatum::util::linear_map<EdgeId,EdgeId> orig_to_new_edge_id(edges().size());
503502

504503
//Determine the new order
@@ -874,7 +873,7 @@ std::vector<std::vector<NodeId>> identify_combinational_loops(const TimingGraph&
874873
}
875874

876875
std::vector<NodeId> find_transitively_connected_nodes(const TimingGraph& tg,
877-
const std::vector<NodeId> through_nodes,
876+
const std::vector<NodeId>& through_nodes,
878877
size_t max_depth) {
879878
std::vector<NodeId> nodes;
880879

@@ -890,7 +889,7 @@ std::vector<NodeId> find_transitively_connected_nodes(const TimingGraph& tg,
890889
}
891890

892891
std::vector<NodeId> find_transitive_fanin_nodes(const TimingGraph& tg,
893-
const std::vector<NodeId> sinks,
892+
const std::vector<NodeId>& sinks,
894893
size_t max_depth) {
895894
std::vector<NodeId> nodes;
896895

@@ -905,7 +904,7 @@ std::vector<NodeId> find_transitive_fanin_nodes(const TimingGraph& tg,
905904
}
906905

907906
std::vector<NodeId> find_transitive_fanout_nodes(const TimingGraph& tg,
908-
const std::vector<NodeId> sources,
907+
const std::vector<NodeId>& sources,
909908
size_t max_depth) {
910909
std::vector<NodeId> nodes;
911910

‎libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.hpp

Lines changed: 21 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@
1111
* store all edges as bi-directional edges.
1212
*
1313
* NOTE: We store only the static connectivity and node information in the 'TimingGraph' class.
14-
* Other dynamic information (edge delays, node arrival/required times) is stored seperately.
15-
* This means that most actions opearting on the timing graph (e.g. TimingAnalyzers) only
14+
* Other dynamic information (edge delays, node arrival/required times) is stored separately.
15+
* This means that most actions operating on the timing graph (e.g. TimingAnalyzers) only
1616
* require read-only access to the timing graph.
1717
*
1818
* Accessing Graph Data
@@ -28,9 +28,9 @@
2828
* rather than the more typical "Array of Structs (AoS)" data layout.
2929
*
3030
* By using a SoA layout we keep all data for a particular field (e.g. node types) in contiguous
31-
* memory. Using an AoS layout the various fields accross nodes would *not* be contiguous
31+
* memory. Using an AoS layout the various fields across nodes would *not* be contiguous
3232
* (although the different fields within each object (e.g. a TimingNode class) would be contiguous.
33-
* Since we typically perform operations on particular fields accross nodes the SoA layout performs
33+
* Since we typically perform operations on particular fields across nodes the SoA layout performs
3434
* better (and enables memory ordering optimizations). The edges are also stored in a SOA format.
3535
*
3636
* The SoA layout also motivates the ID based approach, which allows direct indexing into the required
@@ -48,11 +48,12 @@
4848
* and ensures that each cache line pulled into the cache will (likely) be accessed multiple times
4949
* before being evicted.
5050
*
51-
* Note that performing these optimizations is currently done explicity by calling the optimize_edge_layout()
52-
* and optimize_node_layout() member functions. In the future (particularily if incremental modification
51+
* Note that performing these optimizations is currently done explicitly by calling the optimize_edge_layout()
52+
* and optimize_node_layout() member functions. In the future (particularly if incremental modification
5353
* support is added), it may be a good idea apply these modifications automatically as needed.
5454
*
5555
*/
56+
#include <utility>
5657
#include <vector>
5758
#include <set>
5859
#include <limits>
@@ -149,7 +150,7 @@ class TimingGraph {
149150

150151
///\pre The graph must be levelized.
151152
///\returns A range containing the nodes which are primary inputs (i.e. SOURCE's with no fanin, corresponding to top level design inputs pins)
152-
///\warning Not all SOURCE nodes in the graph are primary inputs (e.g. FF Q pins are SOURCE's but have incomming edges from the clock network)
153+
///\warning Not all SOURCE nodes in the graph are primary inputs (e.g. FF Q pins are SOURCE's but have incoming edges from the clock network)
153154
///\see levelize()
154155
node_range primary_inputs() const {
155156
TATUM_ASSERT_MSG(is_levelized_, "Timing graph must be levelized");
@@ -282,7 +283,7 @@ class TimingGraph {
282283
//Node data
283284
tatum::util::linear_map<NodeId,NodeId> node_ids_; //The node IDs in the graph
284285
tatum::util::linear_map<NodeId,NodeType> node_types_; //Type of node
285-
tatum::util::linear_map<NodeId,std::vector<EdgeId>> node_in_edges_; //Incomiing edge IDs for node
286+
tatum::util::linear_map<NodeId,std::vector<EdgeId>> node_in_edges_; //Incoming edge IDs for node
286287
tatum::util::linear_map<NodeId,std::vector<EdgeId>> node_out_edges_; //Out going edge IDs for node
287288
tatum::util::linear_map<NodeId,LevelId> node_levels_; //Out going edge IDs for node
288289

@@ -293,12 +294,12 @@ class TimingGraph {
293294
tatum::util::linear_map<EdgeId,NodeId> edge_src_nodes_; //Source node for each edge
294295
tatum::util::linear_map<EdgeId,bool> edges_disabled_;
295296

296-
//Auxilary graph-level info, filled in by levelize()
297+
//Auxiliary graph-level info, filled in by levelize()
297298
tatum::util::linear_map<LevelId,LevelId> level_ids_; //The level IDs in the graph
298299
tatum::util::linear_map<LevelId,std::vector<NodeId>> level_nodes_; //Nodes in each level
299300
std::vector<NodeId> primary_inputs_; //Primary input nodes of the timing graph.
300301
std::vector<NodeId> logical_outputs_; //Logical output nodes of the timing graph.
301-
bool is_levelized_ = false; //Inidcates if the current levelization is valid
302+
bool is_levelized_ = false; //Indicates if the current levelization is valid
302303

303304
bool allow_dangling_combinational_nodes_ = false;
304305

@@ -310,26 +311,31 @@ std::vector<std::vector<NodeId>> identify_combinational_loops(const TimingGraph&
310311
//Returns the set of nodes transitively connected (either fanin or fanout) to nodes in through_nodes
311312
//up to max_depth (default infinite) hops away
312313
std::vector<NodeId> find_transitively_connected_nodes(const TimingGraph& tg,
313-
const std::vector<NodeId> through_nodes,
314+
const std::vector<NodeId>& through_nodes,
314315
size_t max_depth=std::numeric_limits<size_t>::max());
315316

316317
//Returns the set of nodes in the transitive fanin of nodes in sinks up to max_depth (default infinite) hops away
317318
std::vector<NodeId> find_transitive_fanin_nodes(const TimingGraph& tg,
318-
const std::vector<NodeId> sinks,
319+
const std::vector<NodeId>& sinks,
319320
size_t max_depth=std::numeric_limits<size_t>::max());
320321

321322
//Returns the set of nodes in the transitive fanout of nodes in sources up to max_depth (default infinite) hops away
322323
std::vector<NodeId> find_transitive_fanout_nodes(const TimingGraph& tg,
323-
const std::vector<NodeId> sources,
324+
const std::vector<NodeId>& sources,
324325
size_t max_depth=std::numeric_limits<size_t>::max());
325326

326327
EdgeType infer_edge_type(const TimingGraph& tg, EdgeId edge);
327328

328329
//Mappings from old to new IDs
329330
struct GraphIdMaps {
330-
GraphIdMaps(tatum::util::linear_map<NodeId,NodeId> node_map,
331-
tatum::util::linear_map<EdgeId,EdgeId> edge_map)
331+
GraphIdMaps(const tatum::util::linear_map<NodeId,NodeId>& node_map,
332+
const tatum::util::linear_map<EdgeId,EdgeId>& edge_map)
332333
: node_id_map(node_map), edge_id_map(edge_map) {}
334+
335+
GraphIdMaps(tatum::util::linear_map<NodeId,NodeId>&& node_map,
336+
tatum::util::linear_map<EdgeId,EdgeId>&& edge_map)
337+
: node_id_map(std::move(node_map)), edge_id_map(std::move(edge_map)) {}
338+
333339
tatum::util::linear_map<NodeId,NodeId> node_id_map;
334340
tatum::util::linear_map<EdgeId,EdgeId> edge_id_map;
335341
};

‎libs/EXTERNAL/libtatum/libtatum/tatum/analyzer_factory.hpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ namespace tatum {
1818
* This file defines the AnalyzerFactory class used to construct timing analyzers.
1919
*
2020
* We assume that the user has already defined the timing graph, constraints and
21-
* thier own delay calculator:
21+
* their own delay calculator:
2222
*
2323
* TimingGraph timing_graph;
2424
* TimingConstraints timing_constraints;
@@ -33,7 +33,7 @@ namespace tatum {
3333
* timing_constraints,
3434
* delay_calculator);
3535
*
36-
* We can similarily generate analyzers for other types of analysis, for instance Hold:
36+
* We can similarly generate analyzers for other types of analysis, for instance Hold:
3737
*
3838
* auto hold_analyzer = AnalyzerFactory<SetupAnalysis>::make(timing_graph,
3939
* timing_constraints,
@@ -45,7 +45,7 @@ namespace tatum {
4545
* timing_constraints,
4646
* delay_calculator);
4747
*
48-
* The AnalzyerFactory returns a std::unique_ptr to the appropriate TimingAnalyzer sub-class:
48+
* The AnalyzerFactory returns a std::unique_ptr to the appropriate TimingAnalyzer sub-class:
4949
*
5050
* SetupAnalysis => SetupTimingAnalyzer
5151
* HoldAnalysis => HoldTimingAnalyzer

‎libs/EXTERNAL/libtatum/libtatum/tatum/delay_calc/FixedDelayCalculator.hpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
namespace tatum {
99

1010
/**
11-
* An exmaple DelayCalculator implementation which takes
11+
* An example DelayCalculator implementation which takes
1212
* a vector of fixed pre-calculated edge delays
1313
*
1414
* \see DelayCalculator

‎libs/EXTERNAL/libtatum/libtatum/tatum/graph_visitors/GraphVisitor.hpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ class GraphVisitor {
2121
virtual void do_reset_node_arrival_tags_from_origin(const NodeId node_id, const NodeId origin) = 0;
2222
virtual void do_reset_node_required_tags_from_origin(const NodeId node_id, const NodeId origin) = 0;
2323

24-
//Returns true if the specified source/sink is unconstrainted
24+
//Returns true if the specified source/sink is unconstrained
2525
virtual bool do_arrival_pre_traverse_node(const TimingGraph& tg, const TimingConstraints& tc, const NodeId node_id) = 0;
2626
virtual bool do_required_pre_traverse_node(const TimingGraph& tg, const TimingConstraints& tc, const NodeId node_id) = 0;
2727

‎libs/libarchfpga/src/device_grid.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,10 @@ class DeviceGrid {
3838
size_t width() const { return grid_.dim_size(1); }
3939
///@brief Return the height of the grid at the specified layer
4040
size_t height() const { return grid_.dim_size(2); }
41+
///@brief Return the grid dimensions in (# of layers, width, height) format
42+
std::tuple<size_t, size_t, size_t> dim_sizes() const {
43+
return {grid_.dim_size(0), grid_.dim_size(1), grid_.dim_size(2)};
44+
}
4145

4246
///@brief Return the size of the flattened grid on the given layer
4347
inline size_t grid_size() const {

‎vpr/src/base/SetupVPR.cpp

Lines changed: 3 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,6 @@ void SetupVPR(const t_options* options,
9292
t_packer_opts* packerOpts,
9393
t_placer_opts* placerOpts,
9494
t_ap_opts* apOpts,
95-
t_annealing_sched* annealSched,
9695
t_router_opts* routerOpts,
9796
t_analysis_opts* analysisOpts,
9897
t_noc_opts* nocOpts,
@@ -140,7 +139,7 @@ void SetupVPR(const t_options* options,
140139

141140
SetupNetlistOpts(*options, *netlistOpts);
142141
SetupPlacerOpts(*options, placerOpts);
143-
SetupAnnealSched(*options, annealSched);
142+
SetupAnnealSched(*options, &placerOpts->anneal_sched);
144143
SetupRouterOpts(*options, routerOpts);
145144
SetupAnalysisOpts(*options, *analysisOpts);
146145
SetupPowerOpts(*options, powerOpts, arch);
@@ -395,7 +394,7 @@ static void SetupSwitches(const t_arch& Arch,
395394
device_ctx.delayless_switch_idx = RoutingArch->delayless_switch;
396395

397396
//Warn about non-zero Cout values for the ipin switch, since these values have no effect.
398-
//VPR do not model the R/C's of block internal routing connectsion.
397+
//VPR do not model the R/C's of block internal routing connection.
399398
//
400399
//Note that we don't warn about the R value as it may be used to size the buffer (if buf_size_type is AUTO)
401400
if (device_ctx.arch_switch_inf[RoutingArch->wire_to_arch_ipin_switch].Cout != 0.) {
@@ -531,31 +530,6 @@ static void SetupAnnealSched(const t_options& Options,
531530
VPR_FATAL_ERROR(VPR_ERROR_OTHER, "inner_num must be greater than 0.\n");
532531
}
533532

534-
AnnealSched->alpha_min = Options.PlaceAlphaMin;
535-
if (AnnealSched->alpha_min >= 1 || AnnealSched->alpha_min <= 0) {
536-
VPR_FATAL_ERROR(VPR_ERROR_OTHER, "alpha_min must be between 0 and 1 exclusive.\n");
537-
}
538-
539-
AnnealSched->alpha_max = Options.PlaceAlphaMax;
540-
if (AnnealSched->alpha_max >= 1 || AnnealSched->alpha_max <= AnnealSched->alpha_min) {
541-
VPR_FATAL_ERROR(VPR_ERROR_OTHER, "alpha_max must be between alpha_min and 1 exclusive.\n");
542-
}
543-
544-
AnnealSched->alpha_decay = Options.PlaceAlphaDecay;
545-
if (AnnealSched->alpha_decay >= 1 || AnnealSched->alpha_decay <= 0) {
546-
VPR_FATAL_ERROR(VPR_ERROR_OTHER, "alpha_decay must be between 0 and 1 exclusive.\n");
547-
}
548-
549-
AnnealSched->success_min = Options.PlaceSuccessMin;
550-
if (AnnealSched->success_min >= 1 || AnnealSched->success_min <= 0) {
551-
VPR_FATAL_ERROR(VPR_ERROR_OTHER, "success_min must be between 0 and 1 exclusive.\n");
552-
}
553-
554-
AnnealSched->success_target = Options.PlaceSuccessTarget;
555-
if (AnnealSched->success_target >= 1 || AnnealSched->success_target <= 0) {
556-
VPR_FATAL_ERROR(VPR_ERROR_OTHER, "success_target must be between 0 and 1 exclusive.\n");
557-
}
558-
559533
AnnealSched->type = Options.anneal_sched_type;
560534
}
561535

@@ -600,7 +574,6 @@ void SetupPackerOpts(const t_options& Options,
600574
//TODO: document?
601575
PackerOpts->inter_cluster_net_delay = 1.0; /* DEFAULT */
602576
PackerOpts->auto_compute_inter_cluster_net_delay = true;
603-
PackerOpts->packer_algorithm = PACK_GREEDY; /* DEFAULT */
604577

605578
PackerOpts->device_layout = Options.device_layout;
606579

@@ -782,7 +755,7 @@ static void SetupServerOpts(const t_options& Options, t_server_opts* ServerOpts)
782755
}
783756

784757
static void find_ipin_cblock_switch_index(const t_arch& Arch, int& wire_to_arch_ipin_switch, int& wire_to_arch_ipin_switch_between_dice) {
785-
for (auto cb_switch_name_index = 0; cb_switch_name_index < (int)Arch.ipin_cblock_switch_name.size(); cb_switch_name_index++) {
758+
for (int cb_switch_name_index = 0; cb_switch_name_index < (int)Arch.ipin_cblock_switch_name.size(); cb_switch_name_index++) {
786759
int ipin_cblock_switch_index = UNDEFINED;
787760
for (int iswitch = 0; iswitch < (int)Arch.switches.size(); ++iswitch) {
788761
if (Arch.switches[iswitch].name == Arch.ipin_cblock_switch_name[cb_switch_name_index]) {

‎vpr/src/base/SetupVPR.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,6 @@ void SetupVPR(const t_options* Options,
1717
t_packer_opts* PackerOpts,
1818
t_placer_opts* PlacerOpts,
1919
t_ap_opts* APOpts,
20-
t_annealing_sched* AnnealSched,
2120
t_router_opts* RouterOpts,
2221
t_analysis_opts* AnalysisOpts,
2322
t_noc_opts* NocOpts,

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