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SamuelHo10SamuelHo10
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Repaced prop and value in t_pin_to_pin_annotation with std::pair
1 parent c0bf94c commit e7b470a

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7 files changed

+71
-98
lines changed

7 files changed

+71
-98
lines changed

‎libs/libarchfpga/src/arch_util.cpp

Lines changed: 12 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -328,11 +328,7 @@ static void free_pb_type(t_pb_type* pb_type) {
328328
if (pb_type->modes[i].interconnect[j].annotations[k].output_pins) {
329329
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].output_pins);
330330
}
331-
for (int m = 0; m < pb_type->modes[i].interconnect[j].annotations[k].num_value_prop_pairs; ++m) {
332-
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value[m]);
333-
}
334-
delete[] pb_type->modes[i].interconnect[j].annotations[k].prop;
335-
delete[] pb_type->modes[i].interconnect[j].annotations[k].value;
331+
336332
}
337333
delete[] pb_type->modes[i].interconnect[j].annotations;
338334
if (pb_type->modes[i].interconnect[j].interconnect_power)
@@ -347,11 +343,7 @@ static void free_pb_type(t_pb_type* pb_type) {
347343
delete[] pb_type->modes;
348344

349345
for (int i = 0; i < pb_type->num_annotations; ++i) {
350-
for (int j = 0; j < pb_type->annotations[i].num_value_prop_pairs; ++j) {
351-
vtr::free(pb_type->annotations[i].value[j]);
352-
}
353-
delete[] pb_type->annotations[i].value;
354-
delete[] pb_type->annotations[i].prop;
346+
355347
if (pb_type->annotations[i].input_pins) {
356348
vtr::free(pb_type->annotations[i].input_pins);
357349
}
@@ -472,7 +464,7 @@ std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical
472464
void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
473465
char* new_name,
474466
t_pb_type* copy) {
475-
int i, j;
467+
int i;
476468
char* dot;
477469

478470
VTR_ASSERT(pb_type->blif_model != nullptr);
@@ -542,13 +534,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
542534
copy->annotations[i].line_num = pb_type->annotations[i].line_num;
543535
copy->annotations[i].format = pb_type->annotations[i].format;
544536
copy->annotations[i].type = pb_type->annotations[i].type;
545-
copy->annotations[i].num_value_prop_pairs = pb_type->annotations[i].num_value_prop_pairs;
546-
copy->annotations[i].prop = new int[pb_type->annotations[i].num_value_prop_pairs];
547-
copy->annotations[i].value = new char*[pb_type->annotations[i].num_value_prop_pairs];
548-
for (j = 0; j < pb_type->annotations[i].num_value_prop_pairs; j++) {
549-
copy->annotations[i].prop[j] = pb_type->annotations[i].prop[j];
550-
copy->annotations[i].value[j] = vtr::strdup(pb_type->annotations[i].value[j]);
551-
}
537+
copy->annotations[i].pairs = pb_type->annotations[i].pairs;
552538
}
553539
}
554540

@@ -557,7 +543,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
557543
char* default_name;
558544
t_port* in_port;
559545
t_port* out_port;
560-
int i, j;
546+
int i;
561547

562548
if (strcmp(lut_pb_type->name, "lut") != 0) {
563549
default_name = vtr::strdup("lut");
@@ -618,13 +604,8 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
618604
lut_pb_type->modes[0].interconnect[0].annotations[i].line_num = lut_pb_type->annotations[i].line_num;
619605
lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format;
620606
lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type;
621-
lut_pb_type->modes[0].interconnect[0].annotations[i].num_value_prop_pairs = lut_pb_type->annotations[i].num_value_prop_pairs;
622-
lut_pb_type->modes[0].interconnect[0].annotations[i].prop = new int[lut_pb_type->annotations[i].num_value_prop_pairs];
623-
lut_pb_type->modes[0].interconnect[0].annotations[i].value = new char*[lut_pb_type->annotations[i].num_value_prop_pairs];
624-
for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) {
625-
lut_pb_type->modes[0].interconnect[0].annotations[i].prop[j] = lut_pb_type->annotations[i].prop[j];
626-
lut_pb_type->modes[0].interconnect[0].annotations[i].value[j] = vtr::strdup(lut_pb_type->annotations[i].value[j]);
627-
}
607+
608+
lut_pb_type->modes[0].interconnect[0].annotations[i].pairs = lut_pb_type->annotations[i].pairs;
628609
}
629610

630611
/* Second mode, LUT */
@@ -639,11 +620,6 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
639620
lut_pb_type->modes[1].pb_type_children);
640621
/* moved annotations to child so delete old annotations */
641622
for (i = 0; i < lut_pb_type->num_annotations; i++) {
642-
for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) {
643-
vtr::free(lut_pb_type->annotations[i].value[j]);
644-
}
645-
delete[] lut_pb_type->annotations[i].value;
646-
delete[] lut_pb_type->annotations[i].prop;
647623
if (lut_pb_type->annotations[i].input_pins) {
648624
vtr::free(lut_pb_type->annotations[i].input_pins);
649625
}
@@ -1095,8 +1071,8 @@ const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_ty
10951071
const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot];
10961072
InstPort annot_in(annot->input_pins);
10971073
if (annot_in.port_name() == port->name) {
1098-
for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) {
1099-
if (annot->prop[iprop] == annot_type) {
1074+
for (size_t iprop = 0; iprop < annot->pairs.size(); ++iprop) {
1075+
if (annot->pairs[iprop].first == annot_type) {
11001076
return annot;
11011077
}
11021078
}
@@ -1114,9 +1090,9 @@ const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb
11141090
for (const auto& annot_out_str : vtr::split(annot->output_pins)) {
11151091
InstPort out_pins(annot_out_str);
11161092
if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) {
1117-
for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) {
1118-
if (annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MAX
1119-
|| annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
1093+
for (size_t iprop = 0; iprop < annot->pairs.size(); ++iprop) {
1094+
if (annot->pairs[iprop].first == E_ANNOT_PIN_TO_PIN_DELAY_MAX
1095+
|| annot->pairs[iprop].first == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
11201096
return annot;
11211097
}
11221098
}

‎libs/libarchfpga/src/echo_arch.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -419,7 +419,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
419419
pb_type->modes[i].interconnect[j].annotations[k].input_pins,
420420
pb_type->modes[i].interconnect[j].annotations[k].output_pins,
421421
pb_type->modes[i].interconnect[j].annotations[k].format,
422-
pb_type->modes[i].interconnect[j].annotations[k].value[0]);
422+
pb_type->modes[i].interconnect[j].annotations[k].pairs[0].second.c_str());
423423
}
424424
//Print power info for interconnects
425425
if (pb_type->modes[i].interconnect[j].interconnect_power) {
@@ -447,7 +447,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
447447
pb_type->annotations[k].input_pins,
448448
pb_type->annotations[k].output_pins,
449449
pb_type->annotations[k].format,
450-
pb_type->annotations[k].value[0]);
450+
pb_type->annotations[k].pairs[0].second.c_str());
451451
}
452452
}
453453
}

‎libs/libarchfpga/src/physical_types.h

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1158,6 +1158,8 @@ struct t_interconnect {
11581158

11591159
t_interconnect_power* interconnect_power = nullptr;
11601160
t_metadata_dict meta;
1161+
1162+
t_interconnect() = default;
11611163
};
11621164

11631165
/** Describes I/O and clock ports
@@ -1247,10 +1249,9 @@ struct t_mode_power {
12471249
* output_pins: output pins as string affected by annotation
12481250
* clock_pin: clock as string affected by annotation
12491251
*/
1250-
struct t_pin_to_pin_annotation {
1251-
char** value; /* [0..num_value_prop_pairs - 1] */
1252-
int* prop; /* [0..num_value_prop_pairs - 1] */
1253-
int num_value_prop_pairs;
1252+
struct t_pin_to_pin_annotation{
1253+
1254+
std::vector<std::pair<int, std::string>> pairs;
12541255

12551256
enum e_pin_to_pin_annotation_type type;
12561257
enum e_pin_to_pin_annotation_format format;
@@ -1260,6 +1261,8 @@ struct t_pin_to_pin_annotation {
12601261
char* clock;
12611262

12621263
int line_num; /* used to report what line number this annotation is found in architecture file */
1264+
1265+
t_pin_to_pin_annotation() = default;
12631266
};
12641267

12651268
/*************************************************************************************************

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -243,16 +243,12 @@ static bool block_port_exists(t_pb_type* pb_type, std::string port_name) {
243243
static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) {
244244
t_pin_to_pin_annotation pp;
245245

246-
pp.prop = new int();
247-
pp.value = new char*();
248-
249246
pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
250247
pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT;
251-
pp.prop[0] = (int)E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME;
252-
pp.value[0] = vtr::strdup(pp_name.c_str());
248+
pp.pairs.push_back(std::make_pair(E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name));
253249
pp.input_pins = vtr::strdup(input.c_str());
254250
pp.output_pins = vtr::strdup(output.c_str());
255-
pp.num_value_prop_pairs = 1;
251+
256252
pp.clock = nullptr;
257253

258254
return pp;

‎libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 23 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -882,9 +882,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
882882
i = 1;
883883
}
884884

885-
annotation->num_value_prop_pairs = i;
886-
annotation->prop = new int[i]();
887-
annotation->value = new char*[i]();
885+
annotation->pairs.resize(i);
888886
annotation->line_num = loc_data.line(Parent);
889887
/* Todo: This is slow, I should use a case lookup */
890888
i = 0;
@@ -893,14 +891,14 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
893891
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
894892
Prop = get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
895893
if (Prop) {
896-
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MAX;
897-
annotation->value[i] = vtr::strdup(Prop);
894+
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MAX;
895+
annotation->pairs[i].second = Prop;
898896
i++;
899897
}
900898
Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
901899
if (Prop) {
902-
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MIN;
903-
annotation->value[i] = vtr::strdup(Prop);
900+
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MIN;
901+
annotation->pairs[i].second = Prop;
904902
i++;
905903
}
906904
Prop = get_attribute(Parent, "in_port", loc_data).value();
@@ -913,13 +911,13 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
913911
annotation->type = E_ANNOT_PIN_TO_PIN_DELAY;
914912
annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX;
915913
Prop = get_attribute(Parent, "type", loc_data).value();
916-
annotation->value[i] = vtr::strdup(Parent.child_value());
914+
annotation->pairs[i].second = Parent.child_value();
917915

918916
if (0 == strcmp(Prop, "max")) {
919-
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MAX;
917+
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MAX;
920918
} else {
921919
VTR_ASSERT(0 == strcmp(Prop, "min"));
922-
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MIN;
920+
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MIN;
923921
}
924922

925923
i++;
@@ -933,8 +931,8 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
933931
annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE;
934932
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
935933
Prop = get_attribute(Parent, "C", loc_data).value();
936-
annotation->value[i] = vtr::strdup(Prop);
937-
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_CAPACITANCE_C;
934+
annotation->pairs[i].second = Prop;
935+
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_CAPACITANCE_C;
938936
i++;
939937

940938
Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
@@ -947,8 +945,8 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
947945
} else if (0 == strcmp(Parent.name(), "C_matrix")) {
948946
annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE;
949947
annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX;
950-
annotation->value[i] = vtr::strdup(Parent.child_value());
951-
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_CAPACITANCE_C;
948+
annotation->pairs[i].second = Parent.child_value();
949+
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_CAPACITANCE_C;
952950
i++;
953951

954952
Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
@@ -962,8 +960,8 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
962960
annotation->type = E_ANNOT_PIN_TO_PIN_DELAY;
963961
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
964962
Prop = get_attribute(Parent, "value", loc_data).value();
965-
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_TSETUP;
966-
annotation->value[i] = vtr::strdup(Prop);
963+
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_TSETUP;
964+
annotation->pairs[i].second = Prop;
967965

968966
i++;
969967
Prop = get_attribute(Parent, "port", loc_data).value();
@@ -981,15 +979,15 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
981979

982980
bool found_min_max_attrib = false;
983981
if (Prop) {
984-
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX;
985-
annotation->value[i] = vtr::strdup(Prop);
982+
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX;
983+
annotation->pairs[i].second = Prop;
986984
i++;
987985
found_min_max_attrib = true;
988986
}
989987
Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
990988
if (Prop) {
991-
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN;
992-
annotation->value[i] = vtr::strdup(Prop);
989+
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN;
990+
annotation->pairs[i].second = Prop;
993991
i++;
994992
found_min_max_attrib = true;
995993
}
@@ -1012,8 +1010,8 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
10121010
annotation->type = E_ANNOT_PIN_TO_PIN_DELAY;
10131011
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
10141012
Prop = get_attribute(Parent, "value", loc_data).value();
1015-
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_THOLD;
1016-
annotation->value[i] = vtr::strdup(Prop);
1013+
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_THOLD;
1014+
annotation->pairs[i].second = Prop;
10171015
i++;
10181016

10191017
Prop = get_attribute(Parent, "port", loc_data).value();
@@ -1028,8 +1026,8 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
10281026
annotation->type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
10291027
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
10301028
Prop = get_attribute(Parent, "name", loc_data).value();
1031-
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME;
1032-
annotation->value[i] = vtr::strdup(Prop);
1029+
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME;
1030+
annotation->pairs[i].second = Prop;
10331031
i++;
10341032

10351033
Prop = get_attribute(Parent, "in_port", loc_data).value();
@@ -1043,7 +1041,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
10431041
"Unknown port type %s in %s in %s", Parent.name(),
10441042
Parent.parent().name(), Parent.parent().parent().name());
10451043
}
1046-
VTR_ASSERT(i == annotation->num_value_prop_pairs);
1044+
VTR_ASSERT(i == static_cast<int>(annotation->pairs.size()));
10471045
}
10481046

10491047
static void ProcessPb_TypePowerPinToggle(pugi::xml_node parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data) {

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