[vpr] add a new option to enable perimeter cbx and cby

Author: tangxifan

libs/libarchfpga/src/physical_types.h

@@ -2009,6 +2009,7 @@ struct t_arch {
 
     /* Xifan Tang: options for tileable routing architectures */
     bool tileable;
+    bool perimeter_cb;
     bool shrink_boundary;
     bool through_channel;
     bool opin2all_sides;

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -2535,6 +2535,7 @@ static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiuti
     //expect_only_attributes(layout_tag, {}, loc_data);
 
     arch->tileable = get_attribute(layout_tag, "tileable", loc_data, ReqOpt::OPTIONAL).as_bool(false);
+    arch->perimeter_cb = get_attribute(layout_tag, "perimeter_cb", loc_data, ReqOpt::OPTIONAL).as_bool(false);
     arch->shrink_boundary = get_attribute(layout_tag, "shrink_boundary", loc_data, ReqOpt::OPTIONAL).as_bool(false);
     arch->through_channel = get_attribute(layout_tag, "through_channel", loc_data, ReqOpt::OPTIONAL).as_bool(false);
     arch->opin2all_sides = get_attribute(layout_tag, "opin2all_sides", loc_data, ReqOpt::OPTIONAL).as_bool(false);
@@ -4903,4 +4904,4 @@ static T* get_type_by_name(const char* type_name, std::vector<T>& types) {
 
     archfpga_throw(__FILE__, __LINE__,
                    "Could not find type: %s\n", type_name);
-}
+}

vpr/src/base/SetupVPR.cpp

@@ -423,6 +423,7 @@ static void SetupRoutingArch(const t_arch& Arch,
 
     /* Copy the tileable routing setting */
     RoutingArch->tileable = Arch.tileable;
+    RoutingArch->perimeter_cb = Arch.perimeter_cb;
     RoutingArch->shrink_boundary = Arch.shrink_boundary;
     RoutingArch->through_channel = Arch.through_channel;
     RoutingArch->opin2all_sides = Arch.opin2all_sides;

vpr/src/base/vpr_types.h

@@ -1576,6 +1576,7 @@ struct t_det_routing_arch {
 
     /* Xifan Tang: tileable routing */
     bool tileable;
+    bool perimeter_cb;
     bool shrink_boundary;
     bool through_channel;
     bool opin2all_sides;

vpr/src/route/rr_graph.cpp

@@ -721,6 +721,7 @@ void create_rr_graph(const t_graph_type graph_type,
                                                directs, num_directs,
                                                &det_routing_arch->wire_to_rr_ipin_switch,
                                                det_routing_arch->shrink_boundary,                                  /* Shrink to the smallest boundary, no routing wires for empty zone */
+                                               det_routing_arch->perimeter_cb,                                  /* Now I/O or any programmable blocks on perimeter can have full cb access (both cbx and cby) */
                                                router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */
                                                det_routing_arch->opin2all_sides,                                   /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */
                                                det_routing_arch->concat_wire,                                      /* Allow end-point tracks to be wired to a starting point track on the opposite in a switch block. It means a wire can be continued in the same direction to another wire */