Merge branch 'master' of github.com:RapidSilicon/vtr-verilog-to-routing into api_set_node_x_num

Author: Muhammad Haris Zafar

vpr/src/device/rr_graph_builder.h

@@ -84,6 +84,12 @@ class RRGraphBuilder {
     inline void set_node_ptc_num(RRNodeId id, short new_ptc_num) {
         node_storage_.set_node_ptc_num(id, new_ptc_num);
     }
+
+    /** @brief Set the node direction; The node direction is only available of routing channel nodes, such as x-direction routing tracks (CHANX) and y-direction routing tracks (CHANY). For other nodes types, this value is not meaningful and should be set to NONE. */
+    inline void set_node_direction(RRNodeId id, Direction new_direction) {
+        node_storage_.set_node_direction(id, new_direction);
+    }
+
     /* -- Internal data storage -- */
   private:
     /* TODO: When the refactoring effort finishes, 

vpr/src/draw/draw.cpp

@@ -2255,6 +2255,7 @@ static void draw_rr_pin(int inode, const ezgl::color& color, ezgl::renderer* g)
     float xcen, ycen;
     char str[vtr::bufsize];
     auto& device_ctx = g_vpr_ctx.device();
+    const auto& rr_graph = device_ctx.rr_graph;
 
     int ipin = device_ctx.rr_nodes[inode].ptc_num();
 
@@ -2265,7 +2266,7 @@ static void draw_rr_pin(int inode, const ezgl::color& color, ezgl::renderer* g)
      * - draw the pin on each side that it appears
      */
     for (const e_side& pin_side : SIDES) {
-        if (!device_ctx.rr_nodes[inode].is_node_on_specific_side(pin_side)) {
+        if (!rr_graph.is_node_on_specific_side(RRNodeId(inode), pin_side)) {
             continue;
         }
         draw_get_rr_pin_coords(inode, &xcen, &ycen, pin_side);
@@ -3185,7 +3186,7 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
      */
     std::vector<e_side> pin_candidate_sides;
     for (const e_side& pin_candidate_side : SIDES) {
-        if ((pin_rr.is_node_on_specific_side(pin_candidate_side))
+        if ((rr_graph.is_node_on_specific_side(pin_rr.id(), pin_candidate_side))
             && (grid_type->pinloc[grid_tile.width_offset][grid_tile.height_offset][pin_candidate_side][pin_rr.pin_num()])) {
             pin_candidate_sides.push_back(pin_candidate_side);
         }
@@ -3312,7 +3313,7 @@ static void draw_pin_to_pin(int opin_node, int ipin_node, ezgl::renderer* g) {
     float x1 = 0, y1 = 0;
     std::vector<e_side> opin_candidate_sides;
     for (const e_side& opin_candidate_side : SIDES) {
-        if (device_ctx.rr_nodes[opin_node].is_node_on_specific_side(opin_candidate_side)) {
+        if (rr_graph.is_node_on_specific_side(RRNodeId(opin_node), opin_candidate_side)) {
             opin_candidate_sides.push_back(opin_candidate_side);
         }
     }
@@ -3322,7 +3323,7 @@ static void draw_pin_to_pin(int opin_node, int ipin_node, ezgl::renderer* g) {
     float x2 = 0, y2 = 0;
     std::vector<e_side> ipin_candidate_sides;
     for (const e_side& ipin_candidate_side : SIDES) {
-        if (device_ctx.rr_nodes[ipin_node].is_node_on_specific_side(ipin_candidate_side)) {
+        if (rr_graph.is_node_on_specific_side(RRNodeId(ipin_node), ipin_candidate_side)) {
             ipin_candidate_sides.push_back(ipin_candidate_side);
         }
     }
@@ -3338,12 +3339,12 @@ static void draw_pin_to_pin(int opin_node, int ipin_node, ezgl::renderer* g) {
 
 static void draw_pin_to_sink(int ipin_node, int sink_node, ezgl::renderer* g) {
     auto& device_ctx = g_vpr_ctx.device();
+    const auto& rr_graph = device_ctx.rr_graph;
 
     float x1 = 0, y1 = 0;
     /* Draw the line for each ipin on different sides */
     for (const e_side& pin_side : SIDES) {
-        if (!device_ctx.rr_nodes[ipin_node].is_node_on_specific_side(
-                pin_side)) {
+        if (!rr_graph.is_node_on_specific_side(RRNodeId(ipin_node), pin_side)) {
             continue;
         }
 
@@ -3362,14 +3363,14 @@ static void draw_pin_to_sink(int ipin_node, int sink_node, ezgl::renderer* g) {
 
 static void draw_source_to_pin(int source_node, int opin_node, ezgl::renderer* g) {
     auto& device_ctx = g_vpr_ctx.device();
+    const auto& rr_graph = device_ctx.rr_graph;
 
     float x1 = 0, y1 = 0;
     draw_get_rr_src_sink_coords(device_ctx.rr_nodes[source_node], &x1, &y1);
 
     /* Draw the line for each ipin on different sides */
     for (const e_side& pin_side : SIDES) {
-        if (!device_ctx.rr_nodes[opin_node].is_node_on_specific_side(
-                pin_side)) {
+        if (!rr_graph.is_node_on_specific_side(RRNodeId(opin_node), pin_side)) {
             continue;
         }
 

vpr/src/route/check_rr_graph.cpp

@@ -240,7 +240,7 @@ void check_rr_graph(const t_graph_type graph_type,
                             std::string pin_name = block_type_pin_index_to_name(block_type, node.pin_num());
                             /* Print error messages for all the sides that a node may appear */
                             for (const e_side& node_side : SIDES) {
-                                if (!node.is_node_on_specific_side(node_side)) {
+                                if (!rr_graph.is_node_on_specific_side(RRNodeId(rr_node), node_side)) {
                                     continue;
                                 }
                                 VTR_LOG_ERROR("in check_rr_graph: node %d (%s) at (%d,%d) block=%s side=%s pin=%s has no fanin.\n",
@@ -591,10 +591,10 @@ static bool has_adjacent_channel(const t_rr_node& node, const DeviceGrid& grid)
     const auto& rr_graph = g_vpr_ctx.device().rr_graph;
     VTR_ASSERT(rr_graph.node_type(node.id()) == IPIN || rr_graph.node_type(node.id()) == OPIN);
 
-    if ((rr_graph.node_xlow(node.id()) == 0 && !node.is_node_on_specific_side(RIGHT))                          //left device edge connects only along block's right side
-        || (rr_graph.node_ylow(node.id()) == int(grid.height() - 1) && !node.is_node_on_specific_side(BOTTOM)) //top device edge connects only along block's bottom side
-        || (rr_graph.node_xlow(node.id()) == int(grid.width() - 1) && !node.is_node_on_specific_side(LEFT))    //right deivce edge connects only along block's left side
-        || (rr_graph.node_ylow(node.id()) == 0 && !node.is_node_on_specific_side(TOP))                         //bottom deivce edge connects only along block's top side
+    if ((rr_graph.node_xlow(node.id()) == 0 && !rr_graph.is_node_on_specific_side(node.id(), RIGHT))                          //left device edge connects only along block's right side
+        || (rr_graph.node_ylow(node.id()) == int(grid.height() - 1) && !rr_graph.is_node_on_specific_side(node.id(), BOTTOM)) //top device edge connects only along block's bottom side
+        || (rr_graph.node_xlow(node.id()) == int(grid.width() - 1) && !rr_graph.is_node_on_specific_side(node.id(), LEFT))    //right deivce edge connects only along block's left side
+        || (rr_graph.node_ylow(node.id()) == 0 && !rr_graph.is_node_on_specific_side(node.id(), TOP))                         //bottom deivce edge connects only along block's top side
     ) {
         return false;
     }

vpr/src/route/clock_network_builders.cpp

@@ -325,7 +325,7 @@ int ClockRib::create_chanx_wire(int x_start,
     rr_graph_builder.set_node_track_num(chanx_node, ptc_num);
     node.set_rc_index(find_create_rr_rc_data(
         x_chan_wire.layer.r_metal, x_chan_wire.layer.c_metal));
-    node.set_direction(direction);
+    rr_graph_builder.set_node_direction(chanx_node, direction);
 
     short seg_index = 0;
     switch (direction) {
@@ -631,7 +631,7 @@ int ClockSpine::create_chany_wire(int y_start,
     rr_graph_builder.set_node_track_num(chany_node, ptc_num);
     node.set_rc_index(find_create_rr_rc_data(
         y_chan_wire.layer.r_metal, y_chan_wire.layer.c_metal));
-    node.set_direction(direction);
+    rr_graph_builder.set_node_direction(chany_node, direction);
 
     short seg_index = 0;
     switch (direction) {

vpr/src/route/router_lookahead_map.cpp

@@ -1005,10 +1005,9 @@ static void adjust_rr_pin_position(const RRNodeId rr, int& x, int& y) {
      * Similarly for blocks at (*,0) we clip the minimum y to zero.
      */
     auto& device_ctx = g_vpr_ctx.device();
-    const auto& temp_rr_graph = device_ctx.rr_graph; //TODO rename to rr_graph once the rr_graph below is unneeded
-    auto& rr_graph = device_ctx.rr_nodes;
+    auto& rr_graph = device_ctx.rr_graph;
 
-    VTR_ASSERT_SAFE(is_pin(temp_rr_graph.node_type(rr)));
+    VTR_ASSERT_SAFE(is_pin(rr_graph.node_type(rr)));
     VTR_ASSERT_SAFE(rr_graph.node_xlow(rr) == rr_graph.node_xhigh(rr));
     VTR_ASSERT_SAFE(rr_graph.node_ylow(rr) == rr_graph.node_yhigh(rr));