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[vpr][rr_graph] add new switch types when rr graph is read and run-flat is enabled
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‎vpr/src/route/rr_graph.cpp

Lines changed: 43 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -271,7 +271,8 @@ static void connect_src_sink_to_pins(RRGraphBuilder& rr_graph_builder,
271271
const int j,
272272
t_rr_edge_info_set& rr_edges_to_create,
273273
const int delayless_switch,
274-
t_physical_tile_type_ptr physical_type_ptr);
274+
t_physical_tile_type_ptr physical_type_ptr,
275+
bool is_remapped);
275276

276277
static void alloc_and_load_tile_rr_graph(RRGraphBuilder& rr_graph_builder,
277278
std::map<int, t_arch_switch_inf>& arch_sw_inf_map,
@@ -374,6 +375,8 @@ static void add_pb_edges(RRGraphBuilder& rr_graph_builder,
374375
t_logical_block_type_ptr logical_block,
375376
const t_pb* pb,
376377
const t_cluster_pin_chain& nodes_to_collapse,
378+
float R_minW_nmos,
379+
float R_minW_pmos,
377380
int rel_cap,
378381
int layer,
379382
int i,
@@ -741,6 +744,20 @@ void create_rr_graph(const t_graph_type graph_type,
741744
}
742745

743746
if (is_flat) {
747+
short delayless_switch = OPEN;
748+
if (load_rr_graph) {
749+
const auto& rr_switches = device_ctx.rr_graph.rr_switch();
750+
for (int switch_id = 0; switch_id < rr_switches.size(); switch_id++){
751+
const auto& rr_switch = rr_switches[RRSwitchId(switch_id)];
752+
if (rr_switch.name.find("delayless") != std::string::npos) {
753+
delayless_switch = static_cast<short>(switch_id);
754+
break;
755+
}
756+
}
757+
} else {
758+
delayless_switch = det_routing_arch->delayless_switch;
759+
}
760+
VTR_ASSERT(delayless_switch != OPEN);
744761
build_intra_cluster_rr_graph(graph_type,
745762
grid,
746763
block_types,
@@ -2021,6 +2038,9 @@ static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(RRGraphBuilder
20212038
/* If Fc gets clipped, this will be flagged to true */
20222039
*Fc_clipped = false;
20232040

2041+
/* This function is called to build the general routing graph resoruces. Thus, the edges are not remapped yet.*/
2042+
bool is_remapped = false;
2043+
20242044
int num_edges = 0;
20252045
/* Connection SINKS and SOURCES to their pins - Initializing IPINs/OPINs. */
20262046
for (int layer = 0; layer < grid.get_num_layers(); ++layer) {
@@ -2053,7 +2073,8 @@ static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(RRGraphBuilder
20532073
j,
20542074
rr_edges_to_create,
20552075
delayless_switch,
2056-
physical_tile);
2076+
physical_tile,
2077+
is_remapped);
20572078

20582079
//Create the actual SOURCE->OPIN, IPIN->SINK edges
20592080
uniquify_edges(rr_edges_to_create);
@@ -2270,7 +2291,8 @@ static void alloc_and_load_intra_cluster_rr_graph(RRGraphBuilder& rr_graph_build
22702291
j,
22712292
rr_edges_to_create,
22722293
delayless_switch,
2273-
physical_tile);
2294+
physical_tile,
2295+
load_rr_graph);
22742296

22752297
//Create the actual SOURCE->OPIN, IPIN->SINK edges
22762298
uniquify_edges(rr_edges_to_create);
@@ -2454,7 +2476,8 @@ static void connect_src_sink_to_pins(RRGraphBuilder& rr_graph_builder,
24542476
const int j,
24552477
t_rr_edge_info_set& rr_edges_to_create,
24562478
const int delayless_switch,
2457-
t_physical_tile_type_ptr physical_type_ptr) {
2479+
t_physical_tile_type_ptr physical_type_ptr,
2480+
bool is_remapped) {
24582481
for (auto class_num : class_num_vec) {
24592482
const auto& pin_list = get_pin_list_from_class_physical_num(physical_type_ptr, class_num);
24602483
auto class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num);
@@ -2474,11 +2497,11 @@ static void connect_src_sink_to_pins(RRGraphBuilder& rr_graph_builder,
24742497
auto pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num);
24752498
if (class_type == DRIVER) {
24762499
VTR_ASSERT(pin_type == DRIVER);
2477-
rr_edges_to_create.emplace_back(class_rr_node_id, pin_rr_node_id, delayless_switch, false);
2500+
rr_edges_to_create.emplace_back(class_rr_node_id, pin_rr_node_id, delayless_switch, is_remapped);
24782501
} else {
24792502
VTR_ASSERT(class_type == RECEIVER);
24802503
VTR_ASSERT(pin_type == RECEIVER);
2481-
rr_edges_to_create.emplace_back(pin_rr_node_id, class_rr_node_id, delayless_switch, false);
2504+
rr_edges_to_create.emplace_back(pin_rr_node_id, class_rr_node_id, delayless_switch, is_remapped);
24822505
}
24832506
}
24842507
}
@@ -2682,6 +2705,8 @@ static void build_cluster_internal_edges(RRGraphBuilder& rr_graph_builder,
26822705
logical_block,
26832706
pb,
26842707
nodes_to_collapse,
2708+
R_minW_nmos,
2709+
R_minW_pmos,
26852710
rel_cap,
26862711
layer,
26872712
i,
@@ -2714,6 +2739,8 @@ static void add_pb_edges(RRGraphBuilder& rr_graph_builder,
27142739
t_logical_block_type_ptr logical_block,
27152740
const t_pb* pb,
27162741
const t_cluster_pin_chain& nodes_to_collapse,
2742+
float R_minW_nmos,
2743+
float R_minW_pmos,
27172744
int rel_cap,
27182745
int layer,
27192746
int i,
@@ -2773,23 +2800,15 @@ static void add_pb_edges(RRGraphBuilder& rr_graph_builder,
27732800
conn_pin_physical_num);
27742801

27752802
if (is_remapped) {
2776-
bool found = false;
2803+
auto& all_sw_inf = g_vpr_ctx.mutable_device().all_sw_inf;
27772804
float delay = g_vpr_ctx.device().all_sw_inf.at(sw_idx).Tdel();
2778-
const auto& rr_switches = rr_graph_builder.rr_switch();
2779-
for (int sw_id = 0; sw_id < (int)rr_switches.size(); sw_id++) {
2780-
const auto& rr_switch = rr_switches[RRSwitchId(sw_id)];
2781-
if (rr_switch.intra_tile) {
2782-
if (rr_switch.Tdel == delay) {
2783-
sw_idx = sw_id;
2784-
found = true;
2785-
break;
2786-
}
2787-
}
2788-
}
2789-
// If the graph is loaded from a file, we expect that all sw types are already listed there since currently, we are not doing any further
2790-
// Optimization. If the optimization done when the rr graph file was generated is different from the current optimization, in the case that
2791-
// these optimizations create different RR switches, this VTR ASSERT can be removed.
2792-
VTR_ASSERT(found);
2805+
bool is_new_sw;
2806+
std::tie(is_new_sw, sw_idx) = find_create_intra_cluster_sw(rr_graph_builder,
2807+
all_sw_inf,
2808+
R_minW_nmos,
2809+
R_minW_pmos,
2810+
is_remapped,
2811+
delay);
27932812
}
27942813
rr_edges_to_create.emplace_back(parent_pin_node_id, conn_pin_node_id, sw_idx, is_remapped);
27952814
}
@@ -2960,19 +2979,10 @@ static void add_chain_node_fan_in_edges(RRGraphBuilder& rr_graph_builder,
29602979
is_rr_sw_id,
29612980
delay);
29622981

2963-
if (!is_rr_sw_id && is_new_sw) {
2964-
// Currently we assume that if rr graph is read from a file, we shouldn't get into this block
2965-
VTR_ASSERT(!load_rr_graph);
2966-
// The internal edges are added after switch_fanin_remap is initialized; thus, if a new arch_sw is added,
2967-
// switch _fanin_remap should be updated.
2968-
t_rr_switch_inf rr_sw_inf = create_rr_switch_from_arch_switch(create_internal_arch_sw(delay),
2969-
R_minW_nmos,
2970-
R_minW_pmos);
2971-
auto rr_sw_id = rr_graph_builder.add_rr_switch(rr_sw_inf);
2972-
// If rr graph is loaded from a file, switch_fanin_remap is going to be empty
2982+
if (is_new_sw) {
29732983
if (!load_rr_graph) {
29742984
auto& switch_fanin_remap = g_vpr_ctx.mutable_device().switch_fanin_remap;
2975-
switch_fanin_remap.push_back({{UNDEFINED, size_t(rr_sw_id)}});
2985+
switch_fanin_remap.push_back({{UNDEFINED, size_t(sw_id)}});
29762986
}
29772987
}
29782988

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