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Commit e202d6e

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jmah76jmah76
committed
reallocs to vectors
1 parent fc15b62 commit e202d6e

13 files changed

+72847
-66
lines changed

‎libs/libarchfpga/src/arch_util.cpp

Lines changed: 1 addition & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -314,41 +314,19 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
314314
/* Free ports for pb graph node */
315315
for (i = 0; i < pb_graph_node->num_input_ports; i++) {
316316
for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) {
317-
if (pb_graph_node->input_pins[i][j].pin_timing)
318-
vtr::free(pb_graph_node->input_pins[i][j].pin_timing);
319-
if (pb_graph_node->input_pins[i][j].pin_timing_del_max)
320-
vtr::free(pb_graph_node->input_pins[i][j].pin_timing_del_max);
321-
if (pb_graph_node->input_pins[i][j].pin_timing_del_min)
322-
vtr::free(pb_graph_node->input_pins[i][j].pin_timing_del_min);
323-
// if (pb_graph_node->input_pins[i][j].input_edges)
324-
// vtr::free(pb_graph_node->input_pins[i][j].input_edges);
325-
// if (pb_graph_node->input_pins[i][j].output_edges)
326-
// vtr::free(pb_graph_node->input_pins[i][j].output_edges);
327317
if (pb_graph_node->input_pins[i][j].parent_pin_class)
328318
delete[](pb_graph_node->input_pins[i][j].parent_pin_class);
329319
}
330320
delete[] pb_graph_node->input_pins[i];
331321
}
332322
for (i = 0; i < pb_graph_node->num_output_ports; i++) {
333323
for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) {
334-
if (pb_graph_node->output_pins[i][j].pin_timing)
335-
vtr::free(pb_graph_node->output_pins[i][j].pin_timing);
336-
if (pb_graph_node->output_pins[i][j].pin_timing_del_max)
337-
vtr::free(pb_graph_node->output_pins[i][j].pin_timing_del_max);
338-
if (pb_graph_node->output_pins[i][j].pin_timing_del_min)
339-
vtr::free(pb_graph_node->output_pins[i][j].pin_timing_del_min);
340-
// if (pb_graph_node->output_pins[i][j].input_edges)
341-
// vtr::free(pb_graph_node->output_pins[i][j].input_edges);
342-
// if (pb_graph_node->output_pins[i][j].output_edges)
343-
// vtr::free(pb_graph_node->output_pins[i][j].output_edges);
344324
if (pb_graph_node->output_pins[i][j].parent_pin_class)
345325
delete[](pb_graph_node->output_pins[i][j].parent_pin_class);
346326

347327
if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs) {
348328
for (k = 0; k < pb_graph_node->pb_type->depth; k++) {
349-
if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]) {
350-
vtr::free(pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]);
351-
}
329+
delete[](pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]);
352330
}
353331
delete[](pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs);
354332
}
@@ -360,12 +338,6 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
360338
}
361339
for (i = 0; i < pb_graph_node->num_clock_ports; i++) {
362340
for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) {
363-
if (pb_graph_node->clock_pins[i][j].pin_timing)
364-
vtr::free(pb_graph_node->clock_pins[i][j].pin_timing);
365-
if (pb_graph_node->clock_pins[i][j].pin_timing_del_max)
366-
vtr::free(pb_graph_node->clock_pins[i][j].pin_timing_del_max);
367-
if (pb_graph_node->clock_pins[i][j].pin_timing_del_min)
368-
vtr::free(pb_graph_node->clock_pins[i][j].pin_timing_del_min);
369341
if (pb_graph_node->clock_pins[i][j].parent_pin_class)
370342
delete[](pb_graph_node->clock_pins[i][j].parent_pin_class);
371343
}

‎libs/libarchfpga/src/physical_types.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1256,9 +1256,9 @@ class t_pb_graph_pin {
12561256

12571257
/* combinational timing information */
12581258
int num_pin_timing = 0; /* Number of ipin to opin timing edges*/
1259-
t_pb_graph_pin** pin_timing = nullptr; /* timing edge sink pins [0..num_pin_timing-1]*/
1260-
float* pin_timing_del_max = nullptr; /* primitive ipin to opin max-delay [0..num_pin_timing-1]*/
1261-
float* pin_timing_del_min = nullptr; /* primitive ipin to opin min-delay [0..num_pin_timing-1]*/
1259+
std::vector<t_pb_graph_pin*>pin_timing; /* timing edge sink pins [0..num_pin_timing-1]*/
1260+
std::vector<float> pin_timing_del_max; /* primitive ipin to opin max-delay [0..num_pin_timing-1]*/
1261+
std::vector<float> pin_timing_del_min; /* primitive ipin to opin min-delay [0..num_pin_timing-1]*/
12621262
int num_pin_timing_del_max_annotated = 0; //The list of valid pin_timing_del_max entries runs from [0..num_pin_timing_del_max_annotated-1]
12631263
int num_pin_timing_del_min_annotated = 0; //The list of valid pin_timing_del_max entries runs from [0..num_pin_timing_del_min_annotated-1]
12641264

@@ -1333,7 +1333,7 @@ class t_pb_graph_edge {
13331333

13341334
/* pack pattern info */
13351335
int num_pack_patterns;
1336-
const char** pack_pattern_names;
1336+
std::vector<const char*> pack_pattern_names;
13371337
int* pack_pattern_indices;
13381338
bool infer_pattern;
13391339

‎packing_pin_util.rpt

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,65 @@
1+
#Packing pin usage report
2+
Type: io
3+
Input Pin Usage:
4+
Max: 1.00 (0.50)
5+
Avg: 0.70 (0.35)
6+
Min: 0.00 (0.00)
7+
Histogram:
8+
[ 0: 0.2) 52 ( 29.9%) |********************
9+
[ 0.2: 0.4) 0 ( 0.0%) |
10+
[ 0.4: 0.6) 0 ( 0.0%) |
11+
[ 0.6: 0.8) 0 ( 0.0%) |
12+
[ 0.8: 1) 122 ( 70.1%) |***********************************************
13+
[ 1: 1.2) 0 ( 0.0%) |
14+
[ 1.2: 1.4) 0 ( 0.0%) |
15+
[ 1.4: 1.6) 0 ( 0.0%) |
16+
[ 1.6: 1.8) 0 ( 0.0%) |
17+
[ 1.8: 2) 0 ( 0.0%) |
18+
Output Pin Usage:
19+
Max: 1.00 (1.00)
20+
Avg: 0.30 (0.30)
21+
Min: 0.00 (0.00)
22+
Histogram:
23+
[ 0: 0.1) 122 ( 70.1%) |***********************************************
24+
[ 0.1: 0.2) 0 ( 0.0%) |
25+
[ 0.2: 0.3) 0 ( 0.0%) |
26+
[ 0.3: 0.4) 0 ( 0.0%) |
27+
[ 0.4: 0.5) 0 ( 0.0%) |
28+
[ 0.5: 0.6) 0 ( 0.0%) |
29+
[ 0.6: 0.7) 0 ( 0.0%) |
30+
[ 0.7: 0.8) 0 ( 0.0%) |
31+
[ 0.8: 0.9) 0 ( 0.0%) |
32+
[ 0.9: 1) 52 ( 29.9%) |********************
33+
34+
Type: clb
35+
Input Pin Usage:
36+
Max: 42.00 (0.78)
37+
Avg: 21.80 (0.40)
38+
Min: 4.00 (0.07)
39+
Histogram:
40+
[ 0: 5.4) 1 ( 1.8%) |***
41+
[ 5.4: 11) 4 ( 7.3%) |************
42+
[ 11: 16) 5 ( 9.1%) |***************
43+
[ 16: 22) 16 ( 29.1%) |************************************************
44+
[ 22: 27) 16 ( 29.1%) |************************************************
45+
[ 27: 32) 11 ( 20.0%) |*********************************
46+
[ 32: 38) 1 ( 1.8%) |***
47+
[ 38: 43) 1 ( 1.8%) |***
48+
[ 43: 49) 0 ( 0.0%) |
49+
[ 49: 54) 0 ( 0.0%) |
50+
Output Pin Usage:
51+
Max: 12.00 (0.57)
52+
Avg: 7.33 (0.35)
53+
Min: 1.00 (0.05)
54+
Histogram:
55+
[ 0: 2.1) 1 ( 1.8%) |**
56+
[ 2.1: 4.2) 1 ( 1.8%) |**
57+
[ 4.2: 6.3) 15 ( 27.3%) |****************************
58+
[ 6.3: 8.4) 26 ( 47.3%) |************************************************
59+
[ 8.4: 10) 7 ( 12.7%) |*************
60+
[ 10: 13) 5 ( 9.1%) |*********
61+
[ 13: 15) 0 ( 0.0%) |
62+
[ 15: 17) 0 ( 0.0%) |
63+
[ 17: 19) 0 ( 0.0%) |
64+
[ 19: 21) 0 ( 0.0%) |
65+

‎pre_pack.report_timing.setup.rpt

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
#Timing report of worst 0 path(s)
2+
# Unit scale: 1e-09 seconds
3+
# Output precision: 3
4+
5+
#End of timing report

‎report_timing.hold.rpt

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
#Timing report of worst 0 path(s)
2+
# Unit scale: 1e-09 seconds
3+
# Output precision: 3
4+
5+
#End of timing report

‎report_timing.setup.rpt

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
#Timing report of worst 0 path(s)
2+
# Unit scale: 1e-09 seconds
3+
# Output precision: 3
4+
5+
#End of timing report

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