[test] update strong_odin

Author: amin1377

vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt

@@ -1,2 +1,2 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- k6_N10_mem32K_40nm_fc_abs.xml	  stereovision3.v	  common	  4.21	  vpr	  61.17 MiB	  	  0.09	  9948	  -1	  -1	  4	  0.21	  -1	  -1	  33240	  -1	  -1	  19	  11	  0	  0	  success	  v8.0.0-6793-gb52911b9f	  release IPO VTR_ASSERT_LEVEL=2	  GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	  2022-11-27T15:52:14	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing	  62636	  11	  30	  262	  292	  2	  104	  60	  7	  7	  49	  clb	  auto	  22.5 MiB	  0.19	  413	  61.2 MiB	  0.08	  0.00	  2.2252	  -165.149	  -2.2252	  2.11729	  0.10	  0.000819587	  0.000729274	  0.0216996	  0.0188289	  18	  641	  44	  1.07788e+06	  1.02399e+06	  98201.7	  2004.12	  1.72	  0.229385	  0.196708	  540	  20	  851	  1896	  99645	  24454	  2.77005	  2.47124	  -197.916	  -2.77005	  0	  0	  111547.	  2276.47	  0.02	  0.06	  0.0276181	  0.0247444	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+k6_N10_mem32K_40nm_fc_abs.xml	stereovision3.v	common	39.72	vpr	371.32 MiB		4.93	141560	-1	-1	4	0.19	-1	-1	37100	-1	-1	19	11	0	0	success	6bddfe3-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-06-19T14:09:49	gh-actions-runner-vtr-auto-spawned162	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	380228	11	30	262	292	2	104	60	7	7	49	clb	auto	98.8 MiB	2.00	415	2283	332	1882	69	271.0 MiB	0.74	0.03	2.44263	-182.728	-2.44263	2.32857	1.56	0.00603705	0.00530478	0.147109	0.124499	26	488	20	1.07788e+06	1.02399e+06	114650.	2339.80	13.60	1.99053	1.75425	2856	27158	-1	469	20	710	1720	65018	15535	2.43392	2.28763	-181.244	-2.43392	0	0	128849.	2629.56	0.22	1.02	0.86	-1	-1	0.22	0.270374	0.241053	

vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt

@@ -1,2 +1,2 @@
 arch	circuit	script_params	crit_path_delay_mcw	clk_to_clk_cpd	clk_to_clk2_cpd	clk_to_input_cpd	clk_to_output_cpd	clk2_to_clk2_cpd	clk2_to_clk_cpd	clk2_to_input_cpd	clk2_to_output_cpd	input_to_input_cpd	input_to_clk_cpd	input_to_clk2_cpd	input_to_output_cpd	output_to_output_cpd	output_to_clk_cpd	output_to_clk2_cpd	output_to_input_cpd	clk_to_clk_setup_slack	clk_to_clk2_setup_slack	clk_to_input_setup_slack	clk_to_output_setup_slack	clk2_to_clk2_setup_slack	clk2_to_clk_setup_slack	clk2_to_input_setup_slack	clk2_to_output_setup_slack	input_to_input_setup_slack	input_to_clk_setup_slack	input_to_clk2_setup_slack	input_to_output_setup_slack	output_to_output_setup_slack	output_to_clk_setup_slack	output_to_clk2_setup_slack	output_to_input_setup_slack	clk_to_clk_hold_slack	clk_to_clk2_hold_slack	clk_to_input_hold_slack	clk_to_output_hold_slack	clk2_to_clk2_hold_slack	clk2_to_clk_hold_slack	clk2_to_input_hold_slack	clk2_to_output_hold_slack	input_to_input_hold_slack	input_to_clk_hold_slack	input_to_clk2_hold_slack	input_to_output_hold_slack	output_to_output_hold_slack	output_to_clk_hold_slack	output_to_clk2_hold_slack	output_to_input_hold_slack	
-k6_frac_N10_mem32K_40nm.xml	multiclock.blif	common	1.31564	0.595	0.841581	-1	-1	0.57	0.814813	-1	1.31564	-1	1.07053	-1	1.76203	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0.243	1.71958	-1	-1	0.268	3.24281	-1	1.16427	-1	3.30853	-1	-1.48434	-1	-1	-1	-1	
+k6_frac_N10_mem32K_40nm.xml	multiclock.blif	common	1.59823	0.595	0.841581	-1	-1	0.57	0.814813	-1	1.59823	-1	1.07141	-1	1.38001	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0.243	1.71958	-1	-1	0.268	3.24281	-1	1.44686	-1	3.30941	-1	-1.86636	-1	-1	-1	-1	

vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/config.txt

@@ -44,4 +44,4 @@ qor_parse_file=qor_standard.txt
 pass_requirements_file=pass_requirements.txt
 
 #Script parameters
-script_params=-track_memory_usage -check_equivalent -starting_stage abc --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --seed 2
+script_params=-track_memory_usage -check_equivalent -starting_stage abc --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --seed 5