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Merge pull request #2081 from sdamghan/include_dir_scripts
Support "include" feature for the Yosys frontend in run vtr flow scripts
2 parents 9246ff8 + f7065ee commit e0525c5

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‎.github/workflows/test.yml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -155,7 +155,7 @@ jobs:
155155
include: [
156156
{
157157
name: 'Basic',
158-
params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on',
158+
params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DODIN_USE_YOSYS=ON',
159159
suite: 'vtr_reg_basic'
160160
},
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{

‎.gitignore

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@@ -100,6 +100,11 @@ ODIN_II/usefull_tools/**/track_completed
100100
*.o
101101
*.a
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103+
#
104+
#Yosys exec dir
105+
#
106+
Yosys
107+
103108
#
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#Python
105110
#

‎doc/src/vtr/tasks.rst

Lines changed: 7 additions & 5 deletions
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@@ -144,15 +144,17 @@ Optional Fields
144144

145145
Absolute path or relative to ``$VTR_ROOT/vtr_flow/``.
146146

147-
Note: Multiple _includes_dir_ are NOT allowed in a task config file.
147+
Note: Multiple `includes_dir` are NOT allowed in a task config file.
148148

149-
* **include_list_add**: A path to an _include_ file, which is relative to _includes_dir_
149+
* **include_list_add**: A path to an `include` file, which is relative to `includes_dir`
150150

151-
Multiple _include_list_add_ can be provided.
151+
Multiple `include_list_add` can be provided.
152152

153-
_include_ files could act as the top module complementary, like definitions, macros or sub-modules.
153+
`include` files could act as the top module complementary, like definitions, memory initialization files, macros or sub-modules.
154+
155+
Note: Only `include` files, written in supported HDLs by each frontend, are synthesized. The others are only copied to the destination folder.
154156

155-
Note: _include_ files will be shared among all benchmark circuits in the task config file.
157+
Note: `include` files will be shared among all benchmark circuits in the task config file.
156158

157159
* **pass_requirements_file**: :ref:`vtr_pass_requirements` file.
158160

‎doc/src/yosys/dev_guide.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,8 @@ How to add new changes?
3232
-----------------------
3333

3434
The Yosys synthesis commands, including the generic synthesis and additional VTR specific configurations, are provided
35-
in `synthesis.ys <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.ys>`_. To make changes in the overall Yosys synthesis flow, the `synthesis.ys <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.ys>`_
36-
script is perhaps the first file developers may require to change.
35+
in `synthesis.tcl <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.tcl>`_. To make changes in the overall Yosys synthesis flow, the `synthesis.tcl <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.tcl>`_
36+
script is perhaps the first file developers may be required to change.
3737

3838
Moreover, the `yosys_models.v <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/yosys_models.v>`_ file includes the required definitions for Yosys to how it should infer implicit
3939
memories and instantiate arithmetic operations, such as addition, subtraction, and multiplication. Therefore, to alter these

‎doc/src/yosys/structure.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ Structure of Yosys Synthesis Files and the Yosys External Library Library
1818
│ ├── multiply.v
1919
│ ├── single_port_ram.v
2020
│ ├── spram_rename.v
21-
│ ├── synthesis.ys
21+
│ ├── synthesis.tcl
2222
│ └── yosys_models.v
2323
└── libs
2424
└── EXTERNAL

‎libs/EXTERNAL/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -18,6 +18,20 @@ endif()
1818
# Yosys is compiled only if the user ask for it
1919
if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS})
2020
add_subdirectory(libyosys)
21+
22+
# In addition to libyosys in the build folder, we copy the libyosys directory
23+
# into a temporary folder in the VTR root, name Yosys, to have access to Yosys
24+
# execs for using in VTR scripts (similar to VPR/vpr or ODIN_II/odin_II)
25+
add_custom_target(vtr-yosys ALL
26+
DEPENDS yosys
27+
COMMAND ${CMAKE_COMMAND} -E
28+
remove_directory ${VTR_SOURCE_DIR}/Yosys/
29+
COMMAND ${CMAKE_COMMAND} -E
30+
make_directory ${VTR_SOURCE_DIR}/Yosys/
31+
COMMAND ${CMAKE_COMMAND} -E
32+
copy_directory ${CMAKE_CURRENT_BINARY_DIR}/libyosys ${VTR_SOURCE_DIR}/Yosys/
33+
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
34+
2135
endif()
2236

2337
if(${VTR_ENABLE_CAPNPROTO})

‎libs/EXTERNAL/libyosys/CMakeLists.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ add_dependencies(libyosys yosys)
4444
# specify where the library is and where to find the headers
4545
set_target_properties(libyosys
4646
PROPERTIES PREFIX "" #Avoid extra 'lib' prefix
47-
IMPORTED_LOCATION ${LIB_FILE}
47+
IMPORTED_LOCATION ${BINARY_LIB_FILE}
4848
INTERFACE_INCLUDE_DIRECTORIES ${YOSYS_INCLUDE_DIRS})
4949

5050

‎vtr_flow/benchmarks/hdl_include/include/memory_controller.v

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Original file line numberDiff line numberDiff line change
@@ -24,6 +24,8 @@ reg str_write_enable;
2424
reg [7:0] str_in;
2525
wire [7:0] str_out;
2626

27+
defparam _str.ADDR_WIDTH = 5;
28+
defparam _str.DATA_WIDTH = 8;
2729
single_port_ram _str (
2830
.clk( clk ),
2931
.addr( str_address ),

‎vtr_flow/misc/yosyslib/synthesis.ys renamed to ‎vtr_flow/misc/yosyslib/synthesis.tcl

Lines changed: 24 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,19 @@
11
#################################################################
2-
# Yosys synthesis script, including generic 'synth' commands, #
3-
# in addition to techmap asynchronous FFs and VTR hard blocks. #
2+
# Yosys synthesis script, including generic 'synth' commands, #
3+
# in addition to techmap asynchronous FFs and VTR hard blocks. #
44
# Once the VTR flow runs with the Yosys front-end, Yosys #
5-
# synthesizes the input design using the following commands. #
6-
# #
7-
# NOTE: the script is adapted from the one Eddie Hung proposed #
8-
# for VTR-to-Bitstream[1]. However, a few minor changes to make #
9-
# it adaptable with the current VTR flow have been made. #
10-
# #
11-
# [1] http://eddiehung.github.io/vtb.html #
12-
# #
13-
# Author: Eddie Hung #
14-
# Co-author: Seyed Alireza Damghani ([email protected]) #
5+
# synthesizes the input design using the following commands. #
6+
# #
7+
# NOTE: the script is adapted from the one Eddie Hung proposed #
8+
# for VTR-to-Bitstream[1]. However, a few minor changes to make #
9+
# it adaptable with the current VTR flow have been made. #
10+
# #
11+
# [1] http://eddiehung.github.io/vtb.html #
12+
# #
13+
# Author: Eddie Hung #
14+
# Co-author: Seyed Alireza Damghani ([email protected]) #
1515
#################################################################
16+
yosys -import
1617

1718
# XXX (input circuit) is replaced with filename by the run_vtr_flow script
1819
read_verilog -sv -nolatches XXX
@@ -23,7 +24,7 @@ read_verilog -sv -nolatches XXX
2324
# directory for any definitions to modules it doesn't know
2425
# about, such as hand-instantiated (not inferred) memories
2526
hierarchy -check -auto-top -libdir .
26-
proc
27+
procs
2728

2829
# Check that there are no combinational loops
2930
scc -select
@@ -50,7 +51,7 @@ techmap -map +/adff2dff.v
5051
techmap -map TTT/../../../ODIN_II/techlib/adffe2dff.v
5152

5253
# Map multipliers, DSPs, and add/subtracts according to yosys_models.v
53-
techmap -map YYY */t:$mul */t:$mem */t:$sub */t:$add
54+
techmap -map YYY */t:\$mul */t:\$mem */t:\$sub */t:\$add
5455
opt -fast -full
5556

5657
memory_map
@@ -67,15 +68,19 @@ opt -fast
6768
# as blackboxes
6869
read_verilog -lib TTT/adder.v
6970
read_verilog -lib TTT/multiply.v
70-
read_verilog -lib SSS #(SSS) will be replaced by single_port_ram.v by python script
71-
read_verilog -lib DDD #(DDD) will be replaced by dual_port_ram.v by python script
71+
#(SSS) will be replaced by single_port_ram.v by python script
72+
read_verilog -lib SSS
73+
#(DDD) will be replaced by dual_port_ram.v by python script
74+
read_verilog -lib DDD
7275

7376
# Rename singlePortRam to single_port_ram
74-
# Rename dualPortRam to dualZ_port_ram
77+
# Rename dualPortRam to dual_port_ram
7578
# rename function of Yosys not work here
7679
# since it may outcome hierarchy error
77-
read_verilog SSR #(SSR) will be replaced by spram_rename.v by python script
78-
read_verilog DDR #(DDR) will be replaced by dpram_rename.v by python script
80+
#(SSR) will be replaced by spram_rename.v by python script
81+
read_verilog SSR
82+
#(DDR) will be replaced by dpram_rename.v by python script
83+
read_verilog DDR
7984

8085
# Flatten the netlist
8186
flatten

‎vtr_flow/scripts/python_libs/vtr/odin/odin.py

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,12 @@ def create_circuits_list(main_circuit, include_files):
2525
if include_files:
2626
# Verify that files are Paths or convert them to Paths + check that they exist
2727
for include in include_files:
28+
file_extension = os.path.splitext(include)[-1]
29+
# if the include file is not in the supported HDLs, we drop it
30+
# NOTE: the include file is already copied to the temp folder
31+
if file_extension not in FILE_TYPES:
32+
continue
33+
2834
include_file = vtr.verify_file(include, "Circuit")
2935
circuit_list.append(include_file.name)
3036

@@ -109,6 +115,9 @@ def run(
109115
circuit_file :
110116
Circuit file to optimize
111117
118+
include_files :
119+
list of header files
120+
112121
output_netlist :
113122
File name to output the resulting circuit to
114123

‎vtr_flow/scripts/python_libs/vtr/paths.py

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,10 @@
1717
odin_output_on_error_path = odin_path / "regression_test" / ".library" / "output_on_error.conf"
1818

1919
# YOSYS paths
20-
yosys_exe_path = root_path / "libs" / "EXTERNAL" / "libyosys" / "yosys"
20+
yosys_path = root_path / "Yosys"
21+
yosys_exe_path = yosys_path / "bin" / "yosys"
2122
yosys_lib_path = vtr_flow_path / "misc" / "yosyslib"
22-
yosys_script_path = yosys_lib_path / "synthesis.ys"
23+
yosys_script_path = yosys_lib_path / "synthesis.tcl"
2324

2425
# ABC paths
2526
abc_path = root_path / "abc"

‎vtr_flow/scripts/python_libs/vtr/yosys/yosys.py

Lines changed: 23 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -29,12 +29,18 @@
2929

3030

3131
def create_circuits_list(main_circuit, include_files):
32-
"""Create a list of all (.v) and (.vh) files"""
32+
"""Create a list of supported HDL files"""
3333
circuit_list = []
3434
# Check include files exist
3535
if include_files:
3636
# Verify that files are Paths or convert them to Paths + check that they exist
3737
for include in include_files:
38+
file_extension = os.path.splitext(include)[-1]
39+
# if the include file is not in the supported HDLs, we drop it
40+
# NOTE: the include file is already copied to the temp folder
41+
if file_extension not in FILE_TYPES:
42+
continue
43+
3844
include_file = vtr.verify_file(include, "Circuit")
3945
circuit_list.append(include_file.name)
4046

@@ -69,12 +75,12 @@ def init_script_file(
6975
vtr.file_replace(
7076
yosys_script_full_path,
7177
{
72-
"XXX": circuit_list[0],
73-
"YYY": "./" + YOSYS_LIB_FILES["YSMDL"],
74-
"SSS": "./" + YOSYS_LIB_FILES["SPRAM"],
75-
"DDD": "./" + YOSYS_LIB_FILES["DPRAM"],
76-
"SSR": "./" + YOSYS_LIB_FILES["SPRAMR"],
77-
"DDR": "./" + YOSYS_LIB_FILES["DPRAMR"],
78+
"XXX": "{}".format(" ".join(str(s) for s in circuit_list)),
79+
"YYY": yosys_models_full_path,
80+
"SSS": yosys_spram_full_path,
81+
"DDD": yosys_dpram_full_path,
82+
"SSR": yosys_spram_rename_full_path,
83+
"DDR": yosys_dpram_rename_full_path,
7884
"TTT": str(vtr.paths.yosys_lib_path),
7985
"ZZZ": output_netlist,
8086
},
@@ -121,6 +127,9 @@ def run(
121127
circuit_file :
122128
Circuit file to optimize
123129
130+
include_files :
131+
list of header files
132+
124133
output_netlist :
125134
File name to output the resulting circuit to
126135
@@ -165,14 +174,14 @@ def run(
165174
yosys_base_script = str(Path(yosys_script).resolve())
166175

167176
# Copy the script file
168-
yosys_script = "synthesis.ys"
177+
yosys_script = "synthesis.tcl"
169178
yosys_script_full_path = str(temp_dir / yosys_script)
170179
shutil.copyfile(yosys_base_script, yosys_script_full_path)
171180

172181
# Copy the yosys models file
173182
yosys_models = YOSYS_LIB_FILES["YSMDL"]
174183
yosys_base_models = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["YSMDL"])
175-
yosys_models_full_path = str(temp_dir / yosys_models)
184+
yosys_models_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_models)
176185
shutil.copyfile(yosys_base_models, yosys_models_full_path)
177186

178187
# Copy the VTR memory blocks file
@@ -184,10 +193,10 @@ def run(
184193
yosys_base_dpram = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["DPRAM"])
185194
yosys_base_spram_rename = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["SPRAMR"])
186195
yosys_base_dpram_rename = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["DPRAMR"])
187-
yosys_spram_full_path = str(temp_dir / yosys_spram)
188-
yosys_dpram_full_path = str(temp_dir / yosys_dpram)
189-
yosys_spram_rename_full_path = str(temp_dir / yosys_spram_rename)
190-
yosys_dpram_rename_full_path = str(temp_dir / yosys_dpram_rename)
196+
yosys_spram_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_spram)
197+
yosys_dpram_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_dpram)
198+
yosys_spram_rename_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_spram_rename)
199+
yosys_dpram_rename_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_dpram_rename)
191200
shutil.copyfile(yosys_base_spram, yosys_spram_full_path)
192201
shutil.copyfile(yosys_base_dpram, yosys_dpram_full_path)
193202
shutil.copyfile(yosys_base_spram_rename, yosys_spram_rename_full_path)
@@ -220,7 +229,7 @@ def run(
220229
else:
221230
pass
222231

223-
cmd += ["-s", yosys_script]
232+
cmd += ["-c", yosys_script]
224233

225234
command_runner.run_system_command(
226235
cmd, temp_dir=temp_dir, log_filename=log_filename, indent_depth=1

‎vtr_flow/scripts/run_vtr_flow.py

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,14 @@ def vtr_command_argparser(prog=None):
146146
dest="verbose",
147147
help="Verbosity of the script.",
148148
)
149+
parser.add_argument(
150+
"-include",
151+
nargs="*",
152+
default=None,
153+
dest="include_list_file",
154+
help="List of include files to a benchmark circuit (pass to VTR"
155+
+ " frontends as a benchmark design set)",
156+
)
149157

150158
#
151159
# Power arguments
@@ -331,13 +339,6 @@ def vtr_command_argparser(prog=None):
331339
dest="elaborator",
332340
help="Specify the elaborator of the synthesis flow for Odin-II",
333341
)
334-
odin.add_argument(
335-
"-include",
336-
nargs="*",
337-
default=None,
338-
dest="include_list_file",
339-
help="List of include files to a benchmark circuit(pass to Odin as a benchmark design set)",
340-
)
341342
odin.add_argument(
342343
"-top_module",
343344
default=None,

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt

Lines changed: 0 additions & 40 deletions
This file was deleted.

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