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ODIN_II: generating results for complex synthesis optimization
This commit introduces a set of results for implementing half of the available multiply operations in hard blocks, while the other half being implemented in soft logic Signed-off-by: Georgiy Krylov <[email protected]>
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‎ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json

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{
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"mults_auto_full/bm_base_multiply/k6_frac_N10_frac_chain_mem32K_40nm": {
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"test_name": "mults_auto_full/bm_base_multiply/k6_frac_N10_frac_chain_mem32K_40nm",
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"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
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"blif": "bm_base_multiply.blif",
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"max_rss(MiB)": 101,
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"exec_time(ms)": 765.4,
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"simulation_time(ms)": 631.6,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 47,
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"Po": 78,
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"logic element": 110,
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"latch": 71,
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"Multiplier": 3,
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"generic logic size": 4,
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"Longest Path": 9,
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"Average Path": 4,
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"Estimated LUTs": 110,
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"Total Node": 185
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},
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"mults_auto_full/bm_base_multiply/k6_N10_40nm": {
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"test_name": "mults_auto_full/bm_base_multiply/k6_N10_40nm",
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"architecture": "k6_N10_40nm.xml",
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"blif": "bm_base_multiply.blif",
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"max_rss(MiB)": 144.3,
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"exec_time(ms)": 1509.8,
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"simulation_time(ms)": 1445.6,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 47,
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"Po": 78,
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"logic element": 795,
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"latch": 71,
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"generic logic size": 6,
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"Longest Path": 26,
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"Average Path": 6,
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"Estimated LUTs": 795,
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"Total Node": 867
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},
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"mults_auto_full/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
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"test_name": "mults_auto_full/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
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"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
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"blif": "bm_match1_str_arch.blif",
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"max_rss(MiB)": 127.2,
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"exec_time(ms)": 850.2,
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"simulation_time(ms)": 707.2,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 88,
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"Po": 144,
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"logic element": 144,
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"latch": 72,
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"Multiplier": 3,
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"generic logic size": 4,
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"Longest Path": 5,
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"Average Path": 4,
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"Estimated LUTs": 144,
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"Total Node": 220
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},
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"mults_auto_full/bm_match1_str_arch/k6_N10_40nm": {
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"test_name": "mults_auto_full/bm_match1_str_arch/k6_N10_40nm",
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"architecture": "k6_N10_40nm.xml",
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"blif": "bm_match1_str_arch.blif",
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"max_rss(MiB)": 612.9,
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"exec_time(ms)": 4095.3,
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"simulation_time(ms)": 3860.4,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 88,
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"Po": 144,
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"logic element": 3872,
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"latch": 72,
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"generic logic size": 6,
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"Longest Path": 74,
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"Average Path": 6,
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"Estimated LUTs": 3872,
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"Total Node": 3945
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},
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"mults_auto_full/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
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"test_name": "mults_auto_full/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
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"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
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"blif": "bm_match2_str_arch.blif",
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"max_rss(MiB)": 154.5,
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"exec_time(ms)": 1403.8,
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"simulation_time(ms)": 1067.9,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 54,
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"Po": 99,
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"logic element": 99,
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"latch": 54,
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"Adder": 173,
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"Multiplier": 4,
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"generic logic size": 4,
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"Longest Path": 25,
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"Average Path": 5,
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"Estimated LUTs": 99,
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"Total Node": 331
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},
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"mults_auto_full/bm_match2_str_arch/k6_N10_40nm": {
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"test_name": "mults_auto_full/bm_match2_str_arch/k6_N10_40nm",
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"architecture": "k6_N10_40nm.xml",
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"blif": "bm_match2_str_arch.blif",
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"max_rss(MiB)": 489.8,
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"exec_time(ms)": 3560,
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"simulation_time(ms)": 3281.9,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 54,
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"Po": 99,
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"logic element": 3211,
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"latch": 54,
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"generic logic size": 6,
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"Longest Path": 32,
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"Average Path": 7,
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"Estimated LUTs": 3211,
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"Total Node": 3266
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},
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"mults_auto_full/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
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"test_name": "mults_auto_full/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
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"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
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"blif": "bm_match3_str_arch.blif",
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"max_rss(MiB)": 97.8,
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"exec_time(ms)": 542,
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"simulation_time(ms)": 407.2,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 54,
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"Po": 54,
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"logic element": 54,
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"latch": 54,
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"Adder": 50,
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"Multiplier": 1,
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"generic logic size": 4,
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"Longest Path": 24,
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"Average Path": 5,
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"Estimated LUTs": 54,
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"Total Node": 160
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},
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"mults_auto_full/bm_match3_str_arch/k6_N10_40nm": {
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"test_name": "mults_auto_full/bm_match3_str_arch/k6_N10_40nm",
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"architecture": "k6_N10_40nm.xml",
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"blif": "bm_match3_str_arch.blif",
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"max_rss(MiB)": 90.9,
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"exec_time(ms)": 771.6,
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"simulation_time(ms)": 721.5,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 54,
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"Po": 54,
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"logic element": 375,
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"latch": 54,
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"generic logic size": 6,
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"Longest Path": 58,
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"Average Path": 5,
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"Estimated LUTs": 375,
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"Total Node": 430
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},
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"mults_auto_full/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
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"test_name": "mults_auto_full/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
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"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
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"blif": "bm_match4_str_arch.blif",
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"max_rss(MiB)": 155.5,
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"exec_time(ms)": 1251.4,
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"simulation_time(ms)": 1048.9,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 51,
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"Po": 216,
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"logic element": 216,
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"latch": 108,
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"Adder": 74,
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"Multiplier": 3,
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"generic logic size": 4,
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"Longest Path": 42,
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"Average Path": 4,
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"Estimated LUTs": 216,
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"Total Node": 402
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},
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"mults_auto_full/bm_match4_str_arch/k6_N10_40nm": {
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"test_name": "mults_auto_full/bm_match4_str_arch/k6_N10_40nm",
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"architecture": "k6_N10_40nm.xml",
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"blif": "bm_match4_str_arch.blif",
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"max_rss(MiB)": 238.5,
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"exec_time(ms)": 2038.8,
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"simulation_time(ms)": 1925.5,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 51,
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"Po": 216,
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"logic element": 1367,
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"latch": 108,
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"generic logic size": 6,
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"Longest Path": 49,
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"Average Path": 5,
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"Estimated LUTs": 1367,
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"Total Node": 1476
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},
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"mults_auto_full/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": {
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"test_name": "mults_auto_full/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm",
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"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
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"blif": "bm_match5_str_arch.blif",
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"max_rss(MiB)": 140.9,
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"exec_time(ms)": 971.6,
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"simulation_time(ms)": 800.3,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 90,
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"Po": 54,
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"logic element": 54,
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"latch": 54,
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"Adder": 125,
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"Multiplier": 6,
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"generic logic size": 4,
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"Longest Path": 27,
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"Average Path": 5,
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"Estimated LUTs": 54,
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"Total Node": 240
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},
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"mults_auto_full/bm_match5_str_arch/k6_N10_40nm": {
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"test_name": "mults_auto_full/bm_match5_str_arch/k6_N10_40nm",
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"architecture": "k6_N10_40nm.xml",
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"blif": "bm_match5_str_arch.blif",
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"max_rss(MiB)": 319.7,
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"exec_time(ms)": 2530.9,
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"simulation_time(ms)": 2400.5,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 90,
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"Po": 54,
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"logic element": 2147,
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"latch": 54,
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"generic logic size": 6,
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"Longest Path": 34,
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"Average Path": 6,
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"Estimated LUTs": 2147,
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"Total Node": 2202
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},
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"mults_auto_full/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm": {
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"test_name": "mults_auto_full/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm",
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"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
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"blif": "multiply_hard_block.blif",
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"max_rss(MiB)": 59.9,
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"exec_time(ms)": 100.9,
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"simulation_time(ms)": 14.1,
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"test_coverage(%)": 100,
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"Pi": 8,
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"Po": 8,
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"logic element": 8,
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"Multiplier": 2,
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"generic logic size": 4,
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"Longest Path": 4,
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"Average Path": 4,
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"Estimated LUTs": 8,
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"Total Node": 10
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},
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"mults_auto_full/twobits_arithmetic_multiply/k6_frac_N10_frac_chain_mem32K_40nm": {
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"test_name": "mults_auto_full/twobits_arithmetic_multiply/k6_frac_N10_frac_chain_mem32K_40nm",
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"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
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"blif": "twobits_arithmetic_multiply.blif",
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"max_rss(MiB)": 57.5,
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"exec_time(ms)": 91.5,
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"simulation_time(ms)": 5.4,
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"test_coverage(%)": 90.6,
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"Latch Drivers": 1,
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"Pi": 5,
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"Po": 5,
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"logic element": 12,
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"latch": 4,
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"Multiplier": 1,
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"generic logic size": 4,
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"Longest Path": 8,
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"Average Path": 5,
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"Estimated LUTs": 12,
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"Total Node": 18
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},
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"mults_auto_full/twobits_arithmetic_multiply/k6_N10_40nm": {
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"test_name": "mults_auto_full/twobits_arithmetic_multiply/k6_N10_40nm",
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"architecture": "k6_N10_40nm.xml",
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"blif": "twobits_arithmetic_multiply.blif",
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"max_rss(MiB)": 38.2,
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"exec_time(ms)": 19.1,
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"simulation_time(ms)": 7.1,
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"test_coverage(%)": 92.5,
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"Latch Drivers": 1,
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"Pi": 5,
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"Po": 5,
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"logic element": 21,
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"latch": 4,
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"generic logic size": 6,
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"Longest Path": 9,
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"Average Path": 5,
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"Estimated LUTs": 21,
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"Total Node": 26
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},
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"DEFAULT": {
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"test_name": "n/a",
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"architecture": "n/a",
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"blif": "n/a",
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"exit": 0,
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"leaks": 0,
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"errors": [],
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"warnings": [],
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"expectation": [],
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"max_rss(MiB)": -1,
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"exec_time(ms)": -1,
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"simulation_time(ms)": -1,
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"test_coverage(%)": -1,
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"Latch Drivers": 0,
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"Pi": 0,
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"Po": 0,
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"logic element": 0,
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"latch": 0,
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"Adder": -1,
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"Multiplier": -1,
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"Memory": -1,
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"Hard Ip": -1,
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"generic logic size": -1,
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"Longest Path": 0,
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"Average Path": 0,
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"Estimated LUTs": 0,
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"Total Node": 0
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}
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}

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