Add metadata support to architecture and rr_graph XML. (#473)

* Add metadata support to architecture and rr_graph XML.

The metadata is unused by the core VPR algorithms, but
can be attached at useful points throughout the
architecture and rr_graph XML to enable bitstream export.

Signed-off-by: Keith Rothman <[email protected]>

Author: litghost

doc/src/arch/reference.rst

@@ -905,7 +905,7 @@ The following tags are common to all <pb_type> tags:
         Input logical equivalence means that the pin order can be swapped without changing functionality.
         For example, an AND gate has logically equivalent inputs because you can swap the order of the inputs and it’s still correct; an adder, on the otherhand, is not logically equivalent because if you swap the MSB with the LSB, the results are completely wrong.
         LUTs are also considered logically equivalent since the logic function (LUT mask) can be rotated to account for pin swapping.
-        
+
         * ``none``: No input pins are logically equivalent.
 
             Input pins can not be swapped by the router. (Generates a unique SINK rr-node for each block input port pin.)
@@ -945,12 +945,12 @@ The following tags are common to all <pb_type> tags:
 
         * ``full``: All output pins are considered logically equivalent.
 
-            All output pins can be swapped without limitation by the router. For example, this option would be appropriate to model an output port which has a full crossbar between it and the logic within the block that drives it. (Generates a single SRC rr-node shared by each output port pin.) 
+            All output pins can be swapped without limitation by the router. For example, this option would be appropriate to model an output port which has a full crossbar between it and the logic within the block that drives it. (Generates a single SRC rr-node shared by each output port pin.)
 
         * ``instance``: Models that sub-instances within a block (e.g. LUTs/BLEs) can be swapped to achieve a limited form of output pin logical equivalence.
-          
-            Like ``full``, this generates a single SRC rr-node shared by each output port pin. However, each net originating from this source can use only one output pin from the equivalence group. This can be useful in modeling more complex forms of equivalence in which you can swap which BLE implements which function to gain access to different inputs. 
-            
+
+            Like ``full``, this generates a single SRC rr-node shared by each output port pin. However, each net originating from this source can use only one output pin from the equivalence group. This can be useful in modeling more complex forms of equivalence in which you can swap which BLE implements which function to gain access to different inputs.
+
             .. warning:: When using ``instance`` equivalence you must be careful to ensure output swapping would not make the cluster internal routing (previously computed by the clusterer) illegal; the tool does not update the cluster internal routing due to output pin swapping.
 
         **Default:** ``none``
@@ -1051,7 +1051,7 @@ They describe how a complex block interfaces with the inter-block world.
         <fc in_type="frac" in_val="0.1" out_type="abs" out_val="25">
 
     The above specifies that each:
-    
+
     * input pin connects to 20 L4 tracks (10% of the 200 L4s) and 5 L16 tracks (10% of the 50 L16s), and
 
     * output pin connects to 25 L4 tracks and 25 L16 tracks.
@@ -1921,7 +1921,7 @@ The full format is documented below.
                 :width: 100%
 
         Examples:
-        
+
         * ``min(from,to)`` --  Creates number of switchblock edges equal to the minimum of the 'from' and 'to' set sizes.
 
             This ensures *no* element of the 'from' or 'to' sets is connected to multiple elements in the opposing set.
@@ -2036,3 +2036,51 @@ The full format is documented below.
     This specifies that the 'from' set is the union of L4 switchpoints 0, 1, 2 and 3; and L16 switchpoints 0, 4, 8 and 12.
     The 'to' set is all L4 switchpoint 0's.
     Note that since different switchpoints are selected from different segment types it is not possible to specify this without using ``<from>`` sub-tags.
+
+.. _arch_metadata:
+
+Architecture metadata
+---------------------
+
+Architecture metadata enables tagging of architecture or routing graph
+information that exists outside of the normal VPR flow (e.g. pack, place,
+route, etc).  For example this could be used to enable bitstream generation by
+tagging routing edges and pb_type features.
+
+The metadata will not be used by the vpr executable, but can be leveraged by
+new tools using the libvpr library.  These new tools can access the metadata
+on the various VPR internal data structures.
+
+To enable tagging of architecture structures with metadata, the ``<metadata>``
+tag can be inserted under the following XML tags:
+
+* ``<pb_type>``
+* Any tag under ``<interconnect>`` (``<direct>``, ``<mux>``, etc).
+* ``<mode>``
+* Any grid location type (``<perimeter>``, ``<fill>``, ``<corners>``, ``<single>``, ``<col>``, ``<row>``, ``<region>``)
+
+.. arch:tag:: <metadata>
+
+Specifies the root of a metadata block.  Can have 0 or more ``<meta>`` Children.
+
+.. arch:tag:: <meta name="string" >
+
+    :req_param name: Key name of this metadata value.
+
+Specifies a value within a metadata block.  The name is a key
+for looking up the value contained within the ``<meta>`` tag.  Keys can be
+repeated, and will be stored in a vector in order of occurrence.
+
+The value of the ``<meta>`` is the text in the block. Both the ``name`` and
+``<meta>`` value will be stored as a string.  XML children are not supported
+in the ``<meta>`` tag.
+
+Example of a metadata block with 2 keys:
+
+    .. code-block:: xml
+
+      <metadata>
+        <meta name="some_key">Some value</meta>
+        <meta name="other key!">Other value!</meta>
+      </metadata>
+

doc/src/vpr/file_formats.rst

@@ -795,6 +795,12 @@ The final subtag is the ``rr_edges`` tag that encloses information about all the
     :req_param switch_id:
         The type of switch that connects the two nodes.
 
+Node and Edge Metadata
+^^^^^^^^^^^^^^^^^^^^^^
+
+``metadata`` blocks (see :ref:`arch_metadata`) are supported under both ``node`` and ``edge`` tags.
+
+
 Routing Resource Graph Format Example
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 

libs/libarchfpga/src/arch_util.cpp

@@ -420,12 +420,12 @@ static void free_pb_type(t_pb_type *pb_type) {
                 vtr::free(pb_type->modes[i].interconnect[j].interconnect_power);
         }
         if (pb_type->modes[i].interconnect)
-            vtr::free(pb_type->modes[i].interconnect);
+            delete [] pb_type->modes[i].interconnect;
         if (pb_type->modes[i].mode_power)
             vtr::free(pb_type->modes[i].mode_power);
     }
     if (pb_type->modes)
-        vtr::free(pb_type->modes);
+        delete [] pb_type->modes;
 
     for (int i = 0; i < pb_type->num_annotations; ++i) {
         for (int j = 0; j < pb_type->annotations[i].num_value_prop_pairs; ++j) {
@@ -641,8 +641,7 @@ void ProcessLutClass(t_pb_type *lut_pb_type) {
 
 	lut_pb_type->num_modes = 2;
 	lut_pb_type->pb_type_power->leakage_default_mode = 1;
-	lut_pb_type->modes = (t_mode*) vtr::calloc(lut_pb_type->num_modes,
-			sizeof(t_mode));
+	lut_pb_type->modes = new t_mode[lut_pb_type->num_modes];
 
 	/* First mode, route_through */
 	lut_pb_type->modes[0].name = vtr::strdup("wire");
@@ -666,8 +665,7 @@ void ProcessLutClass(t_pb_type *lut_pb_type) {
 		in_port = &lut_pb_type->ports[1];
 	}
 	lut_pb_type->modes[0].num_interconnect = 1;
-	lut_pb_type->modes[0].interconnect = (t_interconnect*) vtr::calloc(1,
-			sizeof(t_interconnect));
+	lut_pb_type->modes[0].interconnect = new t_interconnect[1];
 	lut_pb_type->modes[0].interconnect[0].name = (char*) vtr::calloc(
 			strlen(lut_pb_type->name) + 10, sizeof(char));
 	sprintf(lut_pb_type->modes[0].interconnect[0].name, "complete:%s",
@@ -767,8 +765,7 @@ void ProcessLutClass(t_pb_type *lut_pb_type) {
 
 	/* Process interconnect */
 	lut_pb_type->modes[1].num_interconnect = 2;
-	lut_pb_type->modes[1].interconnect = (t_interconnect*) vtr::calloc(2,
-			sizeof(t_interconnect));
+	lut_pb_type->modes[1].interconnect = new t_interconnect[lut_pb_type->modes[1].num_interconnect];
 	lut_pb_type->modes[1].interconnect[0].name = (char*) vtr::calloc(
 			strlen(lut_pb_type->name) + 10, sizeof(char));
 	sprintf(lut_pb_type->modes[1].interconnect[0].name, "direct:%s",
@@ -831,7 +828,7 @@ void ProcessMemoryClass(t_pb_type *mem_pb_type) {
 		default_name = vtr::strdup("memory_slice_1bit");
 	}
 
-	mem_pb_type->modes = (t_mode*) vtr::calloc(1, sizeof(t_mode));
+	mem_pb_type->modes = new t_mode[1];
 	mem_pb_type->modes[0].name = vtr::strdup(default_name);
 	mem_pb_type->modes[0].parent_pb_type = mem_pb_type;
 	mem_pb_type->modes[0].index = 0;
@@ -869,8 +866,7 @@ void ProcessMemoryClass(t_pb_type *mem_pb_type) {
 	mem_pb_type->model = nullptr;
 
 	mem_pb_type->modes[0].num_interconnect = mem_pb_type->num_ports * num_pb;
-	mem_pb_type->modes[0].interconnect = (t_interconnect*) vtr::calloc(
-			mem_pb_type->modes[0].num_interconnect, sizeof(t_interconnect));
+	mem_pb_type->modes[0].interconnect = new t_interconnect[mem_pb_type->modes[0].num_interconnect];
 
 	for (i = 0; i < mem_pb_type->modes[0].num_interconnect; i++) {
 		mem_pb_type->modes[0].interconnect[i].parent_mode_index = 0;

libs/libarchfpga/src/echo_arch.cpp

@@ -112,7 +112,7 @@ void PrintArchInfo(FILE * Echo, const t_arch *arch) {
 	fprintf(Echo, "Printing architecture... \n\n");
 	//Layout
 	fprintf(Echo, "*************************************************\n");
-    for (auto grid_layout : arch->grid_layouts) {
+    for (const auto &grid_layout : arch->grid_layouts) {
         if (grid_layout.grid_type == GridDefType::AUTO) {
             fprintf(Echo, "Layout: '%s' Type: auto Aspect_Ratio: %f\n", grid_layout.name.c_str(), grid_layout.aspect_ratio);
         } else {
@@ -250,7 +250,7 @@ void PrintArchInfo(FILE * Echo, const t_arch *arch) {
 	fprintf(Echo, "*************************************************\n");
 	fprintf(Echo, "Segment List:\n");
 	for (i = 0; i < (int)(arch->Segments).size(); i++) {
-		struct t_segment_inf seg = arch->Segments[i];
+		const struct t_segment_inf &seg = arch->Segments[i];
 		fprintf(Echo,
 				"\tSegment[%d]: frequency %d length %d R_metal %e C_metal %e\n",
 				i + 1, seg.frequency, seg.length,